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/* Subroutines used for code generation on IBM RS/6000.
Copyright (C) 1991-2013 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "insn-config.h"
#include "conditions.h"
#include "insn-attr.h"
#include "flags.h"
#include "recog.h"
#include "obstack.h"
#include "tree.h"
#include "expr.h"
#include "optabs.h"
#include "except.h"
#include "function.h"
#include "output.h"
#include "dbxout.h"
#include "basic-block.h"
#include "diagnostic-core.h"
#include "toplev.h"
#include "ggc.h"
#include "hashtab.h"
#include "tm_p.h"
#include "target.h"
#include "target-def.h"
#include "common/common-target.h"
#include "langhooks.h"
#include "reload.h"
#include "cfgloop.h"
#include "sched-int.h"
#include "gimple.h"
#include "tree-flow.h"
#include "intl.h"
#include "params.h"
#include "tm-constrs.h"
#include "opts.h"
#include "tree-vectorizer.h"
#include "dumpfile.h"
#if TARGET_XCOFF
#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
#endif
#if TARGET_MACHO
#include "gstab.h" /* for N_SLINE */
#endif
#ifndef TARGET_NO_PROTOTYPE
#define TARGET_NO_PROTOTYPE 0
#endif
#define min(A,B) ((A) < (B) ? (A) : (B))
#define max(A,B) ((A) > (B) ? (A) : (B))
/* Structure used to define the rs6000 stack */
typedef struct rs6000_stack {
int reload_completed; /* stack info won't change from here on */
int first_gp_reg_save; /* first callee saved GP register used */
int first_fp_reg_save; /* first callee saved FP register used */
int first_altivec_reg_save; /* first callee saved AltiVec register used */
int lr_save_p; /* true if the link reg needs to be saved */
int cr_save_p; /* true if the CR reg needs to be saved */
unsigned int vrsave_mask; /* mask of vec registers to save */
int push_p; /* true if we need to allocate stack space */
int calls_p; /* true if the function makes any calls */
int world_save_p; /* true if we're saving *everything*:
r13-r31, cr, f14-f31, vrsave, v20-v31 */
enum rs6000_abi abi; /* which ABI to use */
int gp_save_offset; /* offset to save GP regs from initial SP */
int fp_save_offset; /* offset to save FP regs from initial SP */
int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
int lr_save_offset; /* offset to save LR from initial SP */
int cr_save_offset; /* offset to save CR from initial SP */
int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
int varargs_save_offset; /* offset to save the varargs registers */
int ehrd_offset; /* offset to EH return data */
int reg_size; /* register size (4 or 8) */
HOST_WIDE_INT vars_size; /* variable save area size */
int parm_size; /* outgoing parameter size */
int save_size; /* save area size */
int fixed_size; /* fixed size of stack frame */
int gp_size; /* size of saved GP registers */
int fp_size; /* size of saved FP registers */
int altivec_size; /* size of saved AltiVec registers */
int cr_size; /* size to hold CR if not in save_size */
int vrsave_size; /* size to hold VRSAVE if not in save_size */
int altivec_padding_size; /* size of altivec alignment padding if
not in save_size */
int spe_gp_size; /* size of 64-bit GPR save size for SPE */
int spe_padding_size;
HOST_WIDE_INT total_size; /* total bytes allocated for stack */
int spe_64bit_regs_used;
int savres_strategy;
} rs6000_stack_t;
/* A C structure for machine-specific, per-function data.
This is added to the cfun structure. */
typedef struct GTY(()) machine_function
{
/* Some local-dynamic symbol. */
const char *some_ld_name;
/* Whether the instruction chain has been scanned already. */
int insn_chain_scanned_p;
/* Flags if __builtin_return_address (n) with n >= 1 was used. */
int ra_needs_full_frame;
/* Flags if __builtin_return_address (0) was used. */
int ra_need_lr;
/* Cache lr_save_p after expansion of builtin_eh_return. */
int lr_save_state;
/* Whether we need to save the TOC to the reserved stack location in the
function prologue. */
bool save_toc_in_prologue;
/* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
varargs save area. */
HOST_WIDE_INT varargs_save_offset;
/* Temporary stack slot to use for SDmode copies. This slot is
64-bits wide and is allocated early enough so that the offset
does not overflow the 16-bit load/store offset field. */
rtx sdmode_stack_slot;
} machine_function;
/* Support targetm.vectorize.builtin_mask_for_load. */
static GTY(()) tree altivec_builtin_mask_for_load;
/* Set to nonzero once AIX common-mode calls have been defined. */
static GTY(()) int common_mode_defined;
/* Label number of label created for -mrelocatable, to call to so we can
get the address of the GOT section */
static int rs6000_pic_labelno;
#ifdef USING_ELFOS_H
/* Counter for labels which are to be placed in .fixup. */
int fixuplabelno = 0;
#endif
/* Whether to use variant of AIX ABI for PowerPC64 Linux. */
int dot_symbols;
/* Specify the machine mode that pointers have. After generation of rtl, the
compiler makes no further distinction between pointers and any other objects
of this machine mode. The type is unsigned since not all things that
include rs6000.h also include machmode.h. */
unsigned rs6000_pmode;
/* Width in bits of a pointer. */
unsigned rs6000_pointer_size;
#ifdef HAVE_AS_GNU_ATTRIBUTE
/* Flag whether floating point values have been passed/returned. */
static bool rs6000_passes_float;
/* Flag whether vector values have been passed/returned. */
static bool rs6000_passes_vector;
/* Flag whether small (<= 8 byte) structures have been returned. */
static bool rs6000_returns_struct;
#endif
/* Value is TRUE if register/mode pair is acceptable. */
bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
/* Maximum number of registers needed for a given register class and mode. */
unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
/* How many registers are needed for a given register and mode. */
unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
/* Map register number to register class. */
enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
/* Reload functions based on the type and the vector unit. */
static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
static int dbg_cost_ctrl;
/* Built in types. */
tree rs6000_builtin_types[RS6000_BTI_MAX];
tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
/* Flag to say the TOC is initialized */
int toc_initialized;
char toc_label_name[10];
/* Cached value of rs6000_variable_issue. This is cached in
rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
static short cached_can_issue_more;
static GTY(()) section *read_only_data_section;
static GTY(()) section *private_data_section;
static GTY(()) section *tls_data_section;
static GTY(()) section *tls_private_data_section;
static GTY(()) section *read_only_private_data_section;
static GTY(()) section *sdata2_section;
static GTY(()) section *toc_section;
struct builtin_description
{
const HOST_WIDE_INT mask;
const enum insn_code icode;
const char *const name;
const enum rs6000_builtins code;
};
/* Describe the vector unit used for modes. */
enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
/* Register classes for various constraints that are based on the target
switches. */
enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
/* Describe the alignment of a vector. */
int rs6000_vector_align[NUM_MACHINE_MODES];
/* Map selected modes to types for builtins. */
static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
/* What modes to automatically generate reciprocal divide estimate (fre) and
reciprocal sqrt (frsqrte) for. */
unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
/* Masks to determine which reciprocal esitmate instructions to generate
automatically. */
enum rs6000_recip_mask {
RECIP_SF_DIV = 0x001, /* Use divide estimate */
RECIP_DF_DIV = 0x002,
RECIP_V4SF_DIV = 0x004,
RECIP_V2DF_DIV = 0x008,
RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
RECIP_DF_RSQRT = 0x020,
RECIP_V4SF_RSQRT = 0x040,
RECIP_V2DF_RSQRT = 0x080,
/* Various combination of flags for -mrecip=xxx. */
RECIP_NONE = 0,
RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
| RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
RECIP_HIGH_PRECISION = RECIP_ALL,
/* On low precision machines like the power5, don't enable double precision
reciprocal square root estimate, since it isn't accurate enough. */
RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
};
/* -mrecip options. */
static struct
{
const char *string; /* option name */
unsigned int mask; /* mask bits to set */
} recip_options[] = {
{ "all", RECIP_ALL },
{ "none", RECIP_NONE },
{ "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
| RECIP_V2DF_DIV) },
{ "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
{ "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
{ "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT) },
{ "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
{ "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
};
/* 2 argument gen function typedef. */
typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
/* Pointer to function (in rs6000-c.c) that can define or undefine target
macros that have changed. Languages that don't support the preprocessor
don't link in rs6000-c.c, so we can't call it directly. */
void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
/* Target cpu costs. */
struct processor_costs {
const int mulsi; /* cost of SImode multiplication. */
const int mulsi_const; /* cost of SImode multiplication by constant. */
const int mulsi_const9; /* cost of SImode mult by short constant. */
const int muldi; /* cost of DImode multiplication. */
const int divsi; /* cost of SImode division. */
const int divdi; /* cost of DImode division. */
const int fp; /* cost of simple SFmode and DFmode insns. */
const int dmul; /* cost of DFmode multiplication (and fmadd). */
const int sdiv; /* cost of SFmode division (fdivs). */
const int ddiv; /* cost of DFmode division (fdiv). */
const int cache_line_size; /* cache line size in bytes. */
const int l1_cache_size; /* size of l1 cache, in kilobytes. */
const int l2_cache_size; /* size of l2 cache, in kilobytes. */
const int simultaneous_prefetches; /* number of parallel prefetch
operations. */
};
const struct processor_costs *rs6000_cost;
/* Processor costs (relative to an add) */
/* Instruction size costs on 32bit processors. */
static const
struct processor_costs size32_cost = {
COSTS_N_INSNS (1), /* mulsi */
COSTS_N_INSNS (1), /* mulsi_const */
COSTS_N_INSNS (1), /* mulsi_const9 */
COSTS_N_INSNS (1), /* muldi */
COSTS_N_INSNS (1), /* divsi */
COSTS_N_INSNS (1), /* divdi */
COSTS_N_INSNS (1), /* fp */
COSTS_N_INSNS (1), /* dmul */
COSTS_N_INSNS (1), /* sdiv */
COSTS_N_INSNS (1), /* ddiv */
32,
0,
0,
0,
};
/* Instruction size costs on 64bit processors. */
static const
struct processor_costs size64_cost = {
COSTS_N_INSNS (1), /* mulsi */
COSTS_N_INSNS (1), /* mulsi_const */
COSTS_N_INSNS (1), /* mulsi_const9 */
COSTS_N_INSNS (1), /* muldi */
COSTS_N_INSNS (1), /* divsi */
COSTS_N_INSNS (1), /* divdi */
COSTS_N_INSNS (1), /* fp */
COSTS_N_INSNS (1), /* dmul */
COSTS_N_INSNS (1), /* sdiv */
COSTS_N_INSNS (1), /* ddiv */
128,
0,
0,
0,
};
/* Instruction costs on RS64A processors. */
static const
struct processor_costs rs64a_cost = {
COSTS_N_INSNS (20), /* mulsi */
COSTS_N_INSNS (12), /* mulsi_const */
COSTS_N_INSNS (8), /* mulsi_const9 */
COSTS_N_INSNS (34), /* muldi */
COSTS_N_INSNS (65), /* divsi */
COSTS_N_INSNS (67), /* divdi */
COSTS_N_INSNS (4), /* fp */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (31), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
128, /* cache line size */
128, /* l1 cache */
2048, /* l2 cache */
1, /* streams */
};
/* Instruction costs on MPCCORE processors. */
static const
struct processor_costs mpccore_cost = {
COSTS_N_INSNS (2), /* mulsi */
COSTS_N_INSNS (2), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (2), /* muldi */
COSTS_N_INSNS (6), /* divsi */
COSTS_N_INSNS (6), /* divdi */
COSTS_N_INSNS (4), /* fp */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (10), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
32, /* cache line size */
4, /* l1 cache */
16, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC403 processors. */
static const
struct processor_costs ppc403_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (33), /* divsi */
COSTS_N_INSNS (33), /* divdi */
COSTS_N_INSNS (11), /* fp */
COSTS_N_INSNS (11), /* dmul */
COSTS_N_INSNS (11), /* sdiv */
COSTS_N_INSNS (11), /* ddiv */
32, /* cache line size */
4, /* l1 cache */
16, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC405 processors. */
static const
struct processor_costs ppc405_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (3), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (35), /* divsi */
COSTS_N_INSNS (35), /* divdi */
COSTS_N_INSNS (11), /* fp */
COSTS_N_INSNS (11), /* dmul */
COSTS_N_INSNS (11), /* sdiv */
COSTS_N_INSNS (11), /* ddiv */
32, /* cache line size */
16, /* l1 cache */
128, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC440 processors. */
static const
struct processor_costs ppc440_cost = {
COSTS_N_INSNS (3), /* mulsi */
COSTS_N_INSNS (2), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (3), /* muldi */
COSTS_N_INSNS (34), /* divsi */
COSTS_N_INSNS (34), /* divdi */
COSTS_N_INSNS (5), /* fp */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (19), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
256, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC476 processors. */
static const
struct processor_costs ppc476_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (11), /* divsi */
COSTS_N_INSNS (11), /* divdi */
COSTS_N_INSNS (6), /* fp */
COSTS_N_INSNS (6), /* dmul */
COSTS_N_INSNS (19), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
32, /* l1 cache line size */
32, /* l1 cache */
512, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC601 processors. */
static const
struct processor_costs ppc601_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (5), /* mulsi_const */
COSTS_N_INSNS (5), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (36), /* divsi */
COSTS_N_INSNS (36), /* divdi */
COSTS_N_INSNS (4), /* fp */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
256, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC603 processors. */
static const
struct processor_costs ppc603_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (3), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (37), /* divsi */
COSTS_N_INSNS (37), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
32, /* cache line size */
8, /* l1 cache */
64, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC604 processors. */
static const
struct processor_costs ppc604_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (20), /* divsi */
COSTS_N_INSNS (20), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
32, /* cache line size */
16, /* l1 cache */
512, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC604e processors. */
static const
struct processor_costs ppc604e_cost = {
COSTS_N_INSNS (2), /* mulsi */
COSTS_N_INSNS (2), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (2), /* muldi */
COSTS_N_INSNS (20), /* divsi */
COSTS_N_INSNS (20), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC620 processors. */
static const
struct processor_costs ppc620_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (3), /* mulsi_const9 */
COSTS_N_INSNS (7), /* muldi */
COSTS_N_INSNS (21), /* divsi */
COSTS_N_INSNS (37), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
128, /* cache line size */
32, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC630 processors. */
static const
struct processor_costs ppc630_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (3), /* mulsi_const9 */
COSTS_N_INSNS (7), /* muldi */
COSTS_N_INSNS (21), /* divsi */
COSTS_N_INSNS (37), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (21), /* ddiv */
128, /* cache line size */
64, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
/* Instruction costs on Cell processor. */
/* COSTS_N_INSNS (1) ~ one add. */
static const
struct processor_costs ppccell_cost = {
COSTS_N_INSNS (9/2)+2, /* mulsi */
COSTS_N_INSNS (6/2), /* mulsi_const */
COSTS_N_INSNS (6/2), /* mulsi_const9 */
COSTS_N_INSNS (15/2)+2, /* muldi */
COSTS_N_INSNS (38/2), /* divsi */
COSTS_N_INSNS (70/2), /* divdi */
COSTS_N_INSNS (10/2), /* fp */
COSTS_N_INSNS (10/2), /* dmul */
COSTS_N_INSNS (74/2), /* sdiv */
COSTS_N_INSNS (74/2), /* ddiv */
128, /* cache line size */
32, /* l1 cache */
512, /* l2 cache */
6, /* streams */
};
/* Instruction costs on PPC750 and PPC7400 processors. */
static const
struct processor_costs ppc750_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (3), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (17), /* divsi */
COSTS_N_INSNS (17), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
512, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC7450 processors. */
static const
struct processor_costs ppc7450_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (3), /* mulsi_const */
COSTS_N_INSNS (3), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (23), /* divsi */
COSTS_N_INSNS (23), /* divdi */
COSTS_N_INSNS (5), /* fp */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (21), /* sdiv */
COSTS_N_INSNS (35), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
/* Instruction costs on PPC8540 processors. */
static const
struct processor_costs ppc8540_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (19), /* divsi */
COSTS_N_INSNS (19), /* divdi */
COSTS_N_INSNS (4), /* fp */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (29), /* sdiv */
COSTS_N_INSNS (29), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
256, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on E300C2 and E300C3 cores. */
static const
struct processor_costs ppce300c2c3_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (19), /* divsi */
COSTS_N_INSNS (19), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
32,
16, /* l1 cache */
16, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on PPCE500MC processors. */
static const
struct processor_costs ppce500mc_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (14), /* divsi */
COSTS_N_INSNS (14), /* divdi */
COSTS_N_INSNS (8), /* fp */
COSTS_N_INSNS (10), /* dmul */
COSTS_N_INSNS (36), /* sdiv */
COSTS_N_INSNS (66), /* ddiv */
64, /* cache line size */
32, /* l1 cache */
128, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on PPCE500MC64 processors. */
static const
struct processor_costs ppce500mc64_cost = {
COSTS_N_INSNS (4), /* mulsi */
COSTS_N_INSNS (4), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (14), /* divsi */
COSTS_N_INSNS (14), /* divdi */
COSTS_N_INSNS (4), /* fp */
COSTS_N_INSNS (10), /* dmul */
COSTS_N_INSNS (36), /* sdiv */
COSTS_N_INSNS (66), /* ddiv */
64, /* cache line size */
32, /* l1 cache */
128, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on PPCE5500 processors. */
static const
struct processor_costs ppce5500_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (5), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (14), /* divsi */
COSTS_N_INSNS (14), /* divdi */
COSTS_N_INSNS (7), /* fp */
COSTS_N_INSNS (10), /* dmul */
COSTS_N_INSNS (36), /* sdiv */
COSTS_N_INSNS (66), /* ddiv */
64, /* cache line size */
32, /* l1 cache */
128, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on PPCE6500 processors. */
static const
struct processor_costs ppce6500_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (5), /* mulsi_const */
COSTS_N_INSNS (4), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (14), /* divsi */
COSTS_N_INSNS (14), /* divdi */
COSTS_N_INSNS (7), /* fp */
COSTS_N_INSNS (10), /* dmul */
COSTS_N_INSNS (36), /* sdiv */
COSTS_N_INSNS (66), /* ddiv */
64, /* cache line size */
32, /* l1 cache */
128, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on AppliedMicro Titan processors. */
static const
struct processor_costs titan_cost = {
COSTS_N_INSNS (5), /* mulsi */
COSTS_N_INSNS (5), /* mulsi_const */
COSTS_N_INSNS (5), /* mulsi_const9 */
COSTS_N_INSNS (5), /* muldi */
COSTS_N_INSNS (18), /* divsi */
COSTS_N_INSNS (18), /* divdi */
COSTS_N_INSNS (10), /* fp */
COSTS_N_INSNS (10), /* dmul */
COSTS_N_INSNS (46), /* sdiv */
COSTS_N_INSNS (72), /* ddiv */
32, /* cache line size */
32, /* l1 cache */
512, /* l2 cache */
1, /* prefetch streams /*/
};
/* Instruction costs on POWER4 and POWER5 processors. */
static const
struct processor_costs power4_cost = {
COSTS_N_INSNS (3), /* mulsi */
COSTS_N_INSNS (2), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (4), /* muldi */
COSTS_N_INSNS (18), /* divsi */
COSTS_N_INSNS (34), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
128, /* cache line size */
32, /* l1 cache */
1024, /* l2 cache */
8, /* prefetch streams /*/
};
/* Instruction costs on POWER6 processors. */
static const
struct processor_costs power6_cost = {
COSTS_N_INSNS (8), /* mulsi */
COSTS_N_INSNS (8), /* mulsi_const */
COSTS_N_INSNS (8), /* mulsi_const9 */
COSTS_N_INSNS (8), /* muldi */
COSTS_N_INSNS (22), /* divsi */
COSTS_N_INSNS (28), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (13), /* sdiv */
COSTS_N_INSNS (16), /* ddiv */
128, /* cache line size */
64, /* l1 cache */
2048, /* l2 cache */
16, /* prefetch streams */
};
/* Instruction costs on POWER7 processors. */
static const
struct processor_costs power7_cost = {
COSTS_N_INSNS (2), /* mulsi */
COSTS_N_INSNS (2), /* mulsi_const */
COSTS_N_INSNS (2), /* mulsi_const9 */
COSTS_N_INSNS (2), /* muldi */
COSTS_N_INSNS (18), /* divsi */
COSTS_N_INSNS (34), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (13), /* sdiv */
COSTS_N_INSNS (16), /* ddiv */
128, /* cache line size */
32, /* l1 cache */
256, /* l2 cache */
12, /* prefetch streams */
};
/* Instruction costs on POWER A2 processors. */
static const
struct processor_costs ppca2_cost = {
COSTS_N_INSNS (16), /* mulsi */
COSTS_N_INSNS (16), /* mulsi_const */
COSTS_N_INSNS (16), /* mulsi_const9 */
COSTS_N_INSNS (16), /* muldi */
COSTS_N_INSNS (22), /* divsi */
COSTS_N_INSNS (28), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (59), /* sdiv */
COSTS_N_INSNS (72), /* ddiv */
64,
16, /* l1 cache */
2048, /* l2 cache */
16, /* prefetch streams */
};
/* Table that classifies rs6000 builtin functions (pure, const, etc.). */
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
struct rs6000_builtin_info_type {
const char *name;
const enum insn_code icode;
const HOST_WIDE_INT mask;
const unsigned attr;
};
static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
{
#include "rs6000-builtin.def"
};
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
/* Support for -mveclibabi=<xxx> to control which vector library to use. */
static tree (*rs6000_veclib_handler) (tree, tree, tree);
static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
static bool spe_func_has_64bit_regs_p (void);
static struct machine_function * rs6000_init_machine_status (void);
static int rs6000_ra_ever_killed (void);
static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
static int rs6000_debug_address_cost (rtx, enum machine_mode, addr_space_t,
bool);
static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
static bool is_microcoded_insn (rtx);
static bool is_nonpipeline_insn (rtx);
static bool is_cracked_insn (rtx);
static bool is_load_insn (rtx, rtx *);
static bool is_store_insn (rtx, rtx *);
static bool set_to_load_agen (rtx,rtx);
static bool insn_terminates_group_p (rtx , enum group_termination);
static bool insn_must_be_first_in_group (rtx);
static bool insn_must_be_last_in_group (rtx);
static void altivec_init_builtins (void);
static tree builtin_function_type (enum machine_mode, enum machine_mode,
enum machine_mode, enum machine_mode,
enum rs6000_builtins, const char *name);
static void rs6000_common_init_builtins (void);
static void paired_init_builtins (void);
static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
static void spe_init_builtins (void);
static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
static rs6000_stack_t *rs6000_stack_info (void);
static void is_altivec_return_reg (rtx, void *);
int easy_vector_constant (rtx, enum machine_mode);
static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
static int rs6000_tls_symbol_ref_1 (rtx *, void *);
static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
bool, bool);
#if TARGET_MACHO
static void macho_branch_islands (void);
#endif
static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
int, int *);
static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
int, int, int *);
static bool rs6000_mode_dependent_address (const_rtx);
static bool rs6000_debug_mode_dependent_address (const_rtx);
static enum reg_class rs6000_secondary_reload_class (enum reg_class,
enum machine_mode, rtx);
static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
enum machine_mode,
rtx);
static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
static enum reg_class rs6000_debug_preferred_reload_class (rtx,
enum reg_class);
static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
enum machine_mode);
static bool rs6000_debug_secondary_memory_needed (enum reg_class,
enum reg_class,
enum machine_mode);
static bool rs6000_cannot_change_mode_class (enum machine_mode,
enum machine_mode,
enum reg_class);
static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
enum machine_mode,
enum reg_class);
static bool rs6000_save_toc_in_prologue_p (void);
rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
int, int *)
= rs6000_legitimize_reload_address;
static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
= rs6000_mode_dependent_address;
enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
enum machine_mode, rtx)
= rs6000_secondary_reload_class;
enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
= rs6000_preferred_reload_class;
bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
enum machine_mode)
= rs6000_secondary_memory_needed;
bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
enum machine_mode,
enum reg_class)
= rs6000_cannot_change_mode_class;
const int INSN_NOT_AVAILABLE = -1;
static void rs6000_print_isa_options (FILE *, int, const char *,
HOST_WIDE_INT);
static void rs6000_print_builtin_options (FILE *, int, const char *,
HOST_WIDE_INT);
/* Hash table stuff for keeping track of TOC entries. */
struct GTY(()) toc_hash_struct
{
/* `key' will satisfy CONSTANT_P; in fact, it will satisfy
ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
rtx key;
enum machine_mode key_mode;
int labelno;
};
static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
/* Hash table to keep track of the argument types for builtin functions. */
struct GTY(()) builtin_hash_struct
{
tree type;
enum machine_mode mode[4]; /* return value + 3 arguments. */
unsigned char uns_p[4]; /* and whether the types are unsigned. */
};
static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
/* Default register names. */
char rs6000_reg_names[][8] =
{
"0", "1", "2", "3", "4", "5", "6", "7",
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31",
"0", "1", "2", "3", "4", "5", "6", "7",
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31",
"mq", "lr", "ctr","ap",
"0", "1", "2", "3", "4", "5", "6", "7",
"ca",
/* AltiVec registers. */
"0", "1", "2", "3", "4", "5", "6", "7",
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31",
"vrsave", "vscr",
/* SPE registers. */
"spe_acc", "spefscr",
/* Soft frame pointer. */
"sfp"
};
#ifdef TARGET_REGNAMES
static const char alt_reg_names[][8] =
{
"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
"%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
"%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
"%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
"%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
"%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
"%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
"mq", "lr", "ctr", "ap",
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
"ca",
/* AltiVec registers. */
"%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
"%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
"%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
"%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
"vrsave", "vscr",
/* SPE registers. */
"spe_acc", "spefscr",
/* Soft frame pointer. */
"sfp"
};
#endif
/* Table of valid machine attributes. */
static const struct attribute_spec rs6000_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
affects_type_identity } */
{ "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
false },
{ "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
false },
{ "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
false },
{ "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
false },
{ "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
false },
#ifdef SUBTARGET_ATTRIBUTE_TABLE
SUBTARGET_ATTRIBUTE_TABLE,
#endif
{ NULL, 0, 0, false, false, false, NULL, false }
};
#ifndef TARGET_PROFILE_KERNEL
#define TARGET_PROFILE_KERNEL 0
#endif
/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
/* Initialize the GCC target structure. */
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
#undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
#define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
/* Default unaligned ops are only provided for ELF. Find the ops needed
for non-ELF systems. */
#ifndef OBJECT_FORMAT_ELF
#if TARGET_XCOFF
/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
64-bit targets. */
#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
#else
/* For Darwin. */
#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
#endif
#endif
/* This hook deals with fixups for relocatable code and DI-mode objects
in 64-bit code. */
#undef TARGET_ASM_INTEGER
#define TARGET_ASM_INTEGER rs6000_assemble_integer
#if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
#undef TARGET_ASM_ASSEMBLE_VISIBILITY
#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
#endif
#undef TARGET_SET_UP_BY_PROLOGUE
#define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS HAVE_AS_TLS
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
#undef TARGET_DELEGITIMIZE_ADDRESS
#define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
#undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
#define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
#undef TARGET_ASM_FUNCTION_PROLOGUE
#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
#undef TARGET_SCHED_VARIABLE_ISSUE
#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
#undef TARGET_SCHED_ADJUST_PRIORITY
#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
#undef TARGET_SCHED_INIT
#define TARGET_SCHED_INIT rs6000_sched_init
#undef TARGET_SCHED_FINISH
#define TARGET_SCHED_FINISH rs6000_sched_finish
#undef TARGET_SCHED_REORDER
#define TARGET_SCHED_REORDER rs6000_sched_reorder
#undef TARGET_SCHED_REORDER2
#define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
#undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
#define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
#undef TARGET_SCHED_INIT_SCHED_CONTEXT
#define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
#undef TARGET_SCHED_SET_SCHED_CONTEXT
#define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
#undef TARGET_SCHED_FREE_SCHED_CONTEXT
#define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
rs6000_builtin_support_vector_misalignment
#undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
#define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
#undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
#define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
rs6000_builtin_vectorization_cost
#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
rs6000_preferred_simd_mode
#undef TARGET_VECTORIZE_INIT_COST
#define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
#undef TARGET_VECTORIZE_ADD_STMT_COST
#define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
#undef TARGET_VECTORIZE_FINISH_COST
#define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
#undef TARGET_VECTORIZE_DESTROY_COST_DATA
#define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS rs6000_init_builtins
#undef TARGET_BUILTIN_DECL
#define TARGET_BUILTIN_DECL rs6000_builtin_decl
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
#undef TARGET_MANGLE_TYPE
#define TARGET_MANGLE_TYPE rs6000_mangle_type
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
#if TARGET_MACHO
#undef TARGET_BINDS_LOCAL_P
#define TARGET_BINDS_LOCAL_P darwin_binds_local_p
#endif
#undef TARGET_MS_BITFIELD_LAYOUT_P
#define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
#undef TARGET_INVALID_WITHIN_DOLOOP
#define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
#undef TARGET_REGISTER_MOVE_COST
#define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
#undef TARGET_MEMORY_MOVE_COST
#define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS rs6000_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
#undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
#define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
#undef TARGET_MEMBER_TYPE_FORCES_BLK
#define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
/* On rs6000, function arguments are promoted, as are function return
values. */
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
/* Always strict argument naming on rs6000. */
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
#undef TARGET_SPLIT_COMPLEX_ARG
#define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
#undef TARGET_FUNCTION_ARG_ADVANCE
#define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
#undef TARGET_FUNCTION_ARG
#define TARGET_FUNCTION_ARG rs6000_function_arg
#undef TARGET_FUNCTION_ARG_BOUNDARY
#define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
#undef TARGET_BUILD_BUILTIN_VA_LIST
#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
#undef TARGET_EH_RETURN_FILTER_MODE
#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
#undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE rs6000_option_override
#undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
#define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
rs6000_builtin_vectorized_function
#if !TARGET_MACHO
#undef TARGET_STACK_PROTECT_FAIL
#define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
#endif
/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
The PowerPC architecture requires only weak consistency among
processors--that is, memory accesses between processors need not be
sequentially consistent and memory accesses among processors can occur
in any order. The ability to order memory accesses weakly provides
opportunities for more efficient use of the system bus. Unless a
dependency exists, the 604e allows read operations to precede store
operations. */
#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING true
#ifdef HAVE_AS_TLS
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
#define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
#endif
/* Use a 32-bit anchor range. This leads to sequences like:
addis tmp,anchor,high
add dest,tmp,low
where tmp itself acts as an anchor, and can be shared between
accesses to the same 64k page. */
#undef TARGET_MIN_ANCHOR_OFFSET
#define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
#undef TARGET_MAX_ANCHOR_OFFSET
#define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
#define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
#undef TARGET_USE_BLOCKS_FOR_DECL_P
#define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
#undef TARGET_BUILTIN_RECIPROCAL
#define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
#undef TARGET_EXPAND_TO_RTL_HOOK
#define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
#undef TARGET_INSTANTIATE_DECLS
#define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
#undef TARGET_MODE_DEPENDENT_ADDRESS_P
#define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
#undef TARGET_CAN_ELIMINATE
#define TARGET_CAN_ELIMINATE rs6000_can_eliminate
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
#undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE rs6000_function_value
#undef TARGET_OPTION_VALID_ATTRIBUTE_P
#define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
#undef TARGET_OPTION_SAVE
#define TARGET_OPTION_SAVE rs6000_function_specific_save
#undef TARGET_OPTION_RESTORE
#define TARGET_OPTION_RESTORE rs6000_function_specific_restore
#undef TARGET_OPTION_PRINT
#define TARGET_OPTION_PRINT rs6000_function_specific_print
#undef TARGET_CAN_INLINE_P
#define TARGET_CAN_INLINE_P rs6000_can_inline_p
#undef TARGET_SET_CURRENT_FUNCTION
#define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
#define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
/* Processor table. */
struct rs6000_ptt
{
const char *const name; /* Canonical processor name. */
const enum processor_type processor; /* Processor type enum value. */
const HOST_WIDE_INT target_enable; /* Target flags to enable. */
};
static struct rs6000_ptt const processor_target_table[] =
{
#define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
#include "rs6000-cpus.def"
#undef RS6000_CPU
};
/* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
name is invalid. */
static int
rs6000_cpu_name_lookup (const char *name)
{
size_t i;
if (name != NULL)
{
for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
if (! strcmp (name, processor_target_table[i].name))
return (int)i;
}
return -1;
}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
For the SPE, GPRs are 64 bits but only 32 bits are visible in
scalar instructions. The upper 32 bits are only available to the
SIMD instructions.
POWER and PowerPC GPRs hold 32 bits worth;
PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
static int
rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
{
unsigned HOST_WIDE_INT reg_size;
if (FP_REGNO_P (regno))
reg_size = (VECTOR_MEM_VSX_P (mode)
? UNITS_PER_VSX_WORD
: UNITS_PER_FP_WORD);
else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
reg_size = UNITS_PER_SPE_WORD;
else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
/* The value returned for SCmode in the E500 double case is 2 for
ABI compatibility; storing an SCmode value in a single register
would require function_arg and rs6000_spe_function_arg to handle
SCmode so as to pass the value correctly in a pair of
registers. */
else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
&& !DECIMAL_FLOAT_MODE_P (mode))
reg_size = UNITS_PER_FP_WORD;
else
reg_size = UNITS_PER_WORD;
return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
}
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. */
static int
rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
/* VSX registers that overlap the FPR registers are larger than for non-VSX
implementations. Don't allow an item to be split between a FP register
and an Altivec register. */
if (VECTOR_MEM_VSX_P (mode))
{
if (FP_REGNO_P (regno))
return FP_REGNO_P (last_regno);
if (ALTIVEC_REGNO_P (regno))
return ALTIVEC_REGNO_P (last_regno);
}
/* The GPRs can hold any mode, but values bigger than one register
cannot go past R31. */
if (INT_REGNO_P (regno))
return INT_REGNO_P (last_regno);
/* The float registers (except for VSX vector modes) can only hold floating
modes and DImode. This excludes the 32-bit decimal float mode for
now. */
if (FP_REGNO_P (regno))
{
if (SCALAR_FLOAT_MODE_P (mode)
&& (mode != TDmode || (regno % 2) == 0)
&& FP_REGNO_P (last_regno))
return 1;
if (GET_MODE_CLASS (mode) == MODE_INT
&& GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode))
return 1;
return 0;
}
/* The CR register can only hold CC modes. */
if (CR_REGNO_P (regno))
return GET_MODE_CLASS (mode) == MODE_CC;
if (CA_REGNO_P (regno))
return mode == BImode;
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
/* ...but GPRs can hold SIMD data on the SPE in one register. */
if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
return 1;
/* We cannot put TImode anywhere except general register and it must be able
to fit within the register set. In the future, allow TImode in the
Altivec or VSX registers. */
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}
/* Print interesting facts about registers. */
static void
rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
{
int r, m;
for (r = first_regno; r <= last_regno; ++r)
{
const char *comma = "";
int len;
if (first_regno == last_regno)
fprintf (stderr, "%s:\t", reg_name);
else
fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
len = 8;
for (m = 0; m < NUM_MACHINE_MODES; ++m)
if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
{
if (len > 70)
{
fprintf (stderr, ",\n\t");
len = 8;
comma = "";
}
if (rs6000_hard_regno_nregs[m][r] > 1)
len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
rs6000_hard_regno_nregs[m][r]);
else
len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
comma = ", ";
}
if (call_used_regs[r])
{
if (len > 70)
{
fprintf (stderr, ",\n\t");
len = 8;
comma = "";
}
len += fprintf (stderr, "%s%s", comma, "call-used");
comma = ", ";
}
if (fixed_regs[r])
{
if (len > 70)
{
fprintf (stderr, ",\n\t");
len = 8;
comma = "";
}
len += fprintf (stderr, "%s%s", comma, "fixed");
comma = ", ";
}
if (len > 70)
{
fprintf (stderr, ",\n\t");
comma = "";
}
fprintf (stderr, "%sregno = %d\n", comma, r);
}
}
#define DEBUG_FMT_ID "%-32s= "
#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
#define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
/* Print various interesting information with -mdebug=reg. */
static void
rs6000_debug_reg_global (void)
{
static const char *const tf[2] = { "false", "true" };
const char *nl = (const char *)0;
int m;
char costly_num[20];
char nop_num[20];
char flags_buffer[40];
const char *costly_str;
const char *nop_str;
const char *trace_str;
const char *abi_str;
const char *cmodel_str;
struct cl_target_option cl_opts;
/* Map enum rs6000_vector to string. */
static const char *rs6000_debug_vector_unit[] = {
"none",
"altivec",
"vsx",
"paired",
"spe",
"other"
};
fprintf (stderr, "Register information: (last virtual reg = %d)\n",
LAST_VIRTUAL_REGISTER);
rs6000_debug_reg_print (0, 31, "gr");
rs6000_debug_reg_print (32, 63, "fp");
rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
LAST_ALTIVEC_REGNO,
"vs");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
fprintf (stderr,
"\n"
"d reg_class = %s\n"
"f reg_class = %s\n"
"v reg_class = %s\n"
"wa reg_class = %s\n"
"wd reg_class = %s\n"
"wf reg_class = %s\n"
"ws reg_class = %s\n\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
for (m = 0; m < NUM_MACHINE_MODES; ++m)
if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
{
nl = "\n";
fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
GET_MODE_NAME (m),
rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
}
if (nl)
fputs (nl, stderr);
if (rs6000_recip_control)
{
fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
for (m = 0; m < NUM_MACHINE_MODES; ++m)
if (rs6000_recip_bits[m])
{
fprintf (stderr,
"Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
GET_MODE_NAME (m),
(RS6000_RECIP_AUTO_RE_P (m)
? "auto"
: (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
(RS6000_RECIP_AUTO_RSQRTE_P (m)
? "auto"
: (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
}
fputs ("\n", stderr);
}
if (rs6000_cpu_index >= 0)
{
const char *name = processor_target_table[rs6000_cpu_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_cpu_index].target_enable;
sprintf (flags_buffer, "-mcpu=%s flags", name);
rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
if (rs6000_tune_index >= 0)
{
const char *name = processor_target_table[rs6000_tune_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_tune_index].target_enable;
sprintf (flags_buffer, "-mtune=%s flags", name);
rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
cl_target_option_save (&cl_opts, &global_options);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
rs6000_isa_flags);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
rs6000_isa_flags_explicit);
rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
rs6000_builtin_mask);
rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
switch (rs6000_sched_costly_dep)
{
case max_dep_latency:
costly_str = "max_dep_latency";
break;
case no_dep_costly:
costly_str = "no_dep_costly";
break;
case all_deps_costly:
costly_str = "all_deps_costly";
break;
case true_store_to_load_dep_costly:
costly_str = "true_store_to_load_dep_costly";
break;
case store_to_load_dep_costly:
costly_str = "store_to_load_dep_costly";
break;
default:
costly_str = costly_num;
sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
break;
}
fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
switch (rs6000_sched_insert_nops)
{
case sched_finish_regroup_exact:
nop_str = "sched_finish_regroup_exact";
break;
case sched_finish_pad_groups:
nop_str = "sched_finish_pad_groups";
break;
case sched_finish_none:
nop_str = "sched_finish_none";
break;
default:
nop_str = nop_num;
sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
break;
}
fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
switch (rs6000_sdata)
{
default:
case SDATA_NONE:
break;
case SDATA_DATA:
fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
break;
case SDATA_SYSV:
fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
break;
case SDATA_EABI:
fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
break;
}
switch (rs6000_traceback)
{
case traceback_default: trace_str = "default"; break;
case traceback_none: trace_str = "none"; break;
case traceback_part: trace_str = "part"; break;
case traceback_full: trace_str = "full"; break;
default: trace_str = "unknown"; break;
}
fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
switch (rs6000_current_cmodel)
{
case CMODEL_SMALL: cmodel_str = "small"; break;
case CMODEL_MEDIUM: cmodel_str = "medium"; break;
case CMODEL_LARGE: cmodel_str = "large"; break;
default: cmodel_str = "unknown"; break;
}
fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
switch (rs6000_current_abi)
{
case ABI_NONE: abi_str = "none"; break;
case ABI_AIX: abi_str = "aix"; break;
case ABI_V4: abi_str = "V4"; break;
case ABI_DARWIN: abi_str = "darwin"; break;
default: abi_str = "unknown"; break;
}
fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
if (rs6000_altivec_abi)
fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
if (rs6000_spe_abi)
fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
if (rs6000_darwin64_abi)
fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
if (rs6000_float_gprs)
fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
if (TARGET_LINK_STACK)
fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
fprintf (stderr, DEBUG_FMT_S, "plt-format",
TARGET_SECURE_PLT ? "secure" : "bss");
fprintf (stderr, DEBUG_FMT_S, "struct-return",
aix_struct_return ? "aix" : "sysv");
fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
fprintf (stderr, DEBUG_FMT_S, "align_branch",
tf[!!rs6000_align_branch_targets]);
fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
fprintf (stderr, DEBUG_FMT_D, "long_double_size",
rs6000_long_double_type_size);
fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
(int)rs6000_sched_restricted_insns_priority);
fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
(int)END_BUILTINS);
fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
(int)RS6000_BUILTIN_COUNT);
}
/* Initialize the various global tables that are based on register size. */
static void
rs6000_init_hard_regno_mode_ok (bool global_init_p)
{
int r, m, c;
int align64;
int align32;
/* Precalculate REGNO_REG_CLASS. */
rs6000_regno_regclass[0] = GENERAL_REGS;
for (r = 1; r < 32; ++r)
rs6000_regno_regclass[r] = BASE_REGS;
for (r = 32; r < 64; ++r)
rs6000_regno_regclass[r] = FLOAT_REGS;
for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
rs6000_regno_regclass[r] = NO_REGS;
for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
rs6000_regno_regclass[r] = ALTIVEC_REGS;
rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
rs6000_regno_regclass[r] = CR_REGS;
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
rs6000_regno_regclass[CA_REGNO] = CA_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
/* Precalculate vector information, this must be set up before the
rs6000_hard_regno_nregs_internal below. */
for (m = 0; m < NUM_MACHINE_MODES; ++m)
{
rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
rs6000_vector_reload[m][0] = CODE_FOR_nothing;
rs6000_vector_reload[m][1] = CODE_FOR_nothing;
}
for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
rs6000_constraints[c] = NO_REGS;
/* The VSX hardware allows native alignment for vectors, but control whether the compiler
believes it can use native alignment or still uses 128-bit alignment. */
if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
{
align64 = 64;
align32 = 32;
}
else
{
align64 = 128;
align32 = 128;
}
/* V2DF mode, VSX only. */
if (TARGET_VSX)
{
rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
rs6000_vector_align[V2DFmode] = align64;
}
/* V4SF mode, either VSX or Altivec. */
if (TARGET_VSX)
{
rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
rs6000_vector_align[V4SFmode] = align32;
}
else if (TARGET_ALTIVEC)
{
rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
rs6000_vector_align[V4SFmode] = align32;
}
/* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
and stores. */
if (TARGET_ALTIVEC)
{
rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
rs6000_vector_align[V4SImode] = align32;
rs6000_vector_align[V8HImode] = align32;
rs6000_vector_align[V16QImode] = align32;
if (TARGET_VSX)
{
rs6000_vector_mem[V4SImode] = VECTOR_VSX;
rs6000_vector_mem[V8HImode] = VECTOR_VSX;
rs6000_vector_mem[V16QImode] = VECTOR_VSX;
}
else
{
rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
}
}
/* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
Altivec doesn't have 64-bit support. */
if (TARGET_VSX)
{
rs6000_vector_mem[V2DImode] = VECTOR_VSX;
rs6000_vector_unit[V2DImode] = VECTOR_NONE;
rs6000_vector_align[V2DImode] = align64;
}
/* DFmode, see if we want to use the VSX unit. */
if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
{
rs6000_vector_unit[DFmode] = VECTOR_VSX;
rs6000_vector_mem[DFmode]
= (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
rs6000_vector_align[DFmode] = align64;
}
/* TODO add SPE and paired floating point vector support. */
/* Register class constraints for the constraints that depend on compile
switches. */
if (TARGET_HARD_FLOAT && TARGET_FPRS)
rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
if (TARGET_VSX)
{
/* At present, we just use VSX_REGS, but we have different constraints
based on the use, in case we want to fine tune the default register
class used. wa = any VSX register, wf = register class to use for
V4SF, wd = register class to use for V2DF, and ws = register classs to
use for DF scalars. */
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
? VSX_REGS
: FLOAT_REGS);
}
if (TARGET_ALTIVEC)
rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
/* Set up the reload helper functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
if (TARGET_64BIT)
{
rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
{
rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;
rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;
}
}
else
{
rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
{
rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;
rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;
}
}
}
/* Precalculate HARD_REGNO_NREGS. */
for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
rs6000_hard_regno_nregs[m][r]
= rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
/* Precalculate HARD_REGNO_MODE_OK. */
for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
rs6000_hard_regno_mode_ok_p[m][r] = true;
/* Precalculate CLASS_MAX_NREGS sizes. */
for (c = 0; c < LIM_REG_CLASSES; ++c)
{
int reg_size;
if (TARGET_VSX && VSX_REG_CLASS_P (c))
reg_size = UNITS_PER_VSX_WORD;
else if (c == ALTIVEC_REGS)
reg_size = UNITS_PER_ALTIVEC_WORD;
else if (c == FLOAT_REGS)
reg_size = UNITS_PER_FP_WORD;
else
reg_size = UNITS_PER_WORD;
for (m = 0; m < NUM_MACHINE_MODES; ++m)
{
int reg_size2 = reg_size;
/* TFmode/TDmode always takes 2 registers, even in VSX. */
if (m == TDmode || m == TFmode)
reg_size2 = UNITS_PER_FP_WORD;
rs6000_class_max_nregs[m][c]
= (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2;
}
}
if (TARGET_E500_DOUBLE)
rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
/* Calculate which modes to automatically generate code to use a the
reciprocal divide and square root instructions. In the future, possibly
automatically generate the instructions even if the user did not specify
-mrecip. The older machines double precision reciprocal sqrt estimate is
not accurate enough. */
memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
if (TARGET_FRES)
rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
if (TARGET_FRE)
rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
if (VECTOR_UNIT_VSX_P (V2DFmode))
rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
if (TARGET_FRSQRTES)
rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
if (TARGET_FRSQRTE)
rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
if (VECTOR_UNIT_VSX_P (V2DFmode))
rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
if (rs6000_recip_control)
{
if (!flag_finite_math_only)
warning (0, "-mrecip requires -ffinite-math or -ffast-math");
if (flag_trapping_math)
warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
if (!flag_reciprocal_math)
warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
{
if (RS6000_RECIP_HAVE_RE_P (SFmode)
&& (rs6000_recip_control & RECIP_SF_DIV) != 0)
rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
if (RS6000_RECIP_HAVE_RE_P (DFmode)
&& (rs6000_recip_control & RECIP_DF_DIV) != 0)
rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
&& (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
&& (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
&& (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
&& (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
&& (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
&& (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
}
}
if (global_init_p || TARGET_DEBUG_TARGET)
{
if (TARGET_DEBUG_REG)
rs6000_debug_reg_global ();
if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
fprintf (stderr,
"SImode variable mult cost = %d\n"
"SImode constant mult cost = %d\n"
"SImode short constant mult cost = %d\n"
"DImode multipliciation cost = %d\n"
"SImode division cost = %d\n"
"DImode division cost = %d\n"
"Simple fp operation cost = %d\n"
"DFmode multiplication cost = %d\n"
"SFmode division cost = %d\n"
"DFmode division cost = %d\n"
"cache line size = %d\n"
"l1 cache size = %d\n"
"l2 cache size = %d\n"
"simultaneous prefetches = %d\n"
"\n",
rs6000_cost->mulsi,
rs6000_cost->mulsi_const,
rs6000_cost->mulsi_const9,
rs6000_cost->muldi,
rs6000_cost->divsi,
rs6000_cost->divdi,
rs6000_cost->fp,
rs6000_cost->dmul,
rs6000_cost->sdiv,
rs6000_cost->ddiv,
rs6000_cost->cache_line_size,
rs6000_cost->l1_cache_size,
rs6000_cost->l2_cache_size,
rs6000_cost->simultaneous_prefetches);
}
}
#if TARGET_MACHO
/* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
static void
darwin_rs6000_override_options (void)
{
/* The Darwin ABI always includes AltiVec, can't be (validly) turned
off. */
rs6000_altivec_abi = 1;
TARGET_ALTIVEC_VRSAVE = 1;
rs6000_current_abi = ABI_DARWIN;
if (DEFAULT_ABI == ABI_DARWIN
&& TARGET_64BIT)
darwin_one_byte_bool = 1;
if (TARGET_64BIT && ! TARGET_POWERPC64)
{
rs6000_isa_flags |= OPTION_MASK_POWERPC64;
warning (0, "-m64 requires PowerPC64 architecture, enabling");
}
if (flag_mkernel)
{
rs6000_default_long_calls = 1;
rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
}
/* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
Altivec. */
if (!flag_mkernel && !flag_apple_kext
&& TARGET_64BIT
&& ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
/* Unless the user (not the configurer) has explicitly overridden
it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
G4 unless targeting the kernel. */
if (!flag_mkernel
&& !flag_apple_kext
&& strverscmp (darwin_macosx_version_min, "10.5") >= 0
&& ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
&& ! global_options_set.x_rs6000_cpu_index)
{
rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
}
}
#endif
/* If not otherwise specified by a target, make 'long double' equivalent to
'double'. */
#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
#endif
/* Return the builtin mask of the various options used that could affect which
builtins were used. In the past we used target_flags, but we've run out of
bits, and some options like SPE and PAIRED are no longer in
target_flags. */
HOST_WIDE_INT
rs6000_builtin_mask_calculate (void)
{
return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
| ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
| ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
| ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
| ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
| ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
| ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
| ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
| ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
| ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
}
/* Override command line options. Mostly we process the processor type and
sometimes adjust other TARGET_ options. */
static bool
rs6000_option_override_internal (bool global_init_p)
{
bool ret = true;
bool have_cpu = false;
/* The default cpu requested at configure time, if any. */
const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
HOST_WIDE_INT set_masks;
int cpu_index;
int tune_index;
struct cl_target_option *main_target_opt
= ((global_init_p || target_option_default_node == NULL)
? NULL : TREE_TARGET_OPTION (target_option_default_node));
/* On 64-bit Darwin, power alignment is ABI-incompatible with some C
library functions, so warn about it. The flag may be useful for
performance studies from time to time though, so don't disable it
entirely. */
if (global_options_set.x_rs6000_alignment_flags
&& rs6000_alignment_flags == MASK_ALIGN_POWER
&& DEFAULT_ABI == ABI_DARWIN
&& TARGET_64BIT)
warning (0, "-malign-power is not supported for 64-bit Darwin;"
" it is incompatible with the installed C and C++ libraries");
/* Numerous experiment shows that IRA based loop pressure
calculation works better for RTL loop invariant motion on targets
with enough (>= 32) registers. It is an expensive optimization.
So it is on only for peak performance. */
if (optimize >= 3 && global_init_p)
flag_ira_loop_pressure = 1;
/* Set the pointer size. */
if (TARGET_64BIT)
{
rs6000_pmode = (int)DImode;
rs6000_pointer_size = 64;
}
else
{
rs6000_pmode = (int)SImode;
rs6000_pointer_size = 32;
}
/* Some OSs don't support saving the high part of 64-bit registers on context
switch. Other OSs don't support saving Altivec registers. On those OSs,
we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
if the user wants either, the user must explicitly specify them and we
won't interfere with the user's specification. */
set_masks = POWERPC_MASKS;
#ifdef OS_MISSING_POWERPC64
if (OS_MISSING_POWERPC64)
set_masks &= ~OPTION_MASK_POWERPC64;
#endif
#ifdef OS_MISSING_ALTIVEC
if (OS_MISSING_ALTIVEC)
set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX);
#endif
/* Don't override by the processor default if given explicitly. */
set_masks &= ~rs6000_isa_flags_explicit;
/* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
the cpu in a target attribute or pragma, but did not specify a tuning
option, use the cpu for the tuning option rather than the option specified
with -mtune on the command line. Process a '--with-cpu' configuration
request as an implicit --cpu. */
if (rs6000_cpu_index >= 0)
{
cpu_index = rs6000_cpu_index;
have_cpu = true;
}
else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
{
rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
have_cpu = true;
}
else if (implicit_cpu)
{
rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (implicit_cpu);
have_cpu = true;
}
else
{
const char *default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
have_cpu = false;
}
gcc_assert (cpu_index >= 0);
/* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
with those from the cpu, except for options that were explicitly set. If
we don't have a cpu, do not override the target bits set in
TARGET_DEFAULT. */
if (have_cpu)
{
rs6000_isa_flags &= ~set_masks;
rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
& set_masks);
}
else
rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
& ~rs6000_isa_flags_explicit);
/* If no -mcpu=<xxx>, inherit any default options that were cleared via
POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
to using rs6000_isa_flags, we need to do the initialization here. */
if (!have_cpu)
rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit);
if (rs6000_tune_index >= 0)
tune_index = rs6000_tune_index;
else if (have_cpu)
rs6000_tune_index = tune_index = cpu_index;
else
{
size_t i;
enum processor_type tune_proc
= (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
tune_index = -1;
for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
if (processor_target_table[i].processor == tune_proc)
{
rs6000_tune_index = tune_index = i;
break;
}
}
gcc_assert (tune_index >= 0);
rs6000_cpu = processor_target_table[tune_index].processor;
/* Pick defaults for SPE related control flags. Do this early to make sure
that the TARGET_ macros are representative ASAP. */
{
int spe_capable_cpu =
(rs6000_cpu == PROCESSOR_PPC8540
|| rs6000_cpu == PROCESSOR_PPC8548);
if (!global_options_set.x_rs6000_spe_abi)
rs6000_spe_abi = spe_capable_cpu;
if (!global_options_set.x_rs6000_spe)
rs6000_spe = spe_capable_cpu;
if (!global_options_set.x_rs6000_float_gprs)
rs6000_float_gprs =
(rs6000_cpu == PROCESSOR_PPC8540 ? 1
: rs6000_cpu == PROCESSOR_PPC8548 ? 2
: 0);
}
if (global_options_set.x_rs6000_spe_abi
&& rs6000_spe_abi
&& !TARGET_SPE_ABI)
error ("not configured for SPE ABI");
if (global_options_set.x_rs6000_spe
&& rs6000_spe
&& !TARGET_SPE)
error ("not configured for SPE instruction set");
if (main_target_opt != NULL
&& ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
|| (main_target_opt->x_rs6000_spe != rs6000_spe)
|| (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
error ("target attribute or pragma changes SPE ABI");
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
|| rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
|| rs6000_cpu == PROCESSOR_PPCE5500)
{
if (TARGET_ALTIVEC)
error ("AltiVec not supported in this target");
if (TARGET_SPE)
error ("SPE not supported in this target");
}
if (rs6000_cpu == PROCESSOR_PPCE6500)
{
if (TARGET_SPE)
error ("SPE not supported in this target");
}
/* Disable Cell microcode if we are optimizing for the Cell
and not optimizing for size. */
if (rs6000_gen_cell_microcode == -1)
rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
&& !optimize_size);
/* If we are optimizing big endian systems for space and it's OK to
use instructions that would be microcoded on the Cell, use the
load/store multiple and string instructions. */
if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
| OPTION_MASK_STRING);
/* Don't allow -mmultiple or -mstring on little endian systems
unless the cpu is a 750, because the hardware doesn't support the
instructions used in little endian mode, and causes an alignment
trap. The 750 does not cause an alignment trap (except when the
target is unaligned). */
if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
{
if (TARGET_MULTIPLE)
{
rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
warning (0, "-mmultiple is not supported on little endian systems");
}
if (TARGET_STRING)
{
rs6000_isa_flags &= ~OPTION_MASK_STRING;
if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
warning (0, "-mstring is not supported on little endian systems");
}
}
/* Add some warnings for VSX. */
if (TARGET_VSX)
{
const char *msg = NULL;
if (!TARGET_HARD_FLOAT || !TARGET_FPRS
|| !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx requires hardware floating point");
else
rs6000_isa_flags &= ~ OPTION_MASK_VSX;
}
else if (TARGET_PAIRED_FLOAT)
msg = N_("-mvsx and -mpaired are incompatible");
/* The hardware will allow VSX and little endian, but until we make sure
things like vector select, etc. work don't allow VSX on little endian
systems at this point. */
else if (!BYTES_BIG_ENDIAN)
msg = N_("-mvsx used with little endian code");
else if (TARGET_AVOID_XFORM > 0)
msg = N_("-mvsx needs indexed addressing");
else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC))
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx and -mno-altivec are incompatible");
else
msg = N_("-mno-altivec disables vsx");
}
if (msg)
{
warning (0, msg);
rs6000_isa_flags &= ~ OPTION_MASK_VSX;
rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
}
}
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
else if (TARGET_POPCNTD)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit);
else if (TARGET_CMPB)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
else if (TARGET_FPRND)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit);
else if (TARGET_POPCNTB)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit);
else if (TARGET_ALTIVEC)
rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
/* E500mc does "better" if we inline more aggressively. Respect the
user's opinion, though. */
if (rs6000_block_move_inline_limit == 0
&& (rs6000_cpu == PROCESSOR_PPCE500MC
|| rs6000_cpu == PROCESSOR_PPCE500MC64
|| rs6000_cpu == PROCESSOR_PPCE5500
|| rs6000_cpu == PROCESSOR_PPCE6500))
rs6000_block_move_inline_limit = 128;
/* store_one_arg depends on expand_block_move to handle at least the
size of reg_parm_stack_space. */
if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
if (global_init_p)
{
/* If the appropriate debug option is enabled, replace the target hooks
with debug versions that call the real version and then prints
debugging information. */
if (TARGET_DEBUG_COST)
{
targetm.rtx_costs = rs6000_debug_rtx_costs;
targetm.address_cost = rs6000_debug_address_cost;
targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
}
if (TARGET_DEBUG_ADDR)
{
targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
targetm.legitimize_address = rs6000_debug_legitimize_address;
rs6000_secondary_reload_class_ptr
= rs6000_debug_secondary_reload_class;
rs6000_secondary_memory_needed_ptr
= rs6000_debug_secondary_memory_needed;
rs6000_cannot_change_mode_class_ptr
= rs6000_debug_cannot_change_mode_class;
rs6000_preferred_reload_class_ptr
= rs6000_debug_preferred_reload_class;
rs6000_legitimize_reload_address_ptr
= rs6000_debug_legitimize_reload_address;
rs6000_mode_dependent_address_ptr
= rs6000_debug_mode_dependent_address;
}
if (rs6000_veclibabi_name)
{
if (strcmp (rs6000_veclibabi_name, "mass") == 0)
rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
else
{
error ("unknown vectorization library ABI type (%s) for "
"-mveclibabi= switch", rs6000_veclibabi_name);
ret = false;
}
}
}
if (!global_options_set.x_rs6000_long_double_type_size)
{
if (main_target_opt != NULL
&& (main_target_opt->x_rs6000_long_double_type_size
!= RS6000_DEFAULT_LONG_DOUBLE_SIZE))
error ("target attribute or pragma changes long double size");
else
rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
}
#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
if (!global_options_set.x_rs6000_ieeequad)
rs6000_ieeequad = 1;
#endif
/* Disable VSX and Altivec silently if the user switched cpus to power7 in a
target attribute or pragma which automatically enables both options,
unless the altivec ABI was set. This is set by default for 64-bit, but
not for 32-bit. */
if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
& ~rs6000_isa_flags_explicit);
/* Enable Altivec ABI for AIX -maltivec. */
if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
{
if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
error ("target attribute or pragma changes AltiVec ABI");
else
rs6000_altivec_abi = 1;
}
/* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
be explicitly overridden in either case. */
if (TARGET_ELF)
{
if (!global_options_set.x_rs6000_altivec_abi
&& (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
{
if (main_target_opt != NULL &&
!main_target_opt->x_rs6000_altivec_abi)
error ("target attribute or pragma changes AltiVec ABI");
else
rs6000_altivec_abi = 1;
}
}
/* Set the Darwin64 ABI as default for 64-bit Darwin.
So far, the only darwin64 targets are also MACH-O. */
if (TARGET_MACHO
&& DEFAULT_ABI == ABI_DARWIN
&& TARGET_64BIT)
{
if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
error ("target attribute or pragma changes darwin64 ABI");
else
{
rs6000_darwin64_abi = 1;
/* Default to natural alignment, for better performance. */
rs6000_alignment_flags = MASK_ALIGN_NATURAL;
}
}
/* Place FP constants in the constant pool instead of TOC
if section anchors enabled. */
if (flag_section_anchors)
TARGET_NO_FP_IN_TOC = 1;
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
#endif
#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
SUBSUBTARGET_OVERRIDE_OPTIONS;
#endif
#ifdef SUB3TARGET_OVERRIDE_OPTIONS
SUB3TARGET_OVERRIDE_OPTIONS;
#endif
/* For the E500 family of cores, reset the single/double FP flags to let us
check that they remain constant across attributes or pragmas. Also,
clear a possible request for string instructions, not supported and which
we might have silently queried above for -Os.
For other families, clear ISEL in case it was set implicitly.
*/
switch (rs6000_cpu)
{
case PROCESSOR_PPC8540:
case PROCESSOR_PPC8548:
case PROCESSOR_PPCE500MC:
case PROCESSOR_PPCE500MC64:
case PROCESSOR_PPCE5500:
case PROCESSOR_PPCE6500:
rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
rs6000_double_float = TARGET_E500_DOUBLE;
rs6000_isa_flags &= ~OPTION_MASK_STRING;
break;
default:
if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
rs6000_isa_flags &= ~OPTION_MASK_ISEL;
break;
}
if (main_target_opt)
{
if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
error ("target attribute or pragma changes single precision floating "
"point");
if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
error ("target attribute or pragma changes double precision floating "
"point");
}
/* Detect invalid option combinations with E500. */
CHECK_E500_OPTIONS;
rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
&& rs6000_cpu != PROCESSOR_POWER5
&& rs6000_cpu != PROCESSOR_POWER6
&& rs6000_cpu != PROCESSOR_POWER7
&& rs6000_cpu != PROCESSOR_PPCA2
&& rs6000_cpu != PROCESSOR_CELL
&& rs6000_cpu != PROCESSOR_PPC476);
rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
|| rs6000_cpu == PROCESSOR_POWER5
|| rs6000_cpu == PROCESSOR_POWER7);
rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
|| rs6000_cpu == PROCESSOR_POWER5
|| rs6000_cpu == PROCESSOR_POWER6
|| rs6000_cpu == PROCESSOR_POWER7
|| rs6000_cpu == PROCESSOR_PPCE500MC
|| rs6000_cpu == PROCESSOR_PPCE500MC64
|| rs6000_cpu == PROCESSOR_PPCE5500
|| rs6000_cpu == PROCESSOR_PPCE6500);
/* Allow debug switches to override the above settings. These are set to -1
in rs6000.opt to indicate the user hasn't directly set the switch. */
if (TARGET_ALWAYS_HINT >= 0)
rs6000_always_hint = TARGET_ALWAYS_HINT;
if (TARGET_SCHED_GROUPS >= 0)
rs6000_sched_groups = TARGET_SCHED_GROUPS;
if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
rs6000_sched_restricted_insns_priority
= (rs6000_sched_groups ? 1 : 0);
/* Handle -msched-costly-dep option. */
rs6000_sched_costly_dep
= (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
if (rs6000_sched_costly_dep_str)
{
if (! strcmp (rs6000_sched_costly_dep_str, "no"))
rs6000_sched_costly_dep = no_dep_costly;
else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
rs6000_sched_costly_dep = all_deps_costly;
else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
rs6000_sched_costly_dep = true_store_to_load_dep_costly;
else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
rs6000_sched_costly_dep = store_to_load_dep_costly;
else
rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
atoi (rs6000_sched_costly_dep_str));
}
/* Handle -minsert-sched-nops option. */
rs6000_sched_insert_nops
= (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
if (rs6000_sched_insert_nops_str)
{
if (! strcmp (rs6000_sched_insert_nops_str, "no"))
rs6000_sched_insert_nops = sched_finish_none;
else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
rs6000_sched_insert_nops = sched_finish_pad_groups;
else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
rs6000_sched_insert_nops = sched_finish_regroup_exact;
else
rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
atoi (rs6000_sched_insert_nops_str));
}
if (global_init_p)
{
#ifdef TARGET_REGNAMES
/* If the user desires alternate register names, copy in the
alternate names now. */
if (TARGET_REGNAMES)
memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
#endif
/* Set aix_struct_return last, after the ABI is determined.
If -maix-struct-return or -msvr4-struct-return was explicitly
used, don't override with the ABI default. */
if (!global_options_set.x_aix_struct_return)
aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
#if 0
/* IBM XL compiler defaults to unsigned bitfields. */
if (TARGET_XL_COMPAT)
flag_signed_bitfields = 0;
#endif
if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
if (TARGET_TOC)
ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
/* We can only guarantee the availability of DI pseudo-ops when
assembling for 64-bit targets. */
if (!TARGET_64BIT)
{
targetm.asm_out.aligned_op.di = NULL;
targetm.asm_out.unaligned_op.di = NULL;
}
/* Set branch target alignment, if not optimizing for size. */
if (!optimize_size)
{
/* Cell wants to be aligned 8byte for dual issue. Titan wants to be
aligned 8byte to avoid misprediction by the branch predictor. */
if (rs6000_cpu == PROCESSOR_TITAN
|| rs6000_cpu == PROCESSOR_CELL)
{
if (align_functions <= 0)
align_functions = 8;
if (align_jumps <= 0)
align_jumps = 8;
if (align_loops <= 0)
align_loops = 8;
}
if (rs6000_align_branch_targets)
{
if (align_functions <= 0)
align_functions = 16;
if (align_jumps <= 0)
align_jumps = 16;
if (align_loops <= 0)
{
can_override_loop_align = 1;
align_loops = 16;
}
}
if (align_jumps_max_skip <= 0)
align_jumps_max_skip = 15;
if (align_loops_max_skip <= 0)
align_loops_max_skip = 15;
}
/* Arrange to save and restore machine status around nested functions. */
init_machine_status = rs6000_init_machine_status;
/* We should always be splitting complex arguments, but we can't break
Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
if (DEFAULT_ABI != ABI_AIX)
targetm.calls.split_complex_arg = NULL;
}
/* Initialize rs6000_cost with the appropriate target costs. */
if (optimize_size)
rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
else
switch (rs6000_cpu)
{
case PROCESSOR_RS64A:
rs6000_cost = &rs64a_cost;
break;
case PROCESSOR_MPCCORE:
rs6000_cost = &mpccore_cost;
break;
case PROCESSOR_PPC403:
rs6000_cost = &ppc403_cost;
break;
case PROCESSOR_PPC405:
rs6000_cost = &ppc405_cost;
break;
case PROCESSOR_PPC440:
rs6000_cost = &ppc440_cost;
break;
case PROCESSOR_PPC476:
rs6000_cost = &ppc476_cost;
break;
case PROCESSOR_PPC601:
rs6000_cost = &ppc601_cost;
break;
case PROCESSOR_PPC603:
rs6000_cost = &ppc603_cost;
break;
case PROCESSOR_PPC604:
rs6000_cost = &ppc604_cost;
break;
case PROCESSOR_PPC604e:
rs6000_cost = &ppc604e_cost;
break;
case PROCESSOR_PPC620:
rs6000_cost = &ppc620_cost;
break;
case PROCESSOR_PPC630:
rs6000_cost = &ppc630_cost;
break;
case PROCESSOR_CELL:
rs6000_cost = &ppccell_cost;
break;
case PROCESSOR_PPC750:
case PROCESSOR_PPC7400:
rs6000_cost = &ppc750_cost;
break;
case PROCESSOR_PPC7450:
rs6000_cost = &ppc7450_cost;
break;
case PROCESSOR_PPC8540:
case PROCESSOR_PPC8548:
rs6000_cost = &ppc8540_cost;
break;
case PROCESSOR_PPCE300C2:
case PROCESSOR_PPCE300C3:
rs6000_cost = &ppce300c2c3_cost;
break;
case PROCESSOR_PPCE500MC:
rs6000_cost = &ppce500mc_cost;
break;
case PROCESSOR_PPCE500MC64:
rs6000_cost = &ppce500mc64_cost;
break;
case PROCESSOR_PPCE5500:
rs6000_cost = &ppce5500_cost;
break;
case PROCESSOR_PPCE6500:
rs6000_cost = &ppce6500_cost;
break;
case PROCESSOR_TITAN:
rs6000_cost = &titan_cost;
break;
case PROCESSOR_POWER4:
case PROCESSOR_POWER5:
rs6000_cost = &power4_cost;
break;
case PROCESSOR_POWER6:
rs6000_cost = &power6_cost;
break;
case PROCESSOR_POWER7:
rs6000_cost = &power7_cost;
break;
case PROCESSOR_PPCA2:
rs6000_cost = &ppca2_cost;
break;
default:
gcc_unreachable ();
}
if (global_init_p)
{
maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
rs6000_cost->simultaneous_prefetches,
global_options.x_param_values,
global_options_set.x_param_values);
maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
global_options.x_param_values,
global_options_set.x_param_values);
maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
rs6000_cost->cache_line_size,
global_options.x_param_values,
global_options_set.x_param_values);
maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
global_options.x_param_values,
global_options_set.x_param_values);
/* Increase loop peeling limits based on performance analysis. */
maybe_set_param_