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chromium / native_client / nacl-toolchain / cc3d67a9abb3eceb0d79d5369b40b41f67e2474b / . / gdb / sim / mips / mips.igen
blob: 5a6326fed202936898c1ed1f2b072851a3cc8e09 [file] [log] [blame]
// -*- C -*-
//
// <insn> ::=
// <insn-word> { "+" <insn-word> }
// ":" <format-name>
// ":" <filter-flags>
// ":" <options>
// ":" <name>
// <nl>
// { <insn-model> }
// { <insn-mnemonic> }
// <code-block>
//
// IGEN config - mips16
// :option:16::insn-bit-size:16
// :option:16::hi-bit-nr:15
:option:16::insn-specifying-widths:true
:option:16::gen-delayed-branch:false
// IGEN config - mips32/64..
// :option:32::insn-bit-size:32
// :option:32::hi-bit-nr:31
:option:32::insn-specifying-widths:true
:option:32::gen-delayed-branch:false
// Generate separate simulators for each target
// :option:::multi-sim:true
// Models known by this simulator are defined below.
//
// When placing models in the instruction descriptions, please place
// them one per line, in the order given here.
// MIPS ISAs:
//
// Instructions and related functions for these models are included in
// this file.
:model:::mipsI:mips3000:
:model:::mipsII:mips6000:
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
:model:::mips32:mipsisa32:
:model:::mips32r2:mipsisa32r2:
:model:::mips64:mipsisa64:
:model:::mips64r2:mipsisa64r2:
// Vendor ISAs:
//
// Standard MIPS ISA instructions used for these models are listed here,
// as are functions needed by those standard instructions. Instructions
// which are model-dependent and which are not in the standard MIPS ISAs
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
:model:::vr5400:mips5400:
:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
//
// Instructions for the ASEs are in separate .igen files.
// ASEs add instructions on to a base ISA.
:model:::mips16:mips16: // m16.igen (and m16.dc)
:model:::mips16e:mips16e: // m16e.igen
:model:::mips3d:mips3d: // mips3d.igen
:model:::mdmx:mdmx: // mdmx.igen
:model:::dsp:dsp: // dsp.igen
:model:::dsp2:dsp2: // dsp2.igen
:model:::smartmips:smartmips: // smartmips.igen
// Vendor Extensions
//
// Instructions specific to these extensions are in separate .igen files.
// Extensions add instructions on to a base ISA.
:model:::sb1:sb1: // sb1.igen
// Pseudo instructions known by IGEN
:internal::::illegal:
{
SignalException (ReservedInstruction, 0);
}
// Pseudo instructions known by interp.c
// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
"rsvd <OP>"
{
SignalException (ReservedInstruction, instruction_0);
}
// Helper:
//
// Simulate a 32 bit delayslot instruction
//
:function:::address_word:delayslot32:address_word target
{
instruction_word delay_insn;
sim_events_slip (SD, 1);
DSPC = CIA;
CIA = CIA + 4; /* NOTE not mips16 */
STATE |= simDELAYSLOT;
delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
ENGINE_ISSUE_PREFIX_HOOK();
idecode_issue (CPU_, delay_insn, (CIA));
STATE &= ~simDELAYSLOT;
return target;
}
:function:::address_word:nullify_next_insn32:
{
sim_events_slip (SD, 1);
dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
return CIA + 8;
}
// Helper:
//
// Calculate an effective address given a base and an offset.
//
:function:::address_word:loadstore_ea:address_word base, address_word offset
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*vr4100:
*vr5000:
*r3900:
{
return base + offset;
}
:function:::address_word:loadstore_ea:address_word base, address_word offset
*mips64:
*mips64r2:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
/* If in user mode and UX is not set, use 32-bit compatibility effective
address computations as defined in the MIPS64 Architecture for
Programmers Volume III, Revision 0.95, section 4.9. */
if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
== (ksu_user << status_KSU_shift))
return (address_word)((signed32)base + (signed32)offset);
#endif
return base + offset;
}
// Helper:
//
// Check that a 32-bit register value is properly sign-extended.
// (See NotWordValue in ISA spec.)
//
:function:::int:not_word_value:unsigned_word value
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
{
#if WITH_TARGET_WORD_BITSIZE == 64
return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
#else
return 0;
#endif
}
// Helper:
//
// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
// theoretically portable code which invokes non-portable behaviour from
// running with no indication of the portability issue.
// (See definition of UNPREDICTABLE in ISA spec.)
//
:function:::void:unpredictable:
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
{
}
:function:::void:unpredictable:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
{
unpredictable_action (CPU, CIA);
}
// Helpers:
//
// Check that an access to a HI/LO register meets timing requirements
//
// In all MIPS ISAs,
//
// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
//
// The following restrictions exist for MIPS I - MIPS III:
//
// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
// in between makes MF UNPREDICTABLE. (2)
//
// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
// in between makes MF UNPREDICTABLE. (3)
//
// On the r3900, restriction (2) is not present, and restriction (3) is not
// present for multiplication.
//
// Unfortunately, there seems to be some confusion about whether the last
// two restrictions should apply to "MIPS IV" as well. One edition of
// the MIPS IV ISA says they do, but references in later ISA documents
// suggest they don't.
//
// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
// these restrictions, while others, like the VR5500, don't. To accomodate
// such differences, the MIPS IV and MIPS V version of these helper functions
// use auxillary routines to determine whether the restriction applies.
// check_mf_cycles:
//
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
// to check for restrictions (2) and (3) above.
//
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
itable[MY_INDEX].name,
new, (long) CIA,
(long) history->mf.cia);
return 0;
}
return 1;
}
// check_mt_hilo:
//
// Check for restriction (2) above (for ISAs/processors that have it),
// and record timestamps for restriction (1) above.
//
:function:::int:check_mt_hilo:hilo_history *history
*mipsI:
*mipsII:
*mipsIII:
*vr4100:
*vr5000:
{
signed64 time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
history->mt.timestamp = time;
history->mt.cia = CIA;
return ok;
}
:function:::int:check_mt_hilo:hilo_history *history
*mipsIV:
*mipsV:
{
signed64 time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
|| check_mf_cycles (SD_, history, time, "MT"));
history->mt.timestamp = time;
history->mt.cia = CIA;
return ok;
}
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*r3900:
{
signed64 time = sim_events_time (SD);
history->mt.timestamp = time;
history->mt.cia = CIA;
return 1;
}
// check_mf_hilo:
//
// Check for restriction (1) above, and record timestamps for
// restriction (2) and (3) above.
//
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
int ok = 1;
if (peer != NULL
&& peer->mt.timestamp > history->op.timestamp
&& history->mt.timestamp < history->op.timestamp
&& ! (history->mf.timestamp > history->op.timestamp
&& history->mf.timestamp < peer->mt.timestamp)
&& ! (peer->mf.timestamp > history->op.timestamp
&& peer->mf.timestamp < peer->mt.timestamp))
{
/* The peer has been written to since the last OP yet we have
not */
sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
itable[MY_INDEX].name,
(long) CIA,
(long) history->op.cia,
(long) peer->mt.cia);
ok = 0;
}
history->mf.timestamp = time;
history->mf.cia = CIA;
return ok;
}
// check_mult_hilo:
//
// Check for restriction (3) above (for ISAs/processors that have it)
// for MULT ops, and record timestamps for restriction (1) above.
//
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
*vr4100:
*vr5000:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mipsIV:
*mipsV:
{
signed64 time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return 1;
}
// check_div_hilo:
//
// Check for restriction (3) above (for ISAs/processors that have it)
// for DIV ops, and record timestamps for restriction (1) above.
//
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
*vr4100:
*vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsIV:
*mipsV:
{
signed64 time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips32r2:
*mips64:
*mips64r2:
{
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return 1;
}
// Helper:
//
// Check that the 64-bit instruction can currently be used, and signal
// a ReservedInstruction exception if not.
//
:function:::void:check_u64:instruction_word insn
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*vr5400:
*vr5500:
{
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
:function:::void:check_u64:instruction_word insn
*mips16e:
*mips64:
*mips64r2:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
if (UserMode && (SR & (status_UX|status_PX)) == 0)
SignalException (ReservedInstruction, insn);
#endif
}
//
// MIPS Architecture:
//
// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
//
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (GPR[RT]);
ALU32_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
if (NotWordValue (GPR[RS]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (EXTEND16 (IMMEDIATE));
ALU32_END (GPR[RT]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RT]);
}
:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
{
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
TRACE_ALU_RESULT (GPR[rt]);
}
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_addiu (SD_, RS, RT, IMMEDIATE);
}
:function:::void:do_addu:int rs, int rt, int rd
{
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_addu (SD_, RS, RT, RD);
}
:function:::void:do_and:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] & GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_and (SD_, RS, RT, RD);
}
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
GPR[RT] = GPR[RS] & IMMEDIATE;
TRACE_ALU_RESULT (GPR[RT]);
}
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
DELAY_SLOT (NIA + offset);
}
}
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] >= 0)
{
DELAY_SLOT (NIA + offset);
}
}
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
{
DELAY_SLOT (NIA + offset);
}
}
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] >= 0)
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] >= 0)
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] > 0)
{
DELAY_SLOT (NIA + offset);
}
}
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
{
DELAY_SLOT (NIA + offset);
}
}
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] <= 0)
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] < 0)
{
DELAY_SLOT (NIA + offset);
}
}
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
DELAY_SLOT (NIA + offset);
}
}
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
DELAY_SLOT (NIA + offset);
}
}
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
DELAY_SLOT (NIA + offset);
}
else
NULLIFY_NEXT_INSTRUCTION ();
}
000000,20.CODE,001101:SPECIAL:32::BREAK
"break %#lx<CODE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
/* Check for some break instruction which are reserved for use by the simulator. */
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
{
sim_engine_halt (SD, CPU, NULL, cia,
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
}
else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
{
if (STATE & simDELAYSLOT)
PC = cia - 4; /* reference the branch instruction */
else
PC = cia;
SignalException (BreakPoint, instruction_0);
}
else
{
/* If we get this far, we're not an instruction reserved by the sim. Raise
the exception. */
SignalException (BreakPoint, instruction_0);
}
}
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
"clo r<RD>, r<RS>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
if (RT != RD)
Unpredictable ();
if (NotWordValue (GPR[RS]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[RS]);
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[RD] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[RD]);
}
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
"clz r<RD>, r<RS>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
if (RT != RD)
Unpredictable ();
if (NotWordValue (GPR[RS]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[RS]);
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[RD] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[RD]);
}
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (GPR[RT]);
ALU64_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (EXTEND16 (IMMEDIATE));
ALU64_END (GPR[RT]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RT]);
}
:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
TRACE_ALU_RESULT (GPR[rt]);
}
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
:function:::void:do_daddu:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] + GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_daddu (SD_, RS, RT, RD);
}
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
*mips64r2:
*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
unsigned64 mask;
check_u64 (SD_, instruction_0);
if (RT != RD)
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[RS]);
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[RD] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[RD]);
}
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
*mips64r2:
*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
unsigned64 mask;
check_u64 (SD_, instruction_0);
if (RT != RD)
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[RS]);
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[RD] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_ddiv:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
signed64 n = GPR[rs];
signed64 d = GPR[rt];
signed64 hi;
signed64 lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
hi = 0;
}
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
{
lo = SIGNED64 (0x8000000000000000);
hi = 0;
}
else
{
lo = (n / d);
hi = (n % d);
}
HI = hi;
LO = lo;
}
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_ddiv (SD_, RS, RT);
}
:function:::void:do_ddivu:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
unsigned64 n = GPR[rs];
unsigned64 d = GPR[rt];
unsigned64 hi;
unsigned64 lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
hi = 0;
}
else
{
lo = (n / d);
hi = (n % d);
}
HI = hi;
LO = lo;
}
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
"ddivu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_ddivu (SD_, RS, RT);
}
:function:::void:do_div:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
signed32 n = GPR[rs];
signed32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
else if (n == SIGNED32 (0x80000000) && d == -1)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
else
{
LO = EXTEND32 (n / d);
HI = EXTEND32 (n % d);
}
}
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_div (SD_, RS, RT);
}
:function:::void:do_divu:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
unsigned32 n = GPR[rs];
unsigned32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
else
{
LO = EXTEND32 (n / d);
HI = EXTEND32 (n % d);
}
}
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_divu (SD_, RS, RT);
}
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
unsigned64 hi;
unsigned64 m00;
unsigned64 m01;
unsigned64 m10;
unsigned64 m11;
unsigned64 mid;
int sign;
unsigned64 op1 = GPR[rs];
unsigned64 op2 = GPR[rt];
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
/* make signed multiply unsigned */
sign = 0;
if (signed_p)
{
if ((signed64) op1 < 0)
{
op1 = - op1;
++sign;
}
if ((signed64) op2 < 0)
{
op2 = - op2;
++sign;
}
}
/* multiply out the 4 sub products */
m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
/* add the products */
mid = ((unsigned64) VH4_8 (m00)
+ (unsigned64) VL4_8 (m10)
+ (unsigned64) VL4_8 (m01));
lo = U8_4 (mid, m00);
hi = (m11
+ (unsigned64) VH4_8 (mid)
+ (unsigned64) VH4_8 (m01)
+ (unsigned64) VH4_8 (m10));
/* fix the sign */
if (sign & 1)
{
lo = -lo;
if (lo == 0)
hi = -hi;
else
hi = -hi - 1;
}
/* save the result HI/LO (and a gpr) */
LO = lo;
HI = hi;
if (rd != 0)
GPR[rd] = lo;
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_dmult:int rs, int rt, int rd
{
do_dmultx (SD_, rs, rt, rd, 1);
}
000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, RD);
}
:function:::void:do_dmultu:int rs, int rt, int rd
{
do_dmultx (SD_, rs, rt, rd, 0);
}
000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, RD);
}
:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
{
unsigned64 result;
y &= 63;
TRACE_ALU_INPUT2 (x, y);
result = ROTR64 (x, y);
TRACE_ALU_RESULT (result);
return result;
}
000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
"dror r<RD>, r<RT>, <SHIFT>"
*mips64r2:
*vr5400:
*vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
}
000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
"dror32 r<RD>, r<RT>, <SHIFT>"
*mips64r2:
*vr5400:
*vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
}
000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
"drorv r<RD>, r<RT>, r<RS>"
*mips64r2:
*vr5400:
*vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
}
:function:::void:do_dsll:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = GPR[rt] << shift;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsll (SD_, RT, RD, SHIFT);
}
000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = GPR[RT] << s;
TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_dsllv:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = GPR[rt] << s;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsllv (SD_, RS, RT, RD);
}
:function:::void:do_dsra:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = ((signed64) GPR[rt]) >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsra (SD_, RT, RD, SHIFT);
}
000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = ((signed64) GPR[RT]) >> s;
TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_dsrav:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = ((signed64) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
"dsrav r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsrav (SD_, RS, RT, RD);
}
:function:::void:do_dsrl:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = (unsigned64) GPR[rt] >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsrl (SD_, RT, RD, SHIFT);
}
000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = (unsigned64) GPR[RT] >> s;
TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_dsrlv:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = (unsigned64) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsrlv (SD_, RS, RT, RD);
}
000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
ALU64_SUB (GPR[RT]);
ALU64_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_dsubu:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] - GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
do_dsubu (SD_, RS, RT, RD);
}
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
current instruction */
address_word region = (NIA & MASK (63, 28));
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
/* NOTE: The region used is that of the delay slot and NOT the
current instruction */
address_word region = (NIA & MASK (63, 28));
GPR[31] = CIA + 8;
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
DELAY_SLOT (temp);
}
000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
"jalr.hb r<RS>":RD == 31
"jalr.hb r<RD>, r<RS>"
*mips32r2:
*mips64r2:
{
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
DELAY_SLOT (temp);
}
000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
DELAY_SLOT (GPR[RS]);
}
000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
"jr.hb r<RS>"
*mips32r2:
*mips64r2:
{
DELAY_SLOT (GPR[RS]);
}
:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
int uncached;
unsigned64 memval;
address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
}
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte));
}
:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
unsigned int word;
address_word paddr;
int uncached;
unsigned64 memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
unsigned_word lhs_mask;
unsigned_word temp;
vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
paddr = paddr & ~access;
/* compute where within the word/mem we are */
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
nr_lhs_bits = 8 * byte + 8;
nr_rhs_bits = 8 * access - 8 * byte;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
(long) ((unsigned64) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
if (word == 0)
{
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
temp = (memval << nr_rhs_bits);
}
else
{
/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
temp = (memval >> nr_lhs_bits);
}
lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
(long) ((unsigned64) memval >> 32), (long) memval,
(long) ((unsigned64) temp >> 32), (long) temp,
(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
(long) (rt >> 32), (long) rt); */
return rt;
}
:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
int uncached;
unsigned64 memval;
address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
paddr = paddr & ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
(long) paddr, byte, (long) paddr, (long) memval); */
{
unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
rt &= ~screen;
rt |= (memval >> (8 * byte)) & screen;
}
return rt;
}
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
}
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
}
110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
"ld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
"ldl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
"ldr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
}
110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
"ll r<RT>, <OFFSET>(r<BASE>)"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
}
else
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int shift = 2;
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
byte = ((vaddr & mask) ^ (bigend << shift));
GPR[RT] = EXTEND32 (memval >> (8 * byte));
LLBIT = 1;
}
}
}
}
110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
"lld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
check_u64 (SD_, instruction_0);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
}
else
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
GPR[RT] = memval;
LLBIT = 1;
}
}
}
}
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
TRACE_ALU_INPUT1 (IMMEDIATE);
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
TRACE_ALU_RESULT (GPR[RT]);
}
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
"lwu r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
"madd r<RS>, r<RT>"
*mips32:
*mips64:
*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
"madd r<RS>, r<RT>":AC == 0
"madd ac<AC>, r<RS>, r<RT>"
*mips32r2:
*mips64r2:
*dsp2:
{
signed64 temp;
if (AC == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
DSPLO(AC) = EXTEND32 (temp);
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
if (AC == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
"maddu r<RS>, r<RT>":AC == 0
"maddu ac<AC>, r<RS>, r<RT>"
*mips32r2:
*mips64r2:
*dsp2:
{
unsigned64 temp;
if (AC == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
if (AC == 0)
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
DSPLO(AC) = EXTEND32 (temp);
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
if (AC == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_mfhi:int rd
{
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT1 (HI);
GPR[rd] = HI;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
*mips32:
*mips64:
{
do_mfhi (SD_, RD);
}
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>":AC == 0
"mfhi r<RD>, ac<AC>"
*mips32r2:
*mips64r2:
*dsp:
{
if (AC == 0)
do_mfhi (SD_, RD);
else
GPR[RD] = DSPHI(AC);
}
:function:::void:do_mflo:int rd
{
check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
TRACE_ALU_INPUT1 (LO);
GPR[rd] = LO;
TRACE_ALU_RESULT (GPR[rd]);
}
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
*mips32:
*mips64:
{
do_mflo (SD_, RD);
}
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>":AC == 0
"mflo r<RD>, ac<AC>"
*mips32r2:
*mips64r2:
*dsp:
{
if (AC == 0)
do_mflo (SD_, RD);
else
GPR[RD] = DSPLO(AC);
}
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr5000:
{
if (GPR[RT] != 0)
{
GPR[RD] = GPR[RS];
TRACE_ALU_RESULT (GPR[RD]);
}
}
000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr5000:
{
if (GPR[RT] == 0)
{
GPR[RD] = GPR[RS];
TRACE_ALU_RESULT (GPR[RD]);
}
}
011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
"msub r<RS>, r<RT>"
*mips32:
*mips64:
*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
"msub r<RS>, r<RT>":AC == 0
"msub ac<AC>, r<RS>, r<RT>"
*mips32r2:
*mips64r2:
*dsp2:
{
signed64 temp;
if (AC == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
DSPLO(AC) = EXTEND32 (temp);
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
if (AC == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
"msubu r<RS>, r<RT>":AC == 0
"msubu ac<AC>, r<RS>, r<RT>"
*mips32r2:
*mips64r2:
*dsp2:
{
unsigned64 temp;
if (AC == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
DSPLO(AC) = EXTEND32 (temp);
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
if (AC == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
*mips32:
*mips64:
{
check_mt_hilo (SD_, HIHISTORY);
HI = GPR[RS];
}
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
"mthi r<RS>":AC == 0
"mthi r<RS>, ac<AC>"
*mips32r2:
*mips64r2:
*dsp:
{
if (AC == 0)
check_mt_hilo (SD_, HIHISTORY);
DSPHI(AC) = GPR[RS];
}
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
*mips32:
*mips64:
{
check_mt_hilo (SD_, LOHISTORY);
LO = GPR[RS];
}
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
"mtlo r<RS>":AC == 0
"mtlo r<RS>, ac<AC>"
*mips32r2:
*mips64r2:
*dsp:
{
if (AC == 0)
check_mt_hilo (SD_, LOHISTORY);
DSPLO(AC) = GPR[RS];
}
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
prod = (((signed64)(signed32) GPR[RS])
* ((signed64)(signed32) GPR[RT]));
GPR[RD] = EXTEND32 (VL4_8 (prod));
TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_mult:int rs, int rt, int rd
{
signed64 prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((signed64)(signed32) GPR[rs])
* ((signed64)(signed32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
ACX = 0; /* SmartMIPS */
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":AC == 0
"mult ac<AC>, r<RS>, r<RT>"
*mips32r2:
*mips64r2:
*dsp2:
{
signed64 prod;
if (AC == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
prod = ((signed64)(signed32) GPR[RS])
* ((signed64)(signed32) GPR[RT]);
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
if (AC == 0)
{
ACX = 0; /* SmartMIPS */
TRACE_ALU_RESULT2 (HI, LO);
}
}
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
*r3900:
{
do_mult (SD_, RS, RT, RD);
}
:function:::void:do_multu:int rs, int rt, int rd
{
unsigned64 prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((unsigned64)(unsigned32) GPR[rs])
* ((unsigned64)(unsigned32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":AC == 0
"multu r<RS>, r<RT>"
*mips32r2:
*mips64r2:
*dsp2:
{
unsigned64 prod;
if (AC == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
prod = ((unsigned64)(unsigned32) GPR[RS])
* ((unsigned64)(unsigned32) GPR[RT]);
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
if (AC == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
*r3900:
{
do_multu (SD_, RS, RT, RD);
}
:function:::void:do_nor:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = ~ (GPR[rs] | GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_nor (SD_, RS, RT, RD);
}
:function:::void:do_or:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = (GPR[rs] | GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_or (SD_, RS, RT, RD);
}
:function:::void:do_ori:int rs, int rt, unsigned immediate
{
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = (GPR[rs] | immediate);
TRACE_ALU_RESULT (GPR[rt]);
}
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_ori (SD_, RS, RT, IMMEDIATE);
}
110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
"pref <HINT>, <OFFSET>(r<BASE>)"
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr5000:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
}
}
}
:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
{
unsigned64 result;
y &= 31;
TRACE_ALU_INPUT2 (x, y);
result = EXTEND32 (ROTR32 (x, y));
TRACE_ALU_RESULT (result);
return result;
}
000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
"ror r<RD>, r<RT>, <SHIFT>"
*mips32r2:
*mips64r2:
*smartmips:
*vr5400:
*vr5500:
{
GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
}
000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
"rorv r<RD>, r<RT>, r<RS>"
*mips32r2:
*mips64r2:
*smartmips:
*vr5400:
*vr5500:
{
GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
}
:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
int uncached;
unsigned64 memval;
address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
}
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
memval = (word << (8 * byte));
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
}
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
unsigned int word;
address_word paddr;
int uncached;
unsigned64 memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
paddr = paddr & ~access;
/* compute where within the word/mem we are */
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
nr_lhs_bits = 8 * byte + 8;
nr_rhs_bits = 8 * access - 8 * byte;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
(long) ((unsigned64) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
if (word == 0)
{
memval = (rt >> nr_rhs_bits);
}
else
{
memval = (rt << nr_lhs_bits);
}
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
(long) ((unsigned64) rt >> 32), (long) rt,
(long) ((unsigned64) memval >> 32), (long) memval); */
StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
}
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
int uncached;
unsigned64 memval;
address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
paddr &= ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
memval = (rt << (byte * 8));
StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
}
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
"sc r<RT>, <OFFSET>(r<BASE>)"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
{
unsigned32 instruction = instruction_0;
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
}
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
unsigned64 mask = (