| commit | f664005a2f69486aded87f0a65b623a4bf156c4c | [log] [tgz] |
|---|---|---|
| author | Milad Fa <mfarazma@redhat.com> | Fri Dec 11 17:57:37 2020 |
| committer | Commit Bot <commit-bot@chromium.org> | Fri Dec 11 18:38:41 2020 |
| tree | 7a0655467f35e6755edad7d1c58deaa24ad53908 | |
| parent | 6dc56052ec2af857882b7bb3cb5dc3b8b8d1f4da [diff] |
PPC: [disasm] Introduce Simd128 vector registers PPC has a set of 64 Vector Registers called VSX. The lower 32 of them are shared with Floating Point register (only 64 bit of the registers are used for FP operations). The upper 32 registers are VR registers which are only used for VMX Vector operations. VSX Vector operations have the option to use the lower 32 or upper 32 registers using the TX bit set on the instructions. VMX operations only use the upper 32 registers. In V8 we always set the VSX TX bit to "1" to make sure all the vector operations take place on the upper 32 registers. Change-Id: Ib3ea03254cbdc9547c3b698fe19c0c6b28138741 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2585260 Commit-Queue: Milad Fa <mfarazma@redhat.com> Reviewed-by: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#71722}
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