| /* SPDX-License-Identifier: BSD-3-Clause |
| * |
| * Copyright 2020 The ChromiumOS Authors |
| */ |
| |
| /dts-v1/; |
| #include <st/h7/stm32h743Xi.dtsi> |
| #include <st/h7/stm32h743zitx-pinctrl.dtsi> |
| |
| / { |
| model = "Google Chameleon"; |
| compatible = "st,stm32h743zi", "st,stm32h743"; |
| |
| chosen { |
| zephyr,console = &usart1; |
| zephyr,shell-uart = &usart1; |
| zephyr,sram = &sram0; |
| zephyr,flash = &flash0; |
| }; |
| |
| /* |
| * Note that the GPIO flags (the 0 at the end of the `gpios` tuple) |
| * are ignored by the I/O driver. All flags for GPIOs are specified |
| * in io.c. |
| */ |
| leds { |
| compatible = "gpio-leds"; |
| power_good_led { |
| gpios = <&gpiob 14 0>; |
| label = "POWER_GOOD"; |
| }; |
| }; |
| |
| sd-mux { |
| compatible = "gpio-keys"; |
| |
| sd_mux_sel { |
| gpios = <&gpioe 0 0>; |
| label = "SD_MUX_SEL"; |
| }; |
| |
| sd_mux_en_l { |
| gpios = <&gpioe 1 0>; |
| label = "SD_MUX_EN_L"; |
| }; |
| |
| usd_pwr_sel { |
| gpios = <&gpiob 13 0>; |
| label = "USD_PWR_SEL"; |
| }; |
| |
| usd_pwr_en { |
| gpios = <&gpioe 4 0>; |
| label = "USD_PWR_EN"; |
| }; |
| |
| usd_cd_det { |
| gpios = <&gpioe 2 0>; |
| label = "USD_CD_DET"; |
| }; |
| }; |
| |
| sysmon { |
| compatible = "gpio-keys"; |
| |
| sysmon_sel { |
| gpios = <&gpioc 6 0>; |
| label = "SYSMON_SEL"; |
| }; |
| }; |
| |
| fpga { |
| compatible = "gpio-keys"; |
| |
| pwr_en { |
| gpios = <&gpioc 7 0>; |
| label = "SOM_PWR_EN"; |
| }; |
| |
| pwr_good { |
| gpios = <&gpioc 8 0>; |
| label = "SOM_PWR_GOOD"; |
| }; |
| |
| boot_mode1 { |
| gpios = <&gpiod 1 0>; |
| label = "SOM_BOOT_MODE1"; |
| }; |
| |
| boot_mode0 { |
| gpios = <&gpiod 0 0>; |
| label = "SOM_BOOT_MODE0"; |
| }; |
| |
| por_l_load_l { |
| gpios = <&gpiob 1 0>; |
| label = "SOM_POR_L_LOAD_L"; |
| }; |
| |
| fpga_done { |
| gpios = <&gpiob 0 0>; |
| label = "SOM_FPGA_DONE"; |
| }; |
| |
| fpga_prot { |
| gpios = <&gpioe 13 0>; |
| label = "FPGA_PROT"; |
| }; |
| |
| fpga_comm0 { |
| gpios = <&gpioe 14 0>; |
| label = "FPGA_COMM0"; |
| }; |
| }; |
| |
| misc { |
| compatible = "gpio-keys"; |
| |
| tp126 { |
| gpios = <&u78 11 0>; |
| label = "TP126"; |
| }; |
| |
| tp125 { |
| gpios = <&u78 12 0>; |
| label = "TP125"; |
| }; |
| |
| board_version_2 { |
| gpios = <&u78 15 0>; |
| label = "BOARD_VERSION_2"; |
| }; |
| |
| board_version_1 { |
| gpios = <&u78 14 0>; |
| label = "BOARD_VERSION_1"; |
| }; |
| |
| board_version_0 { |
| gpios = <&u78 13 0>; |
| label = "BOARD_VERSION_0"; |
| }; |
| }; |
| |
| i2c-switch { |
| compatible = "gpio-keys"; |
| |
| exp_reset { |
| gpios = <&gpiob 8 0>; |
| label = "I2C1_EXP_RESET_L"; |
| }; |
| |
| exp_irq { |
| gpios = <&gpiob 5 0>; |
| label = "I2C1_SMBA"; |
| }; |
| }; |
| |
| videomux { |
| compatible = "gpio-keys"; |
| |
| /* |
| * I/Os are initially set to so that none of the signals are |
| * connected to either the FPGA MGTs or the HDMI Receiver. |
| */ |
| gp213_it68051p1_ch_sel { |
| /* GPU_SEL on U18 */ |
| gpios = <&gpiog 1 0>; |
| label = "GP213_IT68051P1_CH_SEL"; |
| }; |
| |
| dp1_ps8468_sw { |
| /* SW on U3 */ |
| gpios = <&gpiog 12 0>; |
| label = "DP1_PS8468_SW"; |
| }; |
| |
| hdmi1_gp213_ch_sel { |
| /* GPU_SEL on U10 */ |
| gpios = <&gpiog 0 0>; |
| label = "HDMI1_GP213_CH_SEL"; |
| }; |
| |
| somp1_mode_sel { |
| /* GPU_SEL on U11 */ |
| gpios = <&gpiog 4 0>; |
| label = "SOMP1_MODE_SEL"; |
| }; |
| |
| /* |
| * Note that all of the channels are designated 1&2 except for |
| * the IT68051, which has ports 1 (channel 1 on the other |
| * switches) and 0 (channel 2 on the other switches). |
| */ |
| gp213_it68051p0_ch_sel { |
| /* GPU_SEL on U31 */ |
| gpios = <&gpiog 3 0>; |
| label = "GP213_IT68051P0_CH_SEL"; |
| }; |
| |
| dp2_ps8468_sw { |
| /* SW on U22 */ |
| gpios = <&gpiog 13 0>; |
| label = "DP2_PS8468_SW"; |
| }; |
| |
| hdmi2_gp213_ch_sel { |
| /* GPU_SEL on U29 */ |
| gpios = <&gpiog 2 0>; |
| label = "HDMI2_GP213_CH_SEL"; |
| }; |
| |
| somp2_mode_sel { |
| /* GPU_SEL on U14 */ |
| gpios = <&gpiog 5 0>; |
| label = "SOMP2_MODE_SEL"; |
| }; |
| |
| /* |
| * Reset lines for the PS8468 demuxes. |
| */ |
| dp1_ps8468_rst_l { |
| /* RESETN on U3 */ |
| gpios = <&gpiof 5 0>; |
| label = "DP1_PS8468_RST_L"; |
| }; |
| |
| dp2_ps8468_rst_l { |
| /* RESETN on U22 */ |
| gpios = <&gpiof 11 0>; |
| label = "DP2_PS8468_RST_L"; |
| }; |
| |
| /* |
| * Reset lines for the MCDP2900 DP->HDMI converters. |
| */ |
| dp1_hdmi_rst_l { |
| /* EX_RESETN on U17 */ |
| gpios = <&gpiog 10 0>; |
| label = "DP1_HDMI_RST_L"; |
| }; |
| |
| dp2_hdmi_rst_l { |
| /* EX_RESETN on U30 */ |
| gpios = <&gpiog 11 0>; |
| label = "DP2_HDMI_RST_L"; |
| }; |
| }; |
| |
| it68051 { |
| compatible = "gpio-keys"; |
| |
| it68051_en { |
| gpios = <&gpioe 7 0>; |
| label = "IT68051_EN"; |
| }; |
| |
| it68051p0_pwr_det { |
| gpios = <&gpiof 0 0>; |
| label = "IT68051P0_PWR_DET"; |
| }; |
| |
| it68051p1_pwr_det { |
| gpios = <&gpiof 1 0>; |
| label = "IT68051P1_PWR_DET"; |
| }; |
| |
| it68051_rst_l { |
| gpios = <&gpiof 2 0>; |
| label = "IT68051_RST_L"; |
| }; |
| |
| gp213_it68051p1_hpd { |
| gpios = <&gpioe 15 0>; |
| label = "GP213_IT68051P1_HPD"; |
| }; |
| |
| i2c2_int_l { |
| gpios = <&gpiob 12 0>; |
| label = "I2C2_INT_L"; |
| }; |
| }; |
| |
| hotplug { |
| compatible = "gpio-keys"; |
| |
| hdmi1_pp3300 { |
| gpios = <&gpioe 9 0>; |
| label = "HDMI1_PP3300"; |
| }; |
| |
| hdmi2_pp3300 { |
| gpios = <&gpioe 10 0>; |
| label = "HDMI2_PP3300"; |
| }; |
| |
| /* |
| * DP1 and DP2 HPD sense lines. There are two downstream HPD |
| * signals for the PS8468. When either one is asserted, the |
| * PS8468 wakes up and asserts its HPD_SRC. These GPIOs are |
| * connected to HPD_SRC, and let us know that the PS8468 is |
| * awake and we can configure the 8468 over the I2C bus. |
| */ |
| dp1_mcu_hpd { |
| gpios = <&gpioe 11 0>; |
| label = "DP1_MCU_HPD"; |
| }; |
| |
| dp2_mcu_hpd { |
| gpios = <&gpioe 12 0>; |
| label = "DP2_MCU_HPD"; |
| }; |
| |
| dp_in_pwr_en { |
| gpios = <&u79 15 0>; |
| label = "DP_IN_PWR_EN"; |
| }; |
| }; |
| |
| dp_cfg { |
| compatible = "gpio-keys"; |
| |
| /* |
| * Most of these are GPIO_INPUT to allow the pull-up/pull-down |
| * resistors to apply the desired level. We only want to actively |
| * drive the MODE pins to select manual mux control by the SW pin. |
| */ |
| dp1_ps8468_mode { |
| gpios = <&u77 0 0>; |
| label = "DP1_PS8468_MODE"; |
| }; |
| |
| dp1_ps8468_cfg0 { |
| gpios = <&u77 1 0>; |
| label = "DP1_PS8468_CFG0"; |
| }; |
| |
| dp1_ps8468_cfg1 { |
| gpios = <&u77 2 0>; |
| label = "DP1_PS8468_CFG1"; |
| }; |
| |
| dp1_ps8468_cfg2 { |
| gpios = <&u77 3 0>; |
| label = "DP1_PS8468_CFG2"; |
| }; |
| |
| dp1_ps8468_cfg3 { |
| gpios = <&u77 4 0>; |
| label = "DP1_PS8468_CFG3"; |
| }; |
| |
| dp1_ps8468_cfg4 { |
| gpios = <&u77 5 0>; |
| label = "DP1_PS8468_CFG4"; |
| }; |
| |
| dp1_ps8468_eq0 { |
| gpios = <&u77 6 0>; |
| label = "DP1_PS8468_EQ0"; |
| }; |
| |
| dp1_ps8468_eq1 { |
| gpios = <&u77 7 0>; |
| label = "DP1_PS8468_EQ1"; |
| }; |
| |
| dp2_ps8468_mode { |
| gpios = <&u77 8 0>; |
| label = "DP2_PS8468_MODE"; |
| }; |
| |
| dp2_ps8468_cfg0 { |
| gpios = <&u77 9 0>; |
| label = "DP2_PS8468_CFG0"; |
| }; |
| |
| dp2_ps8468_cfg1 { |
| gpios = <&u77 10 0>; |
| label = "DP2_PS8468_CFG1"; |
| }; |
| |
| dp2_ps8468_cfg2 { |
| gpios = <&u77 11 0>; |
| label = "DP2_PS8468_CFG2"; |
| }; |
| |
| dp2_ps8468_cfg3 { |
| gpios = <&u77 12 0>; |
| label = "DP2_PS8468_CFG3"; |
| }; |
| |
| dp2_ps8468_cfg4 { |
| gpios = <&u77 13 0>; |
| label = "DP2_PS8468_CFG4"; |
| }; |
| |
| dp2_ps8468_eq0 { |
| gpios = <&u77 14 0>; |
| label = "DP2_PS8468_EQ0"; |
| }; |
| |
| dp2_ps8468_eq1 { |
| gpios = <&u77 15 0>; |
| label = "DP2_PS8468_EQ1"; |
| }; |
| |
| dp1_out_sw { |
| gpios = <&u78 0 0>; |
| label = "DP1_OUT_SW"; |
| }; |
| |
| dp1_out_pd_l { |
| gpios = <&u78 8 0>; |
| label = "DP1_OUT_PD_L"; |
| }; |
| |
| dp1_out_mode { |
| gpios = <&u78 9 0>; |
| label = "DP1_OUT_MODE"; |
| }; |
| |
| dp2_out_sw { |
| gpios = <&u79 0 0>; |
| label = "DP2_OUT_SW"; |
| }; |
| |
| dp2_out_pd_l { |
| gpios = <&u79 8 0>; |
| label = "DP2_OUT_PD_L"; |
| }; |
| |
| dp2_out_mode { |
| gpios = <&u79 9 0>; |
| label = "DP2_OUT_MODE"; |
| }; |
| }; |
| |
| pcie { |
| compatible = "gpio-keys"; |
| |
| pcie_perst { |
| gpios = <&gpiog 14 0>; |
| label = "PCIE_PERST"; |
| }; |
| |
| pcie_wake_l_b { |
| gpios = <&gpiog 15 0>; |
| label = "PCIE_WAKE_L_B"; |
| }; |
| |
| pcie_rsvd1 { |
| gpios = <&gpioc 9 0>; |
| label = "PCIE_RSVD1"; |
| }; |
| |
| pcie_rsvd2 { |
| gpios = <&gpiod 3 0>; |
| label = "PCIE_RSVD2"; |
| }; |
| |
| pcie_rsvd3 { |
| gpios = <&gpiod 4 0>; |
| label = "PCIE_RSVD3"; |
| }; |
| |
| pcie_rsvd4 { |
| gpios = <&gpiod 5 0>; |
| label = "PCIE_RSVD4"; |
| }; |
| |
| pcie_ref_clk_sel { |
| gpios = <&gpiod 8 0>; |
| label = "PCIE_REF_CLK_SEL"; |
| }; |
| |
| som_a34 { |
| gpios = <&gpioe 8 0>; |
| label = "SOM_A34"; |
| }; |
| |
| som_a21 { |
| gpios = <&gpiof 13 0>; |
| label = "SOM_A21"; |
| }; |
| |
| som_a98 { |
| gpios = <&gpiof 14 0>; |
| label = "SOM_A98"; |
| }; |
| |
| som_pcie_perst_l { |
| gpios = <&gpiof 15 0>; |
| label = "SOM_PCIE_PERST_L"; |
| }; |
| }; |
| }; |
| |
| &clk_hse { |
| clock-frequency = <DT_FREQ_M(8)>; |
| status = "okay"; |
| }; |
| |
| &pll { |
| div-m = <1>; |
| mul-n = <24>; |
| div-p = <2>; |
| div-q = <4>; |
| div-r = <2>; |
| clocks = <&clk_hse>; |
| status = "okay"; |
| }; |
| |
| &rcc { |
| clocks = <&pll>; |
| clock-frequency = <DT_FREQ_M(96)>; |
| d1cpre = <1>; |
| hpre = <1>; |
| d1ppre = <2>; |
| d2ppre1 = <2>; |
| d2ppre2 = <2>; |
| d3ppre = <2>; |
| }; |
| |
| &usart1 { |
| pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; |
| pinctrl-names = "default"; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &usart2 { |
| pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; |
| pinctrl-names = "default"; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-0 = <&uart4_tx_pc10 &uart4_rx_pc11>; |
| pinctrl-names = "default"; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &uart5 { |
| pinctrl-0 = <&uart5_tx_pc12 &uart5_rx_pd2>; |
| pinctrl-names = "default"; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &spi1 { |
| pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &i2c2 { |
| pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| |
| /* U77 I/O expander, config signals for PS8468 */ |
| u77: pca95xx@20 { |
| compatible = "nxp,pca95xx"; |
| reg = <0x20>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| /* U78 I/O expander, DP1 OUT config signals, plus misc I/O */ |
| u78: pca95xx@21 { |
| compatible = "nxp,pca95xx"; |
| reg = <0x21>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| /* U79 I/O expander DP2 OUT config, HDMI input reset, DP IN power */ |
| u79: pca95xx@23 { |
| compatible = "nxp,pca95xx"; |
| reg = <0x23>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| /* I2C address for the IT68051 |
| * |
| * Note that the IT68051 documentation uses 8-bit addresses |
| * (ITE docs say that the HDMI block is address 0x90) but all of |
| * our code uses 7-bit addresses. |
| */ |
| it68051_hdmi: it68051@48 { |
| compatible = "i2c-device"; |
| label = "IT68051_HDMI"; |
| reg = <0x48>; |
| }; |
| |
| it68051_edid: it68051@54 { |
| compatible = "i2c-device"; |
| label = "IT68051_EDID"; |
| reg = <0x54>; |
| }; |
| }; |
| |
| &adc1 { |
| pinctrl-0 = <&adc1_inp16_pa0 &adc1_inp17_pa1 &adc1_inp10_pc0 |
| &adc1_inp11_pc1 &adc1_inp4_pc4 &adc1_inp8_pc5 |
| &adc1_inp6_pf12>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| st,adc-clock-source = <SYNC>; |
| st,adc-prescaler = <4>; /* 96MHz AHB / 4 = 24MHz */ |
| }; |
| |
| &adc3 { |
| /* These ADC inputs are only available on ADC3 */ |
| pinctrl-0 = <&adc3_inp0_pc2_c &adc3_inp1_pc3_c &adc3_inp5_pf3 |
| &adc3_inp8_pf6 &adc3_inp3_pf7 &adc3_inp7_pf8 |
| &adc3_inp2_pf9 &adc3_inp6_pf10>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| st,adc-clock-source = <SYNC>; |
| st,adc-prescaler = <4>; /* 96MHz AHB / 4 = 24MHz */ |
| }; |
| |
| &timers1 { |
| status = "okay"; |
| }; |
| |
| &systick { |
| status = "okay"; |
| }; |
