board/poppy: Add support for cr50 SPI TPM
Add support for cr50 SPI TPM, but do not enable it right
away. Following options need to be enabled in order to test SPI TPM on
poppy:
CONFIG_TPM2_MODE
CONFIG_DRIVER_TPM_SPI
BUG=b:36873582
BRANCH=None
TEST=Verified that depthcharge is able to talk to cr50 over SPI.
Change-Id: I0eee60e7973cf216e509cfb7d98ea5d014f12bee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474116
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/board/poppy/defconfig b/board/poppy/defconfig
index e83ab69..6c05fe4 100644
--- a/board/poppy/defconfig
+++ b/board/poppy/defconfig
@@ -27,6 +27,7 @@
CONFIG_DRIVER_INPUT_MKBP=y
CONFIG_DRIVER_INPUT_MKBP_KEYMATRIX_STANDARD=y
CONFIG_DRIVER_INPUT_USB=y
+CONFIG_DRIVER_BUS_SPI_INTEL_GSPI=y
CONFIG_DRIVER_SOUND_GPIO_I2S=y
CONFIG_DRIVER_SOUND_MAX98927=y
CONFIG_DRIVER_SOUND_ROUTE=y
diff --git a/src/board/poppy/board.c b/src/board/poppy/board.c
index 38dd910..cc0a451 100644
--- a/src/board/poppy/board.c
+++ b/src/board/poppy/board.c
@@ -23,8 +23,10 @@
#include "base/init_funcs.h"
#include "base/list.h"
+#include "config.h"
#include "drivers/bus/i2c/designware.h"
#include "drivers/bus/i2c/i2c.h"
+#include "drivers/bus/spi/intel_gspi.h"
#include "drivers/ec/cros/lpc.h"
#include "drivers/flash/flash.h"
#include "drivers/flash/memmapped.h"
@@ -37,6 +39,7 @@
#include "drivers/sound/route.h"
#include "drivers/storage/blockdev.h"
#include "drivers/storage/sdhci.h"
+#include "drivers/tpm/spi.h"
#include "vboot/util/commonparams.h"
#include "vboot/util/flag.h"
@@ -50,10 +53,37 @@
#define EMMC_CLOCK_MAX 200000000
#define SD_CLOCK_MAX 52000000
+static int cr50_irq_status(void)
+{
+ return skylake_get_gpe(GPE0_DW2_00);
+}
+
+static void poppy_setup_tpm(void)
+{
+ if (!IS_ENABLED(CONFIG_DRIVER_TPM_SPI))
+ return;
+
+ /* SPI TPM */
+ const IntelGspiSetupParams gspi0_params = {
+ .dev = PCI_DEV(0, 0x1e, 2),
+ .cs_polarity = SPI_POLARITY_LOW,
+ .clk_phase = SPI_CLOCK_PHASE_FIRST,
+ .clk_polarity = SPI_POLARITY_LOW,
+ .ref_clk_mhz = 120,
+ .gspi_clk_mhz = 1,
+ };
+
+ tpm_set_ops(&new_tpm_spi(new_intel_gspi(&gspi0_params),
+ cr50_irq_status)->ops);
+}
+
static int board_setup(void)
{
sysinfo_install_flags(new_skylake_gpio_input_from_coreboot);
+ /* TPM */
+ poppy_setup_tpm();
+
/* Chrome EC (eSPI) */
CrosEcLpcBus *cros_ec_lpc_bus =
new_cros_ec_lpc_bus(CROS_EC_LPC_BUS_GENERIC);
