| @ LDC group relocation tests. |
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| .text |
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| @ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L |
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| .macro ldctest load store |
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| \load 0, c0, [r0, #:pc_g0:(f + 0x214)] |
| \load 0, c0, [r0, #:pc_g1:(f + 0x214)] |
| \load 0, c0, [r0, #:pc_g2:(f + 0x214)] |
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| \load 0, c0, [r0, #:sb_g0:(f + 0x214)] |
| \load 0, c0, [r0, #:sb_g1:(f + 0x214)] |
| \load 0, c0, [r0, #:sb_g2:(f + 0x214)] |
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| \store 0, c0, [r0, #:pc_g0:(f + 0x214)] |
| \store 0, c0, [r0, #:pc_g1:(f + 0x214)] |
| \store 0, c0, [r0, #:pc_g2:(f + 0x214)] |
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| \store 0, c0, [r0, #:sb_g0:(f + 0x214)] |
| \store 0, c0, [r0, #:sb_g1:(f + 0x214)] |
| \store 0, c0, [r0, #:sb_g2:(f + 0x214)] |
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| \load 0, c0, [r0, #:pc_g0:(f - 0x214)] |
| \load 0, c0, [r0, #:pc_g1:(f - 0x214)] |
| \load 0, c0, [r0, #:pc_g2:(f - 0x214)] |
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| \load 0, c0, [r0, #:sb_g0:(f - 0x214)] |
| \load 0, c0, [r0, #:sb_g1:(f - 0x214)] |
| \load 0, c0, [r0, #:sb_g2:(f - 0x214)] |
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| \store 0, c0, [r0, #:pc_g0:(f - 0x214)] |
| \store 0, c0, [r0, #:pc_g1:(f - 0x214)] |
| \store 0, c0, [r0, #:pc_g2:(f - 0x214)] |
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| \store 0, c0, [r0, #:sb_g0:(f - 0x214)] |
| \store 0, c0, [r0, #:sb_g1:(f - 0x214)] |
| \store 0, c0, [r0, #:sb_g2:(f - 0x214)] |
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| .endm |
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| ldctest ldc stc |
| ldctest ldcl stcl |
| ldctest ldc2 stc2 |
| ldctest ldc2l stc2l |
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| @ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP |
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| .fpu fpa |
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| .macro fpa_test load store |
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| \load f0, [r0, #:pc_g0:(f + 0x214)] |
| \load f0, [r0, #:pc_g1:(f + 0x214)] |
| \load f0, [r0, #:pc_g2:(f + 0x214)] |
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| \load f0, [r0, #:sb_g0:(f + 0x214)] |
| \load f0, [r0, #:sb_g1:(f + 0x214)] |
| \load f0, [r0, #:sb_g2:(f + 0x214)] |
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| \store f0, [r0, #:pc_g0:(f + 0x214)] |
| \store f0, [r0, #:pc_g1:(f + 0x214)] |
| \store f0, [r0, #:pc_g2:(f + 0x214)] |
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| \store f0, [r0, #:sb_g0:(f + 0x214)] |
| \store f0, [r0, #:sb_g1:(f + 0x214)] |
| \store f0, [r0, #:sb_g2:(f + 0x214)] |
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| \load f0, [r0, #:pc_g0:(f - 0x214)] |
| \load f0, [r0, #:pc_g1:(f - 0x214)] |
| \load f0, [r0, #:pc_g2:(f - 0x214)] |
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| \load f0, [r0, #:sb_g0:(f - 0x214)] |
| \load f0, [r0, #:sb_g1:(f - 0x214)] |
| \load f0, [r0, #:sb_g2:(f - 0x214)] |
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| \store f0, [r0, #:pc_g0:(f - 0x214)] |
| \store f0, [r0, #:pc_g1:(f - 0x214)] |
| \store f0, [r0, #:pc_g2:(f - 0x214)] |
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| \store f0, [r0, #:sb_g0:(f - 0x214)] |
| \store f0, [r0, #:sb_g1:(f - 0x214)] |
| \store f0, [r0, #:sb_g2:(f - 0x214)] |
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| .endm |
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| fpa_test ldfs stfs |
| fpa_test ldfd stfd |
| fpa_test ldfe stfe |
| fpa_test ldfp stfp |
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| @ FLDS/FSTS |
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| .fpu vfp |
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| .macro vfp_test load store reg |
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| \load \reg, [r0, #:pc_g0:(f + 0x214)] |
| \load \reg, [r0, #:pc_g1:(f + 0x214)] |
| \load \reg, [r0, #:pc_g2:(f + 0x214)] |
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| \load \reg, [r0, #:sb_g0:(f + 0x214)] |
| \load \reg, [r0, #:sb_g1:(f + 0x214)] |
| \load \reg, [r0, #:sb_g2:(f + 0x214)] |
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| \store \reg, [r0, #:pc_g0:(f + 0x214)] |
| \store \reg, [r0, #:pc_g1:(f + 0x214)] |
| \store \reg, [r0, #:pc_g2:(f + 0x214)] |
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| \store \reg, [r0, #:sb_g0:(f + 0x214)] |
| \store \reg, [r0, #:sb_g1:(f + 0x214)] |
| \store \reg, [r0, #:sb_g2:(f + 0x214)] |
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| \load \reg, [r0, #:pc_g0:(f - 0x214)] |
| \load \reg, [r0, #:pc_g1:(f - 0x214)] |
| \load \reg, [r0, #:pc_g2:(f - 0x214)] |
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| \load \reg, [r0, #:sb_g0:(f - 0x214)] |
| \load \reg, [r0, #:sb_g1:(f - 0x214)] |
| \load \reg, [r0, #:sb_g2:(f - 0x214)] |
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| \store \reg, [r0, #:pc_g0:(f - 0x214)] |
| \store \reg, [r0, #:pc_g1:(f - 0x214)] |
| \store \reg, [r0, #:pc_g2:(f - 0x214)] |
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| \store \reg, [r0, #:sb_g0:(f - 0x214)] |
| \store \reg, [r0, #:sb_g1:(f - 0x214)] |
| \store \reg, [r0, #:sb_g2:(f - 0x214)] |
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| .endm |
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| vfp_test flds fsts s0 |
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| @ FLDD/FSTD |
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| vfp_test fldd fstd d0 |
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| @ VLDR/VSTR |
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| vfp_test vldr vstr d0 |
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| @ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 |
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| .cpu ep9312 |
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| vfp_test cfldrs cfstrs mvf0 |
| vfp_test cfldrd cfstrd mvd0 |
| vfp_test cfldr32 cfstr32 mvfx0 |
| vfp_test cfldr64 cfstr64 mvdx0 |
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