google/trogdor: Update the power on sequence of ps8640
For the Qualcomm PBL configuration of GPIO, we need to initial the
GPIOs for VDD33# and RST# at the beginning of coreboot. According to
the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#.
BUG=b:204637643
BRANCH=trogdor
TEST=verified the waveform of ps8640 at coreboot phase.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GitOrigin-RevId: ba2b1139f1c3479bf7886bb3382216b1e76ad881
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3270123
Tested-by: Copybara Service <copybara-worker-blackhole@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c
index 9006000..90de1e4 100644
--- a/src/mainboard/google/trogdor/chromeos.c
+++ b/src/mainboard/google/trogdor/chromeos.c
@@ -22,6 +22,8 @@
} else {
gpio_output(GPIO_EN_PP3300_DX_EDP, 0);
gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0);
+ gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 0);
+ gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0);
}
if (CONFIG(TROGDOR_HAS_FINGERPRINT)) {
diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c
index 1a60131..5499a07 100644
--- a/src/mainboard/google/trogdor/mainboard.c
+++ b/src/mainboard/google/trogdor/mainboard.c
@@ -106,12 +106,18 @@
gpio_output(GPIO_EN_PP3300_DX_EDP, 1);
gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 1);
- gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1);
- gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0);
/*
- * According to ps8640 app note v0.6, wait for 2ms ("t1") after
- * VDD33 goes high and then deassert RST.
+ * According to ps8640 v1.4 spec, and the raise time of vdd33 is a bit
+ * long, so wait for 4ms after VDD33 goes high and then deassert PD.
+ */
+ mdelay(4);
+
+ gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1);
+
+ /*
+ * According to ps8640 app note v0.6, wait for 2ms after VDD33 goes
+ * high and then deassert RST.
*/
mdelay(2);
