UPSTREAM: mb/google/dedede: Export EC_IN_RW GPIO to payload
Set up EC_IN_RW GPIO in coreboot.
BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Original-Commit-Id: 5273322f7395544dfd82d7e380d34aa4f0e3256c
Original-Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Original-Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Change-Id: I2334d97032c6f96f2c9e392fba685007641ed0f3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2714272
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c
index 0b77ebb..fb904cc 100644
--- a/src/mainboard/google/dedede/chromeos.c
+++ b/src/mainboard/google/dedede/chromeos.c
@@ -12,6 +12,7 @@
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
index 855ab6d..4b72ae3 100644
--- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
@@ -17,6 +17,9 @@
/* EC sync irq is GPP_C15_IRQ */
#define EC_SYNC_IRQ GPP_C15_IRQ
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C14
+
/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_C0
#define GPIO_MEM_CONFIG_1 GPP_C3
