commit | a778ddc285de2ea294480dd785c9e718d4fe0f83 | [log] [tgz] |
---|---|---|
author | Matt Papageorge <matthewpapa07@gmail.com> | Thu Jul 30 20:32:34 2020 |
committer | Commit Bot <commit-bot@chromium.org> | Sat Aug 29 18:57:09 2020 |
tree | 8156a5b88ad23766aec20df0168b3e2e8f44e3db | |
parent | d69eb1a073772623427680be7728fc5206830d68 [diff] |
UPSTREAM: mb/google/zork: Disable SATA device for all Zork platforms to save power SATA is currently turned on in the Dalboz and Trembyle base board variant devicetrees, even though no Google/Zork device uses SATA; for mass storage they either use eMMC or NVME PCIe SSDs. This patch disables both the SATA PCIe device and the bus where it was the only enabled device on. The next patch in this patch train sets a new FSP-M UPD setting BUG=b:162302027 Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: 48b2b2b8c14a6dcc79a4cb2974ef90370586e1a4 Original-Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694 Original-Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068 Original-Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Cq-Depend: chrome-internal:3202602 Cq-Depend: chrome-internal:3201648 Cq-Depend: chrome-internal:3238098 Cq-Depend: chromium:2382516 Cq-Depend: chromium:2382515 Change-Id: I9a31cf609c75500f2078403389aac5e8fa37c989 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2382517 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.