Revert "drm/i915: Lower RM timeout to avoid DSI hard hangs"
This reverts commit d302d64a90b0b390ead3f70832aac2662e34323b.
Needed to reduce conflicts when merging into chromeos-4.14.
Signed-off-by: Guenter Roeck <groeck@chromium.org>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e95547a..ca28456 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6726,10 +6726,6 @@
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT _MMIO(0x42060)
-#define MMIO_TIMEOUT_US(us) ((us) << 0)
-
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 391c248..cb377b0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -121,14 +121,6 @@
*/
I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
-
- /*
- * Lower the display internal timeout.
- * This is needed to avoid any hard hangs when DSI port PLL
- * is off and a MMIO access is attempted by any privilege
- * application, using batch buffers or any other means.
- */
- I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
}
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
