CHROMIUMOS: Add memory barrier implementation for MIPS.
This CL is based on the patch authored by David Turner <digit@google.com>,
see https://code.google.com/p/leveldb/issues/detail?id=109
BUG=chromium:413517
TEST=`emerge-{x86,amd64,arm,mipsel-o32}-generic leveldb`
Change-Id: I85a85a11d0927278ddd437a2702ed690109edff0
Reviewed-on: https://chromium-review.googlesource.com/217834
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Tested-by: Ben Chan <benchan@chromium.org>
Commit-Queue: Ben Chan <benchan@chromium.org>
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 35ae550..341909e 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -36,6 +36,8 @@
#define ARCH_CPU_X86_FAMILY 1
#elif defined(__ARMEL__)
#define ARCH_CPU_ARM_FAMILY 1
+#elif defined(__mips__)
+#define ARCH_CPU_MIPS_FAMILY 1
#endif
namespace leveldb {
@@ -83,6 +85,13 @@
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// MIPS
+#elif defined(ARCH_CPU_MIPS_FAMILY) && defined(__GNUC__)
+inline void MemoryBarrier() {
+ __asm__ __volatile__("sync" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
