| /* Test the `vld4_lanes16' ARM Neon intrinsic. */ |
| /* This file was autogenerated by neon-testgen. */ |
| |
| /* { dg-do assemble } */ |
| /* { dg-require-effective-target arm_neon_ok } */ |
| /* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ |
| |
| #include "arm_neon.h" |
| |
| void test_vld4_lanes16 (void) |
| { |
| int16x4x4_t out_int16x4x4_t; |
| int16x4x4_t arg1_int16x4x4_t; |
| |
| out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); |
| } |
| |
| /* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ |
| /* { dg-final { cleanup-saved-temps } } */ |
