Merge "fix(spmd): fix build error with spmd" into integration
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index c54219f..eaaf59a 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -218,9 +218,7 @@
smc_handler:
/* -----------------------------------------------------
* Save x0-x29 and ARMv8.3-PAuth (if enabled) registers.
- * If Secure Cycle Counter is not disabled in MDCR_EL3
- * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
- * disable Cycle Counter.
+ * Save PMCR_EL0 and disable Cycle Counter.
* TODO: Revisit to store only SMCCC specified registers.
* -----------------------------------------------------
*/
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 5d2534b..dd6b4dc 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -81,9 +81,7 @@
1:
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -123,9 +121,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index a41737a..8bcf94e 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -72,9 +72,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -164,9 +162,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -440,9 +436,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 0ba0a7a..0768e1f 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -52,7 +52,9 @@
+-----------------+---------------------------+------------------------------+
| v2.8 | 5th week of Nov '22 | 3rd week of Nov '22 |
+-----------------+---------------------------+------------------------------+
-| v2.9 | 1st week of May '23 | 3rd week of Apr '23 |
+| v2.9 | 4th week of May '23 | 2nd week of May '23 |
++-----------------+---------------------------+------------------------------+
+| v3.0 | 2nd week of Nov '23 | 2nd week of Oct '23 |
+-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 0f2dfeb..9922fb1 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -568,48 +568,12 @@
stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
mrs x18, sp_el0
str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
-
- /* ----------------------------------------------------------
- * Check if earlier initialization of MDCR_EL3.SCCD/MCCD to 1
- * has failed.
- *
- * MDCR_EL3:
- * MCCD bit set, Prohibits the Cycle Counter PMCCNTR_EL0 from
- * counting at EL3.
- * SCCD bit set, Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0
- * from counting in Secure state.
- * If these bits are not set, meaning that FEAT_PMUv3p5/7 is
- * not implemented and PMCR_EL0 should be saved in non-secure
- * context.
- * ----------------------------------------------------------
- */
- mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
- mrs x9, mdcr_el3
- tst x9, x10
- bne 1f
-
- /* ----------------------------------------------------------
- * If control reaches here, it ensures the Secure Cycle
- * Counter (PMCCNTR_EL0) is not prohibited from counting at
- * EL3 and in secure states.
- * Henceforth, PMCR_EL0 to be saved before world switch.
- * ----------------------------------------------------------
- */
mrs x9, pmcr_el0
-
- /* Check caller's security state */
- mrs x10, scr_el3
- tst x10, #SCR_NS_BIT
- beq 2f
-
- /* Save PMCR_EL0 if called from Non-secure state */
str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
-
/* Disable cycle counter when event counting is prohibited */
-2: orr x9, x9, #PMCR_EL0_DP_BIT
+ orr x9, x9, #PMCR_EL0_DP_BIT
msr pmcr_el0, x9
isb
-1:
#if CTX_INCLUDE_PAUTH_REGS
/* ----------------------------------------------------------
* Save the ARMv8.3-PAuth keys as they are not banked
@@ -687,31 +651,8 @@
msr APGAKeyLo_EL1, x8
msr APGAKeyHi_EL1, x9
#endif /* CTX_INCLUDE_PAUTH_REGS */
-
- /* ----------------------------------------------------------
- * Restore PMCR_EL0 when returning to Non-secure state if
- * Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented.
- * ----------------------------------------------------------
- */
- mrs x0, scr_el3
- tst x0, #SCR_NS_BIT
- beq 2f
-
- /* ----------------------------------------------------------
- * Back to Non-secure state.
- * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
- * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
- * PMCR_EL0 should be restored from non-secure context.
- * ----------------------------------------------------------
- */
- mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
- mrs x0, mdcr_el3
- tst x0, x1
- bne 2f
ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
msr pmcr_el0, x0
-2:
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index ebeb10b..c893476 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -829,8 +829,11 @@
******************************************************************************/
int psci_validate_mpidr(u_register_t mpidr)
{
- if (plat_core_pos_by_mpidr(mpidr) < 0)
+ int pos = plat_core_pos_by_mpidr(mpidr);
+
+ if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) {
return PSCI_E_INVALID_PARAMS;
+ }
return PSCI_E_SUCCESS;
}
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 6c6b23c..76eb50c 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -65,13 +65,10 @@
unsigned int target_idx;
/* Calling function must supply valid input arguments */
+ assert(ret >= 0);
+ assert((unsigned int)ret < PLATFORM_CORE_COUNT);
assert(ep != NULL);
- if ((ret < 0) || (ret >= (int)PLATFORM_CORE_COUNT)) {
- ERROR("Unexpected core index.\n");
- panic();
- }
-
target_idx = (unsigned int)ret;
/*
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 109bfbe..f88eaa8 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -58,23 +58,19 @@
lib/cpus/aarch64/cortex_a73.S
else
# AArch64-only cores
- FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
- lib/cpus/aarch64/cortex_a76ae.S \
- lib/cpus/aarch64/cortex_a77.S \
- lib/cpus/aarch64/cortex_a78.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_n2.S \
- lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/cortex_a78_ae.S \
- lib/cpus/aarch64/cortex_a65.S \
- lib/cpus/aarch64/cortex_a65ae.S \
- lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a710.S \
- lib/cpus/aarch64/cortex_a715.S \
- lib/cpus/aarch64/cortex_x3.S \
- lib/cpus/aarch64/cortex_a78c.S
+ FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_a715.S \
+ lib/cpus/aarch64/cortex_x3.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/cortex_hayes.S \
+ lib/cpus/aarch64/cortex_hunter.S \
+ lib/cpus/aarch64/cortex_hunter_elp_arm.S \
+ lib/cpus/aarch64/cortex_chaberton.S \
+ lib/cpus/aarch64/cortex_blackhawk.S
# AArch64/AArch32 cores
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
