Merge changes I5693ad56,I9ddc077a into integration
* changes:
mediatek: mt8183: Fix AARCH64 init fail on CPU0
mediatek: mt8183: refine GIC driver for low power scenarios
diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c
index c62c3f5..ca7c43b 100644
--- a/drivers/arm/gic/v3/gic600_multichip.c
+++ b/drivers/arm/gic/v3/gic600_multichip.c
@@ -9,13 +9,13 @@
*/
#include <assert.h>
+
#include <common/debug.h>
-
-#include <drivers/arm/gicv3.h>
#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/gicv3.h>
-#include "gic600_multichip_private.h"
#include "../common/gic_common_private.h"
+#include "gic600_multichip_private.h"
#warning "GIC-600 Multichip driver is currently experimental and the API may change in future."
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
new file mode 100644
index 0000000..f35eaf4
--- /dev/null
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/include/ "fvp-base-gicv3-psci-common.dtsi"
+
+&CPU0 {
+ reg = <0x0 0x0>;
+};
+
+&CPU1 {
+ reg = <0x0 0x1>;
+};
+
+&CPU2 {
+ reg = <0x0 0x100>;
+};
+
+&CPU3 {
+ reg = <0x0 0x101>;
+};
+
+&CPU4 {
+ reg = <0x0 0x200>;
+};
+
+&CPU5 {
+ reg = <0x0 0x201>;
+};
+
+&CPU6 {
+ reg = <0x0 0x300>;
+};
+
+&CPU7 {
+ reg = <0x0 0x301>;
+};
diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
index 9823fb3..24e79b4 100644
--- a/plat/arm/board/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,7 +36,8 @@
fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT;
for (i = 0; i < FVP_CLUSTER_COUNT; i++)
- fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER;
+ fvp_power_domain_tree_desc[i + 2] =
+ FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU;
return fvp_power_domain_tree_desc;
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index 4f158ee..b150b89 100644
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -6,11 +6,11 @@
#include <platform_def.h>
+#include <common/debug.h>
#include <drivers/arm/css/css_mhu_doorbell.h>
#include <drivers/arm/css/scmi.h>
#include <drivers/arm/css/sds.h>
#include <drivers/arm/gic600_multichip.h>
-#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat/arm/common/plat_arm.h>
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c
index dcafd55..547af57 100644
--- a/plat/mediatek/mt8183/drivers/spm/spm.c
+++ b/plat/mediatek/mt8183/drivers/spm/spm.c
@@ -12,6 +12,21 @@
DEFINE_BAKERY_LOCK(spm_lock);
+/* CLK_SCP_CFG_0 */
+#define SPM_CK_OFF_CONTROL (0x3FF)
+
+/* CLK_SCP_CFG_1 */
+#define SPM_AXI_26M_SEL (0x1)
+
+/* AP_PLL_CON3 */
+#define SPM_PLL_CONTROL (0x7FAAAAF)
+
+/* AP_PLL_CON4 */
+#define SPM_PLL_OUT_OFF_CONTROL (0xFA0A)
+
+/* AP_PLL_CON6 */
+#define PLL_DLY (0x20000)
+
const char *wakeup_src_str[32] = {
[0] = "R12_PCM_TIMER",
[1] = "R12_SSPM_WDT_EVENT_B",
@@ -324,5 +339,14 @@
spm_lock_init();
mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+ /* switch ck_off/axi_26m control to SPM */
+ mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
+ mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
+
+ /* switch PLL/CLKSQ control to SPM */
+ mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
+ mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
+ mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
+
NOTICE("%s() end\n", __func__);
}
diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index 0a1e038..ad81a33 100644
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -39,7 +39,14 @@
#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
+#define TOPCKGEN_BASE (IO_PHYS + 0x0)
+#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
+#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204)
+
#define APMIXEDSYS (IO_PHYS + 0xC000)
+#define AP_PLL_CON3 (APMIXEDSYS + 0xC)
+#define AP_PLL_CON4 (APMIXEDSYS + 0x10)
+#define AP_PLL_CON6 (APMIXEDSYS + 0x18)
#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)
