| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2006 Advanced Micro Devices, Inc. |
| * Copyright (C) 2008-2010 coresystems GmbH |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| /* We use ELF as output format. So that we can debug the code in some form. */ |
| OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") |
| OUTPUT_ARCH(i386) |
| |
| TARGET(binary) |
| SECTIONS |
| { |
| . = ROMSTAGE_BASE; |
| |
| .rom . : { |
| _rom = .; |
| *(.rom.text); |
| *(.rom.data); |
| *(.rodata); |
| *(.rodata.*); |
| *(.rom.data.*); |
| . = ALIGN(16); |
| _erom = .; |
| } |
| |
| /DISCARD/ : { |
| *(.comment) |
| *(.note) |
| *(.comment.*) |
| *(.note.*) |
| *(.eh_frame); |
| } |
| |
| . = CONFIG_DCACHE_RAM_BASE; |
| .car.data . (NOLOAD) : { |
| *(.car.global_data); |
| *(.car.cbmem_console); |
| } |
| |
| _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); |
| _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage"); |
| } |