tegra132: always bring up PLLD
The kernel does not correctly function without PLLD being enabled.
Additionally, PLLD can be the source for other clocks in the system.
Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT
time in ramstage.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted ryu with display coming up both in dev mode as
well as normal mode.
Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230762
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 099f7b4..7e62504 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
#include <arch/cache.h>
#include <arch/spintable.h>
#include <cpu/cpu.h>
+#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
@@ -145,3 +146,22 @@
.ops = &cpu_dev_ops,
.id_table = ids,
};
+
+static void enable_plld(void *unused)
+{
+ /*
+ * Configure a conservative 300MHz clock for PLLD. The kernel cannot
+ * handle PLLD not being configured so enable PLLD unconditionally
+ * with a default clock rate.
+ */
+ clock_configure_plld(300 * MHz);
+}
+
+/*
+ * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init()
+ * is the first thing called. This ensures PLLD is up and functional before
+ * anything that mainboard can do that implicitly relies on PLLD.
+ */
+BOOT_STATE_INIT_ENTRIES(enable_plld_bscb) = {
+ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL),
+};
