Partial backport of 'dummyflasher: Add a status register to SPI chips'
Here we renames 'JEDEC_RDSR_BIT_WIP' bit flag to 'SPI_SR_WIP' as well
as introduce the flags:
```
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
#define SPI_SR_AAI (0x01 << 6)
```
to spi.h for latter use in follow up resync commits.
This is a partial backport of the upstream `commit 5e695ab`.
There should be no semantic changes resulting from this at
runtime!
BUG=chromium:478356
BRANCH=none
TEST=still builds
Change-Id: Ifd917f25c9ddecaae938487218077b07206cec77
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1502473
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Sam McNally <sammc@chromium.org>
diff --git a/it87spi.c b/it87spi.c
index ce79909..af89841 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -348,7 +348,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 1-10 ms, so wait in 1 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(1000);
return 0;
}
diff --git a/s25f.c b/s25f.c
index 0882b66..c12b2f8 100644
--- a/s25f.c
+++ b/s25f.c
@@ -154,7 +154,7 @@
{
uint8_t tmp = spi_read_status_register(flash);
- while (tmp & JEDEC_RDSR_BIT_WIP) {
+ while (tmp & SPI_SR_WIP) {
/*
* The WIP bit on S25F chips remains set to 1 if erase or
* programming errors occur, so we must check for those
diff --git a/spi.h b/spi.h
index 3044deb..349dfac 100644
--- a/spi.h
+++ b/spi.h
@@ -92,9 +92,13 @@
#define JEDEC_RDSR 0x05
#define JEDEC_RDSR_OUTSIZE 0x01
#define JEDEC_RDSR_INSIZE 0x01
-#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
#define JEDEC_RDSR_BIT_ERASE_ERR (0x01 << 5)
+/* Status Register Bits */
+#define SPI_SR_WIP (0x01 << 0)
+#define SPI_SR_WEL (0x01 << 1)
+#define SPI_SR_AAI (0x01 << 6)
+
/* Write Status Enable */
#define JEDEC_EWSR 0x50
#define JEDEC_EWSR_OUTSIZE 0x01
diff --git a/spi25.c b/spi25.c
index 3696c28..533a6ed 100644
--- a/spi25.c
+++ b/spi25.c
@@ -488,7 +488,7 @@
* This usually takes 1-85 s, so wait in 1 s steps.
*/
/* FIXME: We assume spi_read_status_register will never fail. */
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(1000 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -524,7 +524,7 @@
* This usually takes 1-85 s, so wait in 1 s steps.
*/
/* FIXME: We assume spi_read_status_register will never fail. */
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(1000 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -565,7 +565,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -611,7 +611,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -655,7 +655,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -698,7 +698,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 15-800 ms, so wait in 10 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -780,7 +780,7 @@
* 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
*/
programmer_delay(100 * 1000);
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) {
+ while (spi_read_status_register(flash) & SPI_SR_WIP) {
if (++i > 490) {
msg_cerr("Error: WIP bit after WRSR never cleared\n");
return TIMEOUT_ERROR;
@@ -828,7 +828,7 @@
* 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
*/
programmer_delay(100 * 1000);
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) {
+ while (spi_read_status_register(flash) & SPI_SR_WIP) {
if (++i > 490) {
msg_cerr("Error: WIP bit after WRSR never cleared\n");
return TIMEOUT_ERROR;
@@ -1117,7 +1117,7 @@
buf + starthere - start + j, towrite);
if (rc)
break;
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10);
}
if (rc)
@@ -1145,7 +1145,7 @@
: flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]);
if (result)
return 1;
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10);
}
@@ -1239,7 +1239,7 @@
*/
return result;
}
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10);
/* We already wrote 2 bytes in the multicommand step. */
@@ -1250,7 +1250,7 @@
cmd[1] = buf[pos++ - start];
cmd[2] = buf[pos++ - start];
spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10);
}
diff --git a/spi4ba.c b/spi4ba.c
index e12f6d8..74fe507 100644
--- a/spi4ba.c
+++ b/spi4ba.c
@@ -261,7 +261,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 15-800 ms, so wait in 10 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -306,7 +306,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -352,7 +352,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -580,7 +580,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 15-800 ms, so wait in 10 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -630,7 +630,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -680,7 +680,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -847,7 +847,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 15-800 ms, so wait in 10 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(10 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -896,7 +896,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
@@ -945,7 +945,7 @@
/* Wait until the Write-In-Progress bit is cleared.
* This usually takes 100-4000 ms, so wait in 100 ms steps.
*/
- while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+ while (spi_read_status_register(flash) & SPI_SR_WIP)
programmer_delay(100 * 1000);
/* FIXME: Check the status register for errors. */
return 0;
