| ; Options of Andes NDS32 cpu for GNU compiler |
| ; Copyright (C) 2012-2014 Free Software Foundation, Inc. |
| ; Contributed by Andes Technology Corporation. |
| ; |
| ; This file is part of GCC. |
| ; |
| ; GCC is free software; you can redistribute it and/or modify it |
| ; under the terms of the GNU General Public License as published |
| ; by the Free Software Foundation; either version 3, or (at your |
| ; option) any later version. |
| ; |
| ; GCC is distributed in the hope that it will be useful, but WITHOUT |
| ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| ; License for more details. |
| ; |
| ; You should have received a copy of the GNU General Public License |
| ; along with GCC; see the file COPYING3. If not see |
| ; <http://www.gnu.org/licenses/>. |
| |
| HeaderInclude |
| config/nds32/nds32-opts.h |
| |
| mbig-endian |
| Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN) |
| Generate code in big-endian mode. |
| |
| mlittle-endian |
| Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN) |
| Generate code in little-endian mode. |
| |
| mreduced-regs |
| Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS) |
| Use reduced-set registers for register allocation. |
| |
| mfull-regs |
| Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS) |
| Use full-set registers for register allocation. |
| |
| mcmov |
| Target Report Mask(CMOV) |
| Generate conditional move instructions. |
| |
| mperf-ext |
| Target Report Mask(PERF_EXT) |
| Generate performance extension instructions. |
| |
| mv3push |
| Target Report Mask(V3PUSH) |
| Generate v3 push25/pop25 instructions. |
| |
| m16-bit |
| Target Report Mask(16_BIT) |
| Generate 16-bit instructions. |
| |
| mgp-direct |
| Target Report Mask(GP_DIRECT) |
| Generate GP base instructions directly. |
| |
| misr-vector-size= |
| Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) |
| Specify the size of each interrupt vector, which must be 4 or 16. |
| |
| mcache-block-size= |
| Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE) |
| Specify the size of each cache block, which must be a power of 2 between 4 and 512. |
| |
| march= |
| Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3) |
| Specify the name of the target architecture. |
| |
| Enum |
| Name(nds32_arch_type) Type(enum nds32_arch_type) |
| |
| EnumValue |
| Enum(nds32_arch_type) String(v2) Value(ARCH_V2) |
| |
| EnumValue |
| Enum(nds32_arch_type) String(v3) Value(ARCH_V3) |
| |
| EnumValue |
| Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M) |
| |
| mforce-fp-as-gp |
| Target Report Mask(FORCE_FP_AS_GP) |
| Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization. |
| |
| mforbid-fp-as-gp |
| Target Report Mask(FORBID_FP_AS_GP) |
| Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'. |
| |
| mex9 |
| Target Report Mask(EX9) |
| Use special directives to guide linker doing ex9 optimization. |
| |
| mctor-dtor |
| Target Report |
| Enable constructor/destructor feature. |
| |
| mrelax |
| Target Report |
| Guide linker to relax instructions. |
