gcc/doc/arm-acle-intrinsics.texi

@c Copyright (C) 2013-2014 Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.

@subsubsection CRC32 intrinsics

These intrinsics are available when the CRC32 architecture extension is
specified, e.g. when the @option{-march=armv8-a+crc} switch is used, or when
the target processor specified with @option{-mcpu} supports it.

@itemize @bullet
@item uint32_t __crc32b (uint32_t, uint8_t)
@*@emph{Form of expected instruction(s):} @code{crc32b @var{r0}, @var{r0}, @var{r0}}
@end itemize


@itemize @bullet
@item uint32_t __crc32h (uint32_t, uint16_t)
@*@emph{Form of expected instruction(s):} @code{crc32h @var{r0}, @var{r0}, @var{r0}}
@end itemize


@itemize @bullet
@item uint32_t __crc32w (uint32_t, uint32_t)
@*@emph{Form of expected instruction(s):} @code{crc32w @var{r0}, @var{r0}, @var{r0}}
@end itemize


@itemize @bullet
@item uint32_t __crc32d (uint32_t, uint64_t)
@*@emph{Form of expected instruction(s):} Two @code{crc32w @var{r0}, @var{r0}, @var{r0}}
instructions.
@end itemize

@itemize @bullet
@item uint32_t __crc32cb (uint32_t, uint8_t)
@*@emph{Form of expected instruction(s):} @code{crc32cb @var{r0}, @var{r0}, @var{r0}}
@end itemize


@itemize @bullet
@item uint32_t __crc32ch (uint32_t, uint16_t)
@*@emph{Form of expected instruction(s):} @code{crc32ch @var{r0}, @var{r0}, @var{r0}}
@end itemize


@itemize @bullet
@item uint32_t __crc32cw (uint32_t, uint32_t)
@*@emph{Form of expected instruction(s):} @code{crc32cw @var{r0}, @var{r0}, @var{r0}}
@end itemize


@itemize @bullet
@item uint32_t __crc32cd (uint32_t, uint64_t)
@*@emph{Form of expected instruction(s):} Two @code{crc32cw @var{r0}, @var{r0}, @var{r0}}
instructions.
@end itemize