| From 93d33ade5acf819a0509d3adee7964e126712c42 Mon Sep 17 00:00:00 2001 |
| From: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> |
| Date: Thu, 20 Oct 2022 17:54:33 +0800 |
| Subject: [PATCH] CHROMIUM: arm64: dts: mt8186: Change the clock frequency for |
| spi nor |
| |
| We found some random glitches of the mux in nor_flash during SPI |
| read data. Due to this, spi-mtk-nor dma timeout will occur. |
| Experiments reveal that when the frequency decreases, the issue might |
| go away. |
| |
| We change nor_flash clock parent to the next lowerer level of clock for |
| mt8186-nor. |
| |
| BUG=b:242674543, b:253167106 |
| TEST=emerge-corsola sys-kernel/chromeos-kernel-5_15 |
| UPSTREAM-TASK=b:213000788 |
| |
| Signed-off-by: Dandan He <dandan.he@mediatek.corp-partner.google.com> |
| Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.corp-partner.google.com> |
| Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> |
| Change-Id: Ib3ae80d9b8928cd6450257375271bab18702aef6 |
| Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/4005910 |
| Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> |
| Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org> |
| --- |
| arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi |
| index 41e5a1ce9cc6ccde01e4da2895e64709ed043f10..3551aa4e658352ab87f478ef41360df511fad9e9 100644 |
| --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi |
| +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi |
| @@ -512,6 +512,7 @@ &nor_flash { |
| pinctrl-0 = <&nor_pins_default>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; |
| status = "okay"; |
| |
| flash@0 { |
| -- |
| 2.44.0.478.gd926399ef9-goog |
| |
