| From d5b0e467b62af58782f3b801fe6829126d3d1ae8 Mon Sep 17 00:00:00 2001 |
| From: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> |
| Date: Thu, 23 Jun 2022 15:13:31 +0800 |
| Subject: [PATCH] CHROMIUM: arm64: dts: mt8186: Add svs nodes |
| |
| Add clock/irq/efuse setting in svs nodes for mt8186 SoC. |
| |
| BUG=b:213000788 |
| TEST=emerge-corsola sys-kernel/chromeos-kernel-5_15 |
| |
| Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> |
| Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com> |
| Change-Id: I5db81af088a82eae9f9e9e54b167f9ecd91734b8 |
| Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3419903 |
| Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> |
| Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org> |
| Kcr-patch: 70f18d20e6d1672a95f5edca8ae2dce0d8030ca3f65be102d0eef59f.patch |
| --- |
| arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++ |
| 1 file changed, 16 insertions(+) |
| |
| diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi |
| index 91bbd6efe6afd2acb563baa3af6c917550bb701a..96db238b8e8bb6a72e8c17a40ad38164e83922f5 100644 |
| --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi |
| +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi |
| @@ -1355,6 +1355,18 @@ spi0: spi@1100a000 { |
| status = "disabled"; |
| }; |
| |
| + svs: svs@1100b000 { |
| + compatible = "mediatek,mt8186-svs"; |
| + reg = <0 0x1100b000 0 0x1000>; |
| + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; |
| + clock-names = "main"; |
| + nvmem-cells = <&svs_calibration>, <&lvts_e_data1>; |
| + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; |
| + resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>; |
| + reset-names = "svs_rst"; |
| + }; |
| + |
| pwm0: pwm@1100e000 { |
| compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; |
| reg = <0 0x1100e000 0 0x1000>; |
| @@ -1709,6 +1721,10 @@ efuse: efuse@11cb0000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| + svs_calibration: calib { |
| + reg = <0x550 0x50>; |
| + }; |
| + |
| gpu_speedbin: gpu-speedbin@59c { |
| reg = <0x59c 0x4>; |
| bits = <0 3>; |
| -- |
| 2.43.0.472.g3155946c3a-goog |
| |
