8570014eb66ad0e7dacfa1f42b7aefcc6f410b8d3525c1361592e89e.patch

From 6e63c706ad41421fdffa68f6167cc9788d210288 Mon Sep 17 00:00:00 2001
From: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Date: Tue, 19 Jul 2022 16:02:33 +0800
Subject: [PATCH] CHROMIUM: arm64: dts: mt8186: Add thermal device nodes

Add thermal device nodes for mt8186 SoC.

BUG=b:213000788
TEST=boot KRABBY to shell, read temperature, check thermal throttle

Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Signed-off-by: Dawei Chien <dawei.chien@mediatek.corp-partner.google.com>
Change-Id: I9a8ca18ee27ffeb7a082994344885baf177707e8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3446863
Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 +++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a708aa296ec845a8c5534e2e91f0c79dbdc2c662..7070ee3c8d266fd9af96f4616e46db445287f2ef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/power/mt8186-power.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/reset/mt8186-resets.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "mediatek,mt8186";
@@ -1343,6 +1344,18 @@ spi0: spi@1100a000 {
 			status = "disabled";
 		};
 
+		lvts: lvts@1100b000 {
+			compatible = "mediatek,mt8186-lvts";
+			#thermal-sensor-cells = <1>;
+			reg = <0 0x1100b000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+			clock-names = "lvts_clk";
+			resets = <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>;
+			nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
+			nvmem-cell-names = "e_data1","e_data2";
+		};
+
 		svs: svs@1100b000 {
 			compatible = "mediatek,mt8186-svs";
 			reg = <0 0x1100b000 0 0x1000>;
@@ -1689,6 +1702,14 @@ efuse: efuse@11cb0000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lvts_e_data1: data1 {
+				reg = <0x1cc 0x14>;
+			};
+
+			lvts_e_data2: data1-1 {
+				reg = <0x2f8 0x14>;
+			};
+
 			svs_calibration: calib {
 				reg = <0x550 0x50>;
 			};
@@ -2194,5 +2215,124 @@ larb19: smi@1c10f000 {
 			mediatek,smi = <&smi_common>;
 			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
 		};
+
+		thermal_zones: thermal-zones {
+			soc_max {
+				polling-delay = <1000>; /* milliseconds */
+				polling-delay-passive = <50>; /* milliseconds */
+				thermal-sensors = <&lvts 0>;
+				sustainable-power = <1500>;
+
+				trips {
+					threshold: trip-point@0 {
+						temperature = <58000>;
+						hysteresis = <2000>;
+						type = "passive";
+					};
+
+					target: target@1 {
+						temperature = <82000>;
+						hysteresis = <2000>;
+						type = "passive";
+					};
+
+					soc_max_crit: soc_max_crit@0 {
+						temperature = <103000>;
+						hysteresis = <2000>;
+						type = "critical";
+					};
+				};
+
+				cooling_map: cooling-maps {
+					map0 {
+						trip = <&target>;
+						cooling-device = <&cpu0
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>,
+								<&cpu1
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>,
+								<&cpu2
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>,
+								<&cpu3
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>,
+								<&cpu4
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>,
+								<&cpu5
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+						contribution = <4096>;
+					};
+
+					map1 {
+						trip = <&target>;
+						cooling-device = <&cpu6
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>,
+								<&cpu7
+							THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+						contribution = <1024>;
+					};
+				};
+			};
+
+			cpu_zone0{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 1>;
+			};
+
+			cpu_zone1{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 2>;
+			};
+
+			cpu_zone2{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 3>;
+			};
+
+			cam{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 4>;
+			};
+
+			nna{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 5>;
+			};
+
+			adsp{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 6>;
+			};
+
+			mfg{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 7>;
+			};
+
+			cpu_big0{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 8>;
+			};
+
+			cpu_big1{
+				polling-delay = <0>; /* milliseconds */
+				polling-delay-passive = <0>; /* milliseconds */
+				thermal-sensors = <&lvts 9>;
+			};
+		};
 	};
 };
-- 
2.34.1