b8eccdd1c6cd7a141eefe451bcb8f0383236d719c3468031c0bb01ba.patch

From 010cb0f70f607541084b1c1b8c1e83966b2ce8a1 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Fri, 23 Oct 2020 14:00:57 -0700
Subject: [PATCH] CHROMIUM: HACK: drm/msm/dpu: Give each CRTC a dedicated
 cursor and primary (except for coachz)

Most of the issues that caused us to pin the planes to a single CRTC are
fixed, except for b/168868719.  We are pushing to get hw overlays
enabled on coachz, so re-work the previous hack to let us re-enable hw-
overlays on a per-board basis to avoid disrupting shipping devices.
Once the remaining bug has been fixed, and we have some confidence that
there are no other bugs that we missed, we can revert this patch.

BUG=b:176990056, b:187095776
TEST=verify primary/cursor planes are pinned to one CRTC except for
coachz

Signed-off-by: Rob Clark <robdclark@chromium.org>
Change-Id: Ib76eef92d195c08d470b740365dc558efdc2fac5
Reviewed-on: https: //chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2773884
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Commit-Queue: Stephen Boyd <swboyd@chromium.org>
(cherry picked from commit 30aef5779b6108baaea00750064338bf0ed145c2)
Signed-off-by: Matt Turner <msturner@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3564538
---
 .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi  |  4 ++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       | 23 +++++++++++++++----
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c     |  2 +-
 3 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
index 7ee407f7b6bb5fb52b9f8ba6a6e5052ffea549a6..78ba056beaccfbf8aaef097da7b6e7bbd5ed8e9e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
@@ -114,6 +114,10 @@ &i2c9 {
 	status = "disabled";
 };
 
+&mdp {
+	chromium-enable-overlays;
+};
+
 &panel {
 	compatible = "boe,nv110wtm-n61";
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5e6e2626151e8d174f8ce78facb7cc0e2e0a2361..ea07ae88d4c9dc560082f1974e3693165826e93f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -738,6 +738,9 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 	struct drm_crtc *crtc;
 	struct drm_encoder *encoder;
 	unsigned int num_encoders;
+	unsigned cursor_idx = 0;
+	unsigned primary_idx = 0;
+	bool pin_overlays;
 
 	struct msm_drm_private *priv;
 	const struct dpu_mdss_cfg *catalog;
@@ -748,6 +751,8 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 	priv = dev->dev_private;
 	catalog = dpu_kms->catalog;
 
+	pin_overlays = !of_property_read_bool(dpu_kms->pdev->dev.of_node, "chromium-enable-overlays");
+
 	/*
 	 * Create encoder and query display drivers to create
 	 * bridges and connectors
@@ -765,21 +770,31 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 	/* Create the planes, keeping track of one primary/cursor per crtc */
 	for (i = 0; i < catalog->sspp_count; i++) {
 		enum drm_plane_type type;
+		unsigned possible_crtcs;
 
 		if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
-			&& cursor_planes_idx < max_crtc_count)
+			&& cursor_planes_idx < max_crtc_count) {
 			type = DRM_PLANE_TYPE_CURSOR;
-		else if (primary_planes_idx < max_crtc_count)
+			possible_crtcs = BIT(cursor_idx);
+			cursor_idx++;
+		} else if (primary_planes_idx < max_crtc_count) {
 			type = DRM_PLANE_TYPE_PRIMARY;
-		else
+			possible_crtcs = BIT(primary_idx);
+			primary_idx++;
+		} else {
 			type = DRM_PLANE_TYPE_OVERLAY;
+			possible_crtcs = (1UL << max_crtc_count) - 1;
+		}
 
 		DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
 			  type, catalog->sspp[i].features,
 			  catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
 
+		if (!pin_overlays)
+			possible_crtcs = (1UL << max_crtc_count) - 1;
+
 		plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
-				       (1UL << max_crtc_count) - 1);
+				       possible_crtcs, 0);
 		if (IS_ERR(plane)) {
 			DPU_ERROR("dpu_plane_init failed\n");
 			ret = PTR_ERR(plane);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 658005f609f4b3d1e373dd8d3dbaf888ad80e122..76b2e88afe4421a5cf640966f0a10ab1fc876f57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1496,7 +1496,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	format_list = pdpu->pipe_hw->cap->sblk->format_list;
 	num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
 
-	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
+	ret = drm_universal_plane_init(dev, plane, possible_crtcs, &dpu_plane_funcs,
 				format_list, num_formats,
 				supported_format_modifiers, type, NULL);
 	if (ret)
-- 
2.38.1.584.g0f3c55d4c2-goog