0f72c3adbb6ef058f68aeb18d22a18f081b445ae7dcc6e98bcfddaec.patch

From b8c6a7150c34b6e3ea7fdaf74fd800c2d9afb02f Mon Sep 17 00:00:00 2001
From: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Date: Tue, 24 Nov 2020 21:12:55 +0530
Subject: [PATCH] FROMLIST: drm/amd/display: Extends Tune min clk for MPO for
 RV
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[Why]
Changes in video resolution during playback cause
dispclk to ramp higher but sets incompatile fclk
and dcfclk values for MPO.

[How]
Check for MPO and set proper min clk values
for this case also. This was missed during previous
patch.

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
(am from https://patchwork.freedesktop.org/patch/403354/)

BUG=b:163476639, b:173355232
TEST=Pause video p/b, change resolution, observe no flash line

Signed-off-by: Pratik Vishwakarma <pratik.vishwakarma@amd.corp-partner.google.com>
Change-Id: I2839fe485b03612e3eb6af9c686bc48156187204
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2560077
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
---
 .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -282,9 +282,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 		if (pp_smu->set_hard_min_fclk_by_freq &&
 				pp_smu->set_hard_min_dcfclk_by_freq &&
 				pp_smu->set_min_deep_sleep_dcfclk) {
-			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));
-			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));
-			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));
+			// Only increase clocks when display is active and MPO is enabled
+			if (display_count && is_mpo_enabled(context)) {
+				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+						((new_clocks->fclk_khz / 1000) *  101) / 100);
+				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+						((new_clocks->dcfclk_khz / 1000) * 101) / 100);
+				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+			} else {
+				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+						new_clocks->fclk_khz / 1000);
+				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+						new_clocks->dcfclk_khz / 1000);
+				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+			}
 		}
 	}
 
-- 
2.33.0.685.g46640cef36-goog