| From a302bcc4b5b1ef2444d468306b5cfafbed66ab37 Mon Sep 17 00:00:00 2001 |
| From: Chandan Uddaraju <chandanu@codeaurora.org> |
| Date: Tue, 30 Jun 2020 11:45:02 -0700 |
| Subject: [PATCH] BACKPORT: FROMLIST: dt-bindings: msm/dp: add bindings of |
| DP/DP-PLL driver for Snapdragon |
| |
| Add bindings for Snapdragon DisplayPort controller driver. |
| |
| Changes in V2: |
| Provide details about sel-gpio |
| |
| Changes in V4: |
| Provide details about max dp lanes |
| Change the commit text |
| |
| Changes in V5: |
| moved dp.txt to yaml file |
| |
| Changes in v6: |
| - Squash all AUX LUT properties into one pattern Property |
| - Make aux-cfg[0-9]-settings properties optional |
| - Remove PLL/PHY bindings from DP controller dts |
| - Add DP clocks description |
| - Remove _clk suffix from clock names |
| - Rename pixel clock to stream_pixel |
| - Remove redundant bindings (GPIO, PHY, HDCP clock, etc..) |
| - Fix indentation |
| - Add Display Port as interface of DPU in DPU bindings |
| and add port mapping accordingly. |
| |
| Chages in v7: |
| - Add dp-controller.yaml file common between multiple SOC |
| - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml |
| - change compatible string and add SOC name to it. |
| - Remove Root clock generator for pixel clock |
| - Add assigned-clocks and assigned-clock-parents bindings |
| - Remove redundant properties, descriptions and blank lines |
| - Add DP port in DPU bindings |
| - Update depends-on tag in commit message and rebase change accordingly |
| |
| Changes in v8: |
| - Add MDSS AHB clock in bindings |
| |
| This change depends-on: |
| - https://patchwork.freedesktop.org/patch/366159/ |
| |
| Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> |
| Signed-off-by: Vara Reddy <varar@codeaurora.org> |
| Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> |
| (am from https://lore.kernel.org/patchwork/patch/1265864/) |
| (also found at https://lore.kernel.org/r/20200630184507.15589-2-tanmay@codeaurora.org) |
| |
| BUG=b:148864048 |
| TEST=Connect DP cable to type-c ports, see secondary display output, try |
| |
| Signed-off-by: Stephen Boyd <swboyd@chromium.org> |
| Change-Id: Ib807ce69aa7ce110f32b9a05d3d673dacf8621c4 |
| Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2079480 |
| Reviewed-by: Rob Clark <robdclark@chromium.org> |
| --- |
| .../display/msm/dp-controller-sc7180.yaml | 144 ++++++++++++++++++ |
| .../bindings/display/msm/dp-controller.yaml | 123 +++------------ |
| .../bindings/display/msm/dpu-sc7180.yaml | 11 ++ |
| 3 files changed, 174 insertions(+), 104 deletions(-) |
| create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml |
| |
| diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml |
| new file mode 100644 |
| index 000000000000..ce89ea73e778 |
| --- /dev/null |
| +++ b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml |
| @@ -0,0 +1,144 @@ |
| +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| +%YAML 1.2 |
| +--- |
| +$id: http://devicetree.org/schemas/display/msm/dp-controller-sc7180.yaml# |
| +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| + |
| +title: MSM SC7180 Display Port Controller. |
| + |
| +maintainers: |
| + - Chandan Uddaraju <chandanu@codeaurora.org> |
| + - Vara Reddy <varar@codeaurora.org> |
| + - Tanmay Shah <tanmay@codeaurora.org> |
| + |
| +description: | |
| + Device tree bindings for DP host controller for MSM SC7180 target |
| + that are compatible with VESA Display Port interface specification. |
| + |
| +allOf: |
| + - $ref: dp-controller.yaml# |
| + |
| +properties: |
| + compatible: |
| + items: |
| + - enum: |
| + - qcom,sc7180-dp |
| + |
| + reg: |
| + maxItems: 1 |
| + reg-names: |
| + const: dp_controller |
| + |
| + interrupts: |
| + maxItems: 1 |
| + |
| + clocks: |
| + maxItems: 5 |
| + |
| + clock-names: |
| + items: |
| + - const: core_iface |
| + - const: core_aux |
| + - const: ctrl_link |
| + - const: ctrl_link_iface |
| + - const: stream_pixel |
| + |
| + "#clock-cells": |
| + const: 1 |
| + |
| + assigned-clocks: |
| + maxItems: 1 |
| + assigned-clock-parents: |
| + maxItems: 1 |
| + |
| + data-lanes: |
| + $ref: "/schemas/types.yaml#/definitions/uint32-array" |
| + minItems: 1 |
| + maxItems: 4 |
| + |
| + vdda-1p2-supply: |
| + description: phandle to vdda 1.2V regulator node. |
| + |
| + vdda-0p9-supply: |
| + description: phandle to vdda 0.9V regulator node. |
| + |
| + ports: |
| + type: object |
| + properties: |
| + "#address-cells": |
| + const: 1 |
| + |
| + "#size-cells": |
| + const: 0 |
| + |
| + port@0: |
| + type: object |
| + port@1: |
| + type: object |
| + |
| +required: |
| + - compatible |
| + - reg |
| + - reg-names |
| + - interrupts |
| + - clocks |
| + - clock-names |
| + - assigned-clocks |
| + - assigned-clock-parents |
| + - vdda-1p2-supply |
| + - vdda-0p9-supply |
| + - data-lanes |
| + - ports |
| + |
| +additionalProperties: false |
| + |
| +examples: |
| + - | |
| + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| + #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| + msm_dp: displayport-controller@ae90000{ |
| + compatible = "qcom,sc7180-dp"; |
| + reg = <0 0xae90000 0 0x1400>; |
| + reg-names = "dp_controller"; |
| + |
| + interrupt-parent = <&mdss>; |
| + interrupts = <12 0>; |
| + |
| + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; |
| + clock-names = "core_iface", "core_aux", |
| + "ctrl_link", |
| + "ctrl_link_iface", "stream_pixel"; |
| + #clock-cells = <1>; |
| + |
| + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; |
| + assigned-clock-parents = <&dp_phy 1>; |
| + |
| + vdda-1p2-supply = <&vreg_l3c_1p2>; |
| + vdda-0p9-supply = <&vreg_l4a_0p8>; |
| + |
| + data-lanes = <0 1>; |
| + |
| + ports { |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + |
| + port@0 { |
| + reg = <0>; |
| + dp_in: endpoint { |
| + remote-endpoint = <&dpu_intf0_out>; |
| + }; |
| + }; |
| + |
| + port@1 { |
| + reg = <1>; |
| + dp_out: endpoint { |
| + }; |
| + }; |
| + }; |
| + }; |
| +... |
| diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml |
| index 64d8d9e5e47a..f69b8505516c 100644 |
| --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml |
| +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml |
| @@ -1,30 +1,36 @@ |
| -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| -title: MSM Display Port Controller |
| +title: Qualcomm Display Port Controller. |
| |
| maintainers: |
| - - Kuogee Hsieh <khsieh@codeaurora.org> |
| + - Chandan Uddaraju <chandanu@codeaurora.org> |
| + - Vara Reddy <varar@codeaurora.org> |
| + - Tanmay Shah <tanmay@codeaurora.org> |
| |
| description: | |
| - Device tree bindings for DisplayPort host controller for MSM targets |
| - that are compatible with VESA DisplayPort interface specification. |
| + Device tree bindings for MSM Display Port which supports DP host controllers |
| + that are compatible with VESA Display Port interface specification. |
| |
| properties: |
| compatible: |
| - enum: |
| - - qcom,sc7180-dp |
| + items: |
| + - enum: |
| + - qcom,sc7180-dp |
| |
| reg: |
| maxItems: 1 |
| + reg-names: |
| + const: dp_controller |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: |
| + maxItems: 5 |
| items: |
| - description: AHB clock to enable register access |
| - description: Display Port AUX clock |
| @@ -41,106 +47,15 @@ properties: |
| - const: stream_pixel |
| |
| assigned-clocks: |
| - items: |
| - - description: link clock source |
| - - description: pixel clock source |
| - |
| - assigned-clock-parents: |
| - items: |
| - - description: phy 0 parent |
| - - description: phy 1 parent |
| - |
| - phys: |
| maxItems: 1 |
| - |
| - phy-names: |
| - items: |
| - - const: dp |
| - |
| - operating-points-v2: |
| - maxItems: 1 |
| - |
| - power-domains: |
| + assigned-clock-parents: |
| maxItems: 1 |
| |
| - "#sound-dai-cells": |
| - const: 0 |
| + data-lanes: |
| + $ref: "/schemas/types.yaml#/definitions/uint32-array" |
| + minItems: 1 |
| + maxItems: 4 |
| |
| ports: |
| - $ref: /schemas/graph.yaml#/properties/ports |
| - properties: |
| - port@0: |
| - $ref: /schemas/graph.yaml#/properties/port |
| - description: Input endpoint of the controller |
| - |
| - port@1: |
| - $ref: /schemas/graph.yaml#/properties/port |
| - description: Output endpoint of the controller |
| - |
| -required: |
| - - compatible |
| - - reg |
| - - interrupts |
| - - clocks |
| - - clock-names |
| - - phys |
| - - phy-names |
| - - "#sound-dai-cells" |
| - - power-domains |
| - - ports |
| - |
| -additionalProperties: false |
| - |
| -examples: |
| - - | |
| - #include <dt-bindings/interrupt-controller/arm-gic.h> |
| - #include <dt-bindings/clock/qcom,dispcc-sc7180.h> |
| - #include <dt-bindings/power/qcom-aoss-qmp.h> |
| - #include <dt-bindings/power/qcom-rpmpd.h> |
| - |
| - displayport-controller@ae90000 { |
| - compatible = "qcom,sc7180-dp"; |
| - reg = <0xae90000 0x1400>; |
| - interrupt-parent = <&mdss>; |
| - interrupts = <12>; |
| - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| - <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, |
| - <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, |
| - <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, |
| - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; |
| - clock-names = "core_iface", "core_aux", |
| - "ctrl_link", |
| - "ctrl_link_iface", "stream_pixel"; |
| - |
| - assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, |
| - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; |
| - |
| - assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; |
| - |
| - phys = <&dp_phy>; |
| - phy-names = "dp"; |
| - |
| - #sound-dai-cells = <0>; |
| - |
| - power-domains = <&rpmhpd SC7180_CX>; |
| - |
| - ports { |
| - #address-cells = <1>; |
| - #size-cells = <0>; |
| - |
| - port@0 { |
| - reg = <0>; |
| - endpoint { |
| - remote-endpoint = <&dpu_intf0_out>; |
| - }; |
| - }; |
| - |
| - port@1 { |
| - reg = <1>; |
| - endpoint { |
| - remote-endpoint = <&typec>; |
| - }; |
| - }; |
| - }; |
| - }; |
| + type: object |
| ... |
| diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml |
| index df70393aec82..b824684ec998 100644 |
| --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml |
| +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml |
| @@ -133,6 +133,9 @@ patternProperties: |
| port@1: |
| type: object |
| description: DPU_INTF2 (DSI2) |
| + port@2: |
| + type: object |
| + description: DPU_INTF0 (DP) |
| |
| assigned-clocks: |
| maxItems: 4 |
| @@ -229,6 +232,14 @@ examples: |
| remote-endpoint = <&dsi0_in>; |
| }; |
| }; |
| + |
| + port@2 { |
| + reg = <2>; |
| + dpu_intf0_out: endpoint { |
| + remote-endpoint = <&dp_in>; |
| + }; |
| + }; |
| + |
| }; |
| }; |
| }; |
| -- |
| 2.32.0.93.g670b81a890-goog |
| |
