433733e6ece669fe3af3306460f8ccf88cf9ababf5e3614077f318d3.patch

From 60ccbdcc644cb56b7575649589a4295a256abacf Mon Sep 17 00:00:00 2001
From: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Date: Tue, 3 Nov 2020 11:13:16 +0530
Subject: [PATCH] FROMLIST: drm/amd/display: Tune fclk for 4K OLED display

[Why]
On 4K SKU, in DC mode, there is a visible slowness
observed on system compared to AC mode.

[How]
Tuning min fclk up by 2% resolved this issue.

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
(am from https://patchwork.freedesktop.org/patch/399484/)

BUG=b:170931252
TEST=Disconnect AC and use DUT. Observe no slowness.

Signed-off-by: Pratik Vishwakarma <pratik.vishwakarma@amd.corp-partner.google.com>
Change-Id: Ib57732f3ef49c6f3bc815992633a7a772773de79
Signed-off-by: Pratik Vishwakarma <pratik.vishwakarma@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2526005
Commit-Queue: Drew Davenport <ddavenport@chromium.org>
Reviewed-by: Deepak Sharma <deepak.sharma@amd.com>
Reviewed-by: Drew Davenport <ddavenport@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c   | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 75b8240ed059..e2e76be9e637 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -210,6 +210,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 	bool send_request_to_increase = false;
 	bool send_request_to_lower = false;
 	int display_count;
+	int i, clock_factor = 0;
 
 	bool enter_display_off = false;
 
@@ -220,6 +221,12 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 
 	pp_smu = &clk_mgr->pp_smu->rv_funcs;
 
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->streams[i]->timing.h_total > 3840
+			|| context->streams[i]->timing.v_total > 2160)
+			clock_factor = 2;
+	}
+
 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
 
 	if (display_count == 0)
@@ -305,7 +312,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
 			} else {
 				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
-						new_clocks->fclk_khz / 1000);
+						((new_clocks->fclk_khz / 1000) * (100 + clock_factor)) / 100);
 				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
 						new_clocks->dcfclk_khz / 1000);
 				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
-- 
2.17.1