| From f61306212af6a5f10a6054bbfe158effebf62e44 Mon Sep 17 00:00:00 2001 |
| From: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> |
| Date: Fri, 21 May 2021 17:50:28 +0800 |
| Subject: [PATCH] UPSTREAM: drm/amdgpu: Fix inconsistent indenting |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| Eliminate the follow smatch warning: |
| |
| drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449 |
| sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting. |
| |
| Reviewed-by: Christian Kรถnig <christian.koenig@amd.com> |
| Reported-by: Abaci Robot <abaci@linux.alibaba.com> |
| Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| (cherry picked from commit f43ae2d1806c2b8a0934cb4acddd3cf3750d10f8) |
| Signed-off-by: Sean Paul <seanpaul@chromium.org> |
| |
| BUG=b:187300590 |
| TEST=Tested with single/multiple displays, suspend/resume, hotplugs on volteer/trogdor/dedede/zork, build tested on amd64/arm64-generic |
| |
| Change-Id: I0aecb306eee10cdeb50480ce16f15f0047e4e5e5 |
| --- |
| drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 13 ++++++------- |
| 1 file changed, 6 insertions(+), 7 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c |
| index deb907f96090..f3fa29e0983c 100644 |
| --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c |
| @@ -385,20 +385,19 @@ static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, |
| */ |
| static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) |
| { |
| - uint32_t gcr_cntl = |
| - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | |
| - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | |
| - SDMA_GCR_GLI_INV(1); |
| + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | |
| + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | |
| + SDMA_GCR_GLI_INV(1); |
| |
| /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ |
| amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); |
| amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); |
| amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | |
| - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); |
| + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); |
| amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | |
| - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); |
| + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); |
| amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | |
| - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); |
| + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); |
| } |
| |
| /** |
| -- |
| 2.17.1 |
| |
