| From e0df71ac52c006882d84c8bbbc3a403d774c3b9d Mon Sep 17 00:00:00 2001 |
| From: Tanmay Shah <tanmay@codeaurora.org> |
| Date: Tue, 30 Jun 2020 12:51:51 -0700 |
| Subject: [PATCH] FROMLIST: arm64: dts: qcom: sc7180: Add Display Port dt node |
| |
| Add DP device node on sc7180. |
| |
| Changes in v2: |
| |
| - Add assigned-clocks and assigned-clock-parents |
| - Remove cell-index and pixel_rcg |
| - Change compatible to qcom,sc7180-dp |
| |
| Changes in v3: |
| - Update commit text |
| - Make DP child node of MDSS |
| - Remove data-lanes property from SOC dts |
| - Disable DP node in SOC dts |
| - Assign DP to Port2 in MDP node |
| - Add MDSS AHB clock in DP device node |
| |
| This patch depends-on: |
| https://patchwork.freedesktop.org/series/78953/ |
| |
| Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> |
| (am from https://lore.kernel.org/patchwork/patch/1265895/) |
| (also found at https://lore.kernel.org/r/20200630195151.347-1-tanmay@codeaurora.org) |
| |
| BUG=b:148864048 |
| TEST=Connect DP cable to type-c ports, see secondary display |
| |
| Signed-off-by: Stephen Boyd <swboyd@chromium.org> |
| Change-Id: I3e98e0eda22b238488cdb862e5429727f78dd39d |
| Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2253384 |
| Reviewed-by: Rob Clark <robdclark@chromium.org> |
| Reviewed-by: Sean Paul <seanpaul@chromium.org> |
| Signed-off-by: Stephen Boyd <swboyd@chromium.org> |
| --- |
| arch/arm64/boot/dts/qcom/sc7180.dtsi | 74 ++++++++++++++++++++++++++++ |
| 1 file changed, 74 insertions(+) |
| |
| diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi |
| index 6228ba2d8513..883623aa33d8 100644 |
| --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi |
| +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi |
| @@ -3032,6 +3032,13 @@ dpu_intf1_out: endpoint { |
| remote-endpoint = <&dsi0_in>; |
| }; |
| }; |
| + |
| + port@2 { |
| + reg = <2>; |
| + dpu_intf0_out: endpoint { |
| + remote-endpoint = <&dp_in>; |
| + }; |
| + }; |
| }; |
| |
| mdp_opp_table: mdp-opp-table { |
| @@ -3148,6 +3155,73 @@ dsi_phy: dsi-phy@ae94400 { |
| |
| status = "disabled"; |
| }; |
| + |
| + msm_dp: displayport-controller@ae90000 { |
| + status = "disabled"; |
| + compatible = "qcom,sc7180-dp"; |
| + |
| + reg = <0 0x0ae90000 0 0x1400>; |
| + |
| + interrupt-parent = <&mdss>; |
| + interrupts = <12 IRQ_TYPE_NONE>; |
| + |
| + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, |
| + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; |
| + clock-names = "core_iface", "core_aux", "ctrl_link", |
| + "ctrl_link_iface", "stream_pixel"; |
| + #clock-cells = <1>; |
| + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, |
| + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; |
| + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; |
| + phys = <&dp_phy>; |
| + phy-names = "dp"; |
| + |
| + operating-points-v2 = <&dp_opp_table>; |
| + power-domains = <&rpmhpd SC7180_CX>; |
| + |
| + ports { |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + port@0 { |
| + reg = <0>; |
| + dp_in: endpoint { |
| + remote-endpoint = <&dpu_intf0_out>; |
| + }; |
| + }; |
| + |
| + port@1 { |
| + reg = <1>; |
| + dp_out: endpoint { }; |
| + }; |
| + }; |
| + |
| + dp_opp_table: dp-opp-table { |
| + compatible = "operating-points-v2"; |
| + |
| + opp-160000000 { |
| + opp-hz = /bits/ 64 <160000000>; |
| + required-opps = <&rpmhpd_opp_low_svs>; |
| + }; |
| + |
| + opp-270000000 { |
| + opp-hz = /bits/ 64 <270000000>; |
| + required-opps = <&rpmhpd_opp_svs>; |
| + }; |
| + |
| + opp-540000000 { |
| + opp-hz = /bits/ 64 <540000000>; |
| + required-opps = <&rpmhpd_opp_svs_l1>; |
| + }; |
| + |
| + opp-810000000 { |
| + opp-hz = /bits/ 64 <810000000>; |
| + required-opps = <&rpmhpd_opp_nom>; |
| + }; |
| + }; |
| + }; |
| }; |
| |
| dispcc: clock-controller@af00000 { |
| -- |
| 2.31.1.607.g51e8a6a459-goog |
| |