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chromium / chromiumos / third_party / kernel-rebase-patches / ba418e97732e54f14a683795e612e8b91d4b5134 / . / a5e530dd5a619ae8569e2b7e8fef01e45d580c1a9dbadfab35212d23.patch
blob: 1c609f652cdbff1b56bfeece1ac99249f8763b2b [file] [log] [blame]
From d3e07ecb9f5753e0dd4dccbf151717febfe69d2b Mon Sep 17 00:00:00 2001
From: Douglas Anderson <dianders@chromium.org>
Date: Tue, 22 Sep 2020 15:23:22 -0700
Subject: [PATCH] CHROMIUM: arm64: dts: qcom: Add sc7180-coachz
Initial attempt at CoachZ device tree.
BUG=b:168569041
TEST=Compile
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Change-Id: I67b7c08df5aa26c86bf589217b461d1a27632b0d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2425146
---
arch/arm64/boot/dts/qcom/Makefile | 2 +
.../dts/qcom/sc7180-trogdor-coachz-lte.dts | 14 ++
.../boot/dts/qcom/sc7180-trogdor-coachz.dts | 225 ++++++++++++++++++
3 files changed, 241 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-lte.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 584b4c614e61..5259affb2014 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -33,6 +33,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-lte.dts
new file mode 100644
index 000000000000..33629acdd47b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-lte.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google CoachZ board device tree source
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+#include "sc7180-trogdor-coachz.dts"
+#include "sc7180-trogdor-lte-sku.dtsi"
+
+/ {
+ model = "Google CoachZ with LTE";
+ compatible = "google,coachz-sku0", "qcom,sc7180";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dts
new file mode 100644
index 000000000000..c8d08b73a49e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dts
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google CoachZ board device tree source
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180.dtsi"
+
+ap_ec_spi: &spi6 {};
+ap_h1_spi: &spi0 {};
+
+#include "sc7180-trogdor.dtsi"
+
+/ {
+ model = "Google CoachZ";
+ compatible = "google,coachz", "qcom,sc7180";
+};
+
+&alc5682 {
+ status = "disabled";
+};
+
+&ap_tp_i2c {
+ status = "disabled";
+};
+
+&ap_spi_fp {
+ status = "okay";
+};
+
+&hp_i2c {
+ status = "disabled";
+};
+
+ap_ts_pen_1v8: &i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ap_ts: touchscreen@5d {
+ compatible = "hid-over-i2c";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+ post-power-on-delay-ms = <20>;
+ hid-descr-addr = <0x0001>;
+
+ vdd-supply = <&pp3300_ts>;
+ };
+};
+
+/*
+ * There's no SAR sensor, so i2c5 is re-purposed. We leave the
+ * proximity@28 node under i2c5 (from trogdor.dtsi) since it's "disabled"
+ * and doesn't hurt.
+ */
+i2c_wlc: &i2c5 {
+ /* Currently not connected to anything; see b/168652326 */
+};
+
+&panel {
+ compatible = "boe,nv110wtm-n61";
+};
+
+&pp3300_codec {
+ status = "disabled";
+};
+
+&pp3300_dx_edp {
+ gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+};
+
+&sdhc_2 {
+ status = "okay";
+};
+
+&sn65dsi86_out {
+ data-lanes = <0 1 2 4>;
+};
+
+/* PINCTRL - modifications to sc7180-trogdor.dtsi */
+
+&en_pp3300_dx_edp {
+ pinmux {
+ pins = "gpio52";
+ };
+
+ pinconf {
+ pins = "gpio52";
+ };
+};
+
+/* PINCTRL - board-specific pinctrl */
+
+&tlmm {
+ gpio-line-names = "HUB_RST_L",
+ "AP_RAM_ID0",
+ "AP_SKU_ID2",
+ "AP_RAM_ID1",
+ "FP_TO_AP_IRQ_L",
+ "AP_RAM_ID2",
+ "UF_CAM_EN",
+ "WF_CAM_EN",
+ "TS_RESET_L",
+ "TS_INT_L",
+ "FPMCU_BOOT0",
+ "EDP_BRIJ_IRQ",
+ "AP_EDP_BKLTEN",
+ "UF_CAM_MCLK",
+ "WF_CAM_CLK",
+ "EDP_BRIJ_I2C_SDA",
+ "EDP_BRIJ_I2C_SCL",
+ "UF_CAM_SDA",
+ "UF_CAM_SCL",
+ "WF_CAM_SDA",
+ "WF_CAM_SCL",
+ "WLC_IRQ",
+ "FP_RST_L",
+ "AMP_EN",
+ "WLC_NRST",
+ "AP_SAR_SENSOR_SDA",
+ "AP_SAR_SENSOR_SCL",
+ "",
+ "",
+ "WF_CAM_RST_L",
+ "UF_CAM_RST_L",
+ "AP_BRD_ID2",
+ "BRIJ_SUSPEND",
+ "AP_BRD_ID0",
+ "AP_H1_SPI_MISO",
+ "AP_H1_SPI_MOSI",
+ "AP_H1_SPI_CLK",
+ "AP_H1_SPI_CS_L",
+ "",
+ "",
+ "",
+ "",
+ "H1_AP_INT_ODL",
+ "",
+ "UART_AP_TX_DBG_RX",
+ "UART_DBG_TX_AP_RX",
+ "",
+ "",
+ "FORCED_USB_BOOT",
+ "AMP_BCLK",
+ "AMP_LRCLK",
+ "AMP_DIN",
+ "EN_PP3300_DX_EDP",
+ "HP_BCLK",
+ "HP_LRCLK",
+ "HP_DOUT",
+ "HP_DIN",
+ "HP_MCLK",
+ "AP_SKU_ID0",
+ "AP_EC_SPI_MISO",
+ "AP_EC_SPI_MOSI",
+ "AP_EC_SPI_CLK",
+ "AP_EC_SPI_CS_L",
+ "AP_SPI_CLK",
+ "AP_SPI_MOSI",
+ "AP_SPI_MISO",
+ /*
+ * AP_FLASH_WP_L is crossystem ABI. Schematics
+ * call it BIOS_FLASH_WP_L.
+ */
+ "AP_FLASH_WP_L",
+ "",
+ "AP_SPI_CS0_L",
+ "SD_CD_ODL",
+ "",
+ "",
+ "",
+ "",
+ "FPMCU_SEL",
+ "UIM2_DATA",
+ "UIM2_CLK",
+ "UIM2_RST",
+ "UIM2_PRESENT_L",
+ "UIM1_DATA",
+ "UIM1_CLK",
+ "UIM1_RST",
+ "",
+ "DMIC_CLK_EN",
+ "HUB_EN",
+ "",
+ "AP_SPI_FP_MISO",
+ "AP_SPI_FP_MOSI",
+ "AP_SPI_FP_CLK",
+ "AP_SPI_FP_CS_L",
+ "AP_SKU_ID1",
+ "AP_RST_REQ",
+ "",
+ "AP_BRD_ID1",
+ "AP_EC_INT_L",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "EDP_BRIJ_EN",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AP_TS_PEN_I2C_SDA",
+ "AP_TS_PEN_I2C_SCL",
+ "DP_HOT_PLUG_DET",
+ "EC_IN_RW_ODL";
+};
--
2.31.1.607.g51e8a6a459-goog