| From 40d7045386b3e97ad2b470593ce0391f6fae585e Mon Sep 17 00:00:00 2001 |
| From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> |
| Date: Fri, 24 Sep 2021 12:14:39 -0700 |
| Subject: [PATCH] FROMGIT: BACKPORT: drm/i915/pxp: allocate a vcs context for |
| pxp usage |
| |
| The context is required to send the session termination commands to the |
| VCS, which will be implemented in a follow-up patch. We can also use the |
| presence of the context as a check of pxp initialization completion. |
| |
| v2: use perma-pinned context (Chris) |
| v3: rename pinned_context functions (Chris) |
| v4: split export of pinned_context functions to a separate patch (Rodrigo) |
| v10: remove inclusion of intel_gt_types.h from intel_pxp.h (Jani) |
| v13: fixed for loop pointer dereference (Vinay) |
| |
| Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> |
| Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> |
| Cc: Chris Wilson <chris@chris-wilson.co.uk> |
| Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
| Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20210924191452.1539378-5-alan.previn.teres.alexis@intel.com |
| (cherry picked from commit 3ad2dd9c4caa7330dd08244e94bec49a62fee6e4 |
| https://anongit.freedesktop.org/git/drm-intel.git drm-intel-gt-next) |
| |
| - conflict in intel_gt_types.h due to mocs not in 5.10 |
| - conflict in intel_gt.c and intel_engine.h due to migrate not being in |
| 5.10 |
| |
| BUG=b:191508777 |
| TEST=tast run <IP> video.PlayDRM* |
| |
| Signed-off-by: Juston Li <juston.li@intel.com> |
| Change-Id: Ifcaa7798b673761568e6120241398994250515ba |
| Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3203379 |
| Tested-by: Jeffrey Kardatzke <jkardatzke@google.com> |
| Reviewed-by: Jeffrey Kardatzke <jkardatzke@google.com> |
| Commit-Queue: Jeffrey Kardatzke <jkardatzke@google.com> |
| --- |
| drivers/gpu/drm/i915/Makefile | 4 ++ |
| drivers/gpu/drm/i915/gt/intel_engine.h | 2 + |
| drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++ |
| drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + |
| drivers/gpu/drm/i915/pxp/intel_pxp.c | 70 ++++++++++++++++++++++ |
| drivers/gpu/drm/i915/pxp/intel_pxp.h | 30 ++++++++++ |
| drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 17 ++++++ |
| 7 files changed, 130 insertions(+) |
| create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c |
| create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h |
| create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h |
| |
| diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile |
| --- a/drivers/gpu/drm/i915/Makefile |
| +++ b/drivers/gpu/drm/i915/Makefile |
| @@ -279,6 +279,10 @@ i915-y += \ |
| |
| i915-y += i915_perf.o |
| |
| +# Protected execution platform (PXP) support |
| +i915-$(CONFIG_DRM_I915_PXP) += \ |
| + pxp/intel_pxp.o |
| + |
| # Post-mortem debug and GPU hang state capture |
| i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o |
| i915-$(CONFIG_DRM_I915_SELFTEST) += \ |
| diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h |
| --- a/drivers/gpu/drm/i915/gt/intel_engine.h |
| +++ b/drivers/gpu/drm/i915/gt/intel_engine.h |
| @@ -174,6 +174,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) |
| #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32)) |
| #define I915_GEM_HWS_SEQNO 0x40 |
| #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) |
| +#define I915_GEM_HWS_PXP 0x60 |
| +#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32)) |
| #define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32)) |
| #define I915_GEM_HWS_SCRATCH 0x80 |
| |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c |
| --- a/drivers/gpu/drm/i915/gt/intel_gt.c |
| +++ b/drivers/gpu/drm/i915/gt/intel_gt.c |
| @@ -21,6 +21,7 @@ |
| #include "intel_uncore.h" |
| #include "intel_pm.h" |
| #include "shmem_utils.h" |
| +#include "pxp/intel_pxp.h" |
| |
| void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) |
| { |
| @@ -709,6 +710,7 @@ int intel_gt_init(struct intel_gt *gt) |
| goto err_gt; |
| |
| intel_migrate_init(>->migrate, gt); |
| + intel_pxp_init(>->pxp); |
| |
| goto out_fw; |
| err_gt: |
| @@ -745,6 +747,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt) |
| |
| intel_rps_driver_unregister(>->rps); |
| |
| + intel_pxp_fini(>->pxp); |
| + |
| /* |
| * Upon unregistering the device to prevent any new users, cancel |
| * all in-flight requests so that we can quickly unbind the active |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h |
| --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h |
| +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h |
| @@ -26,6 +26,7 @@ |
| #include "intel_rps_types.h" |
| #include "intel_migrate_types.h" |
| #include "intel_wakeref.h" |
| +#include "pxp/intel_pxp_types.h" |
| |
| struct drm_i915_private; |
| struct i915_ggtt; |
| @@ -192,6 +193,8 @@ struct intel_gt { |
| |
| unsigned long mslice_mask; |
| } info; |
| + |
| + struct intel_pxp pxp; |
| }; |
| |
| enum intel_gt_scratch_field { |
| diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c |
| new file mode 100644 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c |
| @@ -0,0 +1,70 @@ |
| +// SPDX-License-Identifier: MIT |
| +/* |
| + * Copyright(c) 2020 Intel Corporation. |
| + */ |
| +#include "intel_pxp.h" |
| +#include "gt/intel_context.h" |
| +#include "i915_drv.h" |
| + |
| +struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) |
| +{ |
| + return container_of(pxp, struct intel_gt, pxp); |
| +} |
| + |
| +static int create_vcs_context(struct intel_pxp *pxp) |
| +{ |
| + static struct lock_class_key pxp_lock; |
| + struct intel_gt *gt = pxp_to_gt(pxp); |
| + struct intel_engine_cs *engine; |
| + struct intel_context *ce; |
| + int i; |
| + |
| + /* |
| + * Find the first VCS engine present. We're guaranteed there is one |
| + * if we're in this function due to the check in has_pxp |
| + */ |
| + for (i = 0, engine = NULL; !engine; i++) |
| + engine = gt->engine_class[VIDEO_DECODE_CLASS][i]; |
| + |
| + GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS); |
| + |
| + ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, |
| + I915_GEM_HWS_PXP_ADDR, |
| + &pxp_lock, "pxp_context"); |
| + if (IS_ERR(ce)) { |
| + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n"); |
| + return PTR_ERR(ce); |
| + } |
| + |
| + pxp->ce = ce; |
| + |
| + return 0; |
| +} |
| + |
| +static void destroy_vcs_context(struct intel_pxp *pxp) |
| +{ |
| + intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce)); |
| +} |
| + |
| +void intel_pxp_init(struct intel_pxp *pxp) |
| +{ |
| + struct intel_gt *gt = pxp_to_gt(pxp); |
| + int ret; |
| + |
| + if (!HAS_PXP(gt->i915)) |
| + return; |
| + |
| + ret = create_vcs_context(pxp); |
| + if (ret) |
| + return; |
| + |
| + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); |
| +} |
| + |
| +void intel_pxp_fini(struct intel_pxp *pxp) |
| +{ |
| + if (!intel_pxp_is_enabled(pxp)) |
| + return; |
| + |
| + destroy_vcs_context(pxp); |
| +} |
| diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h |
| new file mode 100644 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h |
| @@ -0,0 +1,30 @@ |
| +/* SPDX-License-Identifier: MIT */ |
| +/* |
| + * Copyright(c) 2020, Intel Corporation. All rights reserved. |
| + */ |
| + |
| +#ifndef __INTEL_PXP_H__ |
| +#define __INTEL_PXP_H__ |
| + |
| +#include "intel_pxp_types.h" |
| + |
| +static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp) |
| +{ |
| + return pxp->ce; |
| +} |
| + |
| +#ifdef CONFIG_DRM_I915_PXP |
| +struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); |
| +void intel_pxp_init(struct intel_pxp *pxp); |
| +void intel_pxp_fini(struct intel_pxp *pxp); |
| +#else |
| +static inline void intel_pxp_init(struct intel_pxp *pxp) |
| +{ |
| +} |
| + |
| +static inline void intel_pxp_fini(struct intel_pxp *pxp) |
| +{ |
| +} |
| +#endif |
| + |
| +#endif /* __INTEL_PXP_H__ */ |
| diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h |
| new file mode 100644 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h |
| @@ -0,0 +1,17 @@ |
| +/* SPDX-License-Identifier: MIT */ |
| +/* |
| + * Copyright(c) 2020, Intel Corporation. All rights reserved. |
| + */ |
| + |
| +#ifndef __INTEL_PXP_TYPES_H__ |
| +#define __INTEL_PXP_TYPES_H__ |
| + |
| +#include <linux/types.h> |
| + |
| +struct intel_context; |
| + |
| +struct intel_pxp { |
| + struct intel_context *ce; |
| +}; |
| + |
| +#endif /* __INTEL_PXP_TYPES_H__ */ |
| -- |
| 2.33.0.1079.g6e70778dc9-goog |
| |