| From 9e08fd37c114957563d88fb9a000d1f021286ad3 Mon Sep 17 00:00:00 2001 |
| From: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> |
| Date: Thu, 29 Oct 2020 09:31:00 +0530 |
| Subject: [PATCH] FROMLIST: drm/amd/display: Tune min clk values for MPO for RV |
| |
| [Why] |
| Incorrect values were resulting in flash lines |
| when MPO was enabled and system was left idle. |
| |
| [How] |
| Increase min clk values only when MPO is enabled |
| and display is active to not affect S3 power. |
| |
| Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> |
| Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
| (am from https://patchwork.freedesktop.org/patch/397720/) |
| |
| BUG=b:163476639, b:171282557, b:170777798 |
| TEST=Pause Youtube p/b, no flash line occurs |
| |
| Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> |
| Change-Id: I7b6e8fcd94bdbacedbb7718597874ca82c855b58 |
| Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2507197 |
| Reviewed-by: Drew Davenport <ddavenport@chromium.org> |
| Reviewed-by: Sean Paul <seanpaul@chromium.org> |
| --- |
| .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 30 +++++++++++++++++-- |
| 1 file changed, 27 insertions(+), 3 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c |
| --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c |
| +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c |
| @@ -187,6 +187,17 @@ static void ramp_up_dispclk_with_dpp( |
| clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; |
| } |
| |
| +static bool is_mpo_enabled(struct dc_state *context) |
| +{ |
| + int i; |
| + |
| + for (i = 0; i < context->stream_count; i++) { |
| + if (context->stream_status[i].plane_count > 1) |
| + return true; |
| + } |
| + return false; |
| +} |
| + |
| static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, |
| struct dc_state *context, |
| bool safe_to_lower) |
| @@ -284,9 +295,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, |
| if (pp_smu->set_hard_min_fclk_by_freq && |
| pp_smu->set_hard_min_dcfclk_by_freq && |
| pp_smu->set_min_deep_sleep_dcfclk) { |
| - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); |
| - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); |
| - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz)); |
| + // Only increase clocks when display is active and MPO is enabled |
| + if (display_count && is_mpo_enabled(context)) { |
| + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, |
| + ((new_clocks->fclk_khz / 1000) * 101) / 100); |
| + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, |
| + ((new_clocks->dcfclk_khz / 1000) * 101) / 100); |
| + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, |
| + (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000); |
| + } else { |
| + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, |
| + new_clocks->fclk_khz / 1000); |
| + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, |
| + new_clocks->dcfclk_khz / 1000); |
| + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, |
| + (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000); |
| + } |
| } |
| } |
| } |
| -- |
| 2.33.0.464.g1972c5931b-goog |
| |