4de310c1579f7ebc4c0be354d073fee325f6c61daa0806b2daa12de7.patch

From 4e0f723c4b89f4f751b68b88504cd9d89212cfe2 Mon Sep 17 00:00:00 2001
From: V sujith kumar Reddy <vsujithkumar.reddy@amd.corp-partner.google.com>
Date: Fri, 7 Jul 2023 12:25:07 +0530
Subject: [PATCH] CHROMIUM: ASoC: SOF: amd: Configure MCLK 196.6 MHz and select
 lpfll as input.

Select lpfll to generate MCLK, configure the register values to get
196.6Mhz value.

BUG=b:290189450
TEST=TESTED on myst

Change-Id: Id2e34e11bf08e525d4620c23cc52936cda214cc7
Signed-off-by: V sujith kumar Reddy <vsujithkumar.reddy@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/4672740
Tested-by: Baili Deng <bailideng@google.com>
Commit-Queue: Baili Deng <bailideng@google.com>
Reviewed-by: Baili Deng <bailideng@google.com>
---
 sound/soc/sof/amd/acp.c | 59 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c
index 9e021957e199268f291f0479ef03ad6a158feef1..2a03efcc13dd26f9b6f02750a4860307e6f65d1f 100644
--- a/sound/soc/sof/amd/acp.c
+++ b/sound/soc/sof/amd/acp.c
@@ -22,6 +22,31 @@
 
 #define SECURED_FIRMWARE 1
 
+#define CLK5_CLK_PLL_PWR_REQ_N0		0X0006C2C0
+#define CLK5_SPLL_FIELD_2_N0		0X0006C114
+#define CLK5_CLK_PLL_REQ_N0		0X0006C0DC
+#define CLK5_CLK_DFSBYPASS_CONTR	0X0006C2C8
+#define CLK5_CLK_DFS_CNTL_N0		0X0006C1A4
+
+#define PLL_AUTO_STOP_REQ		BIT(4)
+#define PLL_AUTO_START_REQ		BIT(0)
+#define PLL_FRANCE_EN			BIT(4)
+#define EXIT_DPF_BYPASS_0		BIT(16)
+#define EXIT_DPF_BYPASS_1		BIT(17)
+#define CLK0_DIVIDER			0X30
+
+union clk5_pll_req_no {
+       struct {
+               u32 fb_mult_int : 9;
+               u32 reserved : 3;
+               u32 pll_spine_div : 4;
+               u32 gb_mult_frac : 16;
+       } bitfields, bits;
+       u32 clk5_pll_req_no_reg;
+};
+
+
+
 static bool enable_fw_debug;
 module_param(enable_fw_debug, bool, 0444);
 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");
@@ -58,6 +83,38 @@ static int smn_read(struct pci_dev *dev, u32 smn_addr)
 	return data;
 }
 
+void master_clock_generate(struct acp_dev_data *adata)
+{
+	struct snd_sof_dev *sdev = adata->dev;
+	union clk5_pll_req_no clk5_pll;
+	u32 data;
+
+	/* Clk5 pll register values to get mclk as 196.6MHz*/
+	clk5_pll.bits.fb_mult_int = 0x31;
+	clk5_pll.bits.pll_spine_div = 0;
+	clk5_pll.bits.gb_mult_frac = 0x26E9;
+
+	snd_sof_dsp_write(sdev, ACP_DSP_BAR, 0x105c, 0x1);
+	smn_read(adata->smn_dev, CLK5_CLK_PLL_PWR_REQ_N0, &data);
+	smn_write(adata->smn_dev, CLK5_CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_STOP_REQ);
+
+	smn_read(adata->smn_dev, CLK5_SPLL_FIELD_2_N0, &data);
+	if (data & PLL_FRANCE_EN)
+		smn_write(adata->smn_dev, CLK5_SPLL_FIELD_2_N0, data | PLL_FRANCE_EN);
+
+	smn_write(adata->smn_dev, CLK5_CLK_PLL_REQ_N0, clk5_pll.clk5_pll_req_no_reg);
+
+	smn_read(adata->smn_dev, CLK5_CLK_PLL_PWR_REQ_N0, &data);
+	smn_write(adata->smn_dev, CLK5_CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_START_REQ);
+
+	smn_read(adata->smn_dev, CLK5_CLK_DFSBYPASS_CONTR, &data);
+	smn_write(adata->smn_dev, CLK5_CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_0);
+	smn_write(adata->smn_dev, CLK5_CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_1);
+
+	smn_write(adata->smn_dev, CLK5_CLK_DFS_CNTL_N0, CLK0_DIVIDER);
+}
+
+
 static void init_dma_descriptor(struct acp_dev_data *adata)
 {
 	struct snd_sof_dev *sdev = adata->dev;
@@ -561,7 +618,7 @@ int amd_sof_acp_probe(struct snd_sof_dev *sdev)
 	}
 	adata->enable_fw_debug = enable_fw_debug;
 	acp_memory_init(sdev);
-
+	master_clock_generate(adata);
 	acp_dsp_stream_init(sdev);
 
 	return 0;
-- 
2.34.1