Merge remote-tracking branch 'upstream/chromeos-4.14' into core35-for-chromeos-4.14
Change-Id: Ib36da2b41bf0acef982f8d888835dfb6d9df73b9
diff --git a/COMMIT-QUEUE.ini b/COMMIT-QUEUE.ini
index a4d97f3..5a31f0d 100644
--- a/COMMIT-QUEUE.ini
+++ b/COMMIT-QUEUE.ini
@@ -9,4 +9,3 @@
pre-cq-configs: grunt-pre-cq
cheza-pre-cq
-subsystem: all
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl
index 640f65e..267920a 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -69,7 +69,9 @@
Contact: linuxppc-dev@lists.ozlabs.org
Description: read/write
Set the mode for prefaulting in segments into the segment table
- when performing the START_WORK ioctl. Possible values:
+ when performing the START_WORK ioctl. Only applicable when
+ running under hashed page table mmu.
+ Possible values:
none: No prefaulting (default)
work_element_descriptor: Treat the work element
descriptor as an effective address and
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index 4182ea3..f33467a 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -7,10 +7,21 @@
and the properties used by the msdc driver.
Required properties:
-- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
+- compatible: value should be either of the following.
+ "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
+ "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
+ "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
+ "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
+ "mediatek,mt7622-mmc": for MT7622 SoC
+ "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
+
+- reg: physical base address of the controller and length
- interrupts: Should contain MSDC interrupt number
-- clocks: MSDC source clock, HCLK
-- clock-names: "source", "hclk"
+- clocks: Should contain phandle for the clock feeding the MMC controller
+- clock-names: Should contain the following:
+ "source" - source clock (required)
+ "hclk" - HCLK which used for host (required)
+ "source_cg" - independent source clock gate (required for MT2712)
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
@@ -30,6 +41,10 @@
- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
If present,HS400 command responses are sampled on rising edges.
If not present,HS400 command responses are sampled on falling edges.
+- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
+ error caused by stop clock(fifo full)
+ Valid range = [0:0x7]. if not present, default value is 0.
+ applied to compatible "mediatek,mt2701-mmc".
Examples:
mmc0: mmc@11230000 {
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index bfdcdc4c..502b3b8 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -4,7 +4,12 @@
and the properties used by the sdhci-msm driver.
Required properties:
-- compatible: Should contain "qcom,sdhci-msm-v4".
+- compatible: Should contain:
+ "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
+ "qcom,sdhci-msm-v5" for sdcc versions >= 5.0
+ For SDCC version 5.0.0, MCI registers are removed from SDCC
+ interface and some registers are moved to HC. New compatible
+ string is added to support this change - "qcom,sdhci-msm-v5".
- reg: Base address and length of the register in the following order:
- Host controller register map (required)
- SD Core register map (required)
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 9ce35af..956bb04 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@
at25df321a
at25df641
at26df081a
+ mr25h128
mr25h256
mr25h10
mr25h40
diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index 8acf51a..47a6a7f 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -10,6 +10,7 @@
"brcm,bcm53128"
"brcm,bcm5365"
"brcm,bcm5395"
+ "brcm,bcm5389"
"brcm,bcm5397"
"brcm,bcm5398"
diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt
index 14335a0..bdbf87d 100644
--- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt
+++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt
@@ -46,6 +46,53 @@
Definition: Must be list of serial data lines used by this dai.
should be one or more of the 1-4 sd lines.
+ - qcom,tdm-sync-mode:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Synchronization mode.
+ 0 - Short sync bit mode
+ 1 - Long sync mode
+ 2 - Short sync slot mode
+
+ - qcom,tdm-sync-src:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Synchronization source.
+ 0 - External source
+ 1 - Internal source
+
+ - qcom,tdm-data-out:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Data out signal to drive with other masters.
+ 0 - Disable
+ 1 - Enable
+
+ - qcom,tdm-invert-sync:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Invert the sync.
+ 0 - Normal
+ 1 - Invert
+
+ - qcom,tdm-data-delay:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Number of bit clock to delay data
+ with respect to sync edge.
+ 0 - 0 bit clock cycle
+ 1 - 1 bit clock cycle
+ 2 - 2 bit clock cycle
+
+ - qcom,tdm-data-align:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Indicate how data is packed
+ within the slot. For example, 32 slot width in case of
+ sample bit width is 24.
+ 0 - MSB
+ 1 - LSB
+
= EXAMPLE
q6afe@4 {
@@ -61,6 +108,27 @@
reg = <1>;
};
+ tdm@24 {
+ reg = <24>;
+ qcom,tdm-sync-mode = <1>:
+ qcom,tdm-sync-src = <1>;
+ qcom,tdm-data-out = <0>;
+ qcom,tdm-invert-sync = <1>;
+ qcom,tdm-data-delay = <1>;
+ qcom,tdm-data-align = <0>;
+
+ };
+
+ tdm@25 {
+ reg = <25>;
+ qcom,tdm-sync-mode = <1>:
+ qcom,tdm-sync-src = <1>;
+ qcom,tdm-data-out = <0>;
+ qcom,tdm-invert-sync = <1>;
+ qcom,tdm-data-delay <1>:
+ qcom,tdm-data-align = <0>;
+ };
+
prim-mi2s-rx@16 {
reg = <16>;
qcom,sd-lines = <1 3>;
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
index 292ed89..06195e8 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
@@ -8,6 +8,7 @@
- reg: Address range of the thermal registers
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
+- #qcom,sensors: Number of sensors in tsens block
- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify
nvmem cells
diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
index 13dd237..e37557b 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -74,15 +74,6 @@
.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
:export:
-Legacy CRTC/Modeset Helper Functions Reference
-==============================================
-
-.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c
- :doc: overview
-
-.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c
- :export:
-
Simple KMS Helper Reference
===========================
@@ -163,6 +154,9 @@
.. kernel-doc:: drivers/gpu/drm/drm_panel.c
:export:
+.. kernel-doc:: drivers/gpu/drm/drm_panel_orientation_quirks.c
+ :export:
+
Display Port Helper Functions Reference
=======================================
@@ -279,15 +273,6 @@
.. kernel-doc:: drivers/gpu/drm/drm_flip_work.c
:export:
-Plane Helper Reference
-======================
-
-.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c
- :doc: overview
-
-.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c
- :export:
-
Auxiliary Modeset Helpers
=========================
@@ -305,3 +290,21 @@
.. kernel-doc:: drivers/gpu/drm/drm_gem_framebuffer_helper.c
:export:
+
+Legacy Plane Helper Reference
+=============================
+
+.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c
+ :export:
+
+Legacy CRTC/Modeset Helper Functions Reference
+==============================================
+
+.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c
+ :export:
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 3072841..2dcf5b42 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -263,14 +263,20 @@
- An atomic update is assembled and validated as an entirely free-standing pile
of structures within the :c:type:`drm_atomic_state <drm_atomic_state>`
- container. Again drivers can subclass that container for their own state
- structure tracking needs. Only when a state is committed is it applied to the
- driver and modeset objects. This way rolling back an update boils down to
- releasing memory and unreferencing objects like framebuffers.
+ container. Driver private state structures are also tracked in the same
+ structure; see the next chapter. Only when a state is committed is it applied
+ to the driver and modeset objects. This way rolling back an update boils down
+ to releasing memory and unreferencing objects like framebuffers.
Read on in this chapter, and also in :ref:`drm_atomic_helper` for more detailed
coverage of specific topics.
+Handling Driver Private State
+-----------------------------
+
+.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
+ :doc: handling driver private state
+
Atomic Mode Setting Function Reference
--------------------------------------
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 16d311e2..ac44af0 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -373,11 +373,6 @@
one of the ideas for having a shared dsi/dbi helper, abstracting away the
transport details more.
-- tinydrm_lastclose could be drm_fb_helper_lastclose. Only thing we need
- for that is to store the drm_fb_helper pointer somewhere in
- drm_device->mode_config. And then we could roll that out to all the
- drivers.
-
- tinydrm_gem_cma_prime_import_sg_table should probably go into the cma
helpers, as a _vmapped variant (since not every driver needs the vmap).
And tinydrm_gem_cma_free_object could the be merged into
@@ -391,11 +386,6 @@
a drm_device wrong. Doesn't matter, since everyone else gets it wrong
too :-)
-- With the fbdev pointer in dev->mode_config we could also make
- suspend/resume helpers entirely generic, at least if we add a
- dev->mode_config.suspend_state. We could even provide a generic pm_ops
- structure with those.
-
- also rework the drm_framebuffer_funcs->dirty hook wire-up, see above.
Contact: Noralf Trønnes, Daniel Vetter
diff --git a/Documentation/kbuild/kbuild.txt b/Documentation/kbuild/kbuild.txt
index ac2363e..82afdb7 100644
--- a/Documentation/kbuild/kbuild.txt
+++ b/Documentation/kbuild/kbuild.txt
@@ -152,15 +152,6 @@
the default option --strip-debug will be used. Otherwise,
INSTALL_MOD_STRIP value will be used as the options to the strip command.
-INSTALL_FW_PATH
---------------------------------------------------
-INSTALL_FW_PATH specifies where to install the firmware blobs.
-The default value is:
-
- $(INSTALL_MOD_PATH)/lib/firmware
-
-The value can be overridden in which case the default value is ignored.
-
INSTALL_HDR_PATH
--------------------------------------------------
INSTALL_HDR_PATH specifies where to install user space headers when
diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt
index 548d630..da1fbff 100644
--- a/Documentation/mtd/spi-nor.txt
+++ b/Documentation/mtd/spi-nor.txt
@@ -60,3 +60,6 @@
initialize the necessary fields for spi_nor{}. Please see
drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to fsl-quadspi.c
when you want to write a new driver for a SPI NOR controller.
+Another API is spi_nor_restore(), this is used to restore the status of SPI
+flash chip such as addressing mode. Call it whenever detach the driver from
+device or reboot the system.
diff --git a/Documentation/printk-formats.txt b/Documentation/printk-formats.txt
index 361789d..d1aecf5 100644
--- a/Documentation/printk-formats.txt
+++ b/Documentation/printk-formats.txt
@@ -397,11 +397,10 @@
%pC pll1
%pCn pll1
- %pCr 1560000000
For printing struct clk structures. ``%pC`` and ``%pCn`` print the name
(Common Clock Framework) or address (legacy clock framework) of the
-structure; ``%pCr`` prints the current clock rate.
+structure.
Passed by reference.
diff --git a/Makefile b/Makefile
index 59e359f..a7936ad 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
PATCHLEVEL = 14
-SUBLEVEL = 52
+SUBLEVEL = 56
EXTRAVERSION =
NAME = Petit Gorille
@@ -712,6 +712,7 @@
KBUILD_CFLAGS += $(call cc-disable-warning, duplicate-decl-specifier)
# Quiet clang warning: comparison of unsigned expression < 0 is always false
KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
+KBUILD_CFLAGS += $(call cc-disable-warning, constant-conversion)
# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
# source of a reference will be _MergedGlobals and not on of the whitelisted names.
# See modpost pattern 2
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 90a7417..4747ede6 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -96,7 +96,7 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
- dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
+ dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
dma-names = "rx", "tx";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 36983a7d..1853573 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -22,11 +22,12 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include <dt-bindings/thermal/thermal.h>
-#include "skeleton64.dtsi"
/ {
compatible = "mediatek,mt7623";
interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
cpu_opp_table: opp_table {
compatible = "operating-points-v2";
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
index 7de7045..e96c0ca 100644
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -100,6 +100,7 @@
};
memory@80000000 {
+ device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index 256c5fd..43c9d7c 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -47,6 +47,7 @@
};
memory@80000000 {
+ device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 8d9f42a..10d2fa18 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -744,13 +744,13 @@
nand0: nand@ff900000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
- compatible = "denali,denali-nand-dt";
+ compatible = "altr,socfpga-denali-nand";
reg = <0xff900000 0x100000>,
<0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0x0 0x90 0x4>;
dma-mask = <0xffffffff>;
- clocks = <&nand_clk>;
+ clocks = <&nand_x_clk>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index bead79e..791ca15c 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,8 +593,7 @@
#size-cells = <0>;
reg = <0xffda5000 0x100>;
interrupts = <0 102 4>;
- num-chipselect = <4>;
- bus-num = <0>;
+ num-cs = <4>;
/*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
@@ -633,7 +632,7 @@
nand: nand@ffb90000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+ compatible = "altr,socfpga-denali-nand";
reg = <0xffb90000 0x72000>,
<0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h
index 3b73fdc..8de1100 100644
--- a/arch/arm/include/asm/kgdb.h
+++ b/arch/arm/include/asm/kgdb.h
@@ -77,7 +77,7 @@
#define KGDB_MAX_NO_CPUS 1
#define BUFMAX 400
-#define NUMREGBYTES (DBG_MAX_REG_NUM << 2)
+#define NUMREGBYTES (GDB_MAX_REGS << 2)
#define NUMCRITREGBYTES (32 << 2)
#define _R0 0
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index 64c54c9..d71cbf5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -205,9 +205,6 @@
bus-width = <4>;
cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
max-frequency = <100000000>;
disable-wp;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
index e2c430e..d6a9e2e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
@@ -38,6 +38,10 @@
};
};
+&qupv3_id_0 {
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c2ce9fe..9c10ff5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -190,6 +190,11 @@
};
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
@@ -253,6 +258,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ status = "disabled";
i2c0: i2c@880000 {
compatible = "qcom,geni-i2c";
diff --git a/arch/arm64/configs/chromiumos-container-vm-arm64_defconfig b/arch/arm64/configs/chromiumos-container-vm-arm64_defconfig
index 673208d..95478c7 100644
--- a/arch/arm64/configs/chromiumos-container-vm-arm64_defconfig
+++ b/arch/arm64/configs/chromiumos-container-vm-arm64_defconfig
@@ -1,17 +1,19 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm64 4.4.44 Kernel Configuration
+# Linux/arm64 4.14.55 Kernel Configuration
#
CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_MMU=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -21,7 +23,7 @@
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
-CONFIG_HAVE_GENERIC_RCU_GUP=y
+CONFIG_HAVE_GENERIC_GUP=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
@@ -31,9 +33,12 @@
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
@@ -64,6 +69,7 @@
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_IRQ_DOMAIN=y
@@ -74,6 +80,8 @@
# CONFIG_IRQ_DOMAIN_DEBUG is not set
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
@@ -95,7 +103,7 @@
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-# CONFIG_SCHED_WALT is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
@@ -105,30 +113,37 @@
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
-# CONFIG_TASKS_RCU is not set
+CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU=y
CONFIG_RCU_STALL_COMMON=y
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_EXPEDITE_BOOT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
# CONFIG_BUILD_BIN2C is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_CPUACCT=y
+CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
-# CONFIG_CGROUP_PERF is not set
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_DEBUG=y
+CONFIG_SOCK_CGROUP_DATA=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
@@ -137,11 +152,10 @@
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SCHED_TUNE is not set
-# CONFIG_DEFAULT_USE_ENERGY_AWARE is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@@ -154,13 +168,18 @@
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_POSIX_TIMERS=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_PRINTK=y
+CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
@@ -174,7 +193,7 @@
CONFIG_MEMBARRIER=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
+# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
@@ -183,10 +202,14 @@
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_SYSTEM_DATA_VERIFICATION is not set
# CONFIG_PROFILING is not set
@@ -194,10 +217,16 @@
# CONFIG_UPROBES is not set
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
@@ -205,29 +234,46 @@
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
+CONFIG_HAVE_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGINS is not set
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_CC_STACKPROTECTOR=y
# CONFIG_CC_STACKPROTECTOR_NONE is not set
# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_THIN_ARCHIVES=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=24
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16
+# CONFIG_HAVE_ARCH_HASH is not set
+# CONFIG_ISA_BUS_API is not set
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
+# CONFIG_CPU_NO_EFFICIENT_FFS is not set
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+# CONFIG_REFCOUNT_FULL is not set
#
# GCOV-based kernel profiling
@@ -241,10 +287,16 @@
# CONFIG_MODULES is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
+CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
# CONFIG_BLK_CMDLINE_PARSER is not set
+# CONFIG_BLK_WBT is not set
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BLK_SED_OPAL is not set
#
# Partition Types
@@ -270,6 +322,8 @@
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
CONFIG_BLOCK_COMPAT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
#
# IO Schedulers
@@ -282,6 +336,9 @@
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
@@ -292,21 +349,35 @@
#
# Platform selection
#
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
-# CONFIG_ARCH_EXYNOS7 is not set
+# CONFIG_ARCH_BRCMSTB is not set
+# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_LAYERSCAPE is not set
+# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VULCAN is not set
# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
#
@@ -316,6 +387,19 @@
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIE_ECRC is not set
+# CONFIG_PCIEAER_INJECT is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+# CONFIG_PCIEASPM_DEFAULT is not set
+CONFIG_PCIEASPM_POWERSAVE=y
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_PTM is not set
CONFIG_PCI_BUS_ADDR_T_64BIT=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
@@ -325,29 +409,36 @@
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# DesignWare PCI Core Support
+#
+# CONFIG_PCIE_DW_PLAT is not set
+# CONFIG_PCI_HISI is not set
+# CONFIG_PCIE_KIRIN is not set
#
# PCI host controller drivers
#
# CONFIG_PCI_HOST_GENERIC is not set
-# CONFIG_PCIE_IPROC is not set
-# CONFIG_PCI_HISI is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIE_ECRC is not set
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEBUG is not set
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_POWERSAVE=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_PCI_XGENE is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+
+#
+# PCI Endpoint
+#
+# CONFIG_PCI_ENDPOINT is not set
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
#
# Kernel Features
#
-CONFIG_RANDOMIZE_BASE=y
#
# ARM errata workarounds via the alternatives framework
@@ -358,9 +449,17 @@
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
# CONFIG_CAVIUM_ERRATUM_27456 is not set
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
@@ -372,6 +471,7 @@
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
+# CONFIG_NUMA is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
@@ -382,6 +482,7 @@
CONFIG_HZ_1000=y
CONFIG_HZ=1000
CONFIG_SCHED_HRTICK=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
@@ -389,7 +490,6 @@
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_SELECT_MEMORY_MODEL=y
@@ -408,12 +508,14 @@
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_MMAP_NOEXEC_TAINT=0
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+# CONFIG_MEMORY_FAILURE is not set
# CONFIG_TRANSPARENT_HUGEPAGE is not set
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
# CONFIG_CLEANCACHE is not set
# CONFIG_CMA is not set
# CONFIG_ZPOOL is not set
@@ -424,13 +526,21 @@
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_LOW_MEM_NOTIFY=y
+# CONFIG_PERCPU_STATS is not set
CONFIG_SECCOMP=y
+# CONFIG_PARAVIRT is not set
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
#
# ARMv8.1 architectural features
@@ -438,19 +548,30 @@
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
# CONFIG_ARM64_LSE_ATOMICS is not set
+CONFIG_ARM64_VHE=y
+
+#
+# ARMv8.2 architectural features
+#
+CONFIG_ARM64_UAO=y
+# CONFIG_ARM64_PMEM is not set
+CONFIG_RELOCATABLE=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
#
# Boot options
#
CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_FORCE is not set
# CONFIG_EFI is not set
-# CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_HAVE_AOUT is not set
@@ -465,7 +586,6 @@
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
-# CONFIG_WAKELOCK is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
@@ -478,10 +598,10 @@
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_DPM_WATCHDOG is not set
-CONFIG_PM_OPP=y
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_CPU_PM=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
@@ -492,6 +612,7 @@
# CPU Idle
#
CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_DT_IDLE_STATES=y
@@ -506,23 +627,21 @@
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHED is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_CPU_FREQ_GOV_SCHED is not set
+# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
# CONFIG_CPU_BOOST is not set
#
@@ -532,6 +651,7 @@
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+# CONFIG_QORIQ_CPUFREQ is not set
CONFIG_NET=y
CONFIG_NET_INGRESS=y
@@ -542,6 +662,7 @@
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
@@ -556,9 +677,9 @@
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
-# CONFIG_NET_IP_TUNNEL is not set
+CONFIG_NET_IP_TUNNEL=y
CONFIG_SYN_COOKIES=y
-# CONFIG_NET_UDP_TUNNEL is not set
+CONFIG_NET_UDP_TUNNEL=y
# CONFIG_NET_FOU is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
@@ -568,7 +689,6 @@
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
-CONFIG_INET_LRO=y
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
@@ -590,16 +710,19 @@
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
# CONFIG_IPV6_SIT is not set
# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_GRE is not set
+# CONFIG_IPV6_FOU is not set
+# CONFIG_IPV6_FOU_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_NETLABEL is not set
CONFIG_NETWORK_SECMARK=y
# CONFIG_NET_PTP_CLASSIFY is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
#
# Core Netfilter Configuration
@@ -708,6 +831,7 @@
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
CONFIG_NETFILTER_XT_TARGET_TEE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
@@ -878,6 +1002,9 @@
# CONFIG_NF_SOCKET_IPV6 is not set
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_CHAIN_ROUTE_IPV6=y
+CONFIG_NFT_CHAIN_NAT_IPV6=y
+CONFIG_NFT_MASQ_IPV6=y
+CONFIG_NFT_REDIR_IPV6=y
CONFIG_NFT_REJECT_IPV6=y
CONFIG_NFT_DUP_IPV6=y
# CONFIG_NFT_FIB_IPV6 is not set
@@ -885,10 +1012,7 @@
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_NF_NAT_IPV6=y
-CONFIG_NFT_CHAIN_NAT_IPV6=y
CONFIG_NF_NAT_MASQUERADE_IPV6=y
-CONFIG_NFT_MASQ_IPV6=y
-CONFIG_NFT_REDIR_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_AH=y
CONFIG_IP6_NF_MATCH_EUI64=y
@@ -988,6 +1112,7 @@
# CONFIG_NET_SCH_PIE is not set
# CONFIG_NET_SCH_INGRESS is not set
# CONFIG_NET_SCH_PLUG is not set
+# CONFIG_NET_SCH_DEFAULT is not set
#
# Classification
@@ -1004,12 +1129,14 @@
# CONFIG_NET_CLS_CGROUP is not set
# CONFIG_NET_CLS_BPF is not set
# CONFIG_NET_CLS_FLOWER is not set
+# CONFIG_NET_CLS_MATCHALL is not set
# CONFIG_NET_EMATCH is not set
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
# CONFIG_GACT_PROB is not set
# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_SAMPLE is not set
# CONFIG_NET_ACT_IPT is not set
# CONFIG_NET_ACT_NAT is not set
# CONFIG_NET_ACT_PEDIT is not set
@@ -1019,6 +1146,9 @@
# CONFIG_NET_ACT_VLAN is not set
# CONFIG_NET_ACT_BPF is not set
# CONFIG_NET_ACT_CONNMARK is not set
+# CONFIG_NET_ACT_SKBMOD is not set
+# CONFIG_NET_ACT_IFE is not set
+# CONFIG_NET_ACT_TUNNEL_KEY is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
# CONFIG_DNS_RESOLVER is not set
@@ -1027,12 +1157,13 @@
CONFIG_VSOCKETS=y
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_VIRTIO_VSOCKETS_COMMON=y
-# CONFIG_NETLINK_MMAP is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
# CONFIG_NET_SWITCHDEV is not set
-# CONFIG_NET_L3_MASTER_DEV is not set
+CONFIG_NET_L3_MASTER_DEV=y
+# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
@@ -1048,9 +1179,10 @@
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_STREAM_PARSER is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
# CONFIG_LIB80211 is not set
@@ -1061,7 +1193,6 @@
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
-CONFIG_RFKILL_PM=y
# CONFIG_RFKILL_INPUT is not set
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
@@ -1069,14 +1200,19 @@
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
-CONFIG_HAVE_BPF_JIT=y
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+# CONFIG_NET_DEVLINK is not set
+CONFIG_MAY_USE_DEVLINK=y
+CONFIG_HAVE_EBPF_JIT=y
#
# Device Drivers
#
CONFIG_ARM_AMBA=y
-# CONFIG_TEGRA_AHB is not set
#
# Generic Driver Options
@@ -1095,27 +1231,36 @@
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
# CONFIG_DMA_SHARED_BUFFER is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
#
# Bus devices
#
# CONFIG_ARM_CCI400_PMU is not set
-# CONFIG_ARM_CCI500_PMU is not set
+# CONFIG_ARM_CCI5xx_PMU is not set
# CONFIG_ARM_CCN is not set
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_SIMPLE_PM_BUS is not set
# CONFIG_VEXPRESS_CONFIG is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_MTD=y
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AR7_PARTS is not set
#
+# Partition parsers
+#
+
+#
# User Modules And Translation Layers
#
# CONFIG_MTD_BLOCK is not set
@@ -1168,7 +1313,6 @@
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
-# CONFIG_MTD_NAND_IDS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
@@ -1191,7 +1335,6 @@
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_MTD=y
CONFIG_OF_RESERVED_MEM=y
# CONFIG_OF_OVERLAY is not set
# CONFIG_PARPORT is not set
@@ -1199,7 +1342,6 @@
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_ZRAM is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
@@ -1214,54 +1356,39 @@
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=y
+# CONFIG_VIRTIO_BLK_SCSI is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set
# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_NVME_FC is not set
#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
-# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_BMP085_I2C is not set
-# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_SRAM is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_CB710_CORE is not set
#
# Texas Instruments shared transport line discipline
#
-# CONFIG_SENSORS_LIS3_I2C is not set
#
# Altera FPGA firmware download module
#
-# CONFIG_ALTERA_STAPL is not set
#
# Intel MIC Bus Driver
@@ -1272,6 +1399,10 @@
#
#
+# VOP Bus Driver
+#
+
+#
# Intel MIC Host Driver
#
@@ -1286,11 +1417,15 @@
#
# Intel MIC Coprocessor State Management (COSM) Drivers
#
+
+#
+# VOP Driver
+#
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_CXL_BASE is not set
-# CONFIG_CXL_KERNEL_API is not set
-# CONFIG_CXL_EEH is not set
+# CONFIG_CXL_AFU_DRIVER_OPS is not set
+# CONFIG_CXL_LIB is not set
#
# SCSI device support
@@ -1341,6 +1476,7 @@
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
@@ -1351,6 +1487,7 @@
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_SNIC is not set
@@ -1474,9 +1611,9 @@
# CONFIG_DM_MQ_DEFAULT is not set
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=y
+# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=y
CONFIG_DM_PERSISTENT_DATA=y
-# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set
CONFIG_DM_CRYPT=y
CONFIG_DM_VERITY_CHROMEOS=y
# CONFIG_DM_SNAPSHOT is not set
@@ -1491,8 +1628,12 @@
# CONFIG_DM_UEVENT is not set
# CONFIG_DM_FLAKEY is not set
CONFIG_DM_VERITY=y
+# CONFIG_DM_VERITY_HASH_PREFETCH_MIN_SIZE_128 is not set
+CONFIG_DM_VERITY_HASH_PREFETCH_MIN_SIZE=1
+# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_DM_INTEGRITY is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set
@@ -1511,7 +1652,12 @@
# CONFIG_NET_TEAM is not set
CONFIG_MACVLAN=y
CONFIG_MACVTAP=y
-# CONFIG_VXLAN is not set
+CONFIG_IPVLAN=y
+CONFIG_IPVTAP=y
+CONFIG_VXLAN=y
+# CONFIG_GENEVE is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
@@ -1530,11 +1676,11 @@
#
# Distributed Switch Architecture drivers
#
-# CONFIG_NET_DSA_MV88E6XXX is not set
-# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
# CONFIG_ETHERNET is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
+# CONFIG_MDIO_DEVICE is not set
+# CONFIG_MDIO_BUS is not set
# CONFIG_PHYLIB is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
@@ -1568,25 +1714,13 @@
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_KEYRESET=y
-CONFIG_INPUT_KEYCOMBO=y
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_TCA8418 is not set
-# CONFIG_KEYBOARD_LM8333 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
@@ -1594,17 +1728,11 @@
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
# CONFIG_MOUSE_SERIAL is not set
-CONFIG_MOUSE_CYAPA=y
-CONFIG_MOUSE_ELAN_I2C=y
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MOUSE_SYNAPTICS_I2C is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
@@ -1625,66 +1753,36 @@
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
-# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_INPUT_TABLET=y
# CONFIG_TABLET_SERIAL_WACOM4 is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
-CONFIG_TOUCHSCREEN_ATMEL_MXT=y
-# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GOODIX is not set
-# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
-CONFIG_TOUCHSCREEN_ELAN=y
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MMS114 is not set
-# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-# CONFIG_TOUCHSCREEN_TSC2004 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_SX8654 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
-# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
-# CONFIG_INPUT_MMA8450 is not set
-# CONFIG_INPUT_MPU3050 is not set
-CONFIG_INPUT_KEYCHORD=y
-# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_UINPUT is not set
-# CONFIG_INPUT_GPIO is not set
-# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_CMA3000 is not set
-# CONFIG_INPUT_DRV2665_HAPTICS is not set
-# CONFIG_INPUT_DRV2667_HAPTICS is not set
+# CONFIG_RMI4_CORE is not set
#
# Hardware I/O ports
@@ -1703,14 +1801,12 @@
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_DEVMEM=y
-# CONFIG_DEVKMEM is not set
#
# Serial drivers
@@ -1718,16 +1814,19 @@
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
-# CONFIG_SERIAL_8250_INGENIC is not set
-# CONFIG_SERIAL_8250_MID is not set
+# CONFIG_SERIAL_8250_MOXA is not set
+CONFIG_SERIAL_OF_PLATFORM=y
#
# Non-8250 serial port support
@@ -1740,9 +1839,7 @@
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
-CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_SERIAL_SCCNXP is not set
-# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
@@ -1750,6 +1847,7 @@
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
@@ -1758,7 +1856,7 @@
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_HW_RANDOM_TPM=y
+CONFIG_HW_RANDOM_CAVIUM=y
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
@@ -1767,13 +1865,10 @@
#
# CONFIG_RAW_DRIVER is not set
CONFIG_TCG_TPM=y
-# CONFIG_TCG_TIS_I2C_ATMEL is not set
-CONFIG_TCG_TIS_I2C_INFINEON=y
-# CONFIG_TCG_TIS_I2C_NUVOTON is not set
+CONFIG_HW_RANDOM_TPM=y
+# CONFIG_TCG_TIS is not set
# CONFIG_TCG_ATMEL is not set
-# CONFIG_TCG_CR50_I2C is not set
# CONFIG_TCG_VTPM_PROXY is not set
-# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
CONFIG_DEVPORT=y
# CONFIG_XILLYBUS is not set
@@ -1781,17 +1876,12 @@
# I2C support
#
# CONFIG_I2C is not set
-
-#
-# PPS support
-#
+# CONFIG_SPI is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
# CONFIG_PPS is not set
#
-# PPS generators support
-#
-
-#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set
@@ -1799,36 +1889,29 @@
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
+# CONFIG_POWER_AVS is not set
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_RESET_XGENE is not set
+# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_LP8727 is not set
-# CONFIG_CHARGER_BQ2415X is not set
-# CONFIG_CHARGER_SMB347 is not set
-# CONFIG_BATTERY_GAUGE_LTC2941 is not set
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_RESTART is not set
-# CONFIG_POWER_RESET_XGENE is not set
-# CONFIG_POWER_RESET_SYSCON is not set
-# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
-# CONFIG_POWER_AVS is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+# CONFIG_WATCHDOG_SYSFS is not set
#
# Watchdog Device Drivers
@@ -1836,18 +1919,23 @@
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
-# CONFIG_BCM7038_WDT is not set
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
CONFIG_SSB_POSSIBLE=y
#
@@ -1855,90 +1943,45 @@
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
# CONFIG_BCMA is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_MFD_AS3722 is not set
-# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
-# CONFIG_MFD_BCM590XX is not set
-# CONFIG_MFD_AXP20X is not set
# CONFIG_MFD_CROS_EC is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-# CONFIG_MFD_DA9062 is not set
-# CONFIG_MFD_DA9063 is not set
-# CONFIG_MFD_DA9150 is not set
-# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
-# CONFIG_MFD_88PM800 is not set
-# CONFIG_MFD_88PM805 is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_MAX14577 is not set
-# CONFIG_MFD_MAX77686 is not set
-# CONFIG_MFD_MAX77693 is not set
-# CONFIG_MFD_MAX77843 is not set
-# CONFIG_MFD_MAX8907 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
-# CONFIG_MFD_MENF21BMC is not set
-# CONFIG_MFD_RETU is not set
-# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RTSX_PCI is not set
-# CONFIG_MFD_RT5033 is not set
-# CONFIG_MFD_RC5T583 is not set
-# CONFIG_MFD_RK808 is not set
-# CONFIG_MFD_RN5T618 is not set
-# CONFIG_MFD_SEC_CORE is not set
-# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_SKY81452 is not set
-# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
-# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
-# CONFIG_MFD_LP3943 is not set
-# CONFIG_MFD_LP8788 is not set
-# CONFIG_MFD_PALMAS is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS65090 is not set
-# CONFIG_MFD_TPS65217 is not set
-# CONFIG_MFD_TPS65218 is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS80031 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TWL6040_CORE is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_LM3533 is not set
-# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_VX855 is not set
-# CONFIG_MFD_ARIZONA_I2C is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
# CONFIG_REGULATOR is not set
+CONFIG_RC_CORE=y
+CONFIG_RC_MAP=y
+CONFIG_RC_DECODERS=y
+# CONFIG_LIRC is not set
+CONFIG_IR_NEC_DECODER=y
+CONFIG_IR_RC5_DECODER=y
+CONFIG_IR_RC6_DECODER=y
+CONFIG_IR_JVC_DECODER=y
+CONFIG_IR_SONY_DECODER=y
+CONFIG_IR_SANYO_DECODER=y
+CONFIG_IR_SHARP_DECODER=y
+CONFIG_IR_MCE_KBD_DECODER=y
+CONFIG_IR_XMP_DECODER=y
+# CONFIG_RC_DEVICES is not set
# CONFIG_MEDIA_SUPPORT is not set
#
@@ -1948,15 +1991,21 @@
# CONFIG_DRM is not set
#
-# ARM GPU Configuration
+# ACP (Audio CoProcessor) Configuration
#
-# CONFIG_MALI_MIDGARD is not set
+
+#
+# AMD Library routines
+#
+# CONFIG_CHASH is not set
+# CONFIG_DRM_LIB_RANDOM is not set
#
# Frame buffer Devices
#
# CONFIG_FB is not set
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
#
# Console display driver support
@@ -1964,10 +2013,6 @@
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_LOGO is not set
# CONFIG_SOUND is not set
#
@@ -1989,6 +2034,7 @@
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
CONFIG_HID_CHICONY=y
+# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
@@ -2001,15 +2047,18 @@
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=y
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTI is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
@@ -2027,16 +2076,12 @@
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_WACOM is not set
+# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
-
-#
-# I2C HID support
-#
-# CONFIG_I2C_HID is not set
+# CONFIG_HID_ALPS is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_UWB is not set
@@ -2054,6 +2099,7 @@
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_NVMEM=y
#
# RTC interfaces
@@ -2067,39 +2113,16 @@
#
# I2C RTC drivers
#
-# CONFIG_RTC_DRV_ABB5ZES3 is not set
-# CONFIG_RTC_DRV_ABX80X is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_HYM8563 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_ISL12057 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF2127 is not set
-# CONFIG_RTC_DRV_PCF8523 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF85063 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-# CONFIG_RTC_DRV_RV8803 is not set
#
# SPI RTC drivers
#
#
+# SPI and I2C RTC drivers
+#
+
+#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
@@ -2123,12 +2146,19 @@
#
CONFIG_RTC_DRV_PL030=y
# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_SNVS is not set
+# CONFIG_RTC_DRV_R7301 is not set
#
# HID Sensor RTC drivers
#
# CONFIG_DMADEVICES is not set
+
+#
+# DMABUF options
+#
+# CONFIG_SYNC_FILE is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
@@ -2141,6 +2171,7 @@
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=y
+# CONFIG_VIRTIO_INPUT is not set
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VIRTIO_WL=y
@@ -2148,35 +2179,34 @@
#
# Microsoft Hyper-V guest support
#
+# CONFIG_HYPERV_TSCPAGE is not set
CONFIG_STAGING=y
+# CONFIG_IRDA is not set
+# CONFIG_COMEDI is not set
# CONFIG_RTS5208 is not set
-# CONFIG_FB_SM750 is not set
-# CONFIG_FB_XGI is not set
#
# Speakup console speech
#
# CONFIG_SPEAKUP is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
# CONFIG_STAGING_MEDIA is not set
#
# Android
#
# CONFIG_ASHMEM is not set
-# CONFIG_ANDROID_TIMED_OUTPUT is not set
-# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
-# CONFIG_SYNC is not set
# CONFIG_ION is not set
-# CONFIG_FIQ_DEBUGGER is not set
-# CONFIG_FIQ_WATCHDOG is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_DGNC is not set
-# CONFIG_DGAP is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
-# CONFIG_FSL_MC_BUS is not set
# CONFIG_MOST is not set
+# CONFIG_GREYBUS is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+
+#
+# USB Power Delivery and Type-C drivers
+#
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
CONFIG_CLKDEV_LOOKUP=y
@@ -2187,26 +2217,25 @@
# Common Clock Framework
#
# CONFIG_COMMON_CLK_VERSATILE is not set
-# CONFIG_COMMON_CLK_SI5351 is not set
-# CONFIG_COMMON_CLK_SI514 is not set
-# CONFIG_COMMON_CLK_SI570 is not set
-# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_CLK_HSDK is not set
# CONFIG_CLK_QORIQ is not set
CONFIG_COMMON_CLK_XGENE=y
+# CONFIG_COMMON_CLK_NXP is not set
# CONFIG_COMMON_CLK_PXA is not set
-# CONFIG_COMMON_CLK_CDCE706 is not set
-
-#
-# Hardware Spinlock drivers
-#
+# CONFIG_COMMON_CLK_PIC32 is not set
+# CONFIG_HWSPINLOCK is not set
#
# Clock Source drivers
#
-CONFIG_CLKSRC_OF=y
-CONFIG_CLKSRC_PROBE=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_HISILICON_ERRATUM_161010101=y
+CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_ARM_TIMER_SP804 is not set
# CONFIG_ATMEL_PIT is not set
# CONFIG_SH_TIMER_CMT is not set
@@ -2215,9 +2244,11 @@
# CONFIG_EM_TIMER_STI is not set
CONFIG_MAILBOX=y
# CONFIG_ARM_MHU is not set
+# CONFIG_PLATFORM_MHU is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
+# CONFIG_BCM_FLEXRM_MBOX is not set
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
@@ -2235,15 +2266,33 @@
#
# Remoteproc drivers
#
-# CONFIG_STE_MODEM_RPROC is not set
+# CONFIG_REMOTEPROC is not set
#
# Rpmsg drivers
#
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
#
# SOC (System On Chip) specific Drivers
#
+
+#
+# Amlogic SoC drivers
+#
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_SOC_BRCMSTB is not set
+
+#
+# i.MX SoC drivers
+#
+
+#
+# Qualcomm SoC drivers
+#
# CONFIG_SUNXI_SRAM is not set
# CONFIG_SOC_TI is not set
# CONFIG_PM_DEVFREQ is not set
@@ -2255,6 +2304,7 @@
# CONFIG_PWM is not set
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
@@ -2267,10 +2317,10 @@
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_XGENE is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
-# CONFIG_BCM_KONA_USB2_PHY is not set
-# CONFIG_PHY_XGENE is not set
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set
@@ -2279,38 +2329,51 @@
#
CONFIG_ARM_PMU=y
CONFIG_RAS=y
-# CONFIG_THUNDERBOLT is not set
#
# Android
#
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# CONFIG_LIBNVDIMM is not set
+CONFIG_DAX=y
CONFIG_NVMEM=y
# CONFIG_STM is not set
-# CONFIG_STM_DUMMY is not set
-# CONFIG_STM_SOURCE_CONSOLE is not set
# CONFIG_INTEL_TH is not set
+# CONFIG_FPGA is not set
#
-# FPGA Configuration Support
+# FSI support
#
-# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_TEE is not set
+CONFIG_PM_OPP=y
+# CONFIG_PKGLIST is not set
#
# Firmware Drivers
#
CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_PSCI_CHECKER is not set
+# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_FW_CFG_SYSFS is not set
CONFIG_HAVE_ARM_SMCCC=y
# CONFIG_GOOGLE_FIRMWARE is not set
+# CONFIG_MESON_SM is not set
+
+#
+# Tegra firmware driver
+#
# CONFIG_ACPI is not set
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
@@ -2328,12 +2391,20 @@
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
CONFIG_BTRFS_FS=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
CONFIG_FS_DAX=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_FS_ENCRYPTION=y
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
@@ -2379,6 +2450,7 @@
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
@@ -2388,7 +2460,6 @@
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
-# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
@@ -2401,6 +2472,7 @@
# CONFIG_SQUASHFS_LZ4 is not set
CONFIG_SQUASHFS_LZO=y
# CONFIG_SQUASHFS_XZ is not set
+# CONFIG_SQUASHFS_ZSTD is not set
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
@@ -2412,6 +2484,9 @@
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
+CONFIG_PSTORE_ZLIB_COMPRESS=y
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=y
@@ -2501,6 +2576,7 @@
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
@@ -2529,6 +2605,7 @@
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
+CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_DEBUG_KERNEL=y
#
@@ -2536,6 +2613,8 @@
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
@@ -2543,6 +2622,8 @@
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
@@ -2556,26 +2637,21 @@
#
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
-CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU=y
-CONFIG_HARDLOCKUP_DETECTOR=y
-CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
-CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=1
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
+# CONFIG_WQ_WATCHDOG is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
-# CONFIG_PANIC_ON_RT_THROTTLING is not set
CONFIG_SCHEDSTATS=y
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_DEBUG_TIMEKEEPING is not set
-CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
#
@@ -2591,7 +2667,9 @@
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_HAVE_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_BUGVERBOSE=y
@@ -2605,15 +2683,18 @@
# RCU Debugging
#
# CONFIG_PROVE_RCU is not set
-# CONFIG_SPARSE_RCU_POINTER is not set
# CONFIG_TORTURE_TEST is not set
+# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
@@ -2622,33 +2703,46 @@
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
#
# Runtime Testing
#
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_SORT is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_UUID is not set
# CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_TEST_HASH is not set
# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_MEMTEST is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
-CONFIG_ERROR_ON_WARNING=y
-# CONFIG_ARM64_PTDUMP is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
+# CONFIG_UBSAN is not set
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_ERROR_ON_WARNING=y
+# CONFIG_ARM64_PTDUMP_CORE is not set
+# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
-CONFIG_DEBUG_RODATA=y
+# CONFIG_DEBUG_WX is not set
CONFIG_DEBUG_ALIGN_RODATA=y
# CONFIG_CORESIGHT is not set
@@ -2656,18 +2750,24 @@
# Security options
#
CONFIG_KEYS=y
+CONFIG_KEYS_COMPAT=y
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_TRUSTED_KEYS is not set
CONFIG_ENCRYPTED_KEYS=y
+# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
CONFIG_SECURITY=y
+# CONFIG_SECURITY_WRITABLE_HOOKS is not set
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
@@ -2676,10 +2776,10 @@
CONFIG_SECURITY_SELINUX_PERMISSIVE_DONTAUDIT=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
-# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_SECURITY_LOADPIN is not set
CONFIG_SECURITY_YAMA=y
CONFIG_SECURITY_CHROMIUMOS=y
# CONFIG_SECURITY_CHROMIUMOS_NO_SYMLINK_MOUNT is not set
@@ -2696,7 +2796,7 @@
CONFIG_DEFAULT_SECURITY="selinux"
CONFIG_ARCH_HAS_ALT_SYSCALL=y
CONFIG_ALT_SYSCALL=y
-CONFIG_KEYS_COMPAT=y
+CONFIG_XOR_BLOCKS=y
CONFIG_CRYPTO=y
#
@@ -2713,9 +2813,12 @@
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_ACOMP2=y
# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_ECDH is not set
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
@@ -2728,7 +2831,8 @@
CONFIG_CRYPTO_CRYPTD=y
# CONFIG_CRYPTO_MCRYPTD is not set
CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_ABLK_HELPER=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_ENGINE=y
#
# Authenticated Encryption with Associated Data
@@ -2777,6 +2881,7 @@
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
@@ -2784,6 +2889,7 @@
# Ciphers
#
CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_BLOWFISH is not set
@@ -2804,7 +2910,6 @@
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
@@ -2824,28 +2929,39 @@
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
# CONFIG_CRYPTO_DEV_CCP is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
+CONFIG_CRYPTO_DEV_VIRTIO=y
# CONFIG_ASYMMETRIC_KEY_TYPE is not set
#
# Certificates for signature checking
#
-# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+# CONFIG_CRYPTO_SHA512_ARM64 is not set
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
+# CONFIG_CRYPTO_CRC32_ARM64_CE is not set
+CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_CRC32_ARM64=y
+# CONFIG_CRYPTO_CHACHA20_NEON is not set
+# CONFIG_CRYPTO_AES_ARM64_BS is not set
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
+CONFIG_RAID6_PQ=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_RATIONAL=y
@@ -2865,16 +2981,21 @@
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC4 is not set
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
# CONFIG_CRC8 is not set
+CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
@@ -2888,22 +3009,27 @@
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
+# CONFIG_DMA_NOOP_OPS is not set
+# CONFIG_DMA_VIRT_OPS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
+# CONFIG_IRQ_POLL is not set
CONFIG_LIBFDT=y
-CONFIG_FONT_SUPPORT=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
# CONFIG_SG_SPLIT is not set
+CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_SBITMAP=y
+# CONFIG_STRING_SELFTEST is not set
diff --git a/arch/arm64/include/asm/simd.h b/arch/arm64/include/asm/simd.h
index fa8b3fe..6495cc5 100644
--- a/arch/arm64/include/asm/simd.h
+++ b/arch/arm64/include/asm/simd.h
@@ -29,20 +29,15 @@
static __must_check inline bool may_use_simd(void)
{
/*
- * The raw_cpu_read() is racy if called with preemption enabled.
- * This is not a bug: kernel_neon_busy is only set when
- * preemption is disabled, so we cannot migrate to another CPU
- * while it is set, nor can we migrate to a CPU where it is set.
- * So, if we find it clear on some CPU then we're guaranteed to
- * find it clear on any CPU we could migrate to.
- *
- * If we are in between kernel_neon_begin()...kernel_neon_end(),
- * the flag will be set, but preemption is also disabled, so we
- * can't migrate to another CPU and spuriously see it become
- * false.
+ * kernel_neon_busy is only set while preemption is disabled,
+ * and is clear whenever preemption is enabled. Since
+ * this_cpu_read() is atomic w.r.t. preemption, kernel_neon_busy
+ * cannot change under our feet -- if it's set we cannot be
+ * migrated, and if it's clear we cannot be migrated to a CPU
+ * where it is set.
*/
return !in_irq() && !irqs_disabled() && !in_nmi() &&
- !raw_cpu_read(kernel_neon_busy);
+ !this_cpu_read(kernel_neon_busy);
}
#else /* ! CONFIG_KERNEL_MODE_NEON */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 345d4e5..718822a 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -877,7 +877,7 @@
__kpti_forced = enabled ? 1 : -1;
return 0;
}
-__setup("kpti=", parse_kpti);
+early_param("kpti", parse_kpti);
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
static const struct arm64_cpu_capabilities arm64_features[] = {
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 0bdc96c..43442b3 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -676,11 +676,12 @@
unsigned long continue_addr = 0, restart_addr = 0;
int retval = 0;
struct ksignal ksig;
+ bool syscall = in_syscall(regs);
/*
* If we were from a system call, check for system call restarting...
*/
- if (in_syscall(regs)) {
+ if (syscall) {
continue_addr = regs->pc;
restart_addr = continue_addr - (compat_thumb_mode(regs) ? 2 : 4);
retval = regs->regs[0];
@@ -732,7 +733,7 @@
* Handle restarting a different system call. As above, if a debugger
* has chosen to restart at a different PC, ignore the restart.
*/
- if (in_syscall(regs) && regs->pc == restart_addr) {
+ if (syscall && regs->pc == restart_addr) {
if (retval == -ERESTART_RESTARTBLOCK)
setup_restart_syscall(regs);
user_rewind_single_step(current);
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index e338165..bf0821b 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -196,8 +196,9 @@
.macro __idmap_kpti_put_pgtable_ent_ng, type
orr \type, \type, #PTE_NG // Same bit for blocks and pages
- str \type, [cur_\()\type\()p] // Update the entry and ensure it
- dc civac, cur_\()\type\()p // is visible to all CPUs.
+ str \type, [cur_\()\type\()p] // Update the entry and ensure
+ dmb sy // that it is visible to all
+ dc civac, cur_\()\type\()p // CPUs.
.endm
/*
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index 22123f7..2004b3f 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -1017,7 +1017,7 @@
struct resource swim_rsrc = {
.flags = IORESOURCE_MEM,
.start = (resource_size_t)swim_base,
- .end = (resource_size_t)swim_base + 0x2000,
+ .end = (resource_size_t)swim_base + 0x1FFF,
};
platform_device_register_simple("swim", -1, &swim_rsrc, 1);
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index c2a38321..3b420f6 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -89,7 +89,8 @@
for (p = &iolist ; (tmp = *p) ; p = &tmp->next) {
if (tmp->addr == addr) {
*p = tmp->next;
- __iounmap(tmp->addr, tmp->size);
+ /* remove gap added in get_io_area() */
+ __iounmap(tmp->addr, tmp->size - IO_SIZE);
kfree(tmp);
return;
}
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 6054d49e..8c9cbf1 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -212,6 +212,12 @@
*/
if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
cpu_wait = NULL;
+
+ /*
+ * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
+ * Enable ExternalSync for sync instruction to take effect
+ */
+ set_c0_config7(MIPS_CONF7_ES);
break;
#endif
}
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index a7d0b83..cea8ad8 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -414,6 +414,8 @@
__val = *__addr; \
slow; \
\
+ /* prevent prefetching of coherent DMA data prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__addr, __val); \
}
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a681092..60c787d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -680,6 +680,8 @@
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+/* ExternalSync */
+#define MIPS_CONF7_ES (_ULCAST_(1) << 8)
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
@@ -2745,6 +2747,7 @@
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
__BUILD_SET_C0(config5)
+__BUILD_SET_C0(config7)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index f2ee7e1..cff52b2 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -119,10 +119,20 @@
EXPORT_SYMBOL(_mcount)
PTR_LA t1, ftrace_stub
PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */
- bne t1, t2, static_trace
+ beq t1, t2, fgraph_trace
nop
+ MCOUNT_SAVE_REGS
+
+ move a0, ra /* arg1: self return address */
+ jalr t2 /* (1) call *ftrace_trace_function */
+ move a1, AT /* arg2: parent's return address */
+
+ MCOUNT_RESTORE_REGS
+
+fgraph_trace:
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ PTR_LA t1, ftrace_stub
PTR_L t3, ftrace_graph_return
bne t1, t3, ftrace_graph_caller
nop
@@ -131,24 +141,11 @@
bne t1, t3, ftrace_graph_caller
nop
#endif
- b ftrace_stub
-#ifdef CONFIG_32BIT
- addiu sp, sp, 8
-#else
- nop
-#endif
-static_trace:
- MCOUNT_SAVE_REGS
-
- move a0, ra /* arg1: self return address */
- jalr t2 /* (1) call *ftrace_trace_function */
- move a1, AT /* arg2: parent's return address */
-
- MCOUNT_RESTORE_REGS
#ifdef CONFIG_32BIT
addiu sp, sp, 8
#endif
+
.globl ftrace_stub
ftrace_stub:
RETURN_BACK
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index e1ddb94..e8d772a 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -29,6 +29,7 @@
#include <linux/kallsyms.h>
#include <linux/random.h>
#include <linux/prctl.h>
+#include <linux/nmi.h>
#include <asm/asm.h>
#include <asm/bootinfo.h>
@@ -655,28 +656,42 @@
return sp & ALMASK;
}
-static void arch_dump_stack(void *info)
+static DEFINE_PER_CPU(call_single_data_t, backtrace_csd);
+static struct cpumask backtrace_csd_busy;
+
+static void handle_backtrace(void *info)
{
- struct pt_regs *regs;
+ nmi_cpu_backtrace(get_irq_regs());
+ cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
+}
- regs = get_irq_regs();
+static void raise_backtrace(cpumask_t *mask)
+{
+ call_single_data_t *csd;
+ int cpu;
- if (regs)
- show_regs(regs);
+ for_each_cpu(cpu, mask) {
+ /*
+ * If we previously sent an IPI to the target CPU & it hasn't
+ * cleared its bit in the busy cpumask then it didn't handle
+ * our previous IPI & it's not safe for us to reuse the
+ * call_single_data_t.
+ */
+ if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
+ pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
+ cpu);
+ continue;
+ }
- dump_stack();
+ csd = &per_cpu(backtrace_csd, cpu);
+ csd->func = handle_backtrace;
+ smp_call_function_single_async(cpu, csd);
+ }
}
void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
{
- long this_cpu = get_cpu();
-
- if (cpumask_test_cpu(this_cpu, mask) && !exclude_self)
- dump_stack();
-
- smp_call_function_many(mask, arch_dump_stack, NULL, 1);
-
- put_cpu();
+ nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
}
int mips_get_process_fp_mode(struct task_struct *task)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 5d19ed0..a2de9f6 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -351,6 +351,7 @@
void show_regs(struct pt_regs *regs)
{
__show_regs((struct pt_regs *)regs);
+ dump_stack();
}
void show_registers(struct pt_regs *regs)
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 1986e09..1601d90 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -9,6 +9,7 @@
#include <linux/export.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
+#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
@@ -98,6 +99,20 @@
return error;
}
+static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages,
+ void *arg)
+{
+ unsigned long i;
+
+ for (i = 0; i < nr_pages; i++) {
+ if (pfn_valid(start_pfn + i) &&
+ !PageReserved(pfn_to_page(start_pfn + i)))
+ return 1;
+ }
+
+ return 0;
+}
+
/*
* Generic mapping function (not visible outside):
*/
@@ -116,8 +131,8 @@
void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long flags)
{
+ unsigned long offset, pfn, last_pfn;
struct vm_struct * area;
- unsigned long offset;
phys_addr_t last_addr;
void * addr;
@@ -137,18 +152,16 @@
return (void __iomem *) CKSEG1ADDR(phys_addr);
/*
- * Don't allow anybody to remap normal RAM that we're using..
+ * Don't allow anybody to remap RAM that may be allocated by the page
+ * allocator, since that could lead to races & data clobbering.
*/
- if (phys_addr < virt_to_phys(high_memory)) {
- char *t_addr, *t_end;
- struct page *page;
-
- t_addr = __va(phys_addr);
- t_end = t_addr + (size - 1);
-
- for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++)
- if(!PageReserved(page))
- return NULL;
+ pfn = PFN_DOWN(phys_addr);
+ last_pfn = PFN_DOWN(last_addr);
+ if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL,
+ __ioremap_check_ram) == 1) {
+ WARN_ONCE(1, "ioremap on RAM at %pa - %pa\n",
+ &phys_addr, &last_addr);
+ return NULL;
}
/*
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 6f07c68..c194f4c 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -597,6 +597,7 @@
* actually hit this code path.
*/
+ isync
slbie r6
slbie r6 /* Workaround POWER5 < DD2.1 issue */
slbmte r7,r0
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
index 29d2b60..d0020bc 100644
--- a/arch/powerpc/kernel/fadump.c
+++ b/arch/powerpc/kernel/fadump.c
@@ -1155,6 +1155,9 @@
init_fadump_mem_struct(&fdm,
be64_to_cpu(fdm_active->cpu_state_data.destination_address));
fadump_invalidate_dump(&fdm);
+ } else if (fw_dump.dump_registered) {
+ /* Un-register Firmware-assisted dump if it was registered. */
+ fadump_unregister_dump(&fdm);
}
}
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index 53b9c1d..ceafad8 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -175,8 +175,8 @@
if (cpu_has_feature(CPU_FTR_DAWR)) {
length_max = 512 ; /* 64 doublewords */
/* DAWR region can't cross 512 boundary */
- if ((bp->attr.bp_addr >> 10) !=
- ((bp->attr.bp_addr + bp->attr.bp_len - 1) >> 10))
+ if ((bp->attr.bp_addr >> 9) !=
+ ((bp->attr.bp_addr + bp->attr.bp_len - 1) >> 9))
return -EINVAL;
}
if (info->len >
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index f52ad5b..81750d9 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -2362,6 +2362,7 @@
/* Create a new breakpoint request if one doesn't exist already */
hw_breakpoint_init(&attr);
attr.bp_addr = hw_brk.address;
+ attr.bp_len = 8;
arch_bp_generic_fields(hw_brk.type,
&attr.bp_type);
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
index da6ba9b..b73961b 100644
--- a/arch/powerpc/perf/imc-pmu.c
+++ b/arch/powerpc/perf/imc-pmu.c
@@ -1131,7 +1131,7 @@
static void cleanup_all_core_imc_memory(void)
{
- int i, nr_cores = DIV_ROUND_UP(num_present_cpus(), threads_per_core);
+ int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
struct imc_mem_info *ptr = core_imc_pmu->mem_info;
int size = core_imc_pmu->counter_mem_size;
@@ -1239,7 +1239,7 @@
if (!pmu_ptr->pmu.name)
return -ENOMEM;
- nr_cores = DIV_ROUND_UP(num_present_cpus(), threads_per_core);
+ nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
GFP_KERNEL);
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
index c9a5036..e9a6c35 100644
--- a/arch/powerpc/platforms/powernv/copy-paste.h
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -42,5 +42,6 @@
: "b" (offset), "b" (paste_address)
: "memory", "cr0");
- return (cr >> CR0_SHIFT) & CR0_MASK;
+ /* We mask with 0xE to ignore SO */
+ return (cr >> CR0_SHIFT) & 0xE;
}
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index 443d5ca..028d6d1 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -78,7 +78,7 @@
uint64_t msr_val = MSR_IDLE;
uint64_t psscr_val = pnv_deepest_stop_psscr_val;
- for_each_possible_cpu(cpu) {
+ for_each_present_cpu(cpu) {
uint64_t pir = get_hard_smp_processor_id(cpu);
uint64_t hsprg0_val = (uint64_t)&paca[cpu];
@@ -741,7 +741,7 @@
int cpu;
pr_info("powernv: idle: Saving PACA pointers of all CPUs in their thread sibling PACA\n");
- for_each_possible_cpu(cpu) {
+ for_each_present_cpu(cpu) {
int base_cpu = cpu_first_thread_sibling(cpu);
int idx = cpu_thread_in_core(cpu);
int i;
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 57f9e55..677b29e 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -3591,7 +3591,6 @@
WARN_ON(pe->table_group.group);
}
- pnv_pci_ioda2_table_free_pages(tbl);
iommu_tce_table_put(tbl);
}
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index be20b1f..e928c2a 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -1244,7 +1244,7 @@
jl 0f
clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
jl .Lcleanup_load_fpu_regs
-0: BR_EX %r14
+0: BR_EX %r14,%r11
.align 8
.Lcleanup_table:
@@ -1280,7 +1280,7 @@
ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
larl %r9,sie_exit # skip forward to sie_exit
- BR_EX %r14
+ BR_EX %r14,%r11
#endif
.Lcleanup_system_call:
diff --git a/arch/x86/configs/chromiumos-container-vm-x86_64_defconfig b/arch/x86/configs/chromiumos-container-vm-x86_64_defconfig
index 89bf3b6..687bb24 100644
--- a/arch/x86/configs/chromiumos-container-vm-x86_64_defconfig
+++ b/arch/x86/configs/chromiumos-container-vm-x86_64_defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/x86 4.14.29 Kernel Configuration
+# Linux/x86 4.14.55 Kernel Configuration
#
CONFIG_64BIT=y
CONFIG_X86_64=y
@@ -792,9 +792,9 @@
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
-# CONFIG_NET_IP_TUNNEL is not set
+CONFIG_NET_IP_TUNNEL=y
CONFIG_SYN_COOKIES=y
-# CONFIG_NET_UDP_TUNNEL is not set
+CONFIG_NET_UDP_TUNNEL=y
# CONFIG_NET_FOU is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
@@ -1117,6 +1117,9 @@
# CONFIG_NF_SOCKET_IPV6 is not set
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_CHAIN_ROUTE_IPV6=y
+CONFIG_NFT_CHAIN_NAT_IPV6=y
+CONFIG_NFT_MASQ_IPV6=y
+CONFIG_NFT_REDIR_IPV6=y
CONFIG_NFT_REJECT_IPV6=y
CONFIG_NFT_DUP_IPV6=y
# CONFIG_NFT_FIB_IPV6 is not set
@@ -1124,10 +1127,7 @@
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_NF_NAT_IPV6=y
-CONFIG_NFT_CHAIN_NAT_IPV6=y
CONFIG_NF_NAT_MASQUERADE_IPV6=y
-CONFIG_NFT_MASQ_IPV6=y
-CONFIG_NFT_REDIR_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_AH=y
CONFIG_IP6_NF_MATCH_EUI64=y
@@ -1277,7 +1277,7 @@
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
# CONFIG_NET_SWITCHDEV is not set
-# CONFIG_NET_L3_MASTER_DEV is not set
+CONFIG_NET_L3_MASTER_DEV=y
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
@@ -1310,7 +1310,7 @@
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
-# CONFIG_DST_CACHE is not set
+CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
# CONFIG_NET_DEVLINK is not set
CONFIG_MAY_USE_DEVLINK=y
@@ -1622,7 +1622,11 @@
# CONFIG_NET_TEAM is not set
CONFIG_MACVLAN=y
CONFIG_MACVTAP=y
-# CONFIG_VXLAN is not set
+CONFIG_IPVLAN=y
+CONFIG_IPVTAP=y
+CONFIG_VXLAN=y
+# CONFIG_GENEVE is not set
+# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
@@ -2476,7 +2480,6 @@
#
# Qualcomm SoC drivers
#
-# CONFIG_QCOM_GENI_SE is not set
# CONFIG_SUNXI_SRAM is not set
# CONFIG_SOC_TI is not set
# CONFIG_PM_DEVFREQ is not set
@@ -2524,6 +2527,8 @@
# FSI support
#
# CONFIG_FSI is not set
+# CONFIG_PKGLIST is not set
+# CONFIG_DRM_EVDI is not set
#
# Firmware Drivers
@@ -2565,7 +2570,7 @@
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
CONFIG_BTRFS_FS=y
-# CONFIG_BTRFS_FS_POSIX_ACL is not set
+CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 5f07333..9c903a42 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -15,7 +15,6 @@
obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o
obj-$(CONFIG_CRYPTO_TWOFISH_586) += twofish-i586.o
-obj-$(CONFIG_CRYPTO_SALSA20_586) += salsa20-i586.o
obj-$(CONFIG_CRYPTO_SERPENT_SSE2_586) += serpent-sse2-i586.o
obj-$(CONFIG_CRYPTO_AES_X86_64) += aes-x86_64.o
@@ -24,7 +23,6 @@
obj-$(CONFIG_CRYPTO_BLOWFISH_X86_64) += blowfish-x86_64.o
obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o
obj-$(CONFIG_CRYPTO_TWOFISH_X86_64_3WAY) += twofish-x86_64-3way.o
-obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o
obj-$(CONFIG_CRYPTO_CHACHA20_X86_64) += chacha20-x86_64.o
obj-$(CONFIG_CRYPTO_SERPENT_SSE2_X86_64) += serpent-sse2-x86_64.o
obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o
@@ -59,7 +57,6 @@
aes-i586-y := aes-i586-asm_32.o aes_glue.o
twofish-i586-y := twofish-i586-asm_32.o twofish_glue.o
-salsa20-i586-y := salsa20-i586-asm_32.o salsa20_glue.o
serpent-sse2-i586-y := serpent-sse2-i586-asm_32.o serpent_sse2_glue.o
aes-x86_64-y := aes-x86_64-asm_64.o aes_glue.o
@@ -68,7 +65,6 @@
blowfish-x86_64-y := blowfish-x86_64-asm_64.o blowfish_glue.o
twofish-x86_64-y := twofish-x86_64-asm_64.o twofish_glue.o
twofish-x86_64-3way-y := twofish-x86_64-asm_64-3way.o twofish_glue_3way.o
-salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o
chacha20-x86_64-y := chacha20-ssse3-x86_64.o chacha20_glue.o
serpent-sse2-x86_64-y := serpent-sse2-x86_64-asm_64.o serpent_sse2_glue.o
diff --git a/arch/x86/crypto/salsa20-i586-asm_32.S b/arch/x86/crypto/salsa20-i586-asm_32.S
deleted file mode 100644
index 329452b8..0000000
--- a/arch/x86/crypto/salsa20-i586-asm_32.S
+++ /dev/null
@@ -1,1114 +0,0 @@
-# salsa20_pm.s version 20051229
-# D. J. Bernstein
-# Public domain.
-
-#include <linux/linkage.h>
-
-.text
-
-# enter salsa20_encrypt_bytes
-ENTRY(salsa20_encrypt_bytes)
- mov %esp,%eax
- and $31,%eax
- add $256,%eax
- sub %eax,%esp
- # eax_stack = eax
- movl %eax,80(%esp)
- # ebx_stack = ebx
- movl %ebx,84(%esp)
- # esi_stack = esi
- movl %esi,88(%esp)
- # edi_stack = edi
- movl %edi,92(%esp)
- # ebp_stack = ebp
- movl %ebp,96(%esp)
- # x = arg1
- movl 4(%esp,%eax),%edx
- # m = arg2
- movl 8(%esp,%eax),%esi
- # out = arg3
- movl 12(%esp,%eax),%edi
- # bytes = arg4
- movl 16(%esp,%eax),%ebx
- # bytes -= 0
- sub $0,%ebx
- # goto done if unsigned<=
- jbe ._done
-._start:
- # in0 = *(uint32 *) (x + 0)
- movl 0(%edx),%eax
- # in1 = *(uint32 *) (x + 4)
- movl 4(%edx),%ecx
- # in2 = *(uint32 *) (x + 8)
- movl 8(%edx),%ebp
- # j0 = in0
- movl %eax,164(%esp)
- # in3 = *(uint32 *) (x + 12)
- movl 12(%edx),%eax
- # j1 = in1
- movl %ecx,168(%esp)
- # in4 = *(uint32 *) (x + 16)
- movl 16(%edx),%ecx
- # j2 = in2
- movl %ebp,172(%esp)
- # in5 = *(uint32 *) (x + 20)
- movl 20(%edx),%ebp
- # j3 = in3
- movl %eax,176(%esp)
- # in6 = *(uint32 *) (x + 24)
- movl 24(%edx),%eax
- # j4 = in4
- movl %ecx,180(%esp)
- # in7 = *(uint32 *) (x + 28)
- movl 28(%edx),%ecx
- # j5 = in5
- movl %ebp,184(%esp)
- # in8 = *(uint32 *) (x + 32)
- movl 32(%edx),%ebp
- # j6 = in6
- movl %eax,188(%esp)
- # in9 = *(uint32 *) (x + 36)
- movl 36(%edx),%eax
- # j7 = in7
- movl %ecx,192(%esp)
- # in10 = *(uint32 *) (x + 40)
- movl 40(%edx),%ecx
- # j8 = in8
- movl %ebp,196(%esp)
- # in11 = *(uint32 *) (x + 44)
- movl 44(%edx),%ebp
- # j9 = in9
- movl %eax,200(%esp)
- # in12 = *(uint32 *) (x + 48)
- movl 48(%edx),%eax
- # j10 = in10
- movl %ecx,204(%esp)
- # in13 = *(uint32 *) (x + 52)
- movl 52(%edx),%ecx
- # j11 = in11
- movl %ebp,208(%esp)
- # in14 = *(uint32 *) (x + 56)
- movl 56(%edx),%ebp
- # j12 = in12
- movl %eax,212(%esp)
- # in15 = *(uint32 *) (x + 60)
- movl 60(%edx),%eax
- # j13 = in13
- movl %ecx,216(%esp)
- # j14 = in14
- movl %ebp,220(%esp)
- # j15 = in15
- movl %eax,224(%esp)
- # x_backup = x
- movl %edx,64(%esp)
-._bytesatleast1:
- # bytes - 64
- cmp $64,%ebx
- # goto nocopy if unsigned>=
- jae ._nocopy
- # ctarget = out
- movl %edi,228(%esp)
- # out = &tmp
- leal 0(%esp),%edi
- # i = bytes
- mov %ebx,%ecx
- # while (i) { *out++ = *m++; --i }
- rep movsb
- # out = &tmp
- leal 0(%esp),%edi
- # m = &tmp
- leal 0(%esp),%esi
-._nocopy:
- # out_backup = out
- movl %edi,72(%esp)
- # m_backup = m
- movl %esi,68(%esp)
- # bytes_backup = bytes
- movl %ebx,76(%esp)
- # in0 = j0
- movl 164(%esp),%eax
- # in1 = j1
- movl 168(%esp),%ecx
- # in2 = j2
- movl 172(%esp),%edx
- # in3 = j3
- movl 176(%esp),%ebx
- # x0 = in0
- movl %eax,100(%esp)
- # x1 = in1
- movl %ecx,104(%esp)
- # x2 = in2
- movl %edx,108(%esp)
- # x3 = in3
- movl %ebx,112(%esp)
- # in4 = j4
- movl 180(%esp),%eax
- # in5 = j5
- movl 184(%esp),%ecx
- # in6 = j6
- movl 188(%esp),%edx
- # in7 = j7
- movl 192(%esp),%ebx
- # x4 = in4
- movl %eax,116(%esp)
- # x5 = in5
- movl %ecx,120(%esp)
- # x6 = in6
- movl %edx,124(%esp)
- # x7 = in7
- movl %ebx,128(%esp)
- # in8 = j8
- movl 196(%esp),%eax
- # in9 = j9
- movl 200(%esp),%ecx
- # in10 = j10
- movl 204(%esp),%edx
- # in11 = j11
- movl 208(%esp),%ebx
- # x8 = in8
- movl %eax,132(%esp)
- # x9 = in9
- movl %ecx,136(%esp)
- # x10 = in10
- movl %edx,140(%esp)
- # x11 = in11
- movl %ebx,144(%esp)
- # in12 = j12
- movl 212(%esp),%eax
- # in13 = j13
- movl 216(%esp),%ecx
- # in14 = j14
- movl 220(%esp),%edx
- # in15 = j15
- movl 224(%esp),%ebx
- # x12 = in12
- movl %eax,148(%esp)
- # x13 = in13
- movl %ecx,152(%esp)
- # x14 = in14
- movl %edx,156(%esp)
- # x15 = in15
- movl %ebx,160(%esp)
- # i = 20
- mov $20,%ebp
- # p = x0
- movl 100(%esp),%eax
- # s = x5
- movl 120(%esp),%ecx
- # t = x10
- movl 140(%esp),%edx
- # w = x15
- movl 160(%esp),%ebx
-._mainloop:
- # x0 = p
- movl %eax,100(%esp)
- # x10 = t
- movl %edx,140(%esp)
- # p += x12
- addl 148(%esp),%eax
- # x5 = s
- movl %ecx,120(%esp)
- # t += x6
- addl 124(%esp),%edx
- # x15 = w
- movl %ebx,160(%esp)
- # r = x1
- movl 104(%esp),%esi
- # r += s
- add %ecx,%esi
- # v = x11
- movl 144(%esp),%edi
- # v += w
- add %ebx,%edi
- # p <<<= 7
- rol $7,%eax
- # p ^= x4
- xorl 116(%esp),%eax
- # t <<<= 7
- rol $7,%edx
- # t ^= x14
- xorl 156(%esp),%edx
- # r <<<= 7
- rol $7,%esi
- # r ^= x9
- xorl 136(%esp),%esi
- # v <<<= 7
- rol $7,%edi
- # v ^= x3
- xorl 112(%esp),%edi
- # x4 = p
- movl %eax,116(%esp)
- # x14 = t
- movl %edx,156(%esp)
- # p += x0
- addl 100(%esp),%eax
- # x9 = r
- movl %esi,136(%esp)
- # t += x10
- addl 140(%esp),%edx
- # x3 = v
- movl %edi,112(%esp)
- # p <<<= 9
- rol $9,%eax
- # p ^= x8
- xorl 132(%esp),%eax
- # t <<<= 9
- rol $9,%edx
- # t ^= x2
- xorl 108(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 9
- rol $9,%ecx
- # s ^= x13
- xorl 152(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 9
- rol $9,%ebx
- # w ^= x7
- xorl 128(%esp),%ebx
- # x8 = p
- movl %eax,132(%esp)
- # x2 = t
- movl %edx,108(%esp)
- # p += x4
- addl 116(%esp),%eax
- # x13 = s
- movl %ecx,152(%esp)
- # t += x14
- addl 156(%esp),%edx
- # x7 = w
- movl %ebx,128(%esp)
- # p <<<= 13
- rol $13,%eax
- # p ^= x12
- xorl 148(%esp),%eax
- # t <<<= 13
- rol $13,%edx
- # t ^= x6
- xorl 124(%esp),%edx
- # r += s
- add %ecx,%esi
- # r <<<= 13
- rol $13,%esi
- # r ^= x1
- xorl 104(%esp),%esi
- # v += w
- add %ebx,%edi
- # v <<<= 13
- rol $13,%edi
- # v ^= x11
- xorl 144(%esp),%edi
- # x12 = p
- movl %eax,148(%esp)
- # x6 = t
- movl %edx,124(%esp)
- # p += x8
- addl 132(%esp),%eax
- # x1 = r
- movl %esi,104(%esp)
- # t += x2
- addl 108(%esp),%edx
- # x11 = v
- movl %edi,144(%esp)
- # p <<<= 18
- rol $18,%eax
- # p ^= x0
- xorl 100(%esp),%eax
- # t <<<= 18
- rol $18,%edx
- # t ^= x10
- xorl 140(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 18
- rol $18,%ecx
- # s ^= x5
- xorl 120(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 18
- rol $18,%ebx
- # w ^= x15
- xorl 160(%esp),%ebx
- # x0 = p
- movl %eax,100(%esp)
- # x10 = t
- movl %edx,140(%esp)
- # p += x3
- addl 112(%esp),%eax
- # p <<<= 7
- rol $7,%eax
- # x5 = s
- movl %ecx,120(%esp)
- # t += x9
- addl 136(%esp),%edx
- # x15 = w
- movl %ebx,160(%esp)
- # r = x4
- movl 116(%esp),%esi
- # r += s
- add %ecx,%esi
- # v = x14
- movl 156(%esp),%edi
- # v += w
- add %ebx,%edi
- # p ^= x1
- xorl 104(%esp),%eax
- # t <<<= 7
- rol $7,%edx
- # t ^= x11
- xorl 144(%esp),%edx
- # r <<<= 7
- rol $7,%esi
- # r ^= x6
- xorl 124(%esp),%esi
- # v <<<= 7
- rol $7,%edi
- # v ^= x12
- xorl 148(%esp),%edi
- # x1 = p
- movl %eax,104(%esp)
- # x11 = t
- movl %edx,144(%esp)
- # p += x0
- addl 100(%esp),%eax
- # x6 = r
- movl %esi,124(%esp)
- # t += x10
- addl 140(%esp),%edx
- # x12 = v
- movl %edi,148(%esp)
- # p <<<= 9
- rol $9,%eax
- # p ^= x2
- xorl 108(%esp),%eax
- # t <<<= 9
- rol $9,%edx
- # t ^= x8
- xorl 132(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 9
- rol $9,%ecx
- # s ^= x7
- xorl 128(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 9
- rol $9,%ebx
- # w ^= x13
- xorl 152(%esp),%ebx
- # x2 = p
- movl %eax,108(%esp)
- # x8 = t
- movl %edx,132(%esp)
- # p += x1
- addl 104(%esp),%eax
- # x7 = s
- movl %ecx,128(%esp)
- # t += x11
- addl 144(%esp),%edx
- # x13 = w
- movl %ebx,152(%esp)
- # p <<<= 13
- rol $13,%eax
- # p ^= x3
- xorl 112(%esp),%eax
- # t <<<= 13
- rol $13,%edx
- # t ^= x9
- xorl 136(%esp),%edx
- # r += s
- add %ecx,%esi
- # r <<<= 13
- rol $13,%esi
- # r ^= x4
- xorl 116(%esp),%esi
- # v += w
- add %ebx,%edi
- # v <<<= 13
- rol $13,%edi
- # v ^= x14
- xorl 156(%esp),%edi
- # x3 = p
- movl %eax,112(%esp)
- # x9 = t
- movl %edx,136(%esp)
- # p += x2
- addl 108(%esp),%eax
- # x4 = r
- movl %esi,116(%esp)
- # t += x8
- addl 132(%esp),%edx
- # x14 = v
- movl %edi,156(%esp)
- # p <<<= 18
- rol $18,%eax
- # p ^= x0
- xorl 100(%esp),%eax
- # t <<<= 18
- rol $18,%edx
- # t ^= x10
- xorl 140(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 18
- rol $18,%ecx
- # s ^= x5
- xorl 120(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 18
- rol $18,%ebx
- # w ^= x15
- xorl 160(%esp),%ebx
- # x0 = p
- movl %eax,100(%esp)
- # x10 = t
- movl %edx,140(%esp)
- # p += x12
- addl 148(%esp),%eax
- # x5 = s
- movl %ecx,120(%esp)
- # t += x6
- addl 124(%esp),%edx
- # x15 = w
- movl %ebx,160(%esp)
- # r = x1
- movl 104(%esp),%esi
- # r += s
- add %ecx,%esi
- # v = x11
- movl 144(%esp),%edi
- # v += w
- add %ebx,%edi
- # p <<<= 7
- rol $7,%eax
- # p ^= x4
- xorl 116(%esp),%eax
- # t <<<= 7
- rol $7,%edx
- # t ^= x14
- xorl 156(%esp),%edx
- # r <<<= 7
- rol $7,%esi
- # r ^= x9
- xorl 136(%esp),%esi
- # v <<<= 7
- rol $7,%edi
- # v ^= x3
- xorl 112(%esp),%edi
- # x4 = p
- movl %eax,116(%esp)
- # x14 = t
- movl %edx,156(%esp)
- # p += x0
- addl 100(%esp),%eax
- # x9 = r
- movl %esi,136(%esp)
- # t += x10
- addl 140(%esp),%edx
- # x3 = v
- movl %edi,112(%esp)
- # p <<<= 9
- rol $9,%eax
- # p ^= x8
- xorl 132(%esp),%eax
- # t <<<= 9
- rol $9,%edx
- # t ^= x2
- xorl 108(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 9
- rol $9,%ecx
- # s ^= x13
- xorl 152(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 9
- rol $9,%ebx
- # w ^= x7
- xorl 128(%esp),%ebx
- # x8 = p
- movl %eax,132(%esp)
- # x2 = t
- movl %edx,108(%esp)
- # p += x4
- addl 116(%esp),%eax
- # x13 = s
- movl %ecx,152(%esp)
- # t += x14
- addl 156(%esp),%edx
- # x7 = w
- movl %ebx,128(%esp)
- # p <<<= 13
- rol $13,%eax
- # p ^= x12
- xorl 148(%esp),%eax
- # t <<<= 13
- rol $13,%edx
- # t ^= x6
- xorl 124(%esp),%edx
- # r += s
- add %ecx,%esi
- # r <<<= 13
- rol $13,%esi
- # r ^= x1
- xorl 104(%esp),%esi
- # v += w
- add %ebx,%edi
- # v <<<= 13
- rol $13,%edi
- # v ^= x11
- xorl 144(%esp),%edi
- # x12 = p
- movl %eax,148(%esp)
- # x6 = t
- movl %edx,124(%esp)
- # p += x8
- addl 132(%esp),%eax
- # x1 = r
- movl %esi,104(%esp)
- # t += x2
- addl 108(%esp),%edx
- # x11 = v
- movl %edi,144(%esp)
- # p <<<= 18
- rol $18,%eax
- # p ^= x0
- xorl 100(%esp),%eax
- # t <<<= 18
- rol $18,%edx
- # t ^= x10
- xorl 140(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 18
- rol $18,%ecx
- # s ^= x5
- xorl 120(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 18
- rol $18,%ebx
- # w ^= x15
- xorl 160(%esp),%ebx
- # x0 = p
- movl %eax,100(%esp)
- # x10 = t
- movl %edx,140(%esp)
- # p += x3
- addl 112(%esp),%eax
- # p <<<= 7
- rol $7,%eax
- # x5 = s
- movl %ecx,120(%esp)
- # t += x9
- addl 136(%esp),%edx
- # x15 = w
- movl %ebx,160(%esp)
- # r = x4
- movl 116(%esp),%esi
- # r += s
- add %ecx,%esi
- # v = x14
- movl 156(%esp),%edi
- # v += w
- add %ebx,%edi
- # p ^= x1
- xorl 104(%esp),%eax
- # t <<<= 7
- rol $7,%edx
- # t ^= x11
- xorl 144(%esp),%edx
- # r <<<= 7
- rol $7,%esi
- # r ^= x6
- xorl 124(%esp),%esi
- # v <<<= 7
- rol $7,%edi
- # v ^= x12
- xorl 148(%esp),%edi
- # x1 = p
- movl %eax,104(%esp)
- # x11 = t
- movl %edx,144(%esp)
- # p += x0
- addl 100(%esp),%eax
- # x6 = r
- movl %esi,124(%esp)
- # t += x10
- addl 140(%esp),%edx
- # x12 = v
- movl %edi,148(%esp)
- # p <<<= 9
- rol $9,%eax
- # p ^= x2
- xorl 108(%esp),%eax
- # t <<<= 9
- rol $9,%edx
- # t ^= x8
- xorl 132(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 9
- rol $9,%ecx
- # s ^= x7
- xorl 128(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 9
- rol $9,%ebx
- # w ^= x13
- xorl 152(%esp),%ebx
- # x2 = p
- movl %eax,108(%esp)
- # x8 = t
- movl %edx,132(%esp)
- # p += x1
- addl 104(%esp),%eax
- # x7 = s
- movl %ecx,128(%esp)
- # t += x11
- addl 144(%esp),%edx
- # x13 = w
- movl %ebx,152(%esp)
- # p <<<= 13
- rol $13,%eax
- # p ^= x3
- xorl 112(%esp),%eax
- # t <<<= 13
- rol $13,%edx
- # t ^= x9
- xorl 136(%esp),%edx
- # r += s
- add %ecx,%esi
- # r <<<= 13
- rol $13,%esi
- # r ^= x4
- xorl 116(%esp),%esi
- # v += w
- add %ebx,%edi
- # v <<<= 13
- rol $13,%edi
- # v ^= x14
- xorl 156(%esp),%edi
- # x3 = p
- movl %eax,112(%esp)
- # x9 = t
- movl %edx,136(%esp)
- # p += x2
- addl 108(%esp),%eax
- # x4 = r
- movl %esi,116(%esp)
- # t += x8
- addl 132(%esp),%edx
- # x14 = v
- movl %edi,156(%esp)
- # p <<<= 18
- rol $18,%eax
- # p ^= x0
- xorl 100(%esp),%eax
- # t <<<= 18
- rol $18,%edx
- # t ^= x10
- xorl 140(%esp),%edx
- # s += r
- add %esi,%ecx
- # s <<<= 18
- rol $18,%ecx
- # s ^= x5
- xorl 120(%esp),%ecx
- # w += v
- add %edi,%ebx
- # w <<<= 18
- rol $18,%ebx
- # w ^= x15
- xorl 160(%esp),%ebx
- # i -= 4
- sub $4,%ebp
- # goto mainloop if unsigned >
- ja ._mainloop
- # x0 = p
- movl %eax,100(%esp)
- # x5 = s
- movl %ecx,120(%esp)
- # x10 = t
- movl %edx,140(%esp)
- # x15 = w
- movl %ebx,160(%esp)
- # out = out_backup
- movl 72(%esp),%edi
- # m = m_backup
- movl 68(%esp),%esi
- # in0 = x0
- movl 100(%esp),%eax
- # in1 = x1
- movl 104(%esp),%ecx
- # in0 += j0
- addl 164(%esp),%eax
- # in1 += j1
- addl 168(%esp),%ecx
- # in0 ^= *(uint32 *) (m + 0)
- xorl 0(%esi),%eax
- # in1 ^= *(uint32 *) (m + 4)
- xorl 4(%esi),%ecx
- # *(uint32 *) (out + 0) = in0
- movl %eax,0(%edi)
- # *(uint32 *) (out + 4) = in1
- movl %ecx,4(%edi)
- # in2 = x2
- movl 108(%esp),%eax
- # in3 = x3
- movl 112(%esp),%ecx
- # in2 += j2
- addl 172(%esp),%eax
- # in3 += j3
- addl 176(%esp),%ecx
- # in2 ^= *(uint32 *) (m + 8)
- xorl 8(%esi),%eax
- # in3 ^= *(uint32 *) (m + 12)
- xorl 12(%esi),%ecx
- # *(uint32 *) (out + 8) = in2
- movl %eax,8(%edi)
- # *(uint32 *) (out + 12) = in3
- movl %ecx,12(%edi)
- # in4 = x4
- movl 116(%esp),%eax
- # in5 = x5
- movl 120(%esp),%ecx
- # in4 += j4
- addl 180(%esp),%eax
- # in5 += j5
- addl 184(%esp),%ecx
- # in4 ^= *(uint32 *) (m + 16)
- xorl 16(%esi),%eax
- # in5 ^= *(uint32 *) (m + 20)
- xorl 20(%esi),%ecx
- # *(uint32 *) (out + 16) = in4
- movl %eax,16(%edi)
- # *(uint32 *) (out + 20) = in5
- movl %ecx,20(%edi)
- # in6 = x6
- movl 124(%esp),%eax
- # in7 = x7
- movl 128(%esp),%ecx
- # in6 += j6
- addl 188(%esp),%eax
- # in7 += j7
- addl 192(%esp),%ecx
- # in6 ^= *(uint32 *) (m + 24)
- xorl 24(%esi),%eax
- # in7 ^= *(uint32 *) (m + 28)
- xorl 28(%esi),%ecx
- # *(uint32 *) (out + 24) = in6
- movl %eax,24(%edi)
- # *(uint32 *) (out + 28) = in7
- movl %ecx,28(%edi)
- # in8 = x8
- movl 132(%esp),%eax
- # in9 = x9
- movl 136(%esp),%ecx
- # in8 += j8
- addl 196(%esp),%eax
- # in9 += j9
- addl 200(%esp),%ecx
- # in8 ^= *(uint32 *) (m + 32)
- xorl 32(%esi),%eax
- # in9 ^= *(uint32 *) (m + 36)
- xorl 36(%esi),%ecx
- # *(uint32 *) (out + 32) = in8
- movl %eax,32(%edi)
- # *(uint32 *) (out + 36) = in9
- movl %ecx,36(%edi)
- # in10 = x10
- movl 140(%esp),%eax
- # in11 = x11
- movl 144(%esp),%ecx
- # in10 += j10
- addl 204(%esp),%eax
- # in11 += j11
- addl 208(%esp),%ecx
- # in10 ^= *(uint32 *) (m + 40)
- xorl 40(%esi),%eax
- # in11 ^= *(uint32 *) (m + 44)
- xorl 44(%esi),%ecx
- # *(uint32 *) (out + 40) = in10
- movl %eax,40(%edi)
- # *(uint32 *) (out + 44) = in11
- movl %ecx,44(%edi)
- # in12 = x12
- movl 148(%esp),%eax
- # in13 = x13
- movl 152(%esp),%ecx
- # in12 += j12
- addl 212(%esp),%eax
- # in13 += j13
- addl 216(%esp),%ecx
- # in12 ^= *(uint32 *) (m + 48)
- xorl 48(%esi),%eax
- # in13 ^= *(uint32 *) (m + 52)
- xorl 52(%esi),%ecx
- # *(uint32 *) (out + 48) = in12
- movl %eax,48(%edi)
- # *(uint32 *) (out + 52) = in13
- movl %ecx,52(%edi)
- # in14 = x14
- movl 156(%esp),%eax
- # in15 = x15
- movl 160(%esp),%ecx
- # in14 += j14
- addl 220(%esp),%eax
- # in15 += j15
- addl 224(%esp),%ecx
- # in14 ^= *(uint32 *) (m + 56)
- xorl 56(%esi),%eax
- # in15 ^= *(uint32 *) (m + 60)
- xorl 60(%esi),%ecx
- # *(uint32 *) (out + 56) = in14
- movl %eax,56(%edi)
- # *(uint32 *) (out + 60) = in15
- movl %ecx,60(%edi)
- # bytes = bytes_backup
- movl 76(%esp),%ebx
- # in8 = j8
- movl 196(%esp),%eax
- # in9 = j9
- movl 200(%esp),%ecx
- # in8 += 1
- add $1,%eax
- # in9 += 0 + carry
- adc $0,%ecx
- # j8 = in8
- movl %eax,196(%esp)
- # j9 = in9
- movl %ecx,200(%esp)
- # bytes - 64
- cmp $64,%ebx
- # goto bytesatleast65 if unsigned>
- ja ._bytesatleast65
- # goto bytesatleast64 if unsigned>=
- jae ._bytesatleast64
- # m = out
- mov %edi,%esi
- # out = ctarget
- movl 228(%esp),%edi
- # i = bytes
- mov %ebx,%ecx
- # while (i) { *out++ = *m++; --i }
- rep movsb
-._bytesatleast64:
- # x = x_backup
- movl 64(%esp),%eax
- # in8 = j8
- movl 196(%esp),%ecx
- # in9 = j9
- movl 200(%esp),%edx
- # *(uint32 *) (x + 32) = in8
- movl %ecx,32(%eax)
- # *(uint32 *) (x + 36) = in9
- movl %edx,36(%eax)
-._done:
- # eax = eax_stack
- movl 80(%esp),%eax
- # ebx = ebx_stack
- movl 84(%esp),%ebx
- # esi = esi_stack
- movl 88(%esp),%esi
- # edi = edi_stack
- movl 92(%esp),%edi
- # ebp = ebp_stack
- movl 96(%esp),%ebp
- # leave
- add %eax,%esp
- ret
-._bytesatleast65:
- # bytes -= 64
- sub $64,%ebx
- # out += 64
- add $64,%edi
- # m += 64
- add $64,%esi
- # goto bytesatleast1
- jmp ._bytesatleast1
-ENDPROC(salsa20_encrypt_bytes)
-
-# enter salsa20_keysetup
-ENTRY(salsa20_keysetup)
- mov %esp,%eax
- and $31,%eax
- add $256,%eax
- sub %eax,%esp
- # eax_stack = eax
- movl %eax,64(%esp)
- # ebx_stack = ebx
- movl %ebx,68(%esp)
- # esi_stack = esi
- movl %esi,72(%esp)
- # edi_stack = edi
- movl %edi,76(%esp)
- # ebp_stack = ebp
- movl %ebp,80(%esp)
- # k = arg2
- movl 8(%esp,%eax),%ecx
- # kbits = arg3
- movl 12(%esp,%eax),%edx
- # x = arg1
- movl 4(%esp,%eax),%eax
- # in1 = *(uint32 *) (k + 0)
- movl 0(%ecx),%ebx
- # in2 = *(uint32 *) (k + 4)
- movl 4(%ecx),%esi
- # in3 = *(uint32 *) (k + 8)
- movl 8(%ecx),%edi
- # in4 = *(uint32 *) (k + 12)
- movl 12(%ecx),%ebp
- # *(uint32 *) (x + 4) = in1
- movl %ebx,4(%eax)
- # *(uint32 *) (x + 8) = in2
- movl %esi,8(%eax)
- # *(uint32 *) (x + 12) = in3
- movl %edi,12(%eax)
- # *(uint32 *) (x + 16) = in4
- movl %ebp,16(%eax)
- # kbits - 256
- cmp $256,%edx
- # goto kbits128 if unsigned<
- jb ._kbits128
-._kbits256:
- # in11 = *(uint32 *) (k + 16)
- movl 16(%ecx),%edx
- # in12 = *(uint32 *) (k + 20)
- movl 20(%ecx),%ebx
- # in13 = *(uint32 *) (k + 24)
- movl 24(%ecx),%esi
- # in14 = *(uint32 *) (k + 28)
- movl 28(%ecx),%ecx
- # *(uint32 *) (x + 44) = in11
- movl %edx,44(%eax)
- # *(uint32 *) (x + 48) = in12
- movl %ebx,48(%eax)
- # *(uint32 *) (x + 52) = in13
- movl %esi,52(%eax)
- # *(uint32 *) (x + 56) = in14
- movl %ecx,56(%eax)
- # in0 = 1634760805
- mov $1634760805,%ecx
- # in5 = 857760878
- mov $857760878,%edx
- # in10 = 2036477234
- mov $2036477234,%ebx
- # in15 = 1797285236
- mov $1797285236,%esi
- # *(uint32 *) (x + 0) = in0
- movl %ecx,0(%eax)
- # *(uint32 *) (x + 20) = in5
- movl %edx,20(%eax)
- # *(uint32 *) (x + 40) = in10
- movl %ebx,40(%eax)
- # *(uint32 *) (x + 60) = in15
- movl %esi,60(%eax)
- # goto keysetupdone
- jmp ._keysetupdone
-._kbits128:
- # in11 = *(uint32 *) (k + 0)
- movl 0(%ecx),%edx
- # in12 = *(uint32 *) (k + 4)
- movl 4(%ecx),%ebx
- # in13 = *(uint32 *) (k + 8)
- movl 8(%ecx),%esi
- # in14 = *(uint32 *) (k + 12)
- movl 12(%ecx),%ecx
- # *(uint32 *) (x + 44) = in11
- movl %edx,44(%eax)
- # *(uint32 *) (x + 48) = in12
- movl %ebx,48(%eax)
- # *(uint32 *) (x + 52) = in13
- movl %esi,52(%eax)
- # *(uint32 *) (x + 56) = in14
- movl %ecx,56(%eax)
- # in0 = 1634760805
- mov $1634760805,%ecx
- # in5 = 824206446
- mov $824206446,%edx
- # in10 = 2036477238
- mov $2036477238,%ebx
- # in15 = 1797285236
- mov $1797285236,%esi
- # *(uint32 *) (x + 0) = in0
- movl %ecx,0(%eax)
- # *(uint32 *) (x + 20) = in5
- movl %edx,20(%eax)
- # *(uint32 *) (x + 40) = in10
- movl %ebx,40(%eax)
- # *(uint32 *) (x + 60) = in15
- movl %esi,60(%eax)
-._keysetupdone:
- # eax = eax_stack
- movl 64(%esp),%eax
- # ebx = ebx_stack
- movl 68(%esp),%ebx
- # esi = esi_stack
- movl 72(%esp),%esi
- # edi = edi_stack
- movl 76(%esp),%edi
- # ebp = ebp_stack
- movl 80(%esp),%ebp
- # leave
- add %eax,%esp
- ret
-ENDPROC(salsa20_keysetup)
-
-# enter salsa20_ivsetup
-ENTRY(salsa20_ivsetup)
- mov %esp,%eax
- and $31,%eax
- add $256,%eax
- sub %eax,%esp
- # eax_stack = eax
- movl %eax,64(%esp)
- # ebx_stack = ebx
- movl %ebx,68(%esp)
- # esi_stack = esi
- movl %esi,72(%esp)
- # edi_stack = edi
- movl %edi,76(%esp)
- # ebp_stack = ebp
- movl %ebp,80(%esp)
- # iv = arg2
- movl 8(%esp,%eax),%ecx
- # x = arg1
- movl 4(%esp,%eax),%eax
- # in6 = *(uint32 *) (iv + 0)
- movl 0(%ecx),%edx
- # in7 = *(uint32 *) (iv + 4)
- movl 4(%ecx),%ecx
- # in8 = 0
- mov $0,%ebx
- # in9 = 0
- mov $0,%esi
- # *(uint32 *) (x + 24) = in6
- movl %edx,24(%eax)
- # *(uint32 *) (x + 28) = in7
- movl %ecx,28(%eax)
- # *(uint32 *) (x + 32) = in8
- movl %ebx,32(%eax)
- # *(uint32 *) (x + 36) = in9
- movl %esi,36(%eax)
- # eax = eax_stack
- movl 64(%esp),%eax
- # ebx = ebx_stack
- movl 68(%esp),%ebx
- # esi = esi_stack
- movl 72(%esp),%esi
- # edi = edi_stack
- movl 76(%esp),%edi
- # ebp = ebp_stack
- movl 80(%esp),%ebp
- # leave
- add %eax,%esp
- ret
-ENDPROC(salsa20_ivsetup)
diff --git a/arch/x86/crypto/salsa20-x86_64-asm_64.S b/arch/x86/crypto/salsa20-x86_64-asm_64.S
deleted file mode 100644
index 10db30d5..0000000
--- a/arch/x86/crypto/salsa20-x86_64-asm_64.S
+++ /dev/null
@@ -1,919 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-
-# enter salsa20_encrypt_bytes
-ENTRY(salsa20_encrypt_bytes)
- mov %rsp,%r11
- and $31,%r11
- add $256,%r11
- sub %r11,%rsp
- # x = arg1
- mov %rdi,%r8
- # m = arg2
- mov %rsi,%rsi
- # out = arg3
- mov %rdx,%rdi
- # bytes = arg4
- mov %rcx,%rdx
- # unsigned>? bytes - 0
- cmp $0,%rdx
- # comment:fp stack unchanged by jump
- # goto done if !unsigned>
- jbe ._done
- # comment:fp stack unchanged by fallthrough
-# start:
-._start:
- # r11_stack = r11
- movq %r11,0(%rsp)
- # r12_stack = r12
- movq %r12,8(%rsp)
- # r13_stack = r13
- movq %r13,16(%rsp)
- # r14_stack = r14
- movq %r14,24(%rsp)
- # r15_stack = r15
- movq %r15,32(%rsp)
- # rbx_stack = rbx
- movq %rbx,40(%rsp)
- # rbp_stack = rbp
- movq %rbp,48(%rsp)
- # in0 = *(uint64 *) (x + 0)
- movq 0(%r8),%rcx
- # in2 = *(uint64 *) (x + 8)
- movq 8(%r8),%r9
- # in4 = *(uint64 *) (x + 16)
- movq 16(%r8),%rax
- # in6 = *(uint64 *) (x + 24)
- movq 24(%r8),%r10
- # in8 = *(uint64 *) (x + 32)
- movq 32(%r8),%r11
- # in10 = *(uint64 *) (x + 40)
- movq 40(%r8),%r12
- # in12 = *(uint64 *) (x + 48)
- movq 48(%r8),%r13
- # in14 = *(uint64 *) (x + 56)
- movq 56(%r8),%r14
- # j0 = in0
- movq %rcx,56(%rsp)
- # j2 = in2
- movq %r9,64(%rsp)
- # j4 = in4
- movq %rax,72(%rsp)
- # j6 = in6
- movq %r10,80(%rsp)
- # j8 = in8
- movq %r11,88(%rsp)
- # j10 = in10
- movq %r12,96(%rsp)
- # j12 = in12
- movq %r13,104(%rsp)
- # j14 = in14
- movq %r14,112(%rsp)
- # x_backup = x
- movq %r8,120(%rsp)
-# bytesatleast1:
-._bytesatleast1:
- # unsigned<? bytes - 64
- cmp $64,%rdx
- # comment:fp stack unchanged by jump
- # goto nocopy if !unsigned<
- jae ._nocopy
- # ctarget = out
- movq %rdi,128(%rsp)
- # out = &tmp
- leaq 192(%rsp),%rdi
- # i = bytes
- mov %rdx,%rcx
- # while (i) { *out++ = *m++; --i }
- rep movsb
- # out = &tmp
- leaq 192(%rsp),%rdi
- # m = &tmp
- leaq 192(%rsp),%rsi
- # comment:fp stack unchanged by fallthrough
-# nocopy:
-._nocopy:
- # out_backup = out
- movq %rdi,136(%rsp)
- # m_backup = m
- movq %rsi,144(%rsp)
- # bytes_backup = bytes
- movq %rdx,152(%rsp)
- # x1 = j0
- movq 56(%rsp),%rdi
- # x0 = x1
- mov %rdi,%rdx
- # (uint64) x1 >>= 32
- shr $32,%rdi
- # x3 = j2
- movq 64(%rsp),%rsi
- # x2 = x3
- mov %rsi,%rcx
- # (uint64) x3 >>= 32
- shr $32,%rsi
- # x5 = j4
- movq 72(%rsp),%r8
- # x4 = x5
- mov %r8,%r9
- # (uint64) x5 >>= 32
- shr $32,%r8
- # x5_stack = x5
- movq %r8,160(%rsp)
- # x7 = j6
- movq 80(%rsp),%r8
- # x6 = x7
- mov %r8,%rax
- # (uint64) x7 >>= 32
- shr $32,%r8
- # x9 = j8
- movq 88(%rsp),%r10
- # x8 = x9
- mov %r10,%r11
- # (uint64) x9 >>= 32
- shr $32,%r10
- # x11 = j10
- movq 96(%rsp),%r12
- # x10 = x11
- mov %r12,%r13
- # x10_stack = x10
- movq %r13,168(%rsp)
- # (uint64) x11 >>= 32
- shr $32,%r12
- # x13 = j12
- movq 104(%rsp),%r13
- # x12 = x13
- mov %r13,%r14
- # (uint64) x13 >>= 32
- shr $32,%r13
- # x15 = j14
- movq 112(%rsp),%r15
- # x14 = x15
- mov %r15,%rbx
- # (uint64) x15 >>= 32
- shr $32,%r15
- # x15_stack = x15
- movq %r15,176(%rsp)
- # i = 20
- mov $20,%r15
-# mainloop:
-._mainloop:
- # i_backup = i
- movq %r15,184(%rsp)
- # x5 = x5_stack
- movq 160(%rsp),%r15
- # a = x12 + x0
- lea (%r14,%rdx),%rbp
- # (uint32) a <<<= 7
- rol $7,%ebp
- # x4 ^= a
- xor %rbp,%r9
- # b = x1 + x5
- lea (%rdi,%r15),%rbp
- # (uint32) b <<<= 7
- rol $7,%ebp
- # x9 ^= b
- xor %rbp,%r10
- # a = x0 + x4
- lea (%rdx,%r9),%rbp
- # (uint32) a <<<= 9
- rol $9,%ebp
- # x8 ^= a
- xor %rbp,%r11
- # b = x5 + x9
- lea (%r15,%r10),%rbp
- # (uint32) b <<<= 9
- rol $9,%ebp
- # x13 ^= b
- xor %rbp,%r13
- # a = x4 + x8
- lea (%r9,%r11),%rbp
- # (uint32) a <<<= 13
- rol $13,%ebp
- # x12 ^= a
- xor %rbp,%r14
- # b = x9 + x13
- lea (%r10,%r13),%rbp
- # (uint32) b <<<= 13
- rol $13,%ebp
- # x1 ^= b
- xor %rbp,%rdi
- # a = x8 + x12
- lea (%r11,%r14),%rbp
- # (uint32) a <<<= 18
- rol $18,%ebp
- # x0 ^= a
- xor %rbp,%rdx
- # b = x13 + x1
- lea (%r13,%rdi),%rbp
- # (uint32) b <<<= 18
- rol $18,%ebp
- # x5 ^= b
- xor %rbp,%r15
- # x10 = x10_stack
- movq 168(%rsp),%rbp
- # x5_stack = x5
- movq %r15,160(%rsp)
- # c = x6 + x10
- lea (%rax,%rbp),%r15
- # (uint32) c <<<= 7
- rol $7,%r15d
- # x14 ^= c
- xor %r15,%rbx
- # c = x10 + x14
- lea (%rbp,%rbx),%r15
- # (uint32) c <<<= 9
- rol $9,%r15d
- # x2 ^= c
- xor %r15,%rcx
- # c = x14 + x2
- lea (%rbx,%rcx),%r15
- # (uint32) c <<<= 13
- rol $13,%r15d
- # x6 ^= c
- xor %r15,%rax
- # c = x2 + x6
- lea (%rcx,%rax),%r15
- # (uint32) c <<<= 18
- rol $18,%r15d
- # x10 ^= c
- xor %r15,%rbp
- # x15 = x15_stack
- movq 176(%rsp),%r15
- # x10_stack = x10
- movq %rbp,168(%rsp)
- # d = x11 + x15
- lea (%r12,%r15),%rbp
- # (uint32) d <<<= 7
- rol $7,%ebp
- # x3 ^= d
- xor %rbp,%rsi
- # d = x15 + x3
- lea (%r15,%rsi),%rbp
- # (uint32) d <<<= 9
- rol $9,%ebp
- # x7 ^= d
- xor %rbp,%r8
- # d = x3 + x7
- lea (%rsi,%r8),%rbp
- # (uint32) d <<<= 13
- rol $13,%ebp
- # x11 ^= d
- xor %rbp,%r12
- # d = x7 + x11
- lea (%r8,%r12),%rbp
- # (uint32) d <<<= 18
- rol $18,%ebp
- # x15 ^= d
- xor %rbp,%r15
- # x15_stack = x15
- movq %r15,176(%rsp)
- # x5 = x5_stack
- movq 160(%rsp),%r15
- # a = x3 + x0
- lea (%rsi,%rdx),%rbp
- # (uint32) a <<<= 7
- rol $7,%ebp
- # x1 ^= a
- xor %rbp,%rdi
- # b = x4 + x5
- lea (%r9,%r15),%rbp
- # (uint32) b <<<= 7
- rol $7,%ebp
- # x6 ^= b
- xor %rbp,%rax
- # a = x0 + x1
- lea (%rdx,%rdi),%rbp
- # (uint32) a <<<= 9
- rol $9,%ebp
- # x2 ^= a
- xor %rbp,%rcx
- # b = x5 + x6
- lea (%r15,%rax),%rbp
- # (uint32) b <<<= 9
- rol $9,%ebp
- # x7 ^= b
- xor %rbp,%r8
- # a = x1 + x2
- lea (%rdi,%rcx),%rbp
- # (uint32) a <<<= 13
- rol $13,%ebp
- # x3 ^= a
- xor %rbp,%rsi
- # b = x6 + x7
- lea (%rax,%r8),%rbp
- # (uint32) b <<<= 13
- rol $13,%ebp
- # x4 ^= b
- xor %rbp,%r9
- # a = x2 + x3
- lea (%rcx,%rsi),%rbp
- # (uint32) a <<<= 18
- rol $18,%ebp
- # x0 ^= a
- xor %rbp,%rdx
- # b = x7 + x4
- lea (%r8,%r9),%rbp
- # (uint32) b <<<= 18
- rol $18,%ebp
- # x5 ^= b
- xor %rbp,%r15
- # x10 = x10_stack
- movq 168(%rsp),%rbp
- # x5_stack = x5
- movq %r15,160(%rsp)
- # c = x9 + x10
- lea (%r10,%rbp),%r15
- # (uint32) c <<<= 7
- rol $7,%r15d
- # x11 ^= c
- xor %r15,%r12
- # c = x10 + x11
- lea (%rbp,%r12),%r15
- # (uint32) c <<<= 9
- rol $9,%r15d
- # x8 ^= c
- xor %r15,%r11
- # c = x11 + x8
- lea (%r12,%r11),%r15
- # (uint32) c <<<= 13
- rol $13,%r15d
- # x9 ^= c
- xor %r15,%r10
- # c = x8 + x9
- lea (%r11,%r10),%r15
- # (uint32) c <<<= 18
- rol $18,%r15d
- # x10 ^= c
- xor %r15,%rbp
- # x15 = x15_stack
- movq 176(%rsp),%r15
- # x10_stack = x10
- movq %rbp,168(%rsp)
- # d = x14 + x15
- lea (%rbx,%r15),%rbp
- # (uint32) d <<<= 7
- rol $7,%ebp
- # x12 ^= d
- xor %rbp,%r14
- # d = x15 + x12
- lea (%r15,%r14),%rbp
- # (uint32) d <<<= 9
- rol $9,%ebp
- # x13 ^= d
- xor %rbp,%r13
- # d = x12 + x13
- lea (%r14,%r13),%rbp
- # (uint32) d <<<= 13
- rol $13,%ebp
- # x14 ^= d
- xor %rbp,%rbx
- # d = x13 + x14
- lea (%r13,%rbx),%rbp
- # (uint32) d <<<= 18
- rol $18,%ebp
- # x15 ^= d
- xor %rbp,%r15
- # x15_stack = x15
- movq %r15,176(%rsp)
- # x5 = x5_stack
- movq 160(%rsp),%r15
- # a = x12 + x0
- lea (%r14,%rdx),%rbp
- # (uint32) a <<<= 7
- rol $7,%ebp
- # x4 ^= a
- xor %rbp,%r9
- # b = x1 + x5
- lea (%rdi,%r15),%rbp
- # (uint32) b <<<= 7
- rol $7,%ebp
- # x9 ^= b
- xor %rbp,%r10
- # a = x0 + x4
- lea (%rdx,%r9),%rbp
- # (uint32) a <<<= 9
- rol $9,%ebp
- # x8 ^= a
- xor %rbp,%r11
- # b = x5 + x9
- lea (%r15,%r10),%rbp
- # (uint32) b <<<= 9
- rol $9,%ebp
- # x13 ^= b
- xor %rbp,%r13
- # a = x4 + x8
- lea (%r9,%r11),%rbp
- # (uint32) a <<<= 13
- rol $13,%ebp
- # x12 ^= a
- xor %rbp,%r14
- # b = x9 + x13
- lea (%r10,%r13),%rbp
- # (uint32) b <<<= 13
- rol $13,%ebp
- # x1 ^= b
- xor %rbp,%rdi
- # a = x8 + x12
- lea (%r11,%r14),%rbp
- # (uint32) a <<<= 18
- rol $18,%ebp
- # x0 ^= a
- xor %rbp,%rdx
- # b = x13 + x1
- lea (%r13,%rdi),%rbp
- # (uint32) b <<<= 18
- rol $18,%ebp
- # x5 ^= b
- xor %rbp,%r15
- # x10 = x10_stack
- movq 168(%rsp),%rbp
- # x5_stack = x5
- movq %r15,160(%rsp)
- # c = x6 + x10
- lea (%rax,%rbp),%r15
- # (uint32) c <<<= 7
- rol $7,%r15d
- # x14 ^= c
- xor %r15,%rbx
- # c = x10 + x14
- lea (%rbp,%rbx),%r15
- # (uint32) c <<<= 9
- rol $9,%r15d
- # x2 ^= c
- xor %r15,%rcx
- # c = x14 + x2
- lea (%rbx,%rcx),%r15
- # (uint32) c <<<= 13
- rol $13,%r15d
- # x6 ^= c
- xor %r15,%rax
- # c = x2 + x6
- lea (%rcx,%rax),%r15
- # (uint32) c <<<= 18
- rol $18,%r15d
- # x10 ^= c
- xor %r15,%rbp
- # x15 = x15_stack
- movq 176(%rsp),%r15
- # x10_stack = x10
- movq %rbp,168(%rsp)
- # d = x11 + x15
- lea (%r12,%r15),%rbp
- # (uint32) d <<<= 7
- rol $7,%ebp
- # x3 ^= d
- xor %rbp,%rsi
- # d = x15 + x3
- lea (%r15,%rsi),%rbp
- # (uint32) d <<<= 9
- rol $9,%ebp
- # x7 ^= d
- xor %rbp,%r8
- # d = x3 + x7
- lea (%rsi,%r8),%rbp
- # (uint32) d <<<= 13
- rol $13,%ebp
- # x11 ^= d
- xor %rbp,%r12
- # d = x7 + x11
- lea (%r8,%r12),%rbp
- # (uint32) d <<<= 18
- rol $18,%ebp
- # x15 ^= d
- xor %rbp,%r15
- # x15_stack = x15
- movq %r15,176(%rsp)
- # x5 = x5_stack
- movq 160(%rsp),%r15
- # a = x3 + x0
- lea (%rsi,%rdx),%rbp
- # (uint32) a <<<= 7
- rol $7,%ebp
- # x1 ^= a
- xor %rbp,%rdi
- # b = x4 + x5
- lea (%r9,%r15),%rbp
- # (uint32) b <<<= 7
- rol $7,%ebp
- # x6 ^= b
- xor %rbp,%rax
- # a = x0 + x1
- lea (%rdx,%rdi),%rbp
- # (uint32) a <<<= 9
- rol $9,%ebp
- # x2 ^= a
- xor %rbp,%rcx
- # b = x5 + x6
- lea (%r15,%rax),%rbp
- # (uint32) b <<<= 9
- rol $9,%ebp
- # x7 ^= b
- xor %rbp,%r8
- # a = x1 + x2
- lea (%rdi,%rcx),%rbp
- # (uint32) a <<<= 13
- rol $13,%ebp
- # x3 ^= a
- xor %rbp,%rsi
- # b = x6 + x7
- lea (%rax,%r8),%rbp
- # (uint32) b <<<= 13
- rol $13,%ebp
- # x4 ^= b
- xor %rbp,%r9
- # a = x2 + x3
- lea (%rcx,%rsi),%rbp
- # (uint32) a <<<= 18
- rol $18,%ebp
- # x0 ^= a
- xor %rbp,%rdx
- # b = x7 + x4
- lea (%r8,%r9),%rbp
- # (uint32) b <<<= 18
- rol $18,%ebp
- # x5 ^= b
- xor %rbp,%r15
- # x10 = x10_stack
- movq 168(%rsp),%rbp
- # x5_stack = x5
- movq %r15,160(%rsp)
- # c = x9 + x10
- lea (%r10,%rbp),%r15
- # (uint32) c <<<= 7
- rol $7,%r15d
- # x11 ^= c
- xor %r15,%r12
- # c = x10 + x11
- lea (%rbp,%r12),%r15
- # (uint32) c <<<= 9
- rol $9,%r15d
- # x8 ^= c
- xor %r15,%r11
- # c = x11 + x8
- lea (%r12,%r11),%r15
- # (uint32) c <<<= 13
- rol $13,%r15d
- # x9 ^= c
- xor %r15,%r10
- # c = x8 + x9
- lea (%r11,%r10),%r15
- # (uint32) c <<<= 18
- rol $18,%r15d
- # x10 ^= c
- xor %r15,%rbp
- # x15 = x15_stack
- movq 176(%rsp),%r15
- # x10_stack = x10
- movq %rbp,168(%rsp)
- # d = x14 + x15
- lea (%rbx,%r15),%rbp
- # (uint32) d <<<= 7
- rol $7,%ebp
- # x12 ^= d
- xor %rbp,%r14
- # d = x15 + x12
- lea (%r15,%r14),%rbp
- # (uint32) d <<<= 9
- rol $9,%ebp
- # x13 ^= d
- xor %rbp,%r13
- # d = x12 + x13
- lea (%r14,%r13),%rbp
- # (uint32) d <<<= 13
- rol $13,%ebp
- # x14 ^= d
- xor %rbp,%rbx
- # d = x13 + x14
- lea (%r13,%rbx),%rbp
- # (uint32) d <<<= 18
- rol $18,%ebp
- # x15 ^= d
- xor %rbp,%r15
- # x15_stack = x15
- movq %r15,176(%rsp)
- # i = i_backup
- movq 184(%rsp),%r15
- # unsigned>? i -= 4
- sub $4,%r15
- # comment:fp stack unchanged by jump
- # goto mainloop if unsigned>
- ja ._mainloop
- # (uint32) x2 += j2
- addl 64(%rsp),%ecx
- # x3 <<= 32
- shl $32,%rsi
- # x3 += j2
- addq 64(%rsp),%rsi
- # (uint64) x3 >>= 32
- shr $32,%rsi
- # x3 <<= 32
- shl $32,%rsi
- # x2 += x3
- add %rsi,%rcx
- # (uint32) x6 += j6
- addl 80(%rsp),%eax
- # x7 <<= 32
- shl $32,%r8
- # x7 += j6
- addq 80(%rsp),%r8
- # (uint64) x7 >>= 32
- shr $32,%r8
- # x7 <<= 32
- shl $32,%r8
- # x6 += x7
- add %r8,%rax
- # (uint32) x8 += j8
- addl 88(%rsp),%r11d
- # x9 <<= 32
- shl $32,%r10
- # x9 += j8
- addq 88(%rsp),%r10
- # (uint64) x9 >>= 32
- shr $32,%r10
- # x9 <<= 32
- shl $32,%r10
- # x8 += x9
- add %r10,%r11
- # (uint32) x12 += j12
- addl 104(%rsp),%r14d
- # x13 <<= 32
- shl $32,%r13
- # x13 += j12
- addq 104(%rsp),%r13
- # (uint64) x13 >>= 32
- shr $32,%r13
- # x13 <<= 32
- shl $32,%r13
- # x12 += x13
- add %r13,%r14
- # (uint32) x0 += j0
- addl 56(%rsp),%edx
- # x1 <<= 32
- shl $32,%rdi
- # x1 += j0
- addq 56(%rsp),%rdi
- # (uint64) x1 >>= 32
- shr $32,%rdi
- # x1 <<= 32
- shl $32,%rdi
- # x0 += x1
- add %rdi,%rdx
- # x5 = x5_stack
- movq 160(%rsp),%rdi
- # (uint32) x4 += j4
- addl 72(%rsp),%r9d
- # x5 <<= 32
- shl $32,%rdi
- # x5 += j4
- addq 72(%rsp),%rdi
- # (uint64) x5 >>= 32
- shr $32,%rdi
- # x5 <<= 32
- shl $32,%rdi
- # x4 += x5
- add %rdi,%r9
- # x10 = x10_stack
- movq 168(%rsp),%r8
- # (uint32) x10 += j10
- addl 96(%rsp),%r8d
- # x11 <<= 32
- shl $32,%r12
- # x11 += j10
- addq 96(%rsp),%r12
- # (uint64) x11 >>= 32
- shr $32,%r12
- # x11 <<= 32
- shl $32,%r12
- # x10 += x11
- add %r12,%r8
- # x15 = x15_stack
- movq 176(%rsp),%rdi
- # (uint32) x14 += j14
- addl 112(%rsp),%ebx
- # x15 <<= 32
- shl $32,%rdi
- # x15 += j14
- addq 112(%rsp),%rdi
- # (uint64) x15 >>= 32
- shr $32,%rdi
- # x15 <<= 32
- shl $32,%rdi
- # x14 += x15
- add %rdi,%rbx
- # out = out_backup
- movq 136(%rsp),%rdi
- # m = m_backup
- movq 144(%rsp),%rsi
- # x0 ^= *(uint64 *) (m + 0)
- xorq 0(%rsi),%rdx
- # *(uint64 *) (out + 0) = x0
- movq %rdx,0(%rdi)
- # x2 ^= *(uint64 *) (m + 8)
- xorq 8(%rsi),%rcx
- # *(uint64 *) (out + 8) = x2
- movq %rcx,8(%rdi)
- # x4 ^= *(uint64 *) (m + 16)
- xorq 16(%rsi),%r9
- # *(uint64 *) (out + 16) = x4
- movq %r9,16(%rdi)
- # x6 ^= *(uint64 *) (m + 24)
- xorq 24(%rsi),%rax
- # *(uint64 *) (out + 24) = x6
- movq %rax,24(%rdi)
- # x8 ^= *(uint64 *) (m + 32)
- xorq 32(%rsi),%r11
- # *(uint64 *) (out + 32) = x8
- movq %r11,32(%rdi)
- # x10 ^= *(uint64 *) (m + 40)
- xorq 40(%rsi),%r8
- # *(uint64 *) (out + 40) = x10
- movq %r8,40(%rdi)
- # x12 ^= *(uint64 *) (m + 48)
- xorq 48(%rsi),%r14
- # *(uint64 *) (out + 48) = x12
- movq %r14,48(%rdi)
- # x14 ^= *(uint64 *) (m + 56)
- xorq 56(%rsi),%rbx
- # *(uint64 *) (out + 56) = x14
- movq %rbx,56(%rdi)
- # bytes = bytes_backup
- movq 152(%rsp),%rdx
- # in8 = j8
- movq 88(%rsp),%rcx
- # in8 += 1
- add $1,%rcx
- # j8 = in8
- movq %rcx,88(%rsp)
- # unsigned>? unsigned<? bytes - 64
- cmp $64,%rdx
- # comment:fp stack unchanged by jump
- # goto bytesatleast65 if unsigned>
- ja ._bytesatleast65
- # comment:fp stack unchanged by jump
- # goto bytesatleast64 if !unsigned<
- jae ._bytesatleast64
- # m = out
- mov %rdi,%rsi
- # out = ctarget
- movq 128(%rsp),%rdi
- # i = bytes
- mov %rdx,%rcx
- # while (i) { *out++ = *m++; --i }
- rep movsb
- # comment:fp stack unchanged by fallthrough
-# bytesatleast64:
-._bytesatleast64:
- # x = x_backup
- movq 120(%rsp),%rdi
- # in8 = j8
- movq 88(%rsp),%rsi
- # *(uint64 *) (x + 32) = in8
- movq %rsi,32(%rdi)
- # r11 = r11_stack
- movq 0(%rsp),%r11
- # r12 = r12_stack
- movq 8(%rsp),%r12
- # r13 = r13_stack
- movq 16(%rsp),%r13
- # r14 = r14_stack
- movq 24(%rsp),%r14
- # r15 = r15_stack
- movq 32(%rsp),%r15
- # rbx = rbx_stack
- movq 40(%rsp),%rbx
- # rbp = rbp_stack
- movq 48(%rsp),%rbp
- # comment:fp stack unchanged by fallthrough
-# done:
-._done:
- # leave
- add %r11,%rsp
- mov %rdi,%rax
- mov %rsi,%rdx
- ret
-# bytesatleast65:
-._bytesatleast65:
- # bytes -= 64
- sub $64,%rdx
- # out += 64
- add $64,%rdi
- # m += 64
- add $64,%rsi
- # comment:fp stack unchanged by jump
- # goto bytesatleast1
- jmp ._bytesatleast1
-ENDPROC(salsa20_encrypt_bytes)
-
-# enter salsa20_keysetup
-ENTRY(salsa20_keysetup)
- mov %rsp,%r11
- and $31,%r11
- add $256,%r11
- sub %r11,%rsp
- # k = arg2
- mov %rsi,%rsi
- # kbits = arg3
- mov %rdx,%rdx
- # x = arg1
- mov %rdi,%rdi
- # in0 = *(uint64 *) (k + 0)
- movq 0(%rsi),%r8
- # in2 = *(uint64 *) (k + 8)
- movq 8(%rsi),%r9
- # *(uint64 *) (x + 4) = in0
- movq %r8,4(%rdi)
- # *(uint64 *) (x + 12) = in2
- movq %r9,12(%rdi)
- # unsigned<? kbits - 256
- cmp $256,%rdx
- # comment:fp stack unchanged by jump
- # goto kbits128 if unsigned<
- jb ._kbits128
-# kbits256:
-._kbits256:
- # in10 = *(uint64 *) (k + 16)
- movq 16(%rsi),%rdx
- # in12 = *(uint64 *) (k + 24)
- movq 24(%rsi),%rsi
- # *(uint64 *) (x + 44) = in10
- movq %rdx,44(%rdi)
- # *(uint64 *) (x + 52) = in12
- movq %rsi,52(%rdi)
- # in0 = 1634760805
- mov $1634760805,%rsi
- # in4 = 857760878
- mov $857760878,%rdx
- # in10 = 2036477234
- mov $2036477234,%rcx
- # in14 = 1797285236
- mov $1797285236,%r8
- # *(uint32 *) (x + 0) = in0
- movl %esi,0(%rdi)
- # *(uint32 *) (x + 20) = in4
- movl %edx,20(%rdi)
- # *(uint32 *) (x + 40) = in10
- movl %ecx,40(%rdi)
- # *(uint32 *) (x + 60) = in14
- movl %r8d,60(%rdi)
- # comment:fp stack unchanged by jump
- # goto keysetupdone
- jmp ._keysetupdone
-# kbits128:
-._kbits128:
- # in10 = *(uint64 *) (k + 0)
- movq 0(%rsi),%rdx
- # in12 = *(uint64 *) (k + 8)
- movq 8(%rsi),%rsi
- # *(uint64 *) (x + 44) = in10
- movq %rdx,44(%rdi)
- # *(uint64 *) (x + 52) = in12
- movq %rsi,52(%rdi)
- # in0 = 1634760805
- mov $1634760805,%rsi
- # in4 = 824206446
- mov $824206446,%rdx
- # in10 = 2036477238
- mov $2036477238,%rcx
- # in14 = 1797285236
- mov $1797285236,%r8
- # *(uint32 *) (x + 0) = in0
- movl %esi,0(%rdi)
- # *(uint32 *) (x + 20) = in4
- movl %edx,20(%rdi)
- # *(uint32 *) (x + 40) = in10
- movl %ecx,40(%rdi)
- # *(uint32 *) (x + 60) = in14
- movl %r8d,60(%rdi)
-# keysetupdone:
-._keysetupdone:
- # leave
- add %r11,%rsp
- mov %rdi,%rax
- mov %rsi,%rdx
- ret
-ENDPROC(salsa20_keysetup)
-
-# enter salsa20_ivsetup
-ENTRY(salsa20_ivsetup)
- mov %rsp,%r11
- and $31,%r11
- add $256,%r11
- sub %r11,%rsp
- # iv = arg2
- mov %rsi,%rsi
- # x = arg1
- mov %rdi,%rdi
- # in6 = *(uint64 *) (iv + 0)
- movq 0(%rsi),%rsi
- # in8 = 0
- mov $0,%r8
- # *(uint64 *) (x + 24) = in6
- movq %rsi,24(%rdi)
- # *(uint64 *) (x + 32) = in8
- movq %r8,32(%rdi)
- # leave
- add %r11,%rsp
- mov %rdi,%rax
- mov %rsi,%rdx
- ret
-ENDPROC(salsa20_ivsetup)
diff --git a/arch/x86/crypto/salsa20_glue.c b/arch/x86/crypto/salsa20_glue.c
deleted file mode 100644
index cb91a64..0000000
--- a/arch/x86/crypto/salsa20_glue.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Glue code for optimized assembly version of Salsa20.
- *
- * Copyright (c) 2007 Tan Swee Heng <thesweeheng@gmail.com>
- *
- * The assembly codes are public domain assembly codes written by Daniel. J.
- * Bernstein <djb@cr.yp.to>. The codes are modified to include indentation
- * and to remove extraneous comments and functions that are not needed.
- * - i586 version, renamed as salsa20-i586-asm_32.S
- * available from <http://cr.yp.to/snuffle/salsa20/x86-pm/salsa20.s>
- * - x86-64 version, renamed as salsa20-x86_64-asm_64.S
- * available from <http://cr.yp.to/snuffle/salsa20/amd64-3/salsa20.s>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- */
-
-#include <crypto/algapi.h>
-#include <linux/module.h>
-#include <linux/crypto.h>
-
-#define SALSA20_IV_SIZE 8U
-#define SALSA20_MIN_KEY_SIZE 16U
-#define SALSA20_MAX_KEY_SIZE 32U
-
-struct salsa20_ctx
-{
- u32 input[16];
-};
-
-asmlinkage void salsa20_keysetup(struct salsa20_ctx *ctx, const u8 *k,
- u32 keysize, u32 ivsize);
-asmlinkage void salsa20_ivsetup(struct salsa20_ctx *ctx, const u8 *iv);
-asmlinkage void salsa20_encrypt_bytes(struct salsa20_ctx *ctx,
- const u8 *src, u8 *dst, u32 bytes);
-
-static int setkey(struct crypto_tfm *tfm, const u8 *key,
- unsigned int keysize)
-{
- struct salsa20_ctx *ctx = crypto_tfm_ctx(tfm);
- salsa20_keysetup(ctx, key, keysize*8, SALSA20_IV_SIZE*8);
- return 0;
-}
-
-static int encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct blkcipher_walk walk;
- struct crypto_blkcipher *tfm = desc->tfm;
- struct salsa20_ctx *ctx = crypto_blkcipher_ctx(tfm);
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt_block(desc, &walk, 64);
-
- salsa20_ivsetup(ctx, walk.iv);
-
- while (walk.nbytes >= 64) {
- salsa20_encrypt_bytes(ctx, walk.src.virt.addr,
- walk.dst.virt.addr,
- walk.nbytes - (walk.nbytes % 64));
- err = blkcipher_walk_done(desc, &walk, walk.nbytes % 64);
- }
-
- if (walk.nbytes) {
- salsa20_encrypt_bytes(ctx, walk.src.virt.addr,
- walk.dst.virt.addr, walk.nbytes);
- err = blkcipher_walk_done(desc, &walk, 0);
- }
-
- return err;
-}
-
-static struct crypto_alg alg = {
- .cra_name = "salsa20",
- .cra_driver_name = "salsa20-asm",
- .cra_priority = 200,
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_type = &crypto_blkcipher_type,
- .cra_blocksize = 1,
- .cra_ctxsize = sizeof(struct salsa20_ctx),
- .cra_alignmask = 3,
- .cra_module = THIS_MODULE,
- .cra_u = {
- .blkcipher = {
- .setkey = setkey,
- .encrypt = encrypt,
- .decrypt = encrypt,
- .min_keysize = SALSA20_MIN_KEY_SIZE,
- .max_keysize = SALSA20_MAX_KEY_SIZE,
- .ivsize = SALSA20_IV_SIZE,
- }
- }
-};
-
-static int __init init(void)
-{
- return crypto_register_alg(&alg);
-}
-
-static void __exit fini(void)
-{
- crypto_unregister_alg(&alg);
-}
-
-module_init(init);
-module_exit(fini);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION ("Salsa20 stream cipher algorithm (optimized assembly version)");
-MODULE_ALIAS_CRYPTO("salsa20");
-MODULE_ALIAS_CRYPTO("salsa20-asm");
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 8243fdb..2dae3f5 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3035,11 +3035,19 @@
NULL,
};
+/* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */
+static struct event_constraint bdx_uncore_pcu_constraints[] = {
+ EVENT_CONSTRAINT(0x80, 0xe, 0x80),
+ EVENT_CONSTRAINT_END
+};
+
void bdx_uncore_cpu_init(void)
{
if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
uncore_msr_uncores = bdx_msr_uncores;
+
+ hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints;
}
static struct intel_uncore_type bdx_uncore_ha = {
diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h
index 386a690..3bf87f9 100644
--- a/arch/x86/include/asm/asm.h
+++ b/arch/x86/include/asm/asm.h
@@ -46,6 +46,65 @@
#define _ASM_SI __ASM_REG(si)
#define _ASM_DI __ASM_REG(di)
+#ifndef __x86_64__
+/* 32 bit */
+
+#define _ASM_ARG1 _ASM_AX
+#define _ASM_ARG2 _ASM_DX
+#define _ASM_ARG3 _ASM_CX
+
+#define _ASM_ARG1L eax
+#define _ASM_ARG2L edx
+#define _ASM_ARG3L ecx
+
+#define _ASM_ARG1W ax
+#define _ASM_ARG2W dx
+#define _ASM_ARG3W cx
+
+#define _ASM_ARG1B al
+#define _ASM_ARG2B dl
+#define _ASM_ARG3B cl
+
+#else
+/* 64 bit */
+
+#define _ASM_ARG1 _ASM_DI
+#define _ASM_ARG2 _ASM_SI
+#define _ASM_ARG3 _ASM_DX
+#define _ASM_ARG4 _ASM_CX
+#define _ASM_ARG5 r8
+#define _ASM_ARG6 r9
+
+#define _ASM_ARG1Q rdi
+#define _ASM_ARG2Q rsi
+#define _ASM_ARG3Q rdx
+#define _ASM_ARG4Q rcx
+#define _ASM_ARG5Q r8
+#define _ASM_ARG6Q r9
+
+#define _ASM_ARG1L edi
+#define _ASM_ARG2L esi
+#define _ASM_ARG3L edx
+#define _ASM_ARG4L ecx
+#define _ASM_ARG5L r8d
+#define _ASM_ARG6L r9d
+
+#define _ASM_ARG1W di
+#define _ASM_ARG2W si
+#define _ASM_ARG3W dx
+#define _ASM_ARG4W cx
+#define _ASM_ARG5W r8w
+#define _ASM_ARG6W r9w
+
+#define _ASM_ARG1B dil
+#define _ASM_ARG2B sil
+#define _ASM_ARG3B dl
+#define _ASM_ARG4B cl
+#define _ASM_ARG5B r8b
+#define _ASM_ARG6B r9b
+
+#endif
+
/*
* Macros to generate condition code outputs from inline assembly,
* The output operand must be type "bool".
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index 4db7773..a04f0c2 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -38,7 +38,7 @@
{
unsigned long mask;
- asm ("cmp %1,%2; sbb %0,%0;"
+ asm volatile ("cmp %1,%2; sbb %0,%0;"
:"=r" (mask)
:"g"(size),"r" (index)
:"cc");
diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h
index 89f0895..c4fc172 100644
--- a/arch/x86/include/asm/irqflags.h
+++ b/arch/x86/include/asm/irqflags.h
@@ -13,7 +13,7 @@
* Interrupt control:
*/
-static inline unsigned long native_save_fl(void)
+extern inline unsigned long native_save_fl(void)
{
unsigned long flags;
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index f2bfbe58..ae13bc9 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -32,12 +32,6 @@
extern u64 relocated_ramdisk;
-#ifdef CONFIG_CHROMEOS
-void cpu_control_vmx(int cpu);
-#else
-static inline void cpu_control_vmx(int cpu) { }
-#endif
-
/* Interrupt control for vSMPowered x86_64 systems */
#ifdef CONFIG_X86_64
void vsmp_init(void);
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 09399da..e240271 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -58,6 +58,7 @@
obj-y += tsc.o tsc_msr.o io_delay.o rtc.o
obj-y += pci-iommu_table.o
obj-y += resource.o
+obj-y += irqflags.o
obj-y += process.o
obj-y += fpu/
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index ebdcc36..090cb47 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -478,6 +478,26 @@
return 0;
}
+static int lapic_event_expired(struct clock_event_device *evt)
+{
+ u32 cct;
+
+ cct = apic_read(APIC_TMCCT);
+ return cct == 0 ? 1 : 0;
+}
+
+static int lapic_deadline_expired(struct clock_event_device *evt)
+{
+ u64 msr;
+
+ /*
+ * When the timer interrupt is triggered, the register is cleared, so a
+ * non-zero value indicates a pending timer event.
+ */
+ rdmsrl(MSR_IA32_TSC_DEADLINE, msr);
+ return msr == 0 ? 1 : 0;
+}
+
static int lapic_timer_shutdown(struct clock_event_device *evt)
{
unsigned int v;
@@ -532,13 +552,15 @@
.name = "lapic",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
- | CLOCK_EVT_FEAT_DUMMY,
+ | CLOCK_EVT_FEAT_DUMMY
+ | CLOCK_EVT_FEAT_FREEZE_NONSTOP,
.shift = 32,
.set_state_shutdown = lapic_timer_shutdown,
.set_state_periodic = lapic_timer_set_periodic,
.set_state_oneshot = lapic_timer_set_oneshot,
.set_state_oneshot_stopped = lapic_timer_shutdown,
.set_next_event = lapic_next_event,
+ .event_expired = lapic_event_expired,
.broadcast = lapic_timer_broadcast,
.rating = 100,
.irq = -1,
@@ -657,6 +679,7 @@
levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_DUMMY);
levt->set_next_event = lapic_next_deadline;
+ levt->event_expired = lapic_deadline_expired;
clockevents_config_and_register(levt,
tsc_khz * (1000 / TSC_DIVISOR),
0xF, ~0UL);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b95c53f..48e9896 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -24,7 +24,6 @@
#include <asm/hypervisor.h>
#include <asm/processor.h>
#include <asm/tlbflush.h>
-#include <asm/virtext.h>
#include <asm/debugreg.h>
#include <asm/sections.h>
#include <asm/vsyscall.h>
@@ -1258,9 +1257,6 @@
setup_smep(c);
setup_smap(c);
- /* Enable or disable virtualization extensions */
- cpu_control_vmx(c->cpu_index);
-
/*
* The vendor-specific functions might have changed features.
* Now we do "generic changes."
@@ -1567,95 +1563,6 @@
#define dbg_restore_debug_regs()
#endif /* ! CONFIG_KGDB */
-#ifdef CONFIG_CHROMEOS
-static int disablevmx = 1;
-static int __init dodisablevmx(char *value)
-{
- if (!value)
- return 0;
- if (!strncmp(value, "on", 2))
- return 0;
- if (!strncmp(value, "off", 3)) {
- disablevmx = 0;
- return 0;
- }
- return 1;
-}
-early_param("disablevmx", dodisablevmx);
-
-static void clear_feature_vmx(int cpu)
-{
- if (disablevmx && cpu == boot_cpu_data.cpu_index)
- setup_clear_cpu_cap(X86_FEATURE_VMX);
-}
-
-void cpu_control_vmx(int cpu)
-{
- int ret;
- u64 msr;
- u64 bits;
- /* ChromeOS currently requires a disablevmx option
- * in the cmdline that will make a reasonable
- * attempt to set the IA32 FEATURE register to
- * 1, meaning vmx disabled and locked out.
- */
- if (!cpu_has_vmx())
- return;
-
- rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
-
- bits = msr;
-
- if (disablevmx)
- bits &= ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX|
- FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX);
- else
- bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX|
- FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
- bits |= FEATURE_CONTROL_LOCKED;
-
- /* If nothing to do, check if VMX Feature flag needs to be disabled. */
- if (msr == bits) {
- clear_feature_vmx(cpu);
- return;
- }
-
- /* if it's locked, there's really nothing we can do. */
- if ((msr & FEATURE_CONTROL_LOCKED) && (msr != bits)) {
- /* But only warn them if it's not what we want. */
- pr_warn("can not %s VMX on CPU%d (already locked)\n",
- disablevmx ? "disable" : "enable", cpu);
- return;
- }
-
- pr_info("%s VMX on cpu %d\n",
- disablevmx ? "Disabling" : "Enabling", cpu);
- ret = wrmsrl_safe(MSR_IA32_FEATURE_CONTROL, bits);
- if (!ret) {
- clear_feature_vmx(cpu);
- return;
- }
-
- pr_warn("wrmsrl_safe (MSR_IA32_FEATURE_CONTROL, %08llx) failed error %d\n",
- bits, ret);
-
- /* Not all CPUs support FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
- * even if they support FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX.
- * If setting both options fails, clear the
- * FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX option and try again.
- * If the second wrmsr fails, there's nothing more we can do.
- */
- bits &= ~FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
-
- ret = wrmsrl_safe(MSR_IA32_FEATURE_CONTROL, bits);
- if (!ret)
- return;
-
- pr_warn("wrmsrl_safe (MSR_IA32_FEATURE_CONTROL, %08llx) failed error %d\n",
- bits, ret);
-}
-#endif
-
static void wait_for_master_cpu(int cpu)
{
#ifdef CONFIG_SMP
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 4b81876..c513535 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -143,6 +143,11 @@
SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
USER
),
+ MCESEV(
+ PANIC, "Data load in unrecoverable area of kernel",
+ SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
+ KERNEL
+ ),
#endif
MCESEV(
PANIC, "Action required: unknown MCACOD",
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 28d27de..58f887f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -760,23 +760,25 @@
static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
struct pt_regs *regs)
{
- int i, ret = 0;
char *tmp;
+ int i;
for (i = 0; i < mca_cfg.banks; i++) {
m->status = mce_rdmsrl(msr_ops.status(i));
- if (m->status & MCI_STATUS_VAL) {
- __set_bit(i, validp);
- if (quirk_no_way_out)
- quirk_no_way_out(i, m, regs);
- }
+ if (!(m->status & MCI_STATUS_VAL))
+ continue;
+
+ __set_bit(i, validp);
+ if (quirk_no_way_out)
+ quirk_no_way_out(i, m, regs);
if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
+ mce_read_aux(m, i);
*msg = tmp;
- ret = 1;
+ return 1;
}
}
- return ret;
+ return 0;
}
/*
@@ -1205,13 +1207,18 @@
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
+ * Local machine check may already know that we have to panic.
+ * Broadcast machine check begins rendezvous in mce_start()
* Go through all banks in exclusion of the other CPUs. This way we
* don't report duplicated events on shared banks because the first one
- * to see it will clear it. If this is a Local MCE, then no need to
- * perform rendezvous.
+ * to see it will clear it.
*/
- if (!lmce)
+ if (lmce) {
+ if (no_way_out)
+ mce_panic("Fatal local machine check", &m, msg);
+ } else {
order = mce_start(&no_way_out);
+ }
for (i = 0; i < cfg->banks; i++) {
__clear_bit(i, toclear);
@@ -1287,12 +1294,17 @@
no_way_out = worst >= MCE_PANIC_SEVERITY;
} else {
/*
- * Local MCE skipped calling mce_reign()
- * If we found a fatal error, we need to panic here.
+ * If there was a fatal machine check we should have
+ * already called mce_panic earlier in this function.
+ * Since we re-read the banks, we might have found
+ * something new. Check again to see if we found a
+ * fatal error. We call "mce_severity()" again to
+ * make sure we have the right "msg".
*/
- if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
- mce_panic("Machine check from unknown source",
- NULL, NULL);
+ if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
+ mce_severity(&m, cfg->tolerant, &msg, true);
+ mce_panic("Local fatal machine check!", &m, msg);
+ }
}
/*
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 1e82f78..dfc38f0 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -531,6 +531,9 @@
INTEL_CNL_IDS(&gen9_early_ops),
};
+struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_stolen_res);
+
static void __init
intel_graphics_stolen(int num, int slot, int func,
const struct intel_early_ops *early_ops)
@@ -545,8 +548,12 @@
return;
end = base + size - 1;
- printk(KERN_INFO "Reserving Intel graphics memory at %pa-%pa\n",
- &base, &end);
+
+ intel_graphics_stolen_res.start = base;
+ intel_graphics_stolen_res.end = end;
+
+ printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
+ &intel_graphics_stolen_res);
/* Mark this space as reserved */
e820__range_add(base, size, E820_TYPE_RESERVED);
diff --git a/arch/x86/kernel/irqflags.S b/arch/x86/kernel/irqflags.S
new file mode 100644
index 0000000..ddeeaac
--- /dev/null
+++ b/arch/x86/kernel/irqflags.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <asm/asm.h>
+#include <asm/export.h>
+#include <linux/linkage.h>
+
+/*
+ * unsigned long native_save_fl(void)
+ */
+ENTRY(native_save_fl)
+ pushf
+ pop %_ASM_AX
+ ret
+ENDPROC(native_save_fl)
+EXPORT_SYMBOL(native_save_fl)
+
+/*
+ * void native_restore_fl(unsigned long flags)
+ * %eax/%rdi: flags
+ */
+ENTRY(native_restore_fl)
+ push %_ASM_ARG1
+ popf
+ ret
+ENDPROC(native_restore_fl)
+EXPORT_SYMBOL(native_restore_fl)
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 697a4ce..736348e 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -645,12 +645,19 @@
/* Skylake */
static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev)
{
- u32 capid0;
+ u32 capid0, capid5;
pci_read_config_dword(pdev, 0x84, &capid0);
+ pci_read_config_dword(pdev, 0x98, &capid5);
- if ((capid0 & 0xc0) == 0xc0)
+ /*
+ * CAPID0{7:6} indicate whether this is an advanced RAS SKU
+ * CAPID5{8:5} indicate that various NVDIMM usage modes are
+ * enabled, so memory machine check recovery is also enabled.
+ */
+ if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
static_branch_inc(&mcsafe_key);
+
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index ef4efb9..ed8d78f 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -828,16 +828,18 @@
char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
"simd exception";
- if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
- return;
cond_local_irq_enable(regs);
if (!user_mode(regs)) {
- if (!fixup_exception(regs, trapnr)) {
- task->thread.error_code = error_code;
- task->thread.trap_nr = trapnr;
+ if (fixup_exception(regs, trapnr))
+ return;
+
+ task->thread.error_code = error_code;
+ task->thread.trap_nr = trapnr;
+
+ if (notify_die(DIE_TRAP, str, regs, error_code,
+ trapnr, SIGFPE) != NOTIFY_STOP)
die(str, regs, error_code);
- }
return;
}
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index e1ea13a..b9a8f34b 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -290,7 +290,7 @@
insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64);
/* has the side-effect of processing the entire instruction */
insn_get_length(insn);
- if (WARN_ON_ONCE(!insn_complete(insn)))
+ if (!insn_complete(insn))
return -ENOEXEC;
if (is_prefix_bad(insn))
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 82f5252..071cbbb 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -706,7 +706,9 @@
*/
int devmem_is_allowed(unsigned long pagenr)
{
- if (page_is_ram(pagenr)) {
+ if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
+ IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
+ != REGION_DISJOINT) {
/*
* For disallowed memory regions in the low 1MB range,
* request that the page be shown as all zeros.
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index f7af598..ae369c2 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -166,14 +166,14 @@
pgd = pgd_offset_k(pgd_idx * PGDIR_SIZE);
set_pgd(pgd_offset_k(pgd_idx * PGDIR_SIZE), save_pgd[pgd_idx]);
- if (!(pgd_val(*pgd) & _PAGE_PRESENT))
+ if (!pgd_present(*pgd))
continue;
for (i = 0; i < PTRS_PER_P4D; i++) {
p4d = p4d_offset(pgd,
pgd_idx * PGDIR_SIZE + i * P4D_SIZE);
- if (!(p4d_val(*p4d) & _PAGE_PRESENT))
+ if (!p4d_present(*p4d))
continue;
pud = (pud_t *)p4d_page_vaddr(*p4d);
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 5fbf0bf..04d5157 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -19,7 +19,6 @@
#include <asm/mtrr.h>
#include <asm/page.h>
#include <asm/mce.h>
-#include <asm/setup.h>
#include <asm/suspend.h>
#include <asm/fpu/internal.h>
#include <asm/debugreg.h>
@@ -264,7 +263,6 @@
mtrr_bp_restore();
perf_restore_debug_store();
msr_restore_context(ctxt);
- cpu_control_vmx(0);
}
/* Needed by apm.c */
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index fcd87894..fd173e64 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -1230,12 +1230,20 @@
xen_setup_features();
- xen_setup_machphys_mapping();
-
/* Install Xen paravirt ops */
pv_info = xen_info;
pv_init_ops.patch = paravirt_patch_default;
pv_cpu_ops = xen_cpu_ops;
+ xen_init_irq_ops();
+
+ /*
+ * Setup xen_vcpu early because it is needed for
+ * local_irq_disable(), irqs_disabled(), e.g. in printk().
+ *
+ * Don't do the full vcpu_info placement stuff until we have
+ * the cpu_possible_mask and a non-dummy shared_info.
+ */
+ xen_vcpu_info_reset(0);
x86_platform.get_nmi_reason = xen_get_nmi_reason;
@@ -1247,6 +1255,7 @@
* Set up some pagetable state before starting to set any ptes.
*/
+ xen_setup_machphys_mapping();
xen_init_mmu_ops();
/* Prevent unwanted bits from being set in PTEs. */
@@ -1271,20 +1280,9 @@
get_cpu_cap(&boot_cpu_data);
x86_configure_nx();
- xen_init_irq_ops();
-
/* Let's presume PV guests always boot on vCPU with id 0. */
per_cpu(xen_vcpu_id, 0) = 0;
- /*
- * Setup xen_vcpu early because idt_setup_early_handler needs it for
- * local_irq_disable(), irqs_disabled().
- *
- * Don't do the full vcpu_info placement stuff until we have
- * the cpu_possible_mask and a non-dummy shared_info.
- */
- xen_vcpu_info_reset(0);
-
idt_setup_early_handler();
xen_init_capabilities();
diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
index 7417985..7515a19 100644
--- a/arch/x86/xen/irq.c
+++ b/arch/x86/xen/irq.c
@@ -128,8 +128,6 @@
void __init xen_init_irq_ops(void)
{
- /* For PVH we use default pv_irq_ops settings. */
- if (!xen_feature(XENFEAT_hvm_callback_vector))
- pv_irq_ops = xen_irq_ops;
+ pv_irq_ops = xen_irq_ops;
x86_init.irqs.intr_init = xen_init_IRQ;
}
diff --git a/arch/x86/xen/smp_pv.c b/arch/x86/xen/smp_pv.c
index c0c756c..db6d90e 100644
--- a/arch/x86/xen/smp_pv.c
+++ b/arch/x86/xen/smp_pv.c
@@ -32,6 +32,7 @@
#include <xen/interface/vcpu.h>
#include <xen/interface/xenpmu.h>
+#include <asm/spec-ctrl.h>
#include <asm/xen/interface.h>
#include <asm/xen/hypercall.h>
@@ -70,6 +71,8 @@
cpu_data(cpu).x86_max_cores = 1;
set_cpu_sibling_map(cpu);
+ speculative_store_bypass_ht_init();
+
xen_setup_cpu_clockevents();
notify_cpu_starting(cpu);
@@ -250,6 +253,8 @@
}
set_cpu_sibling_map(0);
+ speculative_store_bypass_ht_init();
+
xen_pmu_init(0);
if (xen_smp_intr_init(0) || xen_smp_intr_init_pv(0))
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index bae697a..2986bc8 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -336,7 +336,7 @@
info.si_errno = 0;
info.si_code = BUS_ADRALN;
info.si_addr = (void *) regs->excvaddr;
- force_sig_info(SIGSEGV, &info, current);
+ force_sig_info(SIGBUS, &info, current);
}
#endif
diff --git a/block/blk-core.c b/block/blk-core.c
index 1feeb1a..6f6e218 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -3150,6 +3150,10 @@
dst->cpu = src->cpu;
dst->__sector = blk_rq_pos(src);
dst->__data_len = blk_rq_bytes(src);
+ if (src->rq_flags & RQF_SPECIAL_PAYLOAD) {
+ dst->rq_flags |= RQF_SPECIAL_PAYLOAD;
+ dst->special_vec = src->special_vec;
+ }
dst->nr_phys_segments = src->nr_phys_segments;
dst->ioprio = src->ioprio;
dst->extra_len = src->extra_len;
diff --git a/block/blk-lib.c b/block/blk-lib.c
index 63fb971..2bc544c 100644
--- a/block/blk-lib.c
+++ b/block/blk-lib.c
@@ -275,51 +275,18 @@
return min(pages, (sector_t)BIO_MAX_PAGES);
}
-/**
- * __blkdev_issue_zeroout - generate number of zero filed write bios
- * @bdev: blockdev to issue
- * @sector: start sector
- * @nr_sects: number of sectors to write
- * @gfp_mask: memory allocation flags (for bio_alloc)
- * @biop: pointer to anchor bio
- * @flags: controls detailed behavior
- *
- * Description:
- * Zero-fill a block range, either using hardware offload or by explicitly
- * writing zeroes to the device.
- *
- * Note that this function may fail with -EOPNOTSUPP if the driver signals
- * zeroing offload support, but the device fails to process the command (for
- * some devices there is no non-destructive way to verify whether this
- * operation is actually supported). In this case the caller should call
- * retry the call to blkdev_issue_zeroout() and the fallback path will be used.
- *
- * If a device is using logical block provisioning, the underlying space will
- * not be released if %flags contains BLKDEV_ZERO_NOUNMAP.
- *
- * If %flags contains BLKDEV_ZERO_NOFALLBACK, the function will return
- * -EOPNOTSUPP if no explicit hardware offload for zeroing is provided.
- */
-int __blkdev_issue_zeroout(struct block_device *bdev, sector_t sector,
- sector_t nr_sects, gfp_t gfp_mask, struct bio **biop,
- unsigned flags)
+static int __blkdev_issue_zero_pages(struct block_device *bdev,
+ sector_t sector, sector_t nr_sects, gfp_t gfp_mask,
+ struct bio **biop)
{
- int ret;
- int bi_size = 0;
+ struct request_queue *q = bdev_get_queue(bdev);
struct bio *bio = *biop;
+ int bi_size = 0;
unsigned int sz;
- sector_t bs_mask;
- bs_mask = (bdev_logical_block_size(bdev) >> 9) - 1;
- if ((sector | nr_sects) & bs_mask)
- return -EINVAL;
+ if (!q)
+ return -ENXIO;
- ret = __blkdev_issue_write_zeroes(bdev, sector, nr_sects, gfp_mask,
- biop, flags);
- if (ret != -EOPNOTSUPP || (flags & BLKDEV_ZERO_NOFALLBACK))
- goto out;
-
- ret = 0;
while (nr_sects != 0) {
bio = next_bio(bio, __blkdev_sectors_to_bio_pages(nr_sects),
gfp_mask);
@@ -339,8 +306,46 @@
}
*biop = bio;
-out:
- return ret;
+ return 0;
+}
+
+/**
+ * __blkdev_issue_zeroout - generate number of zero filed write bios
+ * @bdev: blockdev to issue
+ * @sector: start sector
+ * @nr_sects: number of sectors to write
+ * @gfp_mask: memory allocation flags (for bio_alloc)
+ * @biop: pointer to anchor bio
+ * @flags: controls detailed behavior
+ *
+ * Description:
+ * Zero-fill a block range, either using hardware offload or by explicitly
+ * writing zeroes to the device.
+ *
+ * If a device is using logical block provisioning, the underlying space will
+ * not be released if %flags contains BLKDEV_ZERO_NOUNMAP.
+ *
+ * If %flags contains BLKDEV_ZERO_NOFALLBACK, the function will return
+ * -EOPNOTSUPP if no explicit hardware offload for zeroing is provided.
+ */
+int __blkdev_issue_zeroout(struct block_device *bdev, sector_t sector,
+ sector_t nr_sects, gfp_t gfp_mask, struct bio **biop,
+ unsigned flags)
+{
+ int ret;
+ sector_t bs_mask;
+
+ bs_mask = (bdev_logical_block_size(bdev) >> 9) - 1;
+ if ((sector | nr_sects) & bs_mask)
+ return -EINVAL;
+
+ ret = __blkdev_issue_write_zeroes(bdev, sector, nr_sects, gfp_mask,
+ biop, flags);
+ if (ret != -EOPNOTSUPP || (flags & BLKDEV_ZERO_NOFALLBACK))
+ return ret;
+
+ return __blkdev_issue_zero_pages(bdev, sector, nr_sects, gfp_mask,
+ biop);
}
EXPORT_SYMBOL(__blkdev_issue_zeroout);
@@ -360,18 +365,49 @@
int blkdev_issue_zeroout(struct block_device *bdev, sector_t sector,
sector_t nr_sects, gfp_t gfp_mask, unsigned flags)
{
- int ret;
- struct bio *bio = NULL;
+ int ret = 0;
+ sector_t bs_mask;
+ struct bio *bio;
struct blk_plug plug;
+ bool try_write_zeroes = !!bdev_write_zeroes_sectors(bdev);
+ bs_mask = (bdev_logical_block_size(bdev) >> 9) - 1;
+ if ((sector | nr_sects) & bs_mask)
+ return -EINVAL;
+
+retry:
+ bio = NULL;
blk_start_plug(&plug);
- ret = __blkdev_issue_zeroout(bdev, sector, nr_sects, gfp_mask,
- &bio, flags);
+ if (try_write_zeroes) {
+ ret = __blkdev_issue_write_zeroes(bdev, sector, nr_sects,
+ gfp_mask, &bio, flags);
+ } else if (!(flags & BLKDEV_ZERO_NOFALLBACK)) {
+ ret = __blkdev_issue_zero_pages(bdev, sector, nr_sects,
+ gfp_mask, &bio);
+ } else {
+ /* No zeroing offload support */
+ ret = -EOPNOTSUPP;
+ }
if (ret == 0 && bio) {
ret = submit_bio_wait(bio);
bio_put(bio);
}
blk_finish_plug(&plug);
+ if (ret && try_write_zeroes) {
+ if (!(flags & BLKDEV_ZERO_NOFALLBACK)) {
+ try_write_zeroes = false;
+ goto retry;
+ }
+ if (!bdev_write_zeroes_sectors(bdev)) {
+ /*
+ * Zeroing offload support was indicated, but the
+ * device reported ILLEGAL REQUEST (for some devices
+ * there is no non-destructive way to verify whether
+ * WRITE ZEROES is actually supported).
+ */
+ ret = -EOPNOTSUPP;
+ }
+ }
return ret;
}
diff --git a/chromeos/config/arm64/chromiumos-arm64.flavour.config b/chromeos/config/arm64/chromiumos-arm64.flavour.config
index 4e59468..15a18f34 100644
--- a/chromeos/config/arm64/chromiumos-arm64.flavour.config
+++ b/chromeos/config/arm64/chromiumos-arm64.flavour.config
@@ -503,6 +503,7 @@
CONFIG_QCOM_APCS_IPC=y
# CONFIG_QCOM_APR is not set
# CONFIG_QCOM_BAM_DMA is not set
+CONFIG_QCOM_CLK_RPMH=y
# CONFIG_QCOM_CLK_SMD_RPM is not set
# CONFIG_QCOM_COINCELL is not set
CONFIG_QCOM_COMMAND_DB=y
diff --git a/chromeos/config/arm64/chromiumos-qualcomm.flavour.config b/chromeos/config/arm64/chromiumos-qualcomm.flavour.config
index f481f56..6022d524 100644
--- a/chromeos/config/arm64/chromiumos-qualcomm.flavour.config
+++ b/chromeos/config/arm64/chromiumos-qualcomm.flavour.config
@@ -112,6 +112,7 @@
CONFIG_QCOM_APCS_IPC=y
# CONFIG_QCOM_APR is not set
# CONFIG_QCOM_BAM_DMA is not set
+CONFIG_QCOM_CLK_RPMH=y
# CONFIG_QCOM_CLK_SMD_RPM is not set
# CONFIG_QCOM_COINCELL is not set
CONFIG_QCOM_COMMAND_DB=y
diff --git a/chromeos/config/arm64/common.config b/chromeos/config/arm64/common.config
index 10185ce..407c730 100644
--- a/chromeos/config/arm64/common.config
+++ b/chromeos/config/arm64/common.config
@@ -830,6 +830,7 @@
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
# CONFIG_SPI_FSL_SPI is not set
+CONFIG_SPI_MEM=y
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX_PCI is not set
# CONFIG_SSB is not set
diff --git a/chromeos/config/armel/common.config b/chromeos/config/armel/common.config
index ee5ae82..3cb715d 100644
--- a/chromeos/config/armel/common.config
+++ b/chromeos/config/armel/common.config
@@ -949,6 +949,7 @@
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_MEM=y
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX_PCI is not set
CONFIG_SPI_ROCKCHIP=y
diff --git a/chromeos/config/base.config b/chromeos/config/base.config
index d6bbe92..a336f99 100644
--- a/chromeos/config/base.config
+++ b/chromeos/config/base.config
@@ -593,10 +593,12 @@
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_MM_SELFTEST is not set
# CONFIG_DRM_DP_AUX_CHARDEV is not set
+CONFIG_DRM_EVDI=m
# CONFIG_DRM_FBDEV_EMULATION is not set
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_SIL164 is not set
+CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIB_RANDOM is not set
@@ -671,12 +673,13 @@
# CONFIG_FB_AUO_K190X is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
# CONFIG_FB_BROADSHEET is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_CMDLINE=y
# CONFIG_FB_DDC is not set
+CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_MACMODES is not set
@@ -689,10 +692,10 @@
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_TFT is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_UDL is not set
@@ -1116,7 +1119,8 @@
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
CONFIG_IPV6_SIT=m
@@ -1974,6 +1978,7 @@
CONFIG_PRINTK_NMI=y
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_PRINTK_TIME=y
+CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_PRISM2_USB is not set
CONFIG_PROBE_EVENTS=y
# CONFIG_PROC_CHILDREN is not set
@@ -1998,11 +2003,16 @@
CONFIG_PSTORE_ZLIB_COMPRESS=y
CONFIG_PTP_1588_CLOCK=m
# CONFIG_QCOM_EMAC is not set
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_QSEMI_PHY is not set
-# CONFIG_QUOTA is not set
-# CONFIG_QUOTACTL is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+# CONFIG_QUOTA_DEBUG is not set
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_QUOTA_TREE=y
# CONFIG_R3964 is not set
# CONFIG_R8188EU is not set
# CONFIG_R8712U is not set
diff --git a/chromeos/config/i386/common.config b/chromeos/config/i386/common.config
index ff73219..f9d899c 100644
--- a/chromeos/config/i386/common.config
+++ b/chromeos/config/i386/common.config
@@ -1211,6 +1211,7 @@
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPI_BITBANG=m
# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_MEM is not set
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_PXA2XX_PCI is not set
# CONFIG_SPI_ROCKCHIP is not set
diff --git a/chromeos/config/x86_64/common.config b/chromeos/config/x86_64/common.config
index 3b3c3b3..c5f1c0f 100644
--- a/chromeos/config/x86_64/common.config
+++ b/chromeos/config/x86_64/common.config
@@ -1085,6 +1085,7 @@
# CONFIG_QTNFMAC_PEARL_PCIE is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTACTL_COMPAT=y
# CONFIG_R6040 is not set
CONFIG_R8169=m
# CONFIG_R8822BE is not set
@@ -1451,6 +1452,7 @@
CONFIG_SPI_BITBANG=m
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_MEM is not set
CONFIG_SPI_PXA2XX=y
CONFIG_SPI_PXA2XX_PCI=y
# CONFIG_SPI_ROCKCHIP is not set
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 42212b6..5579eb8 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -1324,32 +1324,6 @@
The Salsa20 stream cipher algorithm is designed by Daniel J.
Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
-config CRYPTO_SALSA20_586
- tristate "Salsa20 stream cipher algorithm (i586)"
- depends on (X86 || UML_X86) && !64BIT
- select CRYPTO_BLKCIPHER
- help
- Salsa20 stream cipher algorithm.
-
- Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT
- Stream Cipher Project. See <http://www.ecrypt.eu.org/stream/>
-
- The Salsa20 stream cipher algorithm is designed by Daniel J.
- Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
-
-config CRYPTO_SALSA20_X86_64
- tristate "Salsa20 stream cipher algorithm (x86_64)"
- depends on (X86 || UML_X86) && 64BIT
- select CRYPTO_BLKCIPHER
- help
- Salsa20 stream cipher algorithm.
-
- Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT
- Stream Cipher Project. See <http://www.ecrypt.eu.org/stream/>
-
- The Salsa20 stream cipher algorithm is designed by Daniel J.
- Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
-
config CRYPTO_CHACHA20
tristate "ChaCha20 cipher algorithm"
select CRYPTO_BLKCIPHER
diff --git a/crypto/asymmetric_keys/x509_cert_parser.c b/crypto/asymmetric_keys/x509_cert_parser.c
index ce2df8c..7e6a43f 100644
--- a/crypto/asymmetric_keys/x509_cert_parser.c
+++ b/crypto/asymmetric_keys/x509_cert_parser.c
@@ -249,6 +249,15 @@
return -EINVAL;
}
+ if (strcmp(ctx->cert->sig->pkey_algo, "rsa") == 0) {
+ /* Discard the BIT STRING metadata */
+ if (vlen < 1 || *(const u8 *)value != 0)
+ return -EBADMSG;
+
+ value++;
+ vlen--;
+ }
+
ctx->cert->raw_sig = value;
ctx->cert->raw_sig_size = vlen;
return 0;
diff --git a/drivers/Kconfig b/drivers/Kconfig
index a83770a..911153b 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -213,4 +213,6 @@
source "drivers/pkglist/Kconfig"
+source "drivers/gpu/drm/evdi/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 2e4f894..ee623a9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -186,3 +186,5 @@
obj-$(CONFIG_MULTIPLEXER) += mux/
obj-$(CONFIG_PKGLIST) += pkglist/
+obj-$(CONFIG_DRM_EVDI) += gpu/drm/evdi/
+
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index a2be3fd..602ae58 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -229,11 +229,13 @@
static const struct lpss_device_desc byt_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX,
+ .prv_offset = 0x800,
.setup = byt_pwm_setup,
};
static const struct lpss_device_desc bsw_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
+ .prv_offset = 0x800,
.setup = bsw_pwm_setup,
};
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index db78d35..191e86c 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -45,6 +45,8 @@
#include <linux/uaccess.h>
#include <linux/io-64-nonatomic-lo-hi.h>
+#include "acpica/accommon.h"
+#include "acpica/acnamesp.h"
#include "internal.h"
#define _COMPONENT ACPI_OS_SERVICES
@@ -1477,6 +1479,76 @@
}
EXPORT_SYMBOL(acpi_check_region);
+static acpi_status acpi_deactivate_mem_region(acpi_handle handle, u32 level,
+ void *_res, void **return_value)
+{
+ struct acpi_mem_space_context **mem_ctx;
+ union acpi_operand_object *handler_obj;
+ union acpi_operand_object *region_obj2;
+ union acpi_operand_object *region_obj;
+ struct resource *res = _res;
+ acpi_status status;
+
+ region_obj = acpi_ns_get_attached_object(handle);
+ if (!region_obj)
+ return AE_OK;
+
+ handler_obj = region_obj->region.handler;
+ if (!handler_obj)
+ return AE_OK;
+
+ if (region_obj->region.space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY)
+ return AE_OK;
+
+ if (!(region_obj->region.flags & AOPOBJ_SETUP_COMPLETE))
+ return AE_OK;
+
+ region_obj2 = acpi_ns_get_secondary_object(region_obj);
+ if (!region_obj2)
+ return AE_OK;
+
+ mem_ctx = (void *)®ion_obj2->extra.region_context;
+
+ if (!(mem_ctx[0]->address >= res->start &&
+ mem_ctx[0]->address < res->end))
+ return AE_OK;
+
+ status = handler_obj->address_space.setup(region_obj,
+ ACPI_REGION_DEACTIVATE,
+ NULL, (void **)mem_ctx);
+ if (ACPI_SUCCESS(status))
+ region_obj->region.flags &= ~(AOPOBJ_SETUP_COMPLETE);
+
+ return status;
+}
+
+/**
+ * acpi_release_memory - Release any mappings done to a memory region
+ * @handle: Handle to namespace node
+ * @res: Memory resource
+ * @level: A level that terminates the search
+ *
+ * Walks through @handle and unmaps all SystemMemory Operation Regions that
+ * overlap with @res and that have already been activated (mapped).
+ *
+ * This is a helper that allows drivers to place special requirements on memory
+ * region that may overlap with operation regions, primarily allowing them to
+ * safely map the region as non-cached memory.
+ *
+ * The unmapped Operation Regions will be automatically remapped next time they
+ * are called, so the drivers do not need to do anything else.
+ */
+acpi_status acpi_release_memory(acpi_handle handle, struct resource *res,
+ u32 level)
+{
+ if (!(res->flags & IORESOURCE_MEM))
+ return AE_TYPE;
+
+ return acpi_walk_namespace(ACPI_TYPE_REGION, handle, level,
+ acpi_deactivate_mem_region, NULL, res, NULL);
+}
+EXPORT_SYMBOL_GPL(acpi_release_memory);
+
/*
* Let drivers know whether the resource checks are effective
*/
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index d50a7b6..4b2d186 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -791,8 +791,8 @@
return index;
}
-static void acpi_idle_enter_s2idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static int acpi_idle_enter_s2idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
@@ -800,16 +800,18 @@
struct acpi_processor *pr = __this_cpu_read(processors);
if (unlikely(!pr))
- return;
+ return 0;
if (pr->flags.bm_check) {
acpi_idle_enter_bm(pr, cx, false);
- return;
+ return 0;
} else {
ACPI_FLUSH_CPU_CACHE();
}
}
acpi_idle_do_entry(cx);
+
+ return 0;
}
static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c
index 551b71a2..a051ed6 100644
--- a/drivers/acpi/thermal.c
+++ b/drivers/acpi/thermal.c
@@ -223,6 +223,17 @@
if (!tz)
return -EINVAL;
+ if (tz->tz_enabled == THERMAL_DEVICE_DISABLED) {
+ tz->polling_frequency = 0;
+ return 0;
+ }
+
+ /* Get default polling frequency [_TZP] (optional) */
+ if (tzp) {
+ tz->polling_frequency = tzp;
+ return 0;
+ }
+
status = acpi_evaluate_integer(tz->device->handle, "_TZP", NULL, &tmp);
if (ACPI_FAILURE(status))
return -ENODEV;
@@ -582,6 +593,14 @@
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"%s kernel ACPI thermal control\n",
tz->tz_enabled ? "Enable" : "Disable"));
+
+ acpi_thermal_get_polling_frequency(tz);
+
+ mutex_lock(&tz->thermal_zone->lock);
+ tz->thermal_zone->polling_delay = tz->polling_frequency*100;
+ tz->thermal_zone->passive_delay = tz->polling_frequency*100;
+ mutex_unlock(&tz->thermal_zone->lock);
+
acpi_thermal_check(tz);
}
return 0;
@@ -930,8 +949,6 @@
if (ACPI_FAILURE(status))
return -ENODEV;
- tz->tz_enabled = 1;
-
dev_info(&tz->device->dev, "registered as thermal_zone%d\n",
tz->thermal_zone->id);
return 0;
@@ -1039,11 +1056,7 @@
if (!result)
tz->flags.cooling_mode = 1;
- /* Get default polling frequency [_TZP] (optional) */
- if (tzp)
- tz->polling_frequency = tzp;
- else
- acpi_thermal_get_polling_frequency(tz);
+ acpi_thermal_get_polling_frequency(tz);
return 0;
}
@@ -1088,6 +1101,7 @@
return -ENOMEM;
tz->device = device;
+ tz->tz_enabled = 1;
strcpy(tz->name, device->pnp.bus_id);
strcpy(acpi_device_name(device), ACPI_THERMAL_DEVICE_NAME);
strcpy(acpi_device_class(device), ACPI_THERMAL_CLASS);
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 75eb500..f003e30 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1267,6 +1267,59 @@
return strcmp(buf, dmi->driver_data) < 0;
}
+static bool ahci_broken_lpm(struct pci_dev *pdev)
+{
+ static const struct dmi_system_id sysids[] = {
+ /* Various Lenovo 50 series have LPM issues with older BIOSen */
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
+ },
+ .driver_data = "20180406", /* 1.31 */
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
+ },
+ .driver_data = "20180420", /* 1.28 */
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
+ },
+ .driver_data = "20180315", /* 1.33 */
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
+ },
+ /*
+ * Note date based on release notes, 2.35 has been
+ * reported to be good, but I've been unable to get
+ * a hold of the reporter to get the DMI BIOS date.
+ * TODO: fix this.
+ */
+ .driver_data = "20180310", /* 2.35 */
+ },
+ { } /* terminate list */
+ };
+ const struct dmi_system_id *dmi = dmi_first_match(sysids);
+ int year, month, date;
+ char buf[9];
+
+ if (!dmi)
+ return false;
+
+ dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
+ snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
+
+ return strcmp(buf, dmi->driver_data) < 0;
+}
+
static bool ahci_broken_online(struct pci_dev *pdev)
{
#define ENCODE_BUSDEVFN(bus, slot, func) \
@@ -1677,6 +1730,12 @@
"quirky BIOS, skipping spindown on poweroff\n");
}
+ if (ahci_broken_lpm(pdev)) {
+ pi.flags |= ATA_FLAG_NO_LPM;
+ dev_warn(&pdev->dev,
+ "BIOS update required for Link Power Management support\n");
+ }
+
if (ahci_broken_suspend(pdev)) {
hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
dev_warn(&pdev->dev,
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index cad2530..6938bd8 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -2501,6 +2501,9 @@
(id[ATA_ID_SATA_CAPABILITY] & 0xe) == 0x2)
dev->horkage |= ATA_HORKAGE_NOLPM;
+ if (ap->flags & ATA_FLAG_NO_LPM)
+ dev->horkage |= ATA_HORKAGE_NOLPM;
+
if (dev->horkage & ATA_HORKAGE_NOLPM) {
ata_dev_warn(dev, "LPM support broken, forcing max_power\n");
dev->link->ap->target_lpm_policy = ATA_LPM_MAX_POWER;
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 6b0440a..bf5777bc0 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -3801,10 +3801,20 @@
*/
goto invalid_param_len;
}
- if (block > dev->n_sectors)
- goto out_of_range;
all = cdb[14] & 0x1;
+ if (all) {
+ /*
+ * Ignore the block address (zone ID) as defined by ZBC.
+ */
+ block = 0;
+ } else if (block >= dev->n_sectors) {
+ /*
+ * Block must be a valid zone ID (a zone start LBA).
+ */
+ fp = 2;
+ goto invalid_fld;
+ }
if (ata_ncq_enabled(qc->dev) &&
ata_fpdma_zac_mgmt_out_supported(qc->dev)) {
@@ -3833,10 +3843,6 @@
invalid_fld:
ata_scsi_set_invalid_field(qc->dev, scmd, fp, 0xff);
return 1;
- out_of_range:
- /* "Logical Block Address out of range" */
- ata_scsi_set_sense(qc->dev, scmd, ILLEGAL_REQUEST, 0x21, 0x00);
- return 1;
invalid_param_len:
/* "Parameter list length error" */
ata_scsi_set_sense(qc->dev, scmd, ILLEGAL_REQUEST, 0x1a, 0x0);
diff --git a/drivers/atm/zatm.c b/drivers/atm/zatm.c
index 9c9a229..a8d2eb0 100644
--- a/drivers/atm/zatm.c
+++ b/drivers/atm/zatm.c
@@ -1151,8 +1151,8 @@
}
-static unsigned char eprom_try_esi(struct atm_dev *dev, unsigned short cmd,
- int offset, int swap)
+static int eprom_try_esi(struct atm_dev *dev, unsigned short cmd, int offset,
+ int swap)
{
unsigned char buf[ZEPROM_SIZE];
struct zatm_dev *zatm_dev;
diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig
index 2c2ed9c..f9413755 100644
--- a/drivers/auxdisplay/Kconfig
+++ b/drivers/auxdisplay/Kconfig
@@ -14,9 +14,6 @@
If you say N, all options in this submenu will be skipped and disabled.
-config CHARLCD
- tristate "Character LCD core support" if COMPILE_TEST
-
if AUXDISPLAY
config HD44780
@@ -157,8 +154,6 @@
Say yes here to add support for Holtek HT16K33, RAM mapping 16*8
LED controller driver with keyscan.
-endif # AUXDISPLAY
-
config ARM_CHARLCD
bool "ARM Ltd. Character LCD Driver"
depends on PLAT_VERSATILE
@@ -169,6 +164,8 @@
line and the Linux version on the second line, but that's
still useful.
+endif # AUXDISPLAY
+
config PANEL
tristate "Parallel port LCD/Keypad Panel support"
depends on PARPORT
@@ -448,3 +445,6 @@
printf()-formatted message is valid with newline and escape codes.
endif # PANEL
+
+config CHARLCD
+ tristate "Character LCD core support" if COMPILE_TEST
diff --git a/drivers/base/core.c b/drivers/base/core.c
index a359934..b054cb2f 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -217,6 +217,13 @@
link->rpm_active = true;
}
pm_runtime_new_link(consumer);
+ /*
+ * If the link is being added by the consumer driver at probe
+ * time, balance the decrementation of the supplier's runtime PM
+ * usage counter after consumer probe in driver_probe_device().
+ */
+ if (consumer->links.status == DL_DEV_PROBING)
+ pm_runtime_get_noresume(supplier);
}
get_device(supplier);
link->supplier = supplier;
@@ -235,12 +242,12 @@
switch (consumer->links.status) {
case DL_DEV_PROBING:
/*
- * Balance the decrementation of the supplier's
- * runtime PM usage counter after consumer probe
- * in driver_probe_device().
+ * Some callers expect the link creation during
+ * consumer driver probe to resume the supplier
+ * even without DL_FLAG_RPM_ACTIVE.
*/
if (flags & DL_FLAG_PM_RUNTIME)
- pm_runtime_get_sync(supplier);
+ pm_runtime_resume(supplier);
link->status = DL_STATE_CONSUMER_PROBE;
break;
diff --git a/drivers/block/drbd/drbd_worker.c b/drivers/block/drbd/drbd_worker.c
index 03471b3..c2042f8 100644
--- a/drivers/block/drbd/drbd_worker.c
+++ b/drivers/block/drbd/drbd_worker.c
@@ -282,8 +282,8 @@
what = COMPLETED_OK;
}
- bio_put(req->private_bio);
req->private_bio = ERR_PTR(blk_status_to_errno(bio->bi_status));
+ bio_put(bio);
/* not req_mod(), we need irqsave here! */
spin_lock_irqsave(&device->resource->req_lock, flags);
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index 1a87f87..72300f6 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -617,6 +617,36 @@
__func__, lo->lo_number, lo->lo_file_name, rc);
}
+static inline int is_loop_device(struct file *file)
+{
+ struct inode *i = file->f_mapping->host;
+
+ return i && S_ISBLK(i->i_mode) && MAJOR(i->i_rdev) == LOOP_MAJOR;
+}
+
+static int loop_validate_file(struct file *file, struct block_device *bdev)
+{
+ struct inode *inode = file->f_mapping->host;
+ struct file *f = file;
+
+ /* Avoid recursion */
+ while (is_loop_device(f)) {
+ struct loop_device *l;
+
+ if (f->f_mapping->host->i_bdev == bdev)
+ return -EBADF;
+
+ l = f->f_mapping->host->i_bdev->bd_disk->private_data;
+ if (l->lo_state == Lo_unbound) {
+ return -EINVAL;
+ }
+ f = l->lo_backing_file;
+ }
+ if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode))
+ return -EINVAL;
+ return 0;
+}
+
/*
* loop_change_fd switched the backing store of a loopback device to
* a new file. This is useful for operating system installers to free up
@@ -646,14 +676,15 @@
if (!file)
goto out;
+ error = loop_validate_file(file, bdev);
+ if (error)
+ goto out_putf;
+
inode = file->f_mapping->host;
old_file = lo->lo_backing_file;
error = -EINVAL;
- if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode))
- goto out_putf;
-
/* size of the new backing store needs to be the same */
if (get_loop_size(lo, file) != get_loop_size(lo, old_file))
goto out_putf;
@@ -679,13 +710,6 @@
return error;
}
-static inline int is_loop_device(struct file *file)
-{
- struct inode *i = file->f_mapping->host;
-
- return i && S_ISBLK(i->i_mode) && MAJOR(i->i_rdev) == LOOP_MAJOR;
-}
-
/* loop sysfs attributes */
static ssize_t loop_attr_show(struct device *dev, char *page,
@@ -782,16 +806,17 @@
.attrs= loop_attrs,
};
-static int loop_sysfs_init(struct loop_device *lo)
+static void loop_sysfs_init(struct loop_device *lo)
{
- return sysfs_create_group(&disk_to_dev(lo->lo_disk)->kobj,
- &loop_attribute_group);
+ lo->sysfs_inited = !sysfs_create_group(&disk_to_dev(lo->lo_disk)->kobj,
+ &loop_attribute_group);
}
static void loop_sysfs_exit(struct loop_device *lo)
{
- sysfs_remove_group(&disk_to_dev(lo->lo_disk)->kobj,
- &loop_attribute_group);
+ if (lo->sysfs_inited)
+ sysfs_remove_group(&disk_to_dev(lo->lo_disk)->kobj,
+ &loop_attribute_group);
}
static void loop_config_discard(struct loop_device *lo)
@@ -850,7 +875,7 @@
static int loop_set_fd(struct loop_device *lo, fmode_t mode,
struct block_device *bdev, unsigned int arg)
{
- struct file *file, *f;
+ struct file *file;
struct inode *inode;
struct address_space *mapping;
int lo_flags = 0;
@@ -869,29 +894,13 @@
if (lo->lo_state != Lo_unbound)
goto out_putf;
- /* Avoid recursion */
- f = file;
- while (is_loop_device(f)) {
- struct loop_device *l;
-
- if (f->f_mapping->host->i_bdev == bdev)
- goto out_putf;
-
- l = f->f_mapping->host->i_bdev->bd_disk->private_data;
- if (l->lo_state == Lo_unbound) {
- error = -EINVAL;
- goto out_putf;
- }
- f = l->lo_backing_file;
- }
+ error = loop_validate_file(file, bdev);
+ if (error)
+ goto out_putf;
mapping = file->f_mapping;
inode = mapping->host;
- error = -EINVAL;
- if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode))
- goto out_putf;
-
if (!(file->f_mode & FMODE_WRITE) || !(mode & FMODE_WRITE) ||
!file->f_op->write_iter)
lo_flags |= LO_FLAGS_READ_ONLY;
@@ -1565,6 +1574,7 @@
arg = (unsigned long) compat_ptr(arg);
case LOOP_SET_FD:
case LOOP_CHANGE_FD:
+ case LOOP_SET_BLOCK_SIZE:
err = lo_ioctl(bdev, mode, cmd, arg);
break;
default:
diff --git a/drivers/block/loop.h b/drivers/block/loop.h
index 1f395670..dfc54ce 100644
--- a/drivers/block/loop.h
+++ b/drivers/block/loop.h
@@ -58,6 +58,7 @@
struct kthread_worker worker;
struct task_struct *worker_task;
bool use_dio;
+ bool sysfs_inited;
struct request_queue *lo_queue;
struct blk_mq_tag_set tag_set;
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index fe4fd8a..9057dad 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -3841,7 +3841,6 @@
{
dout("%s rbd_dev %p\n", __func__, rbd_dev);
- cancel_delayed_work_sync(&rbd_dev->watch_dwork);
cancel_work_sync(&rbd_dev->acquired_lock_work);
cancel_work_sync(&rbd_dev->released_lock_work);
cancel_delayed_work_sync(&rbd_dev->lock_dwork);
@@ -3859,6 +3858,7 @@
rbd_dev->watch_state = RBD_WATCH_STATE_UNREGISTERED;
mutex_unlock(&rbd_dev->watch_mutex);
+ cancel_delayed_work_sync(&rbd_dev->watch_dwork);
ceph_osdc_flush_notifies(&rbd_dev->rbd_client->client->osdc);
}
diff --git a/drivers/bluetooth/bluecard_cs.c b/drivers/bluetooth/bluecard_cs.c
index b07ca95..d513ef47 100644
--- a/drivers/bluetooth/bluecard_cs.c
+++ b/drivers/bluetooth/bluecard_cs.c
@@ -156,9 +156,9 @@
/* ======================== LED handling routines ======================== */
-static void bluecard_activity_led_timeout(u_long arg)
+static void bluecard_activity_led_timeout(struct timer_list *t)
{
- struct bluecard_info *info = (struct bluecard_info *)arg;
+ struct bluecard_info *info = from_timer(info, t, timer);
unsigned int iobase = info->p_dev->resource[0]->start;
if (test_bit(CARD_ACTIVITY, &(info->hw_state))) {
@@ -691,8 +691,7 @@
spin_lock_init(&(info->lock));
- setup_timer(&(info->timer), &bluecard_activity_led_timeout,
- (u_long)info);
+ timer_setup(&info->timer, bluecard_activity_led_timeout, 0);
skb_queue_head_init(&(info->txq));
diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c
index d880f4e..1a7f0c8 100644
--- a/drivers/bluetooth/hci_bcsp.c
+++ b/drivers/bluetooth/hci_bcsp.c
@@ -65,6 +65,7 @@
u8 rxseq_txack; /* rxseq == txack. */
u8 rxack; /* Last packet sent by us that the peer ack'ed */
struct timer_list tbcsp;
+ struct hci_uart *hu;
enum {
BCSP_W4_PKT_DELIMITER,
@@ -697,10 +698,10 @@
}
/* Arrange to retransmit all messages in the relq. */
-static void bcsp_timed_event(unsigned long arg)
+static void bcsp_timed_event(struct timer_list *t)
{
- struct hci_uart *hu = (struct hci_uart *)arg;
- struct bcsp_struct *bcsp = hu->priv;
+ struct bcsp_struct *bcsp = from_timer(bcsp, t, tbcsp);
+ struct hci_uart *hu = bcsp->hu;
struct sk_buff *skb;
unsigned long flags;
@@ -729,11 +730,12 @@
return -ENOMEM;
hu->priv = bcsp;
+ bcsp->hu = hu;
skb_queue_head_init(&bcsp->unack);
skb_queue_head_init(&bcsp->rel);
skb_queue_head_init(&bcsp->unrel);
- setup_timer(&bcsp->tbcsp, bcsp_timed_event, (u_long)hu);
+ timer_setup(&bcsp->tbcsp, bcsp_timed_event, 0);
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
index c0e4e26..6a8d0d0 100644
--- a/drivers/bluetooth/hci_h5.c
+++ b/drivers/bluetooth/hci_h5.c
@@ -78,6 +78,7 @@
int (*rx_func)(struct hci_uart *hu, u8 c);
struct timer_list timer; /* Retransmission timer */
+ struct hci_uart *hu; /* Parent HCI UART */
u8 tx_seq; /* Next seq number to send */
u8 tx_ack; /* Next ack number to send */
@@ -120,12 +121,12 @@
return h5->tx_win & 0x07;
}
-static void h5_timed_event(unsigned long arg)
+static void h5_timed_event(struct timer_list *t)
{
const unsigned char sync_req[] = { 0x01, 0x7e };
unsigned char conf_req[3] = { 0x03, 0xfc };
- struct hci_uart *hu = (struct hci_uart *)arg;
- struct h5 *h5 = hu->priv;
+ struct h5 *h5 = from_timer(h5, t, timer);
+ struct hci_uart *hu = h5->hu;
struct sk_buff *skb;
unsigned long flags;
@@ -197,6 +198,7 @@
return -ENOMEM;
hu->priv = h5;
+ h5->hu = hu;
skb_queue_head_init(&h5->unack);
skb_queue_head_init(&h5->rel);
@@ -204,7 +206,7 @@
h5_reset_rx(h5);
- setup_timer(&h5->timer, h5_timed_event, (unsigned long)hu);
+ timer_setup(&h5->timer, h5_timed_event, 0);
h5->tx_win = H5_TX_WIN_MAX;
diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
index 6aef3bd..c823914 100644
--- a/drivers/bluetooth/hci_ldisc.c
+++ b/drivers/bluetooth/hci_ldisc.c
@@ -115,12 +115,12 @@
struct sk_buff *skb = hu->tx_skb;
if (!skb) {
- read_lock(&hu->proto_lock);
+ percpu_down_read(&hu->proto_lock);
if (test_bit(HCI_UART_PROTO_READY, &hu->flags))
skb = hu->proto->dequeue(hu);
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
} else {
hu->tx_skb = NULL;
}
@@ -130,7 +130,14 @@
int hci_uart_tx_wakeup(struct hci_uart *hu)
{
- read_lock(&hu->proto_lock);
+ /* This may be called in an IRQ context, so we can't sleep. Therefore
+ * we try to acquire the lock only, and if that fails we assume the
+ * tty is being closed because that is the only time the write lock is
+ * acquired. If, however, at some point in the future the write lock
+ * is also acquired in other situations, then this must be revisited.
+ */
+ if (!percpu_down_read_trylock(&hu->proto_lock))
+ return 0;
if (!test_bit(HCI_UART_PROTO_READY, &hu->flags))
goto no_schedule;
@@ -145,7 +152,7 @@
schedule_work(&hu->write_work);
no_schedule:
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
return 0;
}
@@ -247,12 +254,12 @@
tty_ldisc_flush(tty);
tty_driver_flush_buffer(tty);
- read_lock(&hu->proto_lock);
+ percpu_down_read(&hu->proto_lock);
if (test_bit(HCI_UART_PROTO_READY, &hu->flags))
hu->proto->flush(hu);
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
return 0;
}
@@ -275,15 +282,15 @@
BT_DBG("%s: type %d len %d", hdev->name, hci_skb_pkt_type(skb),
skb->len);
- read_lock(&hu->proto_lock);
+ percpu_down_read(&hu->proto_lock);
if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) {
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
return -EUNATCH;
}
hu->proto->enqueue(hu, skb);
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
hci_uart_tx_wakeup(hu);
@@ -486,7 +493,7 @@
INIT_WORK(&hu->init_ready, hci_uart_init_work);
INIT_WORK(&hu->write_work, hci_uart_write_work);
- rwlock_init(&hu->proto_lock);
+ percpu_init_rwsem(&hu->proto_lock);
/* Flush any pending characters in the driver */
tty_driver_flush_buffer(tty);
@@ -503,7 +510,6 @@
{
struct hci_uart *hu = tty->disc_data;
struct hci_dev *hdev;
- unsigned long flags;
BT_DBG("tty %p", tty);
@@ -518,9 +524,9 @@
hci_uart_close(hdev);
if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) {
- write_lock_irqsave(&hu->proto_lock, flags);
+ percpu_down_write(&hu->proto_lock);
clear_bit(HCI_UART_PROTO_READY, &hu->flags);
- write_unlock_irqrestore(&hu->proto_lock, flags);
+ percpu_up_write(&hu->proto_lock);
cancel_work_sync(&hu->write_work);
@@ -582,10 +588,10 @@
if (!hu || tty != hu->tty)
return;
- read_lock(&hu->proto_lock);
+ percpu_down_read(&hu->proto_lock);
if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) {
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
return;
}
@@ -593,7 +599,7 @@
* tty caller
*/
hu->proto->recv(hu, data, count);
- read_unlock(&hu->proto_lock);
+ percpu_up_read(&hu->proto_lock);
if (hu->hdev)
hu->hdev->stat.byte_rx += count;
diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c
index 1bc028c..51790dd 100644
--- a/drivers/bluetooth/hci_qca.c
+++ b/drivers/bluetooth/hci_qca.c
@@ -321,10 +321,10 @@
serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
}
-static void hci_ibs_tx_idle_timeout(unsigned long arg)
+static void hci_ibs_tx_idle_timeout(struct timer_list *t)
{
- struct hci_uart *hu = (struct hci_uart *)arg;
- struct qca_data *qca = hu->priv;
+ struct qca_data *qca = from_timer(qca, t, tx_idle_timer);
+ struct hci_uart *hu = qca->hu;
unsigned long flags;
BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
@@ -356,10 +356,10 @@
spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
}
-static void hci_ibs_wake_retrans_timeout(unsigned long arg)
+static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
{
- struct hci_uart *hu = (struct hci_uart *)arg;
- struct qca_data *qca = hu->priv;
+ struct qca_data *qca = from_timer(qca, t, wake_retrans_timer);
+ struct hci_uart *hu = qca->hu;
unsigned long flags, retrans_delay;
bool retransmit = false;
@@ -453,11 +453,10 @@
hu->priv = qca;
- setup_timer(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout,
- (u_long)hu);
+ timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
- setup_timer(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, (u_long)hu);
+ timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
qca->tx_idle_delay = IBS_TX_IDLE_TIMEOUT_MS;
if (hu->serdev) {
diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c
index 71664b2..e0e6461 100644
--- a/drivers/bluetooth/hci_serdev.c
+++ b/drivers/bluetooth/hci_serdev.c
@@ -303,6 +303,7 @@
hci_set_drvdata(hdev, hu);
INIT_WORK(&hu->write_work, hci_uart_write_work);
+ percpu_init_rwsem(&hu->proto_lock);
/* Only when vendor specific setup callback is provided, consider
* the manufacturer information valid. This avoids filling in the
diff --git a/drivers/bluetooth/hci_uart.h b/drivers/bluetooth/hci_uart.h
index d9cd95d..66e8c68 100644
--- a/drivers/bluetooth/hci_uart.h
+++ b/drivers/bluetooth/hci_uart.h
@@ -87,7 +87,7 @@
struct work_struct write_work;
const struct hci_uart_proto *proto;
- rwlock_t proto_lock; /* Stop work for proto close */
+ struct percpu_rw_semaphore proto_lock; /* Stop work for proto close */
void *priv;
struct sk_buff *tx_skb;
diff --git a/drivers/char/ipmi/ipmi_bt_sm.c b/drivers/char/ipmi/ipmi_bt_sm.c
index feafdab..4835b58 100644
--- a/drivers/char/ipmi/ipmi_bt_sm.c
+++ b/drivers/char/ipmi/ipmi_bt_sm.c
@@ -522,11 +522,12 @@
if (status & BT_H_BUSY) /* clear a leftover H_BUSY */
BT_CONTROL(BT_H_BUSY);
+ bt->timeout = bt->BT_CAP_req2rsp;
+
/* Read BT capabilities if it hasn't been done yet */
if (!bt->BT_CAP_outreqs)
BT_STATE_CHANGE(BT_STATE_CAPABILITIES_BEGIN,
SI_SM_CALL_WITHOUT_DELAY);
- bt->timeout = bt->BT_CAP_req2rsp;
BT_SI_SM_RETURN(SI_SM_IDLE);
case BT_STATE_XACTION_START:
diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig
index 5afb6374..3deec2d8 100644
--- a/drivers/char/tpm/Kconfig
+++ b/drivers/char/tpm/Kconfig
@@ -115,29 +115,29 @@
config TCG_CR50
boolean
- select TCG_TIS_CORE
---help---
- Common routines shared by drivers for Cr50 devices on SPI and I2C.
+ Common routines shared by drivers for Cr50-based devices.
config TCG_CR50_I2C
- bool "TPM Interface Specification 2.0 Interface (I2C - CR50)"
+ tristate "Cr50 I2C Interface"
depends on I2C=y
select TCG_CR50
---help---
- This is a driver for the Google cr50 I2C TPM interface which is a
- custom microcontroller and requires a custom i2c protocol interface
- to handle the limitations of the hardware. To compile this driver
- as a module, choose M here; the module will be called cr50_i2c.
+ If you have a H1 secure module running Cr50 firmware on I2C bus,
+ say Yes and it will be accessible from within Linux. To compile
+ this driver as a module, choose M here; the module will be called
+ cr50_i2c.
config TCG_CR50_SPI
- tristate "TCG PTP FIFO Interface over SPI - Chips with Cr50 Firmware"
+ tristate "Cr50 SPI Interface"
depends on SPI
select TCG_TIS_CORE
select TCG_CR50
---help---
- If you have a chip running Cr50 firmware on SPI bus, say Yes and it
- will be accessible from within Linux. To compile this driver as a
- module, choose M here; the module will be called cr50_spi.
+ If you have a H1 secure module running Cr50 firmware on SPI bus,
+ say Yes and it will be accessible from within Linux. To compile
+ this driver as a module, choose M here; the module will be called
+ cr50_spi.
config TCG_INFINEON
tristate "Infineon Technologies TPM Interface"
diff --git a/drivers/char/tpm/cr50_i2c.c b/drivers/char/tpm/cr50_i2c.c
index 1eca3b1..7aea109 100644
--- a/drivers/char/tpm/cr50_i2c.c
+++ b/drivers/char/tpm/cr50_i2c.c
@@ -17,7 +17,7 @@
*/
/*
- * cr50 is a TPM 2.0 capable device that requries special
+ * cr50 is a firmware for H1 secure modules that requires special
* handling for the I2C interface.
*
* - Use an interrupt for transaction status instead of hardcoded delays
@@ -637,8 +637,7 @@
return -ENODEV;
}
- dev_info(dev,
- "cr50 TPM 2.0 (i2c 0x%02x irq %d id 0x%x) [gentle shutdown]\n",
+ dev_info(dev, "cr50 TPM 2.0 (i2c 0x%02x irq %d id 0x%x)\n",
client->addr, client->irq, vendor >> 16);
chip->hwrng.quality = rng_quality;
@@ -682,19 +681,13 @@
return cr50_i2c_init(client);
}
-static void cr50_i2c_shutdown(struct i2c_client *client)
+static int cr50_i2c_remove(struct i2c_client *client)
{
struct tpm_chip *chip = i2c_get_clientdata(client);
- struct device *dev = &client->dev;
tpm_chip_unregister(chip);
release_locality(chip, 1);
- dev_info(dev, "gentle shutdown done\n");
-}
-static int cr50_i2c_remove(struct i2c_client *client)
-{
- cr50_i2c_shutdown(client);
return 0;
}
@@ -704,7 +697,6 @@
.id_table = cr50_i2c_table,
.probe = cr50_i2c_probe,
.remove = cr50_i2c_remove,
- .shutdown = cr50_i2c_shutdown,
.driver = {
.name = "cr50_i2c",
.pm = &cr50_i2c_pm,
diff --git a/drivers/char/tpm/cr50_spi.c b/drivers/char/tpm/cr50_spi.c
index 1da62e3..f881ffa 100644
--- a/drivers/char/tpm/cr50_spi.c
+++ b/drivers/char/tpm/cr50_spi.c
@@ -30,7 +30,7 @@
*/
#define CR50_SLEEP_DELAY_MSEC 1000
#define CR50_WAKE_START_DELAY_MSEC 1
-#define CR50_NOIRQ_ACCESS_DELAY_MSEC 10
+#define CR50_NOIRQ_ACCESS_DELAY_MSEC 2
#define CR50_READY_IRQ_TIMEOUT_MSEC TPM2_TIMEOUT_A
#define CR50_FLOW_CONTROL_MSEC TPM2_TIMEOUT_A
#define MAX_IRQ_CONFIRMATION_ATTEMPTS 3
@@ -40,6 +40,11 @@
#define TPM_CR50_FW_VER(l) (0x0F90 | ((l) << 12))
#define TPM_CR50_MAX_FW_VER_LEN 64
+static unsigned short rng_quality = 1022;
+module_param(rng_quality, ushort, 0644);
+MODULE_PARM_DESC(rng_quality,
+ "Estimation of true entropy, in bits per 1024 bits.");
+
struct cr50_spi_phy {
struct tpm_tis_data priv;
struct spi_device *spi_device;
@@ -378,11 +383,12 @@
"No IRQ - will use delays between transactions.\n");
}
+ phy->priv.rng_quality = rng_quality;
+
rc = tpm_tis_core_init(&dev->dev, &phy->priv, -1, &cr50_spi_phy_ops,
NULL);
if (rc < 0)
return rc;
- dev_info(&dev->dev, "registered shutdown handler [gentle shutdown]\n");
cr50_get_fw_version(&phy->priv, fw_ver);
dev_info(&dev->dev, "Cr50 firmware version: %s\n", fw_ver);
@@ -409,18 +415,12 @@
static SIMPLE_DEV_PM_OPS(cr50_spi_pm, cr50_suspend, cr50_spi_resume);
-static void cr50_spi_shutdown(struct spi_device *dev)
+static int cr50_spi_remove(struct spi_device *dev)
{
struct tpm_chip *chip = spi_get_drvdata(dev);
tpm_chip_unregister(chip);
tpm_tis_remove(chip);
- dev_info(&dev->dev, "gentle shutdown done\n");
-}
-
-static int cr50_spi_remove(struct spi_device *dev)
-{
- cr50_spi_shutdown(dev);
return 0;
}
@@ -446,7 +446,6 @@
},
.probe = cr50_spi_probe,
.remove = cr50_spi_remove,
- .shutdown = cr50_spi_shutdown,
.id_table = cr50_spi_id,
};
module_spi_driver(cr50_spi_driver);
diff --git a/drivers/char/tpm/tpm-dev-common.c b/drivers/char/tpm/tpm-dev-common.c
index 461bf0b..98cf36f 100644
--- a/drivers/char/tpm/tpm-dev-common.c
+++ b/drivers/char/tpm/tpm-dev-common.c
@@ -37,7 +37,7 @@
struct file_priv *priv = container_of(work, struct file_priv, work);
mutex_lock(&priv->buffer_mutex);
- atomic_set(&priv->data_pending, 0);
+ priv->data_pending = 0;
memset(priv->data_buffer, 0, sizeof(priv->data_buffer));
mutex_unlock(&priv->buffer_mutex);
}
@@ -46,7 +46,6 @@
struct file_priv *priv)
{
priv->chip = chip;
- atomic_set(&priv->data_pending, 0);
mutex_init(&priv->buffer_mutex);
setup_timer(&priv->user_read_timer, user_reader_timeout,
(unsigned long)priv);
@@ -59,29 +58,24 @@
size_t size, loff_t *off)
{
struct file_priv *priv = file->private_data;
- ssize_t ret_size;
- ssize_t orig_ret_size;
+ ssize_t ret_size = 0;
int rc;
del_singleshot_timer_sync(&priv->user_read_timer);
flush_work(&priv->work);
- ret_size = atomic_read(&priv->data_pending);
- if (ret_size > 0) { /* relay data */
- orig_ret_size = ret_size;
- if (size < ret_size)
- ret_size = size;
+ mutex_lock(&priv->buffer_mutex);
- mutex_lock(&priv->buffer_mutex);
+ if (priv->data_pending) {
+ ret_size = min_t(ssize_t, size, priv->data_pending);
rc = copy_to_user(buf, priv->data_buffer, ret_size);
- memset(priv->data_buffer, 0, orig_ret_size);
+ memset(priv->data_buffer, 0, priv->data_pending);
if (rc)
ret_size = -EFAULT;
- mutex_unlock(&priv->buffer_mutex);
+ priv->data_pending = 0;
}
- atomic_set(&priv->data_pending, 0);
-
+ mutex_unlock(&priv->buffer_mutex);
return ret_size;
}
@@ -92,18 +86,20 @@
size_t in_size = size;
ssize_t out_size;
- /* Cannot perform a write until the read has cleared either via
- * tpm_read or a user_read_timer timeout. This also prevents split
- * buffered writes from blocking here.
- */
- if (atomic_read(&priv->data_pending) != 0)
- return -EBUSY;
-
if (in_size > TPM_BUFSIZE)
return -E2BIG;
mutex_lock(&priv->buffer_mutex);
+ /* Cannot perform a write until the read has cleared either via
+ * tpm_read or a user_read_timer timeout. This also prevents split
+ * buffered writes from blocking here.
+ */
+ if (priv->data_pending != 0) {
+ mutex_unlock(&priv->buffer_mutex);
+ return -EBUSY;
+ }
+
if (copy_from_user
(priv->data_buffer, (void __user *) buf, in_size)) {
mutex_unlock(&priv->buffer_mutex);
@@ -133,7 +129,7 @@
return out_size;
}
- atomic_set(&priv->data_pending, out_size);
+ priv->data_pending = out_size;
mutex_unlock(&priv->buffer_mutex);
/* Set a timeout by which the reader must come claim the result */
@@ -150,5 +146,5 @@
del_singleshot_timer_sync(&priv->user_read_timer);
flush_work(&priv->work);
file->private_data = NULL;
- atomic_set(&priv->data_pending, 0);
+ priv->data_pending = 0;
}
diff --git a/drivers/char/tpm/tpm-dev.h b/drivers/char/tpm/tpm-dev.h
index ba3b6f9..b24cfb4 100644
--- a/drivers/char/tpm/tpm-dev.h
+++ b/drivers/char/tpm/tpm-dev.h
@@ -8,7 +8,7 @@
struct tpm_chip *chip;
/* Data passed to and from the tpm via the read/write calls */
- atomic_t data_pending;
+ size_t data_pending;
struct mutex buffer_mutex;
struct timer_list user_read_timer; /* user needs to claim result */
diff --git a/drivers/char/tpm/tpm2-space.c b/drivers/char/tpm/tpm2-space.c
index e2e059d8f..d26ea75 100644
--- a/drivers/char/tpm/tpm2-space.c
+++ b/drivers/char/tpm/tpm2-space.c
@@ -102,8 +102,9 @@
* TPM_RC_REFERENCE_H0 means the session has been
* flushed outside the space
*/
- rc = -ENOENT;
+ *handle = 0;
tpm_buf_destroy(&tbuf);
+ return -ENOENT;
} else if (rc > 0) {
dev_warn(&chip->dev, "%s: failed with a TPM error 0x%04X\n",
__func__, rc);
diff --git a/drivers/char/tpm/tpm_i2c_infineon.c b/drivers/char/tpm/tpm_i2c_infineon.c
index 944550d..d5b44ca 100644
--- a/drivers/char/tpm/tpm_i2c_infineon.c
+++ b/drivers/char/tpm/tpm_i2c_infineon.c
@@ -653,8 +653,7 @@
goto out_release;
}
- dev_info(dev, "1.2 TPM (device-id 0x%X) [gentle shutdown]\n",
- vendor >> 16);
+ dev_info(dev, "1.2 TPM (device-id 0x%X)\n", vendor >> 16);
tpm_dev.chip = chip;
@@ -727,20 +726,14 @@
return rc;
}
-static void tpm_tis_i2c_shutdown(struct i2c_client *client)
+static int tpm_tis_i2c_remove(struct i2c_client *client)
{
struct tpm_chip *chip = tpm_dev.chip;
- struct device *dev = &(client->dev);
tpm_chip_unregister(chip);
release_locality(chip, tpm_dev.locality, 1);
tpm_dev.client = NULL;
- dev_info(dev, "gentle shutdown done\n");
-}
-static int tpm_tis_i2c_remove(struct i2c_client *client)
-{
- tpm_tis_i2c_shutdown(client);
return 0;
}
@@ -748,7 +741,6 @@
.id_table = tpm_tis_i2c_table,
.probe = tpm_tis_i2c_probe,
.remove = tpm_tis_i2c_remove,
- .shutdown = tpm_tis_i2c_shutdown,
.driver = {
.name = "tpm_i2c_infineon",
.pm = &tpm_tis_i2c_ops,
diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c
index c4ba32e..ae3c135 100644
--- a/drivers/char/tpm/tpm_tis_core.c
+++ b/drivers/char/tpm/tpm_tis_core.c
@@ -776,6 +776,8 @@
chip->acpi_dev_handle = acpi_dev_handle;
#endif
+ chip->hwrng.quality = priv->rng_quality;
+
/* Maximum timeouts */
chip->timeout_a = msecs_to_jiffies(TIS_TIMEOUT_A_MAX);
chip->timeout_b = msecs_to_jiffies(TIS_TIMEOUT_B_MAX);
diff --git a/drivers/char/tpm/tpm_tis_core.h b/drivers/char/tpm/tpm_tis_core.h
index ade3e59..0fcf240 100644
--- a/drivers/char/tpm/tpm_tis_core.h
+++ b/drivers/char/tpm/tpm_tis_core.h
@@ -99,6 +99,7 @@
wait_queue_head_t int_queue;
wait_queue_head_t read_queue;
const struct tpm_tis_phy_ops *phy_ops;
+ unsigned short rng_quality;
};
struct tpm_tis_phy_ops {
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 7d3223f..72b6091 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -132,19 +132,8 @@
unsigned long parent_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
- unsigned int pllr;
- u16 mul;
- u8 div;
- regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-
- div = PLL_DIV(pllr);
- mul = PLL_MUL(pllr, pll->layout);
-
- if (!div || !mul)
- return 0;
-
- return (parent_rate / div) * (mul + 1);
+ return (parent_rate / pll->div) * (pll->mul + 1);
}
static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 2752fe2..3c45b29 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -38,6 +38,15 @@
Say Y if you want to support the clocks exposed by the RPM on
platforms such as apq8016, apq8084, msm8974 etc.
+config QCOM_CLK_RPMH
+ tristate "RPMh Clock Driver"
+ depends on COMMON_CLK_QCOM && QCOM_RPMH
+ help
+ RPMh manages shared resources on some Qualcomm Technologies, Inc.
+ SoCs. It accepts requests from other hardware subsystems via RSC.
+ Say Y if you want to support the clocks exposed by RPMh on
+ platforms such as SDM845.
+
config APQ_GCC_8084
tristate "APQ8084 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 56cb377..4930538 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -34,6 +34,7 @@
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
+obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
new file mode 100644
index 0000000..9f4fc77
--- /dev/null
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <soc/qcom/cmd-db.h>
+#include <soc/qcom/rpmh.h>
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+#define CLK_RPMH_ARC_EN_OFFSET 0
+#define CLK_RPMH_VRM_EN_OFFSET 4
+
+/**
+ * struct clk_rpmh - individual rpmh clock data structure
+ * @hw: handle between common and hardware-specific interfaces
+ * @res_name: resource name for the rpmh clock
+ * @div: clock divider to compute the clock rate
+ * @res_addr: base address of the rpmh resource within the RPMh
+ * @res_on_val: rpmh clock enable value
+ * @state: rpmh clock requested state
+ * @aggr_state: rpmh clock aggregated state
+ * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
+ * @valid_state_mask: mask to determine the state of the rpmh clock
+ * @dev: device to which it is attached
+ * @peer: pointer to the clock rpmh sibling
+ */
+struct clk_rpmh {
+ struct clk_hw hw;
+ const char *res_name;
+ u8 div;
+ u32 res_addr;
+ u32 res_on_val;
+ u32 state;
+ u32 aggr_state;
+ u32 last_sent_aggr_state;
+ u32 valid_state_mask;
+ struct device *dev;
+ struct clk_rpmh *peer;
+};
+
+struct clk_rpmh_desc {
+ struct clk_hw **clks;
+ size_t num_clks;
+};
+
+static DEFINE_MUTEX(rpmh_clk_lock);
+
+#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
+ _res_en_offset, _res_on, _div) \
+ static struct clk_rpmh _platform##_##_name_active; \
+ static struct clk_rpmh _platform##_##_name = { \
+ .res_name = _res_name, \
+ .res_addr = _res_en_offset, \
+ .res_on_val = _res_on, \
+ .div = _div, \
+ .peer = &_platform##_##_name_active, \
+ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
+ BIT(RPMH_ACTIVE_ONLY_STATE) | \
+ BIT(RPMH_SLEEP_STATE)), \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpmh_ops, \
+ .name = #_name, \
+ .parent_names = (const char *[]){ "xo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_rpmh _platform##_##_name_active = { \
+ .res_name = _res_name, \
+ .res_addr = _res_en_offset, \
+ .res_on_val = _res_on, \
+ .div = _div, \
+ .peer = &_platform##_##_name, \
+ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
+ BIT(RPMH_ACTIVE_ONLY_STATE)), \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpmh_ops, \
+ .name = #_name_active, \
+ .parent_names = (const char *[]){ "xo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }
+
+#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
+ _res_on, _div) \
+ __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
+ CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
+
+#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
+ _div) \
+ __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
+ CLK_RPMH_VRM_EN_OFFSET, 1, _div)
+
+static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
+{
+ return container_of(_hw, struct clk_rpmh, hw);
+}
+
+static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
+{
+ return (c->last_sent_aggr_state & BIT(state))
+ != (c->aggr_state & BIT(state));
+}
+
+static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
+{
+ struct tcs_cmd cmd = { 0 };
+ u32 cmd_state, on_val;
+ enum rpmh_state state = RPMH_SLEEP_STATE;
+ int ret;
+
+ cmd.addr = c->res_addr;
+ cmd_state = c->aggr_state;
+ on_val = c->res_on_val;
+
+ for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
+ if (has_state_changed(c, state)) {
+ if (cmd_state & BIT(state))
+ cmd.data = on_val;
+
+ ret = rpmh_write_async(c->dev, state, &cmd, 1);
+ if (ret) {
+ dev_err(c->dev, "set %s state of %s failed: (%d)\n",
+ !state ? "sleep" :
+ state == RPMH_WAKE_ONLY_STATE ?
+ "wake" : "active", c->res_name, ret);
+ return ret;
+ }
+ }
+ }
+
+ c->last_sent_aggr_state = c->aggr_state;
+ c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
+
+ return 0;
+}
+
+/*
+ * Update state and aggregate state values based on enable value.
+ */
+static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
+ bool enable)
+{
+ int ret;
+
+ /* Nothing required to be done if already off or on */
+ if (enable == c->state)
+ return 0;
+
+ c->state = enable ? c->valid_state_mask : 0;
+ c->aggr_state = c->state | c->peer->state;
+ c->peer->aggr_state = c->aggr_state;
+
+ ret = clk_rpmh_send_aggregate_command(c);
+ if (!ret)
+ return 0;
+
+ if (ret && enable)
+ c->state = 0;
+ else if (ret)
+ c->state = c->valid_state_mask;
+
+ WARN(1, "clk: %s failed to %s\n", c->res_name,
+ enable ? "enable" : "disable");
+ return ret;
+}
+
+static int clk_rpmh_prepare(struct clk_hw *hw)
+{
+ struct clk_rpmh *c = to_clk_rpmh(hw);
+ int ret = 0;
+
+ mutex_lock(&rpmh_clk_lock);
+ ret = clk_rpmh_aggregate_state_send_command(c, true);
+ mutex_unlock(&rpmh_clk_lock);
+
+ return ret;
+};
+
+static void clk_rpmh_unprepare(struct clk_hw *hw)
+{
+ struct clk_rpmh *c = to_clk_rpmh(hw);
+
+ mutex_lock(&rpmh_clk_lock);
+ clk_rpmh_aggregate_state_send_command(c, false);
+ mutex_unlock(&rpmh_clk_lock);
+};
+
+static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_rpmh *r = to_clk_rpmh(hw);
+
+ /*
+ * RPMh clocks have a fixed rate. Return static rate.
+ */
+ return prate / r->div;
+}
+
+static const struct clk_ops clk_rpmh_ops = {
+ .prepare = clk_rpmh_prepare,
+ .unprepare = clk_rpmh_unprepare,
+ .recalc_rate = clk_rpmh_recalc_rate,
+};
+
+/* Resource name must match resource id present in cmd-db. */
+DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
+DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
+DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
+
+static struct clk_hw *sdm845_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
+ .clks = sdm845_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
+};
+
+static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ struct clk_rpmh_desc *rpmh = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= rpmh->num_clks) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return rpmh->clks[idx];
+}
+
+static int clk_rpmh_probe(struct platform_device *pdev)
+{
+ struct clk_hw **hw_clks;
+ struct clk_rpmh *rpmh_clk;
+ const struct clk_rpmh_desc *desc;
+ int ret, i;
+
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -ENODEV;
+
+ hw_clks = desc->clks;
+
+ for (i = 0; i < desc->num_clks; i++) {
+ u32 res_addr;
+
+ rpmh_clk = to_clk_rpmh(hw_clks[i]);
+ res_addr = cmd_db_read_addr(rpmh_clk->res_name);
+ if (!res_addr) {
+ dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
+ rpmh_clk->res_name);
+ return -ENODEV;
+ }
+ rpmh_clk->res_addr += res_addr;
+ rpmh_clk->dev = &pdev->dev;
+
+ ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register %s\n",
+ hw_clks[i]->init->name);
+ return ret;
+ }
+ }
+
+ /* typecast to silence compiler warning */
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
+ (void *)desc);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to add clock provider\n");
+ return ret;
+ }
+
+ dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
+
+ return 0;
+}
+
+static const struct of_device_id clk_rpmh_match_table[] = {
+ { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
+
+static struct platform_driver clk_rpmh_driver = {
+ .probe = clk_rpmh_probe,
+ .driver = {
+ .name = "clk-rpmh",
+ .of_match_table = clk_rpmh_match_table,
+ },
+};
+
+static int __init clk_rpmh_init(void)
+{
+ return platform_driver_register(&clk_rpmh_driver);
+}
+subsys_initcall(clk_rpmh_init);
+
+static void __exit clk_rpmh_exit(void)
+{
+ platform_driver_unregister(&clk_rpmh_driver);
+}
+module_exit(clk_rpmh_exit);
+
+MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index e78e6f5..0f694ed 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -1103,6 +1103,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -1129,6 +1130,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -1270,6 +1272,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -1328,6 +1331,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -1397,6 +1401,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -2985,6 +2990,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -3011,6 +3017,7 @@
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
+ .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -3049,6 +3056,36 @@
},
};
+static struct clk_branch gcc_cpuss_dvm_bus_clk = {
+ .halt_reg = 0x48190,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48190,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cpuss_dvm_bus_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cpuss_gnoc_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x48004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cpuss_gnoc_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
@@ -3344,6 +3381,8 @@
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
+ [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
+ [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
@@ -3433,10 +3472,6 @@
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
- /* Enable CPUSS clocks */
- regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
- regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);
-
return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
}
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index e580a5e..30c23b8 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -248,8 +248,9 @@
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
PTR_ERR(clk));
else
- dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
- clkspec->args[0], clkspec->args[1], clk, clk);
+ dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
+ clkspec->args[0], clkspec->args[1], clk,
+ clk_get_rate(clk));
return clk;
}
@@ -314,7 +315,7 @@
if (IS_ERR_OR_NULL(clk))
goto fail;
- dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
+ dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
return;
@@ -380,7 +381,7 @@
if (IS_ERR(clk))
goto fail;
- dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
+ dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
return;
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 20226d4..a905bbb 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -285,6 +285,7 @@
static struct pstate_funcs pstate_funcs __read_mostly;
static int hwp_active __read_mostly;
+static int hwp_mode_bdw __read_mostly;
static bool per_cpu_limits __read_mostly;
static struct cpufreq_driver *intel_pstate_driver __read_mostly;
@@ -1371,7 +1372,15 @@
cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
cpu->pstate.scaling = pstate_funcs.get_scaling();
cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
- cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
+
+ if (hwp_active && !hwp_mode_bdw) {
+ unsigned int phy_max, current_max;
+
+ intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max);
+ cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
+ } else {
+ cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
+ }
if (pstate_funcs.get_aperf_mperf_shift)
cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
@@ -2261,28 +2270,36 @@
static inline void intel_pstate_request_control_from_smm(void) {}
#endif /* CONFIG_ACPI */
+#define INTEL_PSTATE_HWP_BROADWELL 0x01
+
+#define ICPU_HWP(model, hwp_mode) \
+ { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
+
static const struct x86_cpu_id hwp_support_ids[] __initconst = {
- { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
+ ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
+ ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
+ ICPU_HWP(X86_MODEL_ANY, 0),
{}
};
static int __init intel_pstate_init(void)
{
+ const struct x86_cpu_id *id;
int rc;
if (no_load)
return -ENODEV;
- if (x86_match_cpu(hwp_support_ids)) {
+ id = x86_match_cpu(hwp_support_ids);
+ if (id) {
copy_cpu_funcs(&core_funcs);
if (!no_hwp) {
hwp_active++;
+ hwp_mode_bdw = id->driver_data;
intel_pstate.attr = hwp_cpufreq_attrs;
goto hwp_cpu_matched;
}
} else {
- const struct x86_cpu_id *id;
-
id = x86_match_cpu(intel_pstate_cpu_ids);
if (!id)
return -ENODEV;
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index e06605b..1d7d5d1 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -43,9 +43,31 @@
static struct stop_psscr_table stop_psscr_table[CPUIDLE_STATE_MAX] __read_mostly;
-static u64 snooze_timeout __read_mostly;
+static u64 default_snooze_timeout __read_mostly;
static bool snooze_timeout_en __read_mostly;
+static u64 get_snooze_timeout(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ int i;
+
+ if (unlikely(!snooze_timeout_en))
+ return default_snooze_timeout;
+
+ for (i = index + 1; i < drv->state_count; i++) {
+ struct cpuidle_state *s = &drv->states[i];
+ struct cpuidle_state_usage *su = &dev->states_usage[i];
+
+ if (s->disabled || su->disable)
+ continue;
+
+ return s->target_residency * tb_ticks_per_usec;
+ }
+
+ return default_snooze_timeout;
+}
+
static int snooze_loop(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -56,7 +78,7 @@
local_irq_enable();
- snooze_exit_time = get_tb() + snooze_timeout;
+ snooze_exit_time = get_tb() + get_snooze_timeout(dev, drv, index);
ppc64_runlatch_off();
HMT_very_low();
while (!need_resched()) {
@@ -463,11 +485,9 @@
cpuidle_state_table = powernv_states;
/* Device tree can indicate more idle states */
max_idle_state = powernv_add_idle_states();
- if (max_idle_state > 1) {
+ default_snooze_timeout = TICK_USEC * tb_ticks_per_usec;
+ if (max_idle_state > 1)
snooze_timeout_en = true;
- snooze_timeout = powernv_states[1].target_residency *
- tb_ticks_per_usec;
- }
} else
return -ENODEV;
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index ed4df58..dc47fc8 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -128,9 +128,14 @@
}
#ifdef CONFIG_SUSPEND
-static void enter_s2idle_proper(struct cpuidle_driver *drv,
+static int cpuidle_freeze_error;
+
+static int enter_s2idle_proper(struct cpuidle_driver *drv,
struct cpuidle_device *dev, int index)
+
{
+ int ret;
+
/*
* trace_suspend_resume() called by tick_freeze() for the last CPU
* executing it contains RCU usage regarded as invalid in the idle
@@ -143,7 +148,7 @@
* suspended is generally unsafe.
*/
stop_critical_timings();
- drv->states[index].enter_s2idle(dev, drv, index);
+ ret = drv->states[index].enter_s2idle(dev, drv, index);
WARN_ON(!irqs_disabled());
/*
* timekeeping_resume() that will be called by tick_unfreeze() for the
@@ -152,6 +157,7 @@
*/
RCU_NONIDLE(tick_unfreeze());
start_critical_timings();
+ return ret;
}
/**
@@ -164,7 +170,7 @@
*/
int cpuidle_enter_s2idle(struct cpuidle_driver *drv, struct cpuidle_device *dev)
{
- int index;
+ int index, ret = 0;
/*
* Find the deepest state with ->enter_s2idle present, which guarantees
@@ -173,10 +179,27 @@
*/
index = find_deepest_state(drv, dev, UINT_MAX, 0, true);
if (index > 0)
- enter_s2idle_proper(drv, dev, index);
+ ret = enter_s2idle_proper(drv, dev, index);
+
+ if (ret < 0) {
+ cpuidle_freeze_error = ret;
+ pm_system_wakeup();
+ }
return index;
}
+
+void cpuidle_prepare_freeze(void)
+{
+ cpuidle_freeze_error = 0;
+ cpuidle_resume();
+}
+
+int cpuidle_complete_freeze(void)
+{
+ cpuidle_pause();
+ return cpuidle_freeze_error;
+}
#endif /* CONFIG_SUSPEND */
/**
diff --git a/drivers/dax/super.c b/drivers/dax/super.c
index c4cd034..6c179c2 100644
--- a/drivers/dax/super.c
+++ b/drivers/dax/super.c
@@ -73,42 +73,50 @@
/**
* __bdev_dax_supported() - Check if the device supports dax for filesystem
- * @sb: The superblock of the device
+ * @bdev: block device to check
* @blocksize: The block size of the device
*
* This is a library function for filesystems to check if the block device
* can be mounted with dax option.
*
- * Return: negative errno if unsupported, 0 if supported.
+ * Return: true if supported, false if unsupported
*/
-int __bdev_dax_supported(struct super_block *sb, int blocksize)
+bool __bdev_dax_supported(struct block_device *bdev, int blocksize)
{
- struct block_device *bdev = sb->s_bdev;
struct dax_device *dax_dev;
+ struct request_queue *q;
pgoff_t pgoff;
int err, id;
void *kaddr;
pfn_t pfn;
long len;
+ char buf[BDEVNAME_SIZE];
if (blocksize != PAGE_SIZE) {
- pr_err("VFS (%s): error: unsupported blocksize for dax\n",
- sb->s_id);
- return -EINVAL;
+ pr_debug("%s: error: unsupported blocksize for dax\n",
+ bdevname(bdev, buf));
+ return false;
+ }
+
+ q = bdev_get_queue(bdev);
+ if (!q || !blk_queue_dax(q)) {
+ pr_debug("%s: error: request queue doesn't support dax\n",
+ bdevname(bdev, buf));
+ return false;
}
err = bdev_dax_pgoff(bdev, 0, PAGE_SIZE, &pgoff);
if (err) {
- pr_err("VFS (%s): error: unaligned partition for dax\n",
- sb->s_id);
- return err;
+ pr_debug("%s: error: unaligned partition for dax\n",
+ bdevname(bdev, buf));
+ return false;
}
dax_dev = dax_get_by_host(bdev->bd_disk->disk_name);
if (!dax_dev) {
- pr_err("VFS (%s): error: device does not support dax\n",
- sb->s_id);
- return -EOPNOTSUPP;
+ pr_debug("%s: error: device does not support dax\n",
+ bdevname(bdev, buf));
+ return false;
}
id = dax_read_lock();
@@ -118,12 +126,12 @@
put_dax(dax_dev);
if (len < 1) {
- pr_err("VFS (%s): error: dax access failed (%ld)",
- sb->s_id, len);
- return len < 0 ? len : -EIO;
+ pr_debug("%s: error: dax access failed (%ld)\n",
+ bdevname(bdev, buf), len);
+ return false;
}
- return 0;
+ return true;
}
EXPORT_SYMBOL_GPL(__bdev_dax_supported);
#endif
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index af9e706..83662d5 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -7,6 +7,7 @@
menuconfig DRM
tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && HAS_DMA
+ select DRM_PANEL_ORIENTATION_QUIRKS
select HDMI
select FB_CMDLINE
select I2C
@@ -149,6 +150,10 @@
bool
depends on DRM && MMU
+config DRM_SCHED
+ tristate
+ depends on DRM
+
source "drivers/gpu/drm/i2c/Kconfig"
source "drivers/gpu/drm/arm/Kconfig"
@@ -178,6 +183,7 @@
depends on DRM && PCI && MMU
select FW_LOADER
select DRM_KMS_HELPER
+ select DRM_SCHED
select DRM_TTM
select POWER_SUPPLY
select HWMON
@@ -360,6 +366,10 @@
endif # DRM_LEGACY
+# Separate option because drm_panel_orientation_quirks.c is shared with fbdev
+config DRM_PANEL_ORIENTATION_QUIRKS
+ tristate
+
config DRM_LIB_RANDOM
bool
default n
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 0ca845e..ffac5fd 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -47,8 +47,10 @@
obj-$(CONFIG_DRM) += drm.o
obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
+obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o
obj-$(CONFIG_DRM_ARM) += arm/
obj-$(CONFIG_DRM_TTM) += ttm/
+obj-$(CONFIG_DRM_SCHED) += scheduler/
obj-$(CONFIG_DRM_TDFX) += tdfx/
obj-$(CONFIG_DRM_R128) += r128/
obj-y += amd/lib/
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 90202cf..d6e5b72 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -52,7 +52,8 @@
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
- amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o
+ amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o \
+ amdgpu_ids.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
@@ -62,7 +63,7 @@
amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
amdgpu-y += \
- vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o
+ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o
# add GMC block
amdgpu-y += \
@@ -135,10 +136,7 @@
amdgpu-y += amdgpu_cgs.o
# GPU scheduler
-amdgpu-y += \
- ../scheduler/gpu_scheduler.o \
- ../scheduler/sched_fence.o \
- amdgpu_job.o
+amdgpu-y += amdgpu_job.o
# ACP componet
ifneq ($(CONFIG_DRM_AMD_ACP),)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9e3c95e..37f5f4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -45,8 +45,11 @@
#include <drm/drmP.h>
#include <drm/drm_gem.h>
#include <drm/amdgpu_drm.h>
+#include <drm/gpu_scheduler.h>
#include <kgd_kfd_interface.h>
+#include "dm_pp_interface.h"
+#include "kgd_pp_interface.h"
#include "amd_shared.h"
#include "amdgpu_mode.h"
@@ -59,7 +62,6 @@
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
#include "amdgpu_vm.h"
-#include "amd_powerplay.h"
#include "amdgpu_dpm.h"
#include "amdgpu_acp.h"
#include "amdgpu_uvd.h"
@@ -67,10 +69,9 @@
#include "amdgpu_vcn.h"
#include "amdgpu_mn.h"
#include "amdgpu_dm.h"
-
-#include "gpu_scheduler.h"
#include "amdgpu_virt.h"
#include "amdgpu_gart.h"
+#include "amdgpu_debugfs.h"
/*
* Modules parameters.
@@ -125,6 +126,7 @@
extern int amdgpu_job_hang_limit;
extern int amdgpu_lbpw;
extern int amdgpu_compute_multipipe;
+extern int amdgpu_gpu_recovery;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
@@ -223,17 +225,18 @@
AMDGPU_CP_KIQ_IRQ_LAST
};
-int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type,
- enum amd_clockgating_state state);
-int amdgpu_set_powergating_state(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type,
- enum amd_powergating_state state);
-void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
-int amdgpu_wait_for_idle(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type);
-bool amdgpu_is_idle(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type);
+int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type,
+ enum amd_clockgating_state state);
+int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type,
+ enum amd_powergating_state state);
+void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
+ u32 *flags);
+int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type);
+bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type);
#define AMDGPU_MAX_IP_NUM 16
@@ -258,15 +261,16 @@
const struct amdgpu_ip_block_version *version;
};
-int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
- enum amd_ip_block_type type,
- u32 major, u32 minor);
+int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
+ enum amd_ip_block_type type,
+ u32 major, u32 minor);
-struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
- enum amd_ip_block_type type);
+struct amdgpu_ip_block *
+amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
+ enum amd_ip_block_type type);
-int amdgpu_ip_block_add(struct amdgpu_device *adev,
- const struct amdgpu_ip_block_version *ip_block_version);
+int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
+ const struct amdgpu_ip_block_version *ip_block_version);
/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
struct amdgpu_buffer_funcs {
@@ -346,8 +350,9 @@
uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
uint32_t flags);
/* get the pde for a given mc addr */
- u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
- uint32_t (*get_invalidate_req)(unsigned int vm_id);
+ void (*get_vm_pde)(struct amdgpu_device *adev, int level,
+ u64 *dst, u64 *flags);
+ uint32_t (*get_invalidate_req)(unsigned int vmid);
};
/* provided by the ih block */
@@ -373,9 +378,6 @@
struct page *page;
dma_addr_t addr;
};
-int amdgpu_dummy_page_init(struct amdgpu_device *adev);
-void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
-
/*
* Clocks
@@ -425,7 +427,6 @@
void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
-int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
/* sub-allocation manager, it has to be protected by another lock.
* By conception this is an helper for other part of the driver
@@ -542,6 +543,7 @@
u64 private_aperture_end;
/* protects concurrent invalidation */
spinlock_t invalidate_lock;
+ bool translate_further;
};
/*
@@ -652,12 +654,6 @@
AMDGPU_DOORBELL64_INVALID = 0xFFFF
} AMDGPU_DOORBELL64_ASSIGNMENT;
-
-void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
- phys_addr_t *aperture_base,
- size_t *aperture_size,
- size_t *start_offset);
-
/*
* IRQS.
*/
@@ -691,7 +687,7 @@
uint32_t flags;
};
-extern const struct amd_sched_backend_ops amdgpu_sched_ops;
+extern const struct drm_sched_backend_ops amdgpu_sched_ops;
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
struct amdgpu_job **job, struct amdgpu_vm *vm);
@@ -701,7 +697,7 @@
void amdgpu_job_free_resources(struct amdgpu_job *job);
void amdgpu_job_free(struct amdgpu_job *job);
int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
- struct amd_sched_entity *entity, void *owner,
+ struct drm_sched_entity *entity, void *owner,
struct dma_fence **f);
/*
@@ -734,7 +730,7 @@
struct amdgpu_ctx_ring {
uint64_t sequence;
struct dma_fence **fences;
- struct amd_sched_entity entity;
+ struct drm_sched_entity entity;
};
struct amdgpu_ctx {
@@ -748,8 +744,8 @@
struct dma_fence **fences;
struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
bool preamble_presented;
- enum amd_sched_priority init_priority;
- enum amd_sched_priority override_priority;
+ enum drm_sched_priority init_priority;
+ enum drm_sched_priority override_priority;
struct mutex lock;
atomic_t guilty;
};
@@ -769,7 +765,7 @@
struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
struct amdgpu_ring *ring, uint64_t seq);
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
- enum amd_sched_priority priority);
+ enum drm_sched_priority priority);
int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
@@ -966,6 +962,7 @@
};
struct amdgpu_cu_info {
+ uint32_t simd_per_cu;
uint32_t max_waves_per_simd;
uint32_t wave_front_size;
uint32_t max_scratch_slots_per_cu;
@@ -1118,12 +1115,11 @@
#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
struct amdgpu_job {
- struct amd_sched_job base;
+ struct drm_sched_job base;
struct amdgpu_device *adev;
struct amdgpu_vm *vm;
struct amdgpu_ring *ring;
struct amdgpu_sync sync;
- struct amdgpu_sync dep_sync;
struct amdgpu_sync sched_sync;
struct amdgpu_ib *ibs;
struct dma_fence *fence; /* the hw fence */
@@ -1132,7 +1128,7 @@
void *owner;
uint64_t fence_ctx; /* the fence_context this job uses */
bool vm_needs_flush;
- unsigned vm_id;
+ unsigned vmid;
uint64_t vm_pd_addr;
uint32_t gds_base, gds_size;
uint32_t gws_base, gws_size;
@@ -1163,7 +1159,7 @@
/*
* Writeback
*/
-#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
struct amdgpu_wb {
struct amdgpu_bo *wb_obj;
@@ -1176,7 +1172,7 @@
int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
-void amdgpu_get_pcie_info(struct amdgpu_device *adev);
+void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
/*
* SDMA
@@ -1241,24 +1237,6 @@
*/
void amdgpu_test_moves(struct amdgpu_device *adev);
-/*
- * Debugfs
- */
-struct amdgpu_debugfs {
- const struct drm_info_list *files;
- unsigned num_files;
-};
-
-int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
- const struct drm_info_list *files,
- unsigned nfiles);
-int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
-
-#if defined(CONFIG_DEBUG_FS)
-int amdgpu_debugfs_init(struct drm_minor *minor);
-#endif
-
-int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
/*
* amdgpu smumgr functions
@@ -1413,8 +1391,6 @@
void *va;
};
-int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
-
/*
* CGS
*/
@@ -1430,6 +1406,87 @@
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
+
+/*
+ * amdgpu nbio functions
+ *
+ */
+struct nbio_hdp_flush_reg {
+ u32 ref_and_mask_cp0;
+ u32 ref_and_mask_cp1;
+ u32 ref_and_mask_cp2;
+ u32 ref_and_mask_cp3;
+ u32 ref_and_mask_cp4;
+ u32 ref_and_mask_cp5;
+ u32 ref_and_mask_cp6;
+ u32 ref_and_mask_cp7;
+ u32 ref_and_mask_cp8;
+ u32 ref_and_mask_cp9;
+ u32 ref_and_mask_sdma0;
+ u32 ref_and_mask_sdma1;
+};
+
+struct amdgpu_nbio_funcs {
+ const struct nbio_hdp_flush_reg *hdp_flush_reg;
+ u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
+ u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
+ u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
+ u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+ u32 (*get_rev_id)(struct amdgpu_device *adev);
+ void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
+ void (*hdp_flush)(struct amdgpu_device *adev);
+ u32 (*get_memsize)(struct amdgpu_device *adev);
+ void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index);
+ void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
+ bool enable);
+ void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
+ bool enable);
+ void (*ih_doorbell_range)(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index);
+ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+ bool enable);
+ void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
+ bool enable);
+ void (*get_clockgating_state)(struct amdgpu_device *adev,
+ u32 *flags);
+ void (*ih_control)(struct amdgpu_device *adev);
+ void (*init_registers)(struct amdgpu_device *adev);
+ void (*detect_hw_virt)(struct amdgpu_device *adev);
+};
+
+
+/* Define the HW IP blocks will be used in driver , add more if necessary */
+enum amd_hw_ip_block_type {
+ GC_HWIP = 1,
+ HDP_HWIP,
+ SDMA0_HWIP,
+ SDMA1_HWIP,
+ MMHUB_HWIP,
+ ATHUB_HWIP,
+ NBIO_HWIP,
+ MP0_HWIP,
+ UVD_HWIP,
+ VCN_HWIP = UVD_HWIP,
+ VCE_HWIP,
+ DF_HWIP,
+ DCE_HWIP,
+ OSSSYS_HWIP,
+ SMUIO_HWIP,
+ PWR_HWIP,
+ NBIF_HWIP,
+ MAX_HWIP
+};
+
+#define HWIP_MAX_INSTANCE 6
+
+struct amd_powerplay {
+ struct cgs_device *cgs_device;
+ void *pp_handle;
+ const struct amd_ip_funcs *ip_funcs;
+ const struct amd_pm_funcs *pp_funcs;
+};
+
#define AMDGPU_RESET_MAGIC_NUM 64
struct amdgpu_device {
struct device *dev;
@@ -1615,6 +1672,11 @@
/* amdkfd interface */
struct kfd_dev *kfd;
+ /* soc15 register offset based on ip, instance and segment */
+ uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+
+ const struct amdgpu_nbio_funcs *nbio_funcs;
+
/* delayed work_func for deferring clockgating during resume */
struct delayed_work late_init_work;
@@ -1625,9 +1687,6 @@
/* link all shadow bo */
struct list_head shadow_list;
struct mutex shadow_list_lock;
- /* link all gtt */
- spinlock_t gtt_list_lock;
- struct list_head gtt_list;
/* keep an lru list of rings by HW IP */
struct list_head ring_lru_list;
spinlock_t ring_lru_list_lock;
@@ -1638,7 +1697,8 @@
/* record last mm index being written through WREG32*/
unsigned long last_mm_index;
- bool in_sriov_reset;
+ bool in_gpu_reset;
+ struct mutex lock_reset;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1782,7 +1842,7 @@
#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
-#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
+#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))
#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
@@ -1793,7 +1853,7 @@
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
+#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
@@ -1832,22 +1892,25 @@
#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
/* Common functions */
-int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job);
-bool amdgpu_need_backup(struct amdgpu_device *adev);
-void amdgpu_pci_config_reset(struct amdgpu_device *adev);
-bool amdgpu_need_post(struct amdgpu_device *adev);
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ struct amdgpu_job* job, bool force);
+void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
+bool amdgpu_device_need_post(struct amdgpu_device *adev);
void amdgpu_update_display_priority(struct amdgpu_device *adev);
void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
u64 num_vis_bytes);
void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
-void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
-void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
+void amdgpu_device_vram_location(struct amdgpu_device *adev,
+ struct amdgpu_mc *mc, u64 base);
+void amdgpu_device_gart_location(struct amdgpu_device *adev,
+ struct amdgpu_mc *mc);
+int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
const u32 *registers,
const u32 array_size);
@@ -1881,7 +1944,7 @@
int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
void amdgpu_driver_postclose_kms(struct drm_device *dev,
struct drm_file *file_priv);
-int amdgpu_suspend(struct amdgpu_device *adev);
+int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 108ecf5..0d994c7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -281,7 +281,7 @@
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
const struct amdgpu_ip_block *ip_block =
- amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
+ amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
if (!ip_block)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5484a4a..1d605e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -93,6 +93,39 @@
adev->pdev, kfd2kgd);
}
+/**
+ * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
+ * setup amdkfd
+ *
+ * @adev: amdgpu_device pointer
+ * @aperture_base: output returning doorbell aperture base physical address
+ * @aperture_size: output returning doorbell aperture size in bytes
+ * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
+ *
+ * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
+ * takes doorbells required for its own rings and reports the setup to amdkfd.
+ * amdgpu reserved doorbells are at the start of the doorbell aperture.
+ */
+static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
+ phys_addr_t *aperture_base,
+ size_t *aperture_size,
+ size_t *start_offset)
+{
+ /*
+ * The first num_doorbells are used by amdgpu.
+ * amdkfd takes whatever's left in the aperture.
+ */
+ if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
+ *aperture_base = adev->doorbell.base;
+ *aperture_size = adev->doorbell.size;
+ *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
+ } else {
+ *aperture_base = 0;
+ *aperture_size = 0;
+ *start_offset = 0;
+ }
+}
+
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
{
int i;
@@ -242,14 +275,34 @@
kfree(mem);
}
-uint64_t get_vmem_size(struct kgd_dev *kgd)
+void get_local_mem_info(struct kgd_dev *kgd,
+ struct kfd_local_mem_info *mem_info)
{
- struct amdgpu_device *adev =
- (struct amdgpu_device *)kgd;
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
+ ~((1ULL << 32) - 1);
+ resource_size_t aper_limit = adev->mc.aper_base + adev->mc.aper_size;
- BUG_ON(kgd == NULL);
+ memset(mem_info, 0, sizeof(*mem_info));
+ if (!(adev->mc.aper_base & address_mask || aper_limit & address_mask)) {
+ mem_info->local_mem_size_public = adev->mc.visible_vram_size;
+ mem_info->local_mem_size_private = adev->mc.real_vram_size -
+ adev->mc.visible_vram_size;
+ } else {
+ mem_info->local_mem_size_public = 0;
+ mem_info->local_mem_size_private = adev->mc.real_vram_size;
+ }
+ mem_info->vram_width = adev->mc.vram_width;
- return adev->mc.real_vram_size;
+ pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
+ &adev->mc.aper_base, &aper_limit,
+ mem_info->local_mem_size_public,
+ mem_info->local_mem_size_private);
+
+ if (amdgpu_sriov_vf(adev))
+ mem_info->mem_clk_max = adev->clock.default_mclk / 100;
+ else
+ mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
}
uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
@@ -271,3 +324,33 @@
return amdgpu_dpm_get_sclk(adev, false) / 100;
}
+
+void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
+
+ memset(cu_info, 0, sizeof(*cu_info));
+ if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
+ return;
+
+ cu_info->cu_active_number = acu_info.number;
+ cu_info->cu_ao_mask = acu_info.ao_cu_mask;
+ memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
+ sizeof(acu_info.bitmap));
+ cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
+ cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
+ cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+ cu_info->simd_per_cu = acu_info.simd_per_cu;
+ cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
+ cu_info->wave_front_size = acu_info.wave_front_size;
+ cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
+ cu_info->lds_size = acu_info.lds_size;
+}
+
+uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+
+ return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 1ef486b..e515ca0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -57,10 +57,13 @@
void **mem_obj, uint64_t *gpu_addr,
void **cpu_ptr);
void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
-uint64_t get_vmem_size(struct kgd_dev *kgd);
+void get_local_mem_info(struct kgd_dev *kgd,
+ struct kfd_local_mem_info *mem_info);
uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
+void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
+uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
#define read_user_wptr(mmptr, wptr, dst) \
({ \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 1e3e9be..a9e6aea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -105,7 +105,14 @@
uint32_t queue_id, uint32_t __user *wptr,
uint32_t wptr_shift, uint32_t wptr_mask,
struct mm_struct *mm);
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
+static int kgd_hqd_dump(struct kgd_dev *kgd,
+ uint32_t pipe_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs);
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ uint32_t __user *wptr, struct mm_struct *mm);
+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ uint32_t engine_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs);
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
@@ -166,17 +173,19 @@
static const struct kfd2kgd_calls kfd2kgd = {
.init_gtt_mem_allocation = alloc_gtt_mem,
.free_gtt_mem = free_gtt_mem,
- .get_vmem_size = get_vmem_size,
+ .get_local_mem_info = get_local_mem_info,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
- .alloc_pasid = amdgpu_vm_alloc_pasid,
- .free_pasid = amdgpu_vm_free_pasid,
+ .alloc_pasid = amdgpu_pasid_alloc,
+ .free_pasid = amdgpu_pasid_free,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
.init_interrupts = kgd_init_interrupts,
.hqd_load = kgd_hqd_load,
.hqd_sdma_load = kgd_hqd_sdma_load,
+ .hqd_dump = kgd_hqd_dump,
+ .hqd_sdma_dump = kgd_hqd_sdma_dump,
.hqd_is_occupied = kgd_hqd_is_occupied,
.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
.hqd_destroy = kgd_hqd_destroy,
@@ -191,6 +200,8 @@
.get_fw_version = get_fw_version,
.set_scratch_backing_va = set_scratch_backing_va,
.get_tile_config = get_tile_config,
+ .get_cu_info = get_cu_info,
+ .get_vram_usage = amdgpu_amdkfd_get_vram_usage
};
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
@@ -375,7 +386,44 @@
return 0;
}
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
+static int kgd_hqd_dump(struct kgd_dev *kgd,
+ uint32_t pipe_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs)
+{
+ struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ uint32_t i = 0, reg;
+#define HQD_N_REGS (35+4)
+#define DUMP_REG(addr) do { \
+ if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
+ break; \
+ (*dump)[i][0] = (addr) << 2; \
+ (*dump)[i++][1] = RREG32(addr); \
+ } while (0)
+
+ *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
+ if (*dump == NULL)
+ return -ENOMEM;
+
+ acquire_queue(kgd, pipe_id, queue_id);
+
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
+
+ for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
+ DUMP_REG(reg);
+
+ release_queue(kgd);
+
+ WARN_ON_ONCE(i != HQD_N_REGS);
+ *n_regs = i;
+
+ return 0;
+}
+
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ uint32_t __user *wptr, struct mm_struct *mm)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct cik_sdma_rlc_registers *m;
@@ -410,10 +458,17 @@
WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
}
- WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
- m->sdma_rlc_doorbell);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
+ data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
+ ENABLE, 1);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
+
+ if (read_user_wptr(mm, wptr, data))
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
+ else
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+ m->sdma_rlc_rb_rptr);
+
WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
m->sdma_rlc_virtual_addr);
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
@@ -423,8 +478,37 @@
m->sdma_rlc_rb_rptr_addr_lo);
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
m->sdma_rlc_rb_rptr_addr_hi);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
- m->sdma_rlc_rb_cntl);
+
+ data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ RB_ENABLE, 1);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+
+ return 0;
+}
+
+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ uint32_t engine_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs)
+{
+ struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
+ queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
+ uint32_t i = 0, reg;
+#undef HQD_N_REGS
+#define HQD_N_REGS (19+4)
+
+ *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
+ if (*dump == NULL)
+ return -ENOMEM;
+
+ for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
+ DUMP_REG(sdma_offset + reg);
+ for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
+ reg++)
+ DUMP_REG(sdma_offset + reg);
+
+ WARN_ON_ONCE(i != HQD_N_REGS);
+ *n_regs = i;
return 0;
}
@@ -575,7 +659,7 @@
struct cik_sdma_rlc_registers *m;
uint32_t sdma_base_addr;
uint32_t temp;
- int timeout = utimeout;
+ unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
m = get_sdma_mqd(mqd);
sdma_base_addr = get_sdma_base_addr(m);
@@ -588,10 +672,9 @@
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
break;
- if (timeout <= 0)
+ if (time_after(jiffies, end_jiffies))
return -ETIME;
- msleep(20);
- timeout -= 20;
+ usleep_range(500, 1000);
}
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
@@ -599,6 +682,8 @@
RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+ m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 056929b..b127259 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -45,7 +45,7 @@
RESET_WAVES
};
-struct cik_sdma_rlc_registers;
+struct vi_sdma_mqd;
/*
* Register access functions
@@ -64,7 +64,14 @@
uint32_t queue_id, uint32_t __user *wptr,
uint32_t wptr_shift, uint32_t wptr_mask,
struct mm_struct *mm);
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
+static int kgd_hqd_dump(struct kgd_dev *kgd,
+ uint32_t pipe_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs);
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ uint32_t __user *wptr, struct mm_struct *mm);
+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ uint32_t engine_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs);
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
@@ -125,17 +132,19 @@
static const struct kfd2kgd_calls kfd2kgd = {
.init_gtt_mem_allocation = alloc_gtt_mem,
.free_gtt_mem = free_gtt_mem,
- .get_vmem_size = get_vmem_size,
+ .get_local_mem_info = get_local_mem_info,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
- .alloc_pasid = amdgpu_vm_alloc_pasid,
- .free_pasid = amdgpu_vm_free_pasid,
+ .alloc_pasid = amdgpu_pasid_alloc,
+ .free_pasid = amdgpu_pasid_free,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
.init_interrupts = kgd_init_interrupts,
.hqd_load = kgd_hqd_load,
.hqd_sdma_load = kgd_hqd_sdma_load,
+ .hqd_dump = kgd_hqd_dump,
+ .hqd_sdma_dump = kgd_hqd_sdma_dump,
.hqd_is_occupied = kgd_hqd_is_occupied,
.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
.hqd_destroy = kgd_hqd_destroy,
@@ -152,6 +161,8 @@
.get_fw_version = get_fw_version,
.set_scratch_backing_va = set_scratch_backing_va,
.get_tile_config = get_tile_config,
+ .get_cu_info = get_cu_info,
+ .get_vram_usage = amdgpu_amdkfd_get_vram_usage
};
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
@@ -268,9 +279,15 @@
return 0;
}
-static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
+static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
{
- return 0;
+ uint32_t retval;
+
+ retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
+ m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
+ pr_debug("kfd: sdma base address: 0x%x\n", retval);
+
+ return retval;
}
static inline struct vi_mqd *get_mqd(void *mqd)
@@ -278,9 +295,9 @@
return (struct vi_mqd *)mqd;
}
-static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
+static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
{
- return (struct cik_sdma_rlc_registers *)mqd;
+ return (struct vi_sdma_mqd *)mqd;
}
static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
@@ -358,8 +375,138 @@
return 0;
}
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
+static int kgd_hqd_dump(struct kgd_dev *kgd,
+ uint32_t pipe_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs)
{
+ struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ uint32_t i = 0, reg;
+#define HQD_N_REGS (54+4)
+#define DUMP_REG(addr) do { \
+ if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
+ break; \
+ (*dump)[i][0] = (addr) << 2; \
+ (*dump)[i++][1] = RREG32(addr); \
+ } while (0)
+
+ *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
+ if (*dump == NULL)
+ return -ENOMEM;
+
+ acquire_queue(kgd, pipe_id, queue_id);
+
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
+ DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
+
+ for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
+ DUMP_REG(reg);
+
+ release_queue(kgd);
+
+ WARN_ON_ONCE(i != HQD_N_REGS);
+ *n_regs = i;
+
+ return 0;
+}
+
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ uint32_t __user *wptr, struct mm_struct *mm)
+{
+ struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ struct vi_sdma_mqd *m;
+ unsigned long end_jiffies;
+ uint32_t sdma_base_addr;
+ uint32_t data;
+
+ m = get_sdma_mqd(mqd);
+ sdma_base_addr = get_sdma_base_addr(m);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+
+ end_jiffies = msecs_to_jiffies(2000) + jiffies;
+ while (true) {
+ data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ break;
+ if (time_after(jiffies, end_jiffies))
+ return -ETIME;
+ usleep_range(500, 1000);
+ }
+ if (m->sdma_engine_id) {
+ data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
+ data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
+ RESUME_CTX, 0);
+ WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
+ } else {
+ data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
+ data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+ RESUME_CTX, 0);
+ WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
+ }
+
+ data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+ ENABLE, 1);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+
+ if (read_user_wptr(mm, wptr, data))
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
+ else
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+ m->sdmax_rlcx_rb_rptr);
+
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
+ m->sdmax_rlcx_virtual_addr);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+ m->sdmax_rlcx_rb_base_hi);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+ m->sdmax_rlcx_rb_rptr_addr_lo);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+ m->sdmax_rlcx_rb_rptr_addr_hi);
+
+ data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ RB_ENABLE, 1);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+
+ return 0;
+}
+
+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ uint32_t engine_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs)
+{
+ struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
+ queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
+ uint32_t i = 0, reg;
+#undef HQD_N_REGS
+#define HQD_N_REGS (19+4+2+3+7)
+
+ *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
+ if (*dump == NULL)
+ return -ENOMEM;
+
+ for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
+ DUMP_REG(sdma_offset + reg);
+ for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
+ reg++)
+ DUMP_REG(sdma_offset + reg);
+ for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
+ reg++)
+ DUMP_REG(sdma_offset + reg);
+ for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
+ reg++)
+ DUMP_REG(sdma_offset + reg);
+ for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
+ reg++)
+ DUMP_REG(sdma_offset + reg);
+
+ WARN_ON_ONCE(i != HQD_N_REGS);
+ *n_regs = i;
+
return 0;
}
@@ -388,7 +535,7 @@
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
- struct cik_sdma_rlc_registers *m;
+ struct vi_sdma_mqd *m;
uint32_t sdma_base_addr;
uint32_t sdma_rlc_rb_cntl;
@@ -509,10 +656,10 @@
unsigned int utimeout)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
- struct cik_sdma_rlc_registers *m;
+ struct vi_sdma_mqd *m;
uint32_t sdma_base_addr;
uint32_t temp;
- int timeout = utimeout;
+ unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
m = get_sdma_mqd(mqd);
sdma_base_addr = get_sdma_base_addr(m);
@@ -523,18 +670,19 @@
while (true) {
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
- if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
+ if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
break;
- if (timeout <= 0)
+ if (time_after(jiffies, end_jiffies))
return -ETIME;
- msleep(20);
- timeout -= 20;
+ usleep_range(500, 1000);
}
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+ SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+
+ m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 057e1ec..a5df80d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -93,7 +93,7 @@
resource_size_t size = 256 * 1024; /* ??? */
if (!(adev->flags & AMD_IS_APU))
- if (amdgpu_need_post(adev))
+ if (amdgpu_device_need_post(adev))
return false;
adev->bios = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index f2b72c7..4466f35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -801,6 +801,11 @@
else
strcpy(fw_name, "amdgpu/vega10_smc.bin");
break;
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ case CHIP_RAVEN:
+ adev->pm.fw_version = info->version;
+ return 0;
default:
DRM_ERROR("SMC firmware not supported\n");
return -EINVAL;
@@ -948,7 +953,6 @@
(amdgpu_crtc->v_border * 2);
mode_info->vblank_time_us = vblank_lines * line_time_us;
mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
- mode_info->ref_clock = adev->clock.spll.reference_freq;
mode_info = NULL;
}
}
@@ -958,7 +962,6 @@
if (mode_info != NULL) {
mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
- mode_info->ref_clock = adev->clock.spll.reference_freq;
}
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 3fdb39d..9b8a3105 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -343,7 +343,12 @@
struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- u64 initial_bytes_moved, bytes_moved;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false,
+ .allow_reserved_eviction = false,
+ .resv = bo->tbo.resv
+ };
uint32_t domain;
int r;
@@ -373,15 +378,13 @@
retry:
amdgpu_ttm_placement_from_domain(bo, domain);
- initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
- bytes_moved = atomic64_read(&adev->num_bytes_moved) -
- initial_bytes_moved;
- p->bytes_moved += bytes_moved;
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+
+ p->bytes_moved += ctx.bytes_moved;
if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
bo->tbo.mem.mem_type == TTM_PL_VRAM &&
bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
- p->bytes_moved_vis += bytes_moved;
+ p->bytes_moved_vis += ctx.bytes_moved;
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
domain = bo->allowed_domains;
@@ -396,6 +399,7 @@
struct amdgpu_bo *validated)
{
uint32_t domain = validated->allowed_domains;
+ struct ttm_operation_ctx ctx = { true, false };
int r;
if (!p->evictable)
@@ -437,7 +441,7 @@
bo->tbo.mem.mem_type == TTM_PL_VRAM &&
bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;
initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
bytes_moved = atomic64_read(&adev->num_bytes_moved) -
initial_bytes_moved;
p->bytes_moved += bytes_moved;
@@ -476,6 +480,7 @@
static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
struct list_head *validated)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct amdgpu_bo_list_entry *lobj;
int r;
@@ -493,8 +498,7 @@
lobj->user_pages) {
amdgpu_ttm_placement_from_domain(bo,
AMDGPU_GEM_DOMAIN_CPU);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true,
- false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r)
return r;
amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
@@ -685,7 +689,7 @@
if (!r && p->uf_entry.robj) {
struct amdgpu_bo *uf = p->uf_entry.robj;
- r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
+ r = amdgpu_ttm_alloc_gart(&uf->tbo);
p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
}
@@ -776,10 +780,6 @@
struct amdgpu_bo *bo;
int i, r;
- r = amdgpu_vm_update_directories(adev, vm);
- if (r)
- return r;
-
r = amdgpu_vm_clear_freed(adev, vm, NULL);
if (r)
return r;
@@ -789,7 +789,7 @@
return r;
r = amdgpu_sync_fence(adev, &p->job->sync,
- fpriv->prt_va->last_pt_update);
+ fpriv->prt_va->last_pt_update, false);
if (r)
return r;
@@ -803,7 +803,7 @@
return r;
f = bo_va->last_pt_update;
- r = amdgpu_sync_fence(adev, &p->job->sync, f);
+ r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
if (r)
return r;
}
@@ -826,7 +826,7 @@
return r;
f = bo_va->last_pt_update;
- r = amdgpu_sync_fence(adev, &p->job->sync, f);
+ r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
if (r)
return r;
}
@@ -837,7 +837,11 @@
if (r)
return r;
- r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);
+ r = amdgpu_vm_update_directories(adev, vm);
+ if (r)
+ return r;
+
+ r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
if (r)
return r;
@@ -1041,8 +1045,8 @@
amdgpu_ctx_put(ctx);
return r;
} else if (fence) {
- r = amdgpu_sync_fence(p->adev, &p->job->sync,
- fence);
+ r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
+ true);
dma_fence_put(fence);
amdgpu_ctx_put(ctx);
if (r)
@@ -1061,7 +1065,7 @@
if (r)
return r;
- r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
+ r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
dma_fence_put(fence);
return r;
@@ -1153,7 +1157,7 @@
union drm_amdgpu_cs *cs)
{
struct amdgpu_ring *ring = p->job->ring;
- struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
+ struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
struct amdgpu_job *job;
unsigned i;
uint64_t seq;
@@ -1176,7 +1180,7 @@
job = p->job;
p->job = NULL;
- r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
+ r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp);
if (r) {
amdgpu_job_free(job);
amdgpu_mn_unlock(p->mn);
@@ -1205,7 +1209,7 @@
amdgpu_ring_priority_get(job->ring, job->base.s_priority);
trace_amdgpu_cs_ioctl(job);
- amd_sched_entity_push_job(&job->base, entity);
+ drm_sched_entity_push_job(&job->base, entity);
ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
amdgpu_mn_unlock(p->mn);
@@ -1577,6 +1581,7 @@
struct amdgpu_bo_va_mapping **map)
{
struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
+ struct ttm_operation_ctx ctx = { false, false };
struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_va_mapping *mapping;
int r;
@@ -1597,11 +1602,10 @@
if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
- r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,
- false);
+ r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
if (r)
return r;
}
- return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem);
+ return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index d71dc16..09d35051 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -28,10 +28,10 @@
#include "amdgpu_sched.h"
static int amdgpu_ctx_priority_permit(struct drm_file *filp,
- enum amd_sched_priority priority)
+ enum drm_sched_priority priority)
{
/* NORMAL and below are accessible by everyone */
- if (priority <= AMD_SCHED_PRIORITY_NORMAL)
+ if (priority <= DRM_SCHED_PRIORITY_NORMAL)
return 0;
if (capable(CAP_SYS_NICE))
@@ -44,14 +44,14 @@
}
static int amdgpu_ctx_init(struct amdgpu_device *adev,
- enum amd_sched_priority priority,
+ enum drm_sched_priority priority,
struct drm_file *filp,
struct amdgpu_ctx *ctx)
{
unsigned i, j;
int r;
- if (priority < 0 || priority >= AMD_SCHED_PRIORITY_MAX)
+ if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
return -EINVAL;
r = amdgpu_ctx_priority_permit(filp, priority);
@@ -78,19 +78,19 @@
ctx->reset_counter_query = ctx->reset_counter;
ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
ctx->init_priority = priority;
- ctx->override_priority = AMD_SCHED_PRIORITY_UNSET;
+ ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
/* create context entity for each ring */
for (i = 0; i < adev->num_rings; i++) {
struct amdgpu_ring *ring = adev->rings[i];
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
rq = &ring->sched.sched_rq[priority];
if (ring == &adev->gfx.kiq.ring)
continue;
- r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
+ r = drm_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
rq, amdgpu_sched_jobs, &ctx->guilty);
if (r)
goto failed;
@@ -104,7 +104,7 @@
failed:
for (j = 0; j < i; j++)
- amd_sched_entity_fini(&adev->rings[j]->sched,
+ drm_sched_entity_fini(&adev->rings[j]->sched,
&ctx->rings[j].entity);
kfree(ctx->fences);
ctx->fences = NULL;
@@ -126,7 +126,7 @@
ctx->fences = NULL;
for (i = 0; i < adev->num_rings; i++)
- amd_sched_entity_fini(&adev->rings[i]->sched,
+ drm_sched_entity_fini(&adev->rings[i]->sched,
&ctx->rings[i].entity);
amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
@@ -137,7 +137,7 @@
static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
struct drm_file *filp,
- enum amd_sched_priority priority,
+ enum drm_sched_priority priority,
uint32_t *id)
{
struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
@@ -266,7 +266,7 @@
{
int r;
uint32_t id;
- enum amd_sched_priority priority;
+ enum drm_sched_priority priority;
union drm_amdgpu_ctx *args = data;
struct amdgpu_device *adev = dev->dev_private;
@@ -278,8 +278,8 @@
/* For backwards compatibility reasons, we need to accept
* ioctls with garbage in the priority field */
- if (priority == AMD_SCHED_PRIORITY_INVALID)
- priority = AMD_SCHED_PRIORITY_NORMAL;
+ if (priority == DRM_SCHED_PRIORITY_INVALID)
+ priority = DRM_SCHED_PRIORITY_NORMAL;
switch (args->in.op) {
case AMDGPU_CTX_OP_ALLOC_CTX:
@@ -385,18 +385,18 @@
}
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
- enum amd_sched_priority priority)
+ enum drm_sched_priority priority)
{
int i;
struct amdgpu_device *adev = ctx->adev;
- struct amd_sched_rq *rq;
- struct amd_sched_entity *entity;
+ struct drm_sched_rq *rq;
+ struct drm_sched_entity *entity;
struct amdgpu_ring *ring;
- enum amd_sched_priority ctx_prio;
+ enum drm_sched_priority ctx_prio;
ctx->override_priority = priority;
- ctx_prio = (ctx->override_priority == AMD_SCHED_PRIORITY_UNSET) ?
+ ctx_prio = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ?
ctx->init_priority : ctx->override_priority;
for (i = 0; i < adev->num_rings; i++) {
@@ -407,7 +407,7 @@
if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
continue;
- amd_sched_entity_set_rq(entity, rq);
+ drm_sched_entity_set_rq(entity, rq);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
new file mode 100644
index 0000000..ee76b46
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -0,0 +1,792 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/kthread.h>
+#include <drm/drmP.h>
+#include <linux/debugfs.h>
+#include "amdgpu.h"
+
+/*
+ * Debugfs
+ */
+int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
+ const struct drm_info_list *files,
+ unsigned nfiles)
+{
+ unsigned i;
+
+ for (i = 0; i < adev->debugfs_count; i++) {
+ if (adev->debugfs[i].files == files) {
+ /* Already registered */
+ return 0;
+ }
+ }
+
+ i = adev->debugfs_count + 1;
+ if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
+ DRM_ERROR("Reached maximum number of debugfs components.\n");
+ DRM_ERROR("Report so we increase "
+ "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
+ return -EINVAL;
+ }
+ adev->debugfs[adev->debugfs_count].files = files;
+ adev->debugfs[adev->debugfs_count].num_files = nfiles;
+ adev->debugfs_count = i;
+#if defined(CONFIG_DEBUG_FS)
+ drm_debugfs_create_files(files, nfiles,
+ adev->ddev->primary->debugfs_root,
+ adev->ddev->primary);
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_DEBUG_FS)
+
+static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+ bool pm_pg_lock, use_bank;
+ unsigned instance_bank, sh_bank, se_bank;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ /* are we reading registers for which a PG lock is necessary? */
+ pm_pg_lock = (*pos >> 23) & 1;
+
+ if (*pos & (1ULL << 62)) {
+ se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
+ sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
+ instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
+
+ if (se_bank == 0x3FF)
+ se_bank = 0xFFFFFFFF;
+ if (sh_bank == 0x3FF)
+ sh_bank = 0xFFFFFFFF;
+ if (instance_bank == 0x3FF)
+ instance_bank = 0xFFFFFFFF;
+ use_bank = 1;
+ } else {
+ use_bank = 0;
+ }
+
+ *pos &= (1UL << 22) - 1;
+
+ if (use_bank) {
+ if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
+ (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
+ return -EINVAL;
+ mutex_lock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_select_se_sh(adev, se_bank,
+ sh_bank, instance_bank);
+ }
+
+ if (pm_pg_lock)
+ mutex_lock(&adev->pm.mutex);
+
+ while (size) {
+ uint32_t value;
+
+ if (*pos > adev->rmmio_size)
+ goto end;
+
+ value = RREG32(*pos >> 2);
+ r = put_user(value, (uint32_t *)buf);
+ if (r) {
+ result = r;
+ goto end;
+ }
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+end:
+ if (use_bank) {
+ amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+ mutex_unlock(&adev->grbm_idx_mutex);
+ }
+
+ if (pm_pg_lock)
+ mutex_unlock(&adev->pm.mutex);
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+ bool pm_pg_lock, use_bank;
+ unsigned instance_bank, sh_bank, se_bank;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ /* are we reading registers for which a PG lock is necessary? */
+ pm_pg_lock = (*pos >> 23) & 1;
+
+ if (*pos & (1ULL << 62)) {
+ se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
+ sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
+ instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
+
+ if (se_bank == 0x3FF)
+ se_bank = 0xFFFFFFFF;
+ if (sh_bank == 0x3FF)
+ sh_bank = 0xFFFFFFFF;
+ if (instance_bank == 0x3FF)
+ instance_bank = 0xFFFFFFFF;
+ use_bank = 1;
+ } else {
+ use_bank = 0;
+ }
+
+ *pos &= (1UL << 22) - 1;
+
+ if (use_bank) {
+ if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
+ (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
+ return -EINVAL;
+ mutex_lock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_select_se_sh(adev, se_bank,
+ sh_bank, instance_bank);
+ }
+
+ if (pm_pg_lock)
+ mutex_lock(&adev->pm.mutex);
+
+ while (size) {
+ uint32_t value;
+
+ if (*pos > adev->rmmio_size)
+ return result;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32(*pos >> 2, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ if (use_bank) {
+ amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+ mutex_unlock(&adev->grbm_idx_mutex);
+ }
+
+ if (pm_pg_lock)
+ mutex_unlock(&adev->pm.mutex);
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ value = RREG32_PCIE(*pos >> 2);
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32_PCIE(*pos >> 2, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ value = RREG32_DIDT(*pos >> 2);
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32_DIDT(*pos >> 2, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ value = RREG32_SMC(*pos);
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32_SMC(*pos, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+ uint32_t *config, no_regs = 0;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
+ if (!config)
+ return -ENOMEM;
+
+ /* version, increment each time something is added */
+ config[no_regs++] = 3;
+ config[no_regs++] = adev->gfx.config.max_shader_engines;
+ config[no_regs++] = adev->gfx.config.max_tile_pipes;
+ config[no_regs++] = adev->gfx.config.max_cu_per_sh;
+ config[no_regs++] = adev->gfx.config.max_sh_per_se;
+ config[no_regs++] = adev->gfx.config.max_backends_per_se;
+ config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
+ config[no_regs++] = adev->gfx.config.max_gprs;
+ config[no_regs++] = adev->gfx.config.max_gs_threads;
+ config[no_regs++] = adev->gfx.config.max_hw_contexts;
+ config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
+ config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
+ config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
+ config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
+ config[no_regs++] = adev->gfx.config.num_tile_pipes;
+ config[no_regs++] = adev->gfx.config.backend_enable_mask;
+ config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
+ config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
+ config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
+ config[no_regs++] = adev->gfx.config.num_gpus;
+ config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
+ config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
+ config[no_regs++] = adev->gfx.config.gb_addr_config;
+ config[no_regs++] = adev->gfx.config.num_rbs;
+
+ /* rev==1 */
+ config[no_regs++] = adev->rev_id;
+ config[no_regs++] = adev->pg_flags;
+ config[no_regs++] = adev->cg_flags;
+
+ /* rev==2 */
+ config[no_regs++] = adev->family;
+ config[no_regs++] = adev->external_rev_id;
+
+ /* rev==3 */
+ config[no_regs++] = adev->pdev->device;
+ config[no_regs++] = adev->pdev->revision;
+ config[no_regs++] = adev->pdev->subsystem_device;
+ config[no_regs++] = adev->pdev->subsystem_vendor;
+
+ while (size && (*pos < no_regs * 4)) {
+ uint32_t value;
+
+ value = config[*pos >> 2];
+ r = put_user(value, (uint32_t *)buf);
+ if (r) {
+ kfree(config);
+ return r;
+ }
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ kfree(config);
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ int idx, x, outsize, r, valuesize;
+ uint32_t values[16];
+
+ if (size & 3 || *pos & 0x3)
+ return -EINVAL;
+
+ if (amdgpu_dpm == 0)
+ return -EINVAL;
+
+ /* convert offset to sensor number */
+ idx = *pos >> 2;
+
+ valuesize = sizeof(values);
+ if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
+ r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
+ else
+ return -EINVAL;
+
+ if (size > valuesize)
+ return -EINVAL;
+
+ outsize = 0;
+ x = 0;
+ if (!r) {
+ while (size) {
+ r = put_user(values[x++], (int32_t *)buf);
+ buf += 4;
+ size -= 4;
+ outsize += 4;
+ }
+ }
+
+ return !r ? outsize : r;
+}
+
+static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ int r, x;
+ ssize_t result=0;
+ uint32_t offset, se, sh, cu, wave, simd, data[32];
+
+ if (size & 3 || *pos & 3)
+ return -EINVAL;
+
+ /* decode offset */
+ offset = (*pos & GENMASK_ULL(6, 0));
+ se = (*pos & GENMASK_ULL(14, 7)) >> 7;
+ sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
+ cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
+ wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
+ simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
+
+ /* switch to the specific se/sh/cu */
+ mutex_lock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_select_se_sh(adev, se, sh, cu);
+
+ x = 0;
+ if (adev->gfx.funcs->read_wave_data)
+ adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
+
+ amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
+ mutex_unlock(&adev->grbm_idx_mutex);
+
+ if (!x)
+ return -EINVAL;
+
+ while (size && (offset < x * 4)) {
+ uint32_t value;
+
+ value = data[offset >> 2];
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ offset += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ int r;
+ ssize_t result = 0;
+ uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
+
+ if (size & 3 || *pos & 3)
+ return -EINVAL;
+
+ /* decode offset */
+ offset = *pos & GENMASK_ULL(11, 0);
+ se = (*pos & GENMASK_ULL(19, 12)) >> 12;
+ sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
+ cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
+ wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
+ simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
+ thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
+ bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
+
+ data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ /* switch to the specific se/sh/cu */
+ mutex_lock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_select_se_sh(adev, se, sh, cu);
+
+ if (bank == 0) {
+ if (adev->gfx.funcs->read_wave_vgprs)
+ adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
+ } else {
+ if (adev->gfx.funcs->read_wave_sgprs)
+ adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
+ }
+
+ amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
+ mutex_unlock(&adev->grbm_idx_mutex);
+
+ while (size) {
+ uint32_t value;
+
+ value = data[offset++];
+ r = put_user(value, (uint32_t *)buf);
+ if (r) {
+ result = r;
+ goto err;
+ }
+
+ result += 4;
+ buf += 4;
+ size -= 4;
+ }
+
+err:
+ kfree(data);
+ return result;
+}
+
+static const struct file_operations amdgpu_debugfs_regs_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_read,
+ .write = amdgpu_debugfs_regs_write,
+ .llseek = default_llseek
+};
+static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_didt_read,
+ .write = amdgpu_debugfs_regs_didt_write,
+ .llseek = default_llseek
+};
+static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_pcie_read,
+ .write = amdgpu_debugfs_regs_pcie_write,
+ .llseek = default_llseek
+};
+static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_smc_read,
+ .write = amdgpu_debugfs_regs_smc_write,
+ .llseek = default_llseek
+};
+
+static const struct file_operations amdgpu_debugfs_gca_config_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_gca_config_read,
+ .llseek = default_llseek
+};
+
+static const struct file_operations amdgpu_debugfs_sensors_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_sensor_read,
+ .llseek = default_llseek
+};
+
+static const struct file_operations amdgpu_debugfs_wave_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_wave_read,
+ .llseek = default_llseek
+};
+static const struct file_operations amdgpu_debugfs_gpr_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_gpr_read,
+ .llseek = default_llseek
+};
+
+static const struct file_operations *debugfs_regs[] = {
+ &amdgpu_debugfs_regs_fops,
+ &amdgpu_debugfs_regs_didt_fops,
+ &amdgpu_debugfs_regs_pcie_fops,
+ &amdgpu_debugfs_regs_smc_fops,
+ &amdgpu_debugfs_gca_config_fops,
+ &amdgpu_debugfs_sensors_fops,
+ &amdgpu_debugfs_wave_fops,
+ &amdgpu_debugfs_gpr_fops,
+};
+
+static const char *debugfs_regs_names[] = {
+ "amdgpu_regs",
+ "amdgpu_regs_didt",
+ "amdgpu_regs_pcie",
+ "amdgpu_regs_smc",
+ "amdgpu_gca_config",
+ "amdgpu_sensors",
+ "amdgpu_wave",
+ "amdgpu_gpr",
+};
+
+int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
+{
+ struct drm_minor *minor = adev->ddev->primary;
+ struct dentry *ent, *root = minor->debugfs_root;
+ unsigned i, j;
+
+ for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
+ ent = debugfs_create_file(debugfs_regs_names[i],
+ S_IFREG | S_IRUGO, root,
+ adev, debugfs_regs[i]);
+ if (IS_ERR(ent)) {
+ for (j = 0; j < i; j++) {
+ debugfs_remove(adev->debugfs_regs[i]);
+ adev->debugfs_regs[i] = NULL;
+ }
+ return PTR_ERR(ent);
+ }
+
+ if (!i)
+ i_size_write(ent->d_inode, adev->rmmio_size);
+ adev->debugfs_regs[i] = ent;
+ }
+
+ return 0;
+}
+
+void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
+ if (adev->debugfs_regs[i]) {
+ debugfs_remove(adev->debugfs_regs[i]);
+ adev->debugfs_regs[i] = NULL;
+ }
+ }
+}
+
+static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+ int r = 0, i;
+
+ /* hold on the scheduler */
+ for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+ struct amdgpu_ring *ring = adev->rings[i];
+
+ if (!ring || !ring->sched.thread)
+ continue;
+ kthread_park(ring->sched.thread);
+ }
+
+ seq_printf(m, "run ib test:\n");
+ r = amdgpu_ib_ring_tests(adev);
+ if (r)
+ seq_printf(m, "ib ring tests failed (%d).\n", r);
+ else
+ seq_printf(m, "ib ring tests passed.\n");
+
+ /* go on the scheduler */
+ for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+ struct amdgpu_ring *ring = adev->rings[i];
+
+ if (!ring || !ring->sched.thread)
+ continue;
+ kthread_unpark(ring->sched.thread);
+ }
+
+ return 0;
+}
+
+static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+
+ seq_write(m, adev->bios, adev->bios_size);
+ return 0;
+}
+
+static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *)m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+
+ seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
+ return 0;
+}
+
+static const struct drm_info_list amdgpu_debugfs_list[] = {
+ {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump},
+ {"amdgpu_test_ib", &amdgpu_debugfs_test_ib},
+ {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram}
+};
+
+int amdgpu_debugfs_init(struct amdgpu_device *adev)
+{
+ return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
+ ARRAY_SIZE(amdgpu_debugfs_list));
+}
+
+#else
+int amdgpu_debugfs_init(struct amdgpu_device *adev)
+{
+ return 0;
+}
+int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
+{
+ return 0;
+}
+void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h
new file mode 100644
index 0000000..8260d80
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Debugfs
+ */
+struct amdgpu_debugfs {
+ const struct drm_info_list *files;
+ unsigned num_files;
+};
+
+int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
+void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
+int amdgpu_debugfs_init(struct amdgpu_device *adev);
+int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
+ const struct drm_info_list *files,
+ unsigned nfiles);
+int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
+int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
+int amdgpu_debugfs_gem_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 50573dd..0400d44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -28,7 +28,6 @@
#include <linux/kthread.h>
#include <linux/console.h>
#include <linux/slab.h>
-#include <linux/debugfs.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_atomic_helper.h>
@@ -64,11 +63,6 @@
#define AMDGPU_RESUME_MS 2000
-static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
-static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
-static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
-static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
-
static const char *amdgpu_asic_name[] = {
"TAHITI",
"PITCAIRN",
@@ -333,7 +327,7 @@
BUG();
}
-static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
+static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
{
return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
@@ -342,13 +336,13 @@
(void **)&adev->vram_scratch.ptr);
}
-static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
+static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
{
amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
}
/**
- * amdgpu_program_register_sequence - program an array of registers.
+ * amdgpu_device_program_register_sequence - program an array of registers.
*
* @adev: amdgpu_device pointer
* @registers: pointer to the register array
@@ -357,9 +351,9 @@
* Programs an array or registers with and and or masks.
* This is a helper for setting golden registers.
*/
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
- const u32 *registers,
- const u32 array_size)
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+ const u32 *registers,
+ const u32 array_size)
{
u32 tmp, reg, and_mask, or_mask;
int i;
@@ -383,7 +377,7 @@
}
}
-void amdgpu_pci_config_reset(struct amdgpu_device *adev)
+void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
{
pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
}
@@ -392,14 +386,14 @@
* GPU doorbell aperture helpers function.
*/
/**
- * amdgpu_doorbell_init - Init doorbell driver information.
+ * amdgpu_device_doorbell_init - Init doorbell driver information.
*
* @adev: amdgpu_device pointer
*
* Init doorbell driver information (CIK)
* Returns 0 on success, error on failure.
*/
-static int amdgpu_doorbell_init(struct amdgpu_device *adev)
+static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
{
/* No doorbell on SI hardware generation */
if (adev->asic_type < CHIP_BONAIRE) {
@@ -410,6 +404,9 @@
return 0;
}
+ if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
+ return -EINVAL;
+
/* doorbell bar mapping */
adev->doorbell.base = pci_resource_start(adev->pdev, 2);
adev->doorbell.size = pci_resource_len(adev->pdev, 2);
@@ -429,66 +426,35 @@
}
/**
- * amdgpu_doorbell_fini - Tear down doorbell driver information.
+ * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
*
* @adev: amdgpu_device pointer
*
* Tear down doorbell driver information (CIK)
*/
-static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
+static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
{
iounmap(adev->doorbell.ptr);
adev->doorbell.ptr = NULL;
}
-/**
- * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
- * setup amdkfd
- *
- * @adev: amdgpu_device pointer
- * @aperture_base: output returning doorbell aperture base physical address
- * @aperture_size: output returning doorbell aperture size in bytes
- * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
- *
- * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
- * takes doorbells required for its own rings and reports the setup to amdkfd.
- * amdgpu reserved doorbells are at the start of the doorbell aperture.
- */
-void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
- phys_addr_t *aperture_base,
- size_t *aperture_size,
- size_t *start_offset)
-{
- /*
- * The first num_doorbells are used by amdgpu.
- * amdkfd takes whatever's left in the aperture.
- */
- if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
- *aperture_base = adev->doorbell.base;
- *aperture_size = adev->doorbell.size;
- *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
- } else {
- *aperture_base = 0;
- *aperture_size = 0;
- *start_offset = 0;
- }
-}
+
/*
- * amdgpu_wb_*()
+ * amdgpu_device_wb_*()
* Writeback is the method by which the GPU updates special pages in memory
* with the status of certain GPU events (fences, ring pointers,etc.).
*/
/**
- * amdgpu_wb_fini - Disable Writeback and free memory
+ * amdgpu_device_wb_fini - Disable Writeback and free memory
*
* @adev: amdgpu_device pointer
*
* Disables Writeback and frees the Writeback memory (all asics).
* Used at driver shutdown.
*/
-static void amdgpu_wb_fini(struct amdgpu_device *adev)
+static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
{
if (adev->wb.wb_obj) {
amdgpu_bo_free_kernel(&adev->wb.wb_obj,
@@ -499,7 +465,7 @@
}
/**
- * amdgpu_wb_init- Init Writeback driver info and allocate memory
+ * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
*
* @adev: amdgpu_device pointer
*
@@ -507,7 +473,7 @@
* Used at driver startup.
* Returns 0 on success or an -error on failure.
*/
-static int amdgpu_wb_init(struct amdgpu_device *adev)
+static int amdgpu_device_wb_init(struct amdgpu_device *adev)
{
int r;
@@ -526,7 +492,7 @@
memset(&adev->wb.used, 0, sizeof(adev->wb.used));
/* clear wb memory */
- memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
+ memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
}
return 0;
@@ -564,52 +530,26 @@
*/
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
{
+ wb >>= 3;
if (wb < adev->wb.num_wb)
- __clear_bit(wb >> 3, adev->wb.used);
+ __clear_bit(wb, adev->wb.used);
}
/**
- * amdgpu_vram_location - try to find VRAM location
+ * amdgpu_device_vram_location - try to find VRAM location
* @adev: amdgpu device structure holding all necessary informations
* @mc: memory controller structure holding memory informations
* @base: base address at which to put VRAM
*
* Function will try to place VRAM at base address provided
- * as parameter (which is so far either PCI aperture address or
- * for IGP TOM base address).
- *
- * If there is not enough space to fit the unvisible VRAM in the 32bits
- * address space then we limit the VRAM size to the aperture.
- *
- * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
- * this shouldn't be a problem as we are using the PCI aperture as a reference.
- * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
- * not IGP.
- *
- * Note: we use mc_vram_size as on some board we need to program the mc to
- * cover the whole aperture even if VRAM size is inferior to aperture size
- * Novell bug 204882 + along with lots of ubuntu ones
- *
- * Note: when limiting vram it's safe to overwritte real_vram_size because
- * we are not in case where real_vram_size is inferior to mc_vram_size (ie
- * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
- * ones)
- *
- * Note: IGP TOM addr should be the same as the aperture addr, we don't
- * explicitly check for that though.
- *
- * FIXME: when reducing VRAM size align new size on power of 2.
+ * as parameter.
*/
-void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
+void amdgpu_device_vram_location(struct amdgpu_device *adev,
+ struct amdgpu_mc *mc, u64 base)
{
uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
mc->vram_start = base;
- if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
- dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
- mc->real_vram_size = mc->aper_size;
- mc->mc_vram_size = mc->aper_size;
- }
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
if (limit && limit < mc->real_vram_size)
mc->real_vram_size = limit;
@@ -619,7 +559,7 @@
}
/**
- * amdgpu_gart_location - try to find GTT location
+ * amdgpu_device_gart_location - try to find GTT location
* @adev: amdgpu device structure holding all necessary informations
* @mc: memory controller structure holding memory informations
*
@@ -630,7 +570,8 @@
*
* FIXME: when reducing GTT size align new size on power of 2.
*/
-void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
+void amdgpu_device_gart_location(struct amdgpu_device *adev,
+ struct amdgpu_mc *mc)
{
u64 size_af, size_bf;
@@ -647,93 +588,91 @@
dev_warn(adev->dev, "limiting GTT\n");
mc->gart_size = size_af;
}
- mc->gart_start = mc->vram_end + 1;
+ /* VCE doesn't like it when BOs cross a 4GB segment, so align
+ * the GART base on a 4GB boundary as well.
+ */
+ mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
}
mc->gart_end = mc->gart_start + mc->gart_size - 1;
dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
}
-/*
- * Firmware Reservation functions
- */
/**
- * amdgpu_fw_reserve_vram_fini - free fw reserved vram
+ * amdgpu_device_resize_fb_bar - try to resize FB BAR
*
* @adev: amdgpu_device pointer
*
- * free fw reserved vram if it has been reserved.
+ * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
+ * to fail, but if any of the BARs is not accessible after the size we abort
+ * driver loading by returning -ENODEV.
*/
-void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
+int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
{
- amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
- NULL, &adev->fw_vram_usage.va);
-}
+ u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
+ u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
+ struct pci_bus *root;
+ struct resource *res;
+ unsigned i;
+ u16 cmd;
+ int r;
-/**
- * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
- *
- * @adev: amdgpu_device pointer
- *
- * create bo vram reservation from fw.
- */
-int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
-{
- int r = 0;
- u64 gpu_addr;
- u64 vram_size = adev->mc.visible_vram_size;
+ /* Bypass for VF */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
- adev->fw_vram_usage.va = NULL;
- adev->fw_vram_usage.reserved_bo = NULL;
+ /* Check if the root BUS has 64bit memory resources */
+ root = adev->pdev->bus;
+ while (root->parent)
+ root = root->parent;
- if (adev->fw_vram_usage.size > 0 &&
- adev->fw_vram_usage.size <= vram_size) {
-
- r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
- PAGE_SIZE, true, 0,
- AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
- &adev->fw_vram_usage.reserved_bo);
- if (r)
- goto error_create;
-
- r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
- if (r)
- goto error_reserve;
- r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
- AMDGPU_GEM_DOMAIN_VRAM,
- adev->fw_vram_usage.start_offset,
- (adev->fw_vram_usage.start_offset +
- adev->fw_vram_usage.size), &gpu_addr);
- if (r)
- goto error_pin;
- r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
- &adev->fw_vram_usage.va);
- if (r)
- goto error_kmap;
-
- amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+ pci_bus_for_each_resource(root, res, i) {
+ if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
+ res->start > 0x100000000ull)
+ break;
}
- return r;
-error_kmap:
- amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
-error_pin:
- amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
-error_reserve:
- amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
-error_create:
- adev->fw_vram_usage.va = NULL;
- adev->fw_vram_usage.reserved_bo = NULL;
- return r;
+ /* Trying to resize is pointless without a root hub window above 4GB */
+ if (!res)
+ return 0;
+
+ /* Disable memory decoding while we change the BAR addresses and size */
+ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
+ pci_write_config_word(adev->pdev, PCI_COMMAND,
+ cmd & ~PCI_COMMAND_MEMORY);
+
+ /* Free the VRAM and doorbell BAR, we most likely need to move both. */
+ amdgpu_device_doorbell_fini(adev);
+ if (adev->asic_type >= CHIP_BONAIRE)
+ pci_release_resource(adev->pdev, 2);
+
+ pci_release_resource(adev->pdev, 0);
+
+ r = pci_resize_resource(adev->pdev, 0, rbar_size);
+ if (r == -ENOSPC)
+ DRM_INFO("Not enough PCI address space for a large BAR.");
+ else if (r && r != -ENOTSUPP)
+ DRM_ERROR("Problem resizing BAR0 (%d).", r);
+
+ pci_assign_unassigned_bus_resources(adev->pdev->bus);
+
+ /* When the doorbell or fb BAR isn't available we have no chance of
+ * using the device.
+ */
+ r = amdgpu_device_doorbell_init(adev);
+ if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
+ return -ENODEV;
+
+ pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
+
+ return 0;
}
-
/*
* GPU helpers function.
*/
/**
- * amdgpu_need_post - check if the hw need post or not
+ * amdgpu_device_need_post - check if the hw need post or not
*
* @adev: amdgpu_device pointer
*
@@ -741,7 +680,7 @@
* or post is needed if hw reset is performed.
* Returns true if need or false if not.
*/
-bool amdgpu_need_post(struct amdgpu_device *adev)
+bool amdgpu_device_need_post(struct amdgpu_device *adev)
{
uint32_t reg;
@@ -786,54 +725,9 @@
return true;
}
-/**
- * amdgpu_dummy_page_init - init dummy page used by the driver
- *
- * @adev: amdgpu_device pointer
- *
- * Allocate the dummy page used by the driver (all asics).
- * This dummy page is used by the driver as a filler for gart entries
- * when pages are taken out of the GART
- * Returns 0 on sucess, -ENOMEM on failure.
- */
-int amdgpu_dummy_page_init(struct amdgpu_device *adev)
-{
- if (adev->dummy_page.page)
- return 0;
- adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
- if (adev->dummy_page.page == NULL)
- return -ENOMEM;
- adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
- 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
- dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
- __free_page(adev->dummy_page.page);
- adev->dummy_page.page = NULL;
- return -ENOMEM;
- }
- return 0;
-}
-
-/**
- * amdgpu_dummy_page_fini - free dummy page used by the driver
- *
- * @adev: amdgpu_device pointer
- *
- * Frees the dummy page used by the driver (all asics).
- */
-void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
-{
- if (adev->dummy_page.page == NULL)
- return;
- pci_unmap_page(adev->pdev, adev->dummy_page.addr,
- PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- __free_page(adev->dummy_page.page);
- adev->dummy_page.page = NULL;
-}
-
/* if we get transitioned to only one device, take VGA back */
/**
- * amdgpu_vga_set_decode - enable/disable vga decode
+ * amdgpu_device_vga_set_decode - enable/disable vga decode
*
* @cookie: amdgpu_device pointer
* @state: enable/disable vga decode
@@ -841,7 +735,7 @@
* Enable/disable vga decode (all asics).
* Returns VGA resource flags.
*/
-static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
+static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
{
struct amdgpu_device *adev = cookie;
amdgpu_asic_set_vga_state(adev, state);
@@ -852,7 +746,7 @@
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
-static void amdgpu_check_block_size(struct amdgpu_device *adev)
+static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
{
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
@@ -863,64 +757,32 @@
if (amdgpu_vm_block_size < 9) {
dev_warn(adev->dev, "VM page table size (%d) too small\n",
amdgpu_vm_block_size);
- goto def_value;
+ amdgpu_vm_block_size = -1;
}
-
- if (amdgpu_vm_block_size > 24 ||
- (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
- dev_warn(adev->dev, "VM page table size (%d) too large\n",
- amdgpu_vm_block_size);
- goto def_value;
- }
-
- return;
-
-def_value:
- amdgpu_vm_block_size = -1;
}
-static void amdgpu_check_vm_size(struct amdgpu_device *adev)
+static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
{
/* no need to check the default value */
if (amdgpu_vm_size == -1)
return;
- if (!is_power_of_2(amdgpu_vm_size)) {
- dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
- amdgpu_vm_size);
- goto def_value;
- }
-
if (amdgpu_vm_size < 1) {
dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
amdgpu_vm_size);
- goto def_value;
+ amdgpu_vm_size = -1;
}
-
- /*
- * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
- */
- if (amdgpu_vm_size > 1024) {
- dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
- amdgpu_vm_size);
- goto def_value;
- }
-
- return;
-
-def_value:
- amdgpu_vm_size = -1;
}
/**
- * amdgpu_check_arguments - validate module params
+ * amdgpu_device_check_arguments - validate module params
*
* @adev: amdgpu_device pointer
*
* Validates certain module parameters and updates
* the associated values used by the driver (all asics).
*/
-static void amdgpu_check_arguments(struct amdgpu_device *adev)
+static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
{
if (amdgpu_sched_jobs < 4) {
dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
@@ -953,9 +815,9 @@
amdgpu_vm_fragment_size = -1;
}
- amdgpu_check_vm_size(adev);
+ amdgpu_device_check_vm_size(adev);
- amdgpu_check_block_size(adev);
+ amdgpu_device_check_block_size(adev);
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!is_power_of_2(amdgpu_vram_page_split))) {
@@ -963,6 +825,11 @@
amdgpu_vram_page_split);
amdgpu_vram_page_split = 1024;
}
+
+ if (amdgpu_lockup_timeout == 0) {
+ dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
+ amdgpu_lockup_timeout = 10000;
+ }
}
/**
@@ -1026,9 +893,9 @@
.can_switch = amdgpu_switcheroo_can_switch,
};
-int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type,
- enum amd_clockgating_state state)
+int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type,
+ enum amd_clockgating_state state)
{
int i, r = 0;
@@ -1048,9 +915,9 @@
return r;
}
-int amdgpu_set_powergating_state(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type,
- enum amd_powergating_state state)
+int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type,
+ enum amd_powergating_state state)
{
int i, r = 0;
@@ -1070,7 +937,8 @@
return r;
}
-void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
+void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
+ u32 *flags)
{
int i;
@@ -1082,8 +950,8 @@
}
}
-int amdgpu_wait_for_idle(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type)
+int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type)
{
int i, r;
@@ -1101,8 +969,8 @@
}
-bool amdgpu_is_idle(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type)
+bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type)
{
int i;
@@ -1116,8 +984,9 @@
}
-struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
- enum amd_ip_block_type type)
+struct amdgpu_ip_block *
+amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
+ enum amd_ip_block_type type)
{
int i;
@@ -1129,7 +998,7 @@
}
/**
- * amdgpu_ip_block_version_cmp
+ * amdgpu_device_ip_block_version_cmp
*
* @adev: amdgpu_device pointer
* @type: enum amd_ip_block_type
@@ -1139,11 +1008,11 @@
* return 0 if equal or greater
* return 1 if smaller or the ip_block doesn't exist
*/
-int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
- enum amd_ip_block_type type,
- u32 major, u32 minor)
+int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
+ enum amd_ip_block_type type,
+ u32 major, u32 minor)
{
- struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
+ struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
if (ip_block && ((ip_block->version->major > major) ||
((ip_block->version->major == major) &&
@@ -1154,7 +1023,7 @@
}
/**
- * amdgpu_ip_block_add
+ * amdgpu_device_ip_block_add
*
* @adev: amdgpu_device pointer
* @ip_block_version: pointer to the IP to add
@@ -1162,8 +1031,8 @@
* Adds the IP block driver information to the collection of IPs
* on the asic.
*/
-int amdgpu_ip_block_add(struct amdgpu_device *adev,
- const struct amdgpu_ip_block_version *ip_block_version)
+int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
+ const struct amdgpu_ip_block_version *ip_block_version)
{
if (!ip_block_version)
return -EINVAL;
@@ -1319,7 +1188,7 @@
return err;
}
-static int amdgpu_early_init(struct amdgpu_device *adev)
+static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
{
int i, r;
@@ -1391,10 +1260,12 @@
if (r)
return r;
+ amdgpu_amdkfd_device_probe(adev);
+
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_request_full_gpu(adev, true);
if (r)
- return r;
+ return -EAGAIN;
}
for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1426,7 +1297,7 @@
return 0;
}
-static int amdgpu_init(struct amdgpu_device *adev)
+static int amdgpu_device_ip_init(struct amdgpu_device *adev)
{
int i, r;
@@ -1442,7 +1313,7 @@
adev->ip_blocks[i].status.sw = true;
/* need to do gmc hw init early so we can allocate gpu mem */
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
- r = amdgpu_vram_scratch_init(adev);
+ r = amdgpu_device_vram_scratch_init(adev);
if (r) {
DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
return r;
@@ -1452,9 +1323,9 @@
DRM_ERROR("hw_init %d failed %d\n", i, r);
return r;
}
- r = amdgpu_wb_init(adev);
+ r = amdgpu_device_wb_init(adev);
if (r) {
- DRM_ERROR("amdgpu_wb_init failed %d\n", r);
+ DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
return r;
}
adev->ip_blocks[i].status.hw = true;
@@ -1485,21 +1356,26 @@
adev->ip_blocks[i].status.hw = true;
}
+ amdgpu_amdkfd_device_init(adev);
+
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_release_full_gpu(adev, true);
+
return 0;
}
-static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
+static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
{
memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
}
-static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
+static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
{
return !!memcmp(adev->gart.ptr, adev->reset_magic,
AMDGPU_RESET_MAGIC_NUM);
}
-static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
+static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
{
int i = 0, r;
@@ -1526,7 +1402,7 @@
return 0;
}
-static int amdgpu_late_init(struct amdgpu_device *adev)
+static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
{
int i = 0, r;
@@ -1547,15 +1423,16 @@
queue_delayed_work(system_wq, &adev->late_init_work,
msecs_to_jiffies(AMDGPU_RESUME_MS));
- amdgpu_fill_reset_magic(adev);
+ amdgpu_device_fill_reset_magic(adev);
return 0;
}
-static int amdgpu_fini(struct amdgpu_device *adev)
+static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
{
int i, r;
+ amdgpu_amdkfd_device_fini(adev);
/* need to disable SMC first */
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.hw)
@@ -1581,12 +1458,11 @@
}
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC &&
+ adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ amdgpu_ucode_fini_bo(adev);
if (!adev->ip_blocks[i].status.hw)
continue;
- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
- amdgpu_wb_fini(adev);
- amdgpu_vram_scratch_fini(adev);
- }
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
@@ -1613,6 +1489,13 @@
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.sw)
continue;
+
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ amdgpu_free_static_csa(adev);
+ amdgpu_device_wb_fini(adev);
+ amdgpu_device_vram_scratch_fini(adev);
+ }
+
r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
/* XXX handle errors */
if (r) {
@@ -1632,19 +1515,20 @@
}
if (amdgpu_sriov_vf(adev))
- amdgpu_virt_release_full_gpu(adev, false);
+ if (amdgpu_virt_release_full_gpu(adev, false))
+ DRM_ERROR("failed to release exclusive mode on fini\n");
return 0;
}
-static void amdgpu_late_init_func_handler(struct work_struct *work)
+static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
{
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, late_init_work.work);
- amdgpu_late_set_cg_state(adev);
+ amdgpu_device_ip_late_set_cg_state(adev);
}
-int amdgpu_suspend(struct amdgpu_device *adev)
+int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
{
int i, r;
@@ -1652,10 +1536,10 @@
amdgpu_virt_request_full_gpu(adev, false);
/* ungate SMC block first */
- r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
- AMD_CG_STATE_UNGATE);
+ r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
+ AMD_CG_STATE_UNGATE);
if (r) {
- DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
+ DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
}
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
@@ -1685,7 +1569,7 @@
return 0;
}
-static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
+static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
{
int i, r;
@@ -1714,7 +1598,7 @@
return 0;
}
-static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
+static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
{
int i, r;
@@ -1747,7 +1631,7 @@
return 0;
}
-static int amdgpu_resume_phase1(struct amdgpu_device *adev)
+static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
{
int i, r;
@@ -1770,7 +1654,7 @@
return 0;
}
-static int amdgpu_resume_phase2(struct amdgpu_device *adev)
+static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
{
int i, r;
@@ -1792,14 +1676,14 @@
return 0;
}
-static int amdgpu_resume(struct amdgpu_device *adev)
+static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
{
int r;
- r = amdgpu_resume_phase1(adev);
+ r = amdgpu_device_ip_resume_phase1(adev);
if (r)
return r;
- r = amdgpu_resume_phase2(adev);
+ r = amdgpu_device_ip_resume_phase2(adev);
return r;
}
@@ -1827,6 +1711,8 @@
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
@@ -1834,12 +1720,6 @@
case CHIP_POLARIS12:
case CHIP_TONGA:
case CHIP_FIJI:
-#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
- return amdgpu_dc != 0;
-#endif
- case CHIP_KABINI:
- case CHIP_MULLINS:
- return amdgpu_dc > 0;
case CHIP_VEGA10:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
@@ -1936,8 +1816,9 @@
mutex_init(&adev->mn_lock);
mutex_init(&adev->virt.vf_errors.lock);
hash_init(adev->mn_hash);
+ mutex_init(&adev->lock_reset);
- amdgpu_check_arguments(adev);
+ amdgpu_device_check_arguments(adev);
spin_lock_init(&adev->mmio_idx_lock);
spin_lock_init(&adev->smc_idx_lock);
@@ -1952,13 +1833,11 @@
INIT_LIST_HEAD(&adev->shadow_list);
mutex_init(&adev->shadow_list_lock);
- INIT_LIST_HEAD(&adev->gtt_list);
- spin_lock_init(&adev->gtt_list_lock);
-
INIT_LIST_HEAD(&adev->ring_lru_list);
spin_lock_init(&adev->ring_lru_list_lock);
- INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
+ INIT_DELAYED_WORK(&adev->late_init_work,
+ amdgpu_device_ip_late_init_func_handler);
/* Registers mapping */
/* TODO: block userspace mapping of io register */
@@ -1978,7 +1857,7 @@
DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
/* doorbell bar mapping */
- amdgpu_doorbell_init(adev);
+ amdgpu_device_doorbell_init(adev);
/* io port mapping */
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
@@ -1992,14 +1871,14 @@
DRM_INFO("PCI I/O BAR is not found.\n");
/* early init functions */
- r = amdgpu_early_init(adev);
+ r = amdgpu_device_ip_early_init(adev);
if (r)
return r;
/* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
/* this will fail for cards that aren't VGA class devices, just
* ignore it */
- vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
+ vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
if (amdgpu_device_is_px(ddev))
runtime = true;
@@ -2026,7 +1905,7 @@
amdgpu_device_detect_sriov_bios(adev);
/* Post card if necessary */
- if (amdgpu_need_post(adev)) {
+ if (amdgpu_device_need_post(adev)) {
if (!adev->bios) {
dev_err(adev->dev, "no vBIOS found\n");
r = -EINVAL;
@@ -2072,11 +1951,23 @@
/* init the mode config */
drm_mode_config_init(adev->ddev);
- r = amdgpu_init(adev);
+ r = amdgpu_device_ip_init(adev);
if (r) {
- dev_err(adev->dev, "amdgpu_init failed\n");
+ /* failed in exclusive mode due to timeout */
+ if (amdgpu_sriov_vf(adev) &&
+ !amdgpu_sriov_runtime(adev) &&
+ amdgpu_virt_mmio_blocked(adev) &&
+ !amdgpu_virt_wait_reset(adev)) {
+ dev_err(adev->dev, "VF exclusive mode timeout\n");
+ /* Don't send request since VF is inactive. */
+ adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
+ adev->virt.ops = NULL;
+ r = -EAGAIN;
+ goto failed;
+ }
+ dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
- amdgpu_fini(adev);
+ amdgpu_device_ip_fini(adev);
goto failed;
}
@@ -2108,7 +1999,7 @@
if (r)
DRM_ERROR("registering pm debugfs failed (%d).\n", r);
- r = amdgpu_gem_debugfs_init(adev);
+ r = amdgpu_debugfs_gem_init(adev);
if (r)
DRM_ERROR("registering gem debugfs failed (%d).\n", r);
@@ -2116,17 +2007,13 @@
if (r)
DRM_ERROR("registering register debugfs failed (%d).\n", r);
- r = amdgpu_debugfs_test_ib_ring_init(adev);
- if (r)
- DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
-
r = amdgpu_debugfs_firmware_init(adev);
if (r)
DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
- r = amdgpu_debugfs_vbios_dump_init(adev);
+ r = amdgpu_debugfs_init(adev);
if (r)
- DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
+ DRM_ERROR("Creating debugfs files failed (%d).\n", r);
if ((amdgpu_testing & 1)) {
if (adev->accel_working)
@@ -2144,9 +2031,9 @@
/* enable clockgating, etc. after ib tests, etc. since some blocks require
* explicit gating rather than handling it automatically.
*/
- r = amdgpu_late_init(adev);
+ r = amdgpu_device_ip_late_init(adev);
if (r) {
- dev_err(adev->dev, "amdgpu_late_init failed\n");
+ dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
goto failed;
}
@@ -2157,6 +2044,7 @@
amdgpu_vf_error_trans_all(adev);
if (runtime)
vga_switcheroo_fini_domain_pm_ops(adev->dev);
+
return r;
}
@@ -2174,15 +2062,16 @@
DRM_INFO("amdgpu: finishing device.\n");
adev->shutdown = true;
- if (adev->mode_info.mode_config_initialized)
- drm_crtc_force_disable_all(adev->ddev);
- /* evict vram memory */
- amdgpu_bo_evict_vram(adev);
+ if (adev->mode_info.mode_config_initialized){
+ if (!amdgpu_device_has_dc_support(adev))
+ drm_crtc_force_disable_all(adev->ddev);
+ else
+ drm_atomic_helper_shutdown(adev->ddev);
+ }
amdgpu_ib_pool_fini(adev);
- amdgpu_fw_reserve_vram_fini(adev);
amdgpu_fence_driver_fini(adev);
amdgpu_fbdev_fini(adev);
- r = amdgpu_fini(adev);
+ r = amdgpu_device_ip_fini(adev);
if (adev->firmware.gpu_info_fw) {
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
@@ -2205,7 +2094,7 @@
adev->rio_mem = NULL;
iounmap(adev->rmmio);
adev->rmmio = NULL;
- amdgpu_doorbell_fini(adev);
+ amdgpu_device_doorbell_fini(adev);
amdgpu_pm_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
}
@@ -2286,7 +2175,7 @@
amdgpu_fence_driver_suspend(adev);
- r = amdgpu_suspend(adev);
+ r = amdgpu_device_ip_suspend(adev);
/* evict remaining vram memory
* This second call to evict vram is to evict the gart page table
@@ -2344,21 +2233,21 @@
}
/* post card */
- if (amdgpu_need_post(adev)) {
+ if (amdgpu_device_need_post(adev)) {
r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
if (r)
DRM_ERROR("amdgpu asic init failed\n");
}
- r = amdgpu_resume(adev);
+ r = amdgpu_device_ip_resume(adev);
if (r) {
- DRM_ERROR("amdgpu_resume failed (%d).\n", r);
+ DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
goto unlock;
}
amdgpu_fence_driver_resume(adev);
- r = amdgpu_late_init(adev);
+ r = amdgpu_device_ip_late_init(adev);
if (r)
goto unlock;
@@ -2383,6 +2272,9 @@
if (r)
return r;
+ /* Make sure IB tests flushed */
+ flush_delayed_work(&adev->late_init_work);
+
/* blat the mode back in */
if (fbcon) {
if (!amdgpu_device_has_dc_support(adev)) {
@@ -2395,14 +2287,6 @@
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
}
drm_modeset_unlock_all(dev);
- } else {
- /*
- * There is no equivalent atomic helper to turn on
- * display, so we defined our own function for this,
- * once suspend resume is supported by the atomic
- * framework this will be reworked
- */
- amdgpu_dm_display_resume(adev);
}
}
@@ -2438,7 +2322,7 @@
return r;
}
-static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
+static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
{
int i;
bool asic_hang = false;
@@ -2460,7 +2344,7 @@
return asic_hang;
}
-static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
+static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
{
int i, r = 0;
@@ -2478,7 +2362,7 @@
return 0;
}
-static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
+static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
{
int i;
@@ -2499,7 +2383,7 @@
return false;
}
-static int amdgpu_soft_reset(struct amdgpu_device *adev)
+static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
{
int i, r = 0;
@@ -2517,7 +2401,7 @@
return 0;
}
-static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
+static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
{
int i, r = 0;
@@ -2534,18 +2418,10 @@
return 0;
}
-bool amdgpu_need_backup(struct amdgpu_device *adev)
-{
- if (adev->flags & AMD_IS_APU)
- return false;
-
- return amdgpu_lockup_timeout > 0 ? true : false;
-}
-
-static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
- struct amdgpu_ring *ring,
- struct amdgpu_bo *bo,
- struct dma_fence **fence)
+static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring,
+ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
{
uint32_t domain;
int r;
@@ -2578,7 +2454,7 @@
}
/*
- * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough
+ * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
*
* @adev: amdgpu device pointer
* @reset_flags: output param tells caller the reset result
@@ -2586,18 +2462,19 @@
* attempt to do soft-reset or full-reset and reinitialize Asic
* return 0 means successed otherwise failed
*/
-static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags)
+static int amdgpu_device_reset(struct amdgpu_device *adev,
+ uint64_t* reset_flags)
{
bool need_full_reset, vram_lost = 0;
int r;
- need_full_reset = amdgpu_need_full_reset(adev);
+ need_full_reset = amdgpu_device_ip_need_full_reset(adev);
if (!need_full_reset) {
- amdgpu_pre_soft_reset(adev);
- r = amdgpu_soft_reset(adev);
- amdgpu_post_soft_reset(adev);
- if (r || amdgpu_check_soft_reset(adev)) {
+ amdgpu_device_ip_pre_soft_reset(adev);
+ r = amdgpu_device_ip_soft_reset(adev);
+ amdgpu_device_ip_post_soft_reset(adev);
+ if (r || amdgpu_device_ip_check_soft_reset(adev)) {
DRM_INFO("soft reset failed, will fallback to full reset!\n");
need_full_reset = true;
}
@@ -2605,7 +2482,7 @@
}
if (need_full_reset) {
- r = amdgpu_suspend(adev);
+ r = amdgpu_device_ip_suspend(adev);
retry:
r = amdgpu_asic_reset(adev);
@@ -2614,26 +2491,27 @@
if (!r) {
dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
- r = amdgpu_resume_phase1(adev);
+ r = amdgpu_device_ip_resume_phase1(adev);
if (r)
goto out;
- vram_lost = amdgpu_check_vram_lost(adev);
+ vram_lost = amdgpu_device_check_vram_lost(adev);
if (vram_lost) {
DRM_ERROR("VRAM is lost!\n");
atomic_inc(&adev->vram_lost_counter);
}
- r = amdgpu_ttm_recover_gart(adev);
+ r = amdgpu_gtt_mgr_recover(
+ &adev->mman.bdev.man[TTM_PL_TT]);
if (r)
goto out;
- r = amdgpu_resume_phase2(adev);
+ r = amdgpu_device_ip_resume_phase2(adev);
if (r)
goto out;
if (vram_lost)
- amdgpu_fill_reset_magic(adev);
+ amdgpu_device_fill_reset_magic(adev);
}
}
@@ -2643,7 +2521,7 @@
r = amdgpu_ib_ring_tests(adev);
if (r) {
dev_err(adev->dev, "ib ring test failed (%d).\n", r);
- r = amdgpu_suspend(adev);
+ r = amdgpu_device_ip_suspend(adev);
need_full_reset = true;
goto retry;
}
@@ -2661,7 +2539,7 @@
}
/*
- * amdgpu_reset_sriov - reset ASIC for SR-IOV vf
+ * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
*
* @adev: amdgpu device pointer
* @reset_flags: output param tells caller the reset result
@@ -2669,7 +2547,9 @@
* do VF FLR and reinitialize Asic
* return 0 means successed otherwise failed
*/
-static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor)
+static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
+ uint64_t *reset_flags,
+ bool from_hypervisor)
{
int r;
@@ -2681,15 +2561,15 @@
return r;
/* Resume IP prior to SMC */
- r = amdgpu_sriov_reinit_early(adev);
+ r = amdgpu_device_ip_reinit_early_sriov(adev);
if (r)
goto error;
/* we need recover gart prior to run SMC/CP/SDMA resume */
- amdgpu_ttm_recover_gart(adev);
+ amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
/* now we are okay to resume SMC/CP/SDMA */
- r = amdgpu_sriov_reinit_late(adev);
+ r = amdgpu_device_ip_reinit_late_sriov(adev);
if (r)
goto error;
@@ -2703,11 +2583,10 @@
amdgpu_virt_release_full_gpu(adev, true);
if (reset_flags) {
- /* will get vram_lost from GIM in future, now all
- * reset request considered VRAM LOST
- */
- (*reset_flags) |= ~AMDGPU_RESET_INFO_VRAM_LOST;
- atomic_inc(&adev->vram_lost_counter);
+ if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
+ (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
+ atomic_inc(&adev->vram_lost_counter);
+ }
/* VF FLR or hotlink reset is always full-reset */
(*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
@@ -2717,30 +2596,38 @@
}
/**
- * amdgpu_gpu_recover - reset the asic and recover scheduler
+ * amdgpu_device_gpu_recover - reset the asic and recover scheduler
*
* @adev: amdgpu device pointer
* @job: which job trigger hang
+ * @force forces reset regardless of amdgpu_gpu_recovery
*
* Attempt to reset the GPU if it has hung (all asics).
* Returns 0 for success or an error on failure.
*/
-int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job)
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ struct amdgpu_job *job, bool force)
{
struct drm_atomic_state *state = NULL;
uint64_t reset_flags = 0;
int i, r, resched;
- if (!amdgpu_check_soft_reset(adev)) {
+ if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
return 0;
}
+ if (!force && (amdgpu_gpu_recovery == 0 ||
+ (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) {
+ DRM_INFO("GPU recovery disabled.\n");
+ return 0;
+ }
+
dev_info(adev->dev, "GPU reset begin!\n");
- mutex_lock(&adev->virt.lock_reset);
+ mutex_lock(&adev->lock_reset);
atomic_inc(&adev->gpu_reset_counter);
- adev->in_sriov_reset = 1;
+ adev->in_gpu_reset = 1;
/* block TTM */
resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
@@ -2760,16 +2647,16 @@
continue;
kthread_park(ring->sched.thread);
- amd_sched_hw_job_reset(&ring->sched, &job->base);
+ drm_sched_hw_job_reset(&ring->sched, &job->base);
/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
amdgpu_fence_driver_force_completion(ring);
}
if (amdgpu_sriov_vf(adev))
- r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true);
+ r = amdgpu_device_reset_sriov(adev, &reset_flags, job ? false : true);
else
- r = amdgpu_reset(adev, &reset_flags);
+ r = amdgpu_device_reset(adev, &reset_flags);
if (!r) {
if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
@@ -2782,7 +2669,7 @@
mutex_lock(&adev->shadow_list_lock);
list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
next = NULL;
- amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
+ amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
if (fence) {
r = dma_fence_wait(fence, false);
if (r) {
@@ -2813,7 +2700,7 @@
if (job && job->ring->idx != i)
continue;
- amd_sched_job_recovery(&ring->sched);
+ drm_sched_job_recovery(&ring->sched);
kthread_unpark(ring->sched.thread);
}
} else {
@@ -2834,7 +2721,6 @@
if (amdgpu_device_has_dc_support(adev)) {
if (drm_atomic_helper_resume(adev->ddev, state))
dev_info(adev->dev, "drm resume failed:%d\n", r);
- amdgpu_dm_display_resume(adev);
} else {
drm_helper_resume_force_mode(adev->ddev);
}
@@ -2850,12 +2736,12 @@
}
amdgpu_vf_error_trans_all(adev);
- adev->in_sriov_reset = 0;
- mutex_unlock(&adev->virt.lock_reset);
+ adev->in_gpu_reset = 0;
+ mutex_unlock(&adev->lock_reset);
return r;
}
-void amdgpu_get_pcie_info(struct amdgpu_device *adev)
+void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
{
u32 mask;
int ret;
@@ -2947,773 +2833,3 @@
}
}
-/*
- * Debugfs
- */
-int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
- const struct drm_info_list *files,
- unsigned nfiles)
-{
- unsigned i;
-
- for (i = 0; i < adev->debugfs_count; i++) {
- if (adev->debugfs[i].files == files) {
- /* Already registered */
- return 0;
- }
- }
-
- i = adev->debugfs_count + 1;
- if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
- DRM_ERROR("Reached maximum number of debugfs components.\n");
- DRM_ERROR("Report so we increase "
- "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
- return -EINVAL;
- }
- adev->debugfs[adev->debugfs_count].files = files;
- adev->debugfs[adev->debugfs_count].num_files = nfiles;
- adev->debugfs_count = i;
-#if defined(CONFIG_DEBUG_FS)
- drm_debugfs_create_files(files, nfiles,
- adev->ddev->primary->debugfs_root,
- adev->ddev->primary);
-#endif
- return 0;
-}
-
-#if defined(CONFIG_DEBUG_FS)
-
-static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
- bool pm_pg_lock, use_bank;
- unsigned instance_bank, sh_bank, se_bank;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- /* are we reading registers for which a PG lock is necessary? */
- pm_pg_lock = (*pos >> 23) & 1;
-
- if (*pos & (1ULL << 62)) {
- se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
- sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
- instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
-
- if (se_bank == 0x3FF)
- se_bank = 0xFFFFFFFF;
- if (sh_bank == 0x3FF)
- sh_bank = 0xFFFFFFFF;
- if (instance_bank == 0x3FF)
- instance_bank = 0xFFFFFFFF;
- use_bank = 1;
- } else {
- use_bank = 0;
- }
-
- *pos &= (1UL << 22) - 1;
-
- if (use_bank) {
- if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
- (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
- return -EINVAL;
- mutex_lock(&adev->grbm_idx_mutex);
- amdgpu_gfx_select_se_sh(adev, se_bank,
- sh_bank, instance_bank);
- }
-
- if (pm_pg_lock)
- mutex_lock(&adev->pm.mutex);
-
- while (size) {
- uint32_t value;
-
- if (*pos > adev->rmmio_size)
- goto end;
-
- value = RREG32(*pos >> 2);
- r = put_user(value, (uint32_t *)buf);
- if (r) {
- result = r;
- goto end;
- }
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
-end:
- if (use_bank) {
- amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
- mutex_unlock(&adev->grbm_idx_mutex);
- }
-
- if (pm_pg_lock)
- mutex_unlock(&adev->pm.mutex);
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
- bool pm_pg_lock, use_bank;
- unsigned instance_bank, sh_bank, se_bank;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- /* are we reading registers for which a PG lock is necessary? */
- pm_pg_lock = (*pos >> 23) & 1;
-
- if (*pos & (1ULL << 62)) {
- se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
- sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
- instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
-
- if (se_bank == 0x3FF)
- se_bank = 0xFFFFFFFF;
- if (sh_bank == 0x3FF)
- sh_bank = 0xFFFFFFFF;
- if (instance_bank == 0x3FF)
- instance_bank = 0xFFFFFFFF;
- use_bank = 1;
- } else {
- use_bank = 0;
- }
-
- *pos &= (1UL << 22) - 1;
-
- if (use_bank) {
- if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
- (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
- return -EINVAL;
- mutex_lock(&adev->grbm_idx_mutex);
- amdgpu_gfx_select_se_sh(adev, se_bank,
- sh_bank, instance_bank);
- }
-
- if (pm_pg_lock)
- mutex_lock(&adev->pm.mutex);
-
- while (size) {
- uint32_t value;
-
- if (*pos > adev->rmmio_size)
- return result;
-
- r = get_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- WREG32(*pos >> 2, value);
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- if (use_bank) {
- amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
- mutex_unlock(&adev->grbm_idx_mutex);
- }
-
- if (pm_pg_lock)
- mutex_unlock(&adev->pm.mutex);
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- while (size) {
- uint32_t value;
-
- value = RREG32_PCIE(*pos >> 2);
- r = put_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- while (size) {
- uint32_t value;
-
- r = get_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- WREG32_PCIE(*pos >> 2, value);
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- while (size) {
- uint32_t value;
-
- value = RREG32_DIDT(*pos >> 2);
- r = put_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- while (size) {
- uint32_t value;
-
- r = get_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- WREG32_DIDT(*pos >> 2, value);
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- while (size) {
- uint32_t value;
-
- value = RREG32_SMC(*pos);
- r = put_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- while (size) {
- uint32_t value;
-
- r = get_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- WREG32_SMC(*pos, value);
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- ssize_t result = 0;
- int r;
- uint32_t *config, no_regs = 0;
-
- if (size & 0x3 || *pos & 0x3)
- return -EINVAL;
-
- config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
- if (!config)
- return -ENOMEM;
-
- /* version, increment each time something is added */
- config[no_regs++] = 3;
- config[no_regs++] = adev->gfx.config.max_shader_engines;
- config[no_regs++] = adev->gfx.config.max_tile_pipes;
- config[no_regs++] = adev->gfx.config.max_cu_per_sh;
- config[no_regs++] = adev->gfx.config.max_sh_per_se;
- config[no_regs++] = adev->gfx.config.max_backends_per_se;
- config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
- config[no_regs++] = adev->gfx.config.max_gprs;
- config[no_regs++] = adev->gfx.config.max_gs_threads;
- config[no_regs++] = adev->gfx.config.max_hw_contexts;
- config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
- config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
- config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
- config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
- config[no_regs++] = adev->gfx.config.num_tile_pipes;
- config[no_regs++] = adev->gfx.config.backend_enable_mask;
- config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
- config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
- config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
- config[no_regs++] = adev->gfx.config.num_gpus;
- config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
- config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
- config[no_regs++] = adev->gfx.config.gb_addr_config;
- config[no_regs++] = adev->gfx.config.num_rbs;
-
- /* rev==1 */
- config[no_regs++] = adev->rev_id;
- config[no_regs++] = adev->pg_flags;
- config[no_regs++] = adev->cg_flags;
-
- /* rev==2 */
- config[no_regs++] = adev->family;
- config[no_regs++] = adev->external_rev_id;
-
- /* rev==3 */
- config[no_regs++] = adev->pdev->device;
- config[no_regs++] = adev->pdev->revision;
- config[no_regs++] = adev->pdev->subsystem_device;
- config[no_regs++] = adev->pdev->subsystem_vendor;
-
- while (size && (*pos < no_regs * 4)) {
- uint32_t value;
-
- value = config[*pos >> 2];
- r = put_user(value, (uint32_t *)buf);
- if (r) {
- kfree(config);
- return r;
- }
-
- result += 4;
- buf += 4;
- *pos += 4;
- size -= 4;
- }
-
- kfree(config);
- return result;
-}
-
-static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = file_inode(f)->i_private;
- int idx, x, outsize, r, valuesize;
- uint32_t values[16];
-
- if (size & 3 || *pos & 0x3)
- return -EINVAL;
-
- if (amdgpu_dpm == 0)
- return -EINVAL;
-
- /* convert offset to sensor number */
- idx = *pos >> 2;
-
- valuesize = sizeof(values);
- if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
- r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
- else
- return -EINVAL;
-
- if (size > valuesize)
- return -EINVAL;
-
- outsize = 0;
- x = 0;
- if (!r) {
- while (size) {
- r = put_user(values[x++], (int32_t *)buf);
- buf += 4;
- size -= 4;
- outsize += 4;
- }
- }
-
- return !r ? outsize : r;
-}
-
-static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = f->f_inode->i_private;
- int r, x;
- ssize_t result=0;
- uint32_t offset, se, sh, cu, wave, simd, data[32];
-
- if (size & 3 || *pos & 3)
- return -EINVAL;
-
- /* decode offset */
- offset = (*pos & GENMASK_ULL(6, 0));
- se = (*pos & GENMASK_ULL(14, 7)) >> 7;
- sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
- cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
- wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
- simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
-
- /* switch to the specific se/sh/cu */
- mutex_lock(&adev->grbm_idx_mutex);
- amdgpu_gfx_select_se_sh(adev, se, sh, cu);
-
- x = 0;
- if (adev->gfx.funcs->read_wave_data)
- adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
-
- amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
- mutex_unlock(&adev->grbm_idx_mutex);
-
- if (!x)
- return -EINVAL;
-
- while (size && (offset < x * 4)) {
- uint32_t value;
-
- value = data[offset >> 2];
- r = put_user(value, (uint32_t *)buf);
- if (r)
- return r;
-
- result += 4;
- buf += 4;
- offset += 4;
- size -= 4;
- }
-
- return result;
-}
-
-static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
- size_t size, loff_t *pos)
-{
- struct amdgpu_device *adev = f->f_inode->i_private;
- int r;
- ssize_t result = 0;
- uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
-
- if (size & 3 || *pos & 3)
- return -EINVAL;
-
- /* decode offset */
- offset = *pos & GENMASK_ULL(11, 0);
- se = (*pos & GENMASK_ULL(19, 12)) >> 12;
- sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
- cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
- wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
- simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
- thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
- bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
-
- data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- /* switch to the specific se/sh/cu */
- mutex_lock(&adev->grbm_idx_mutex);
- amdgpu_gfx_select_se_sh(adev, se, sh, cu);
-
- if (bank == 0) {
- if (adev->gfx.funcs->read_wave_vgprs)
- adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
- } else {
- if (adev->gfx.funcs->read_wave_sgprs)
- adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
- }
-
- amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
- mutex_unlock(&adev->grbm_idx_mutex);
-
- while (size) {
- uint32_t value;
-
- value = data[offset++];
- r = put_user(value, (uint32_t *)buf);
- if (r) {
- result = r;
- goto err;
- }
-
- result += 4;
- buf += 4;
- size -= 4;
- }
-
-err:
- kfree(data);
- return result;
-}
-
-static const struct file_operations amdgpu_debugfs_regs_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_regs_read,
- .write = amdgpu_debugfs_regs_write,
- .llseek = default_llseek
-};
-static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_regs_didt_read,
- .write = amdgpu_debugfs_regs_didt_write,
- .llseek = default_llseek
-};
-static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_regs_pcie_read,
- .write = amdgpu_debugfs_regs_pcie_write,
- .llseek = default_llseek
-};
-static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_regs_smc_read,
- .write = amdgpu_debugfs_regs_smc_write,
- .llseek = default_llseek
-};
-
-static const struct file_operations amdgpu_debugfs_gca_config_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_gca_config_read,
- .llseek = default_llseek
-};
-
-static const struct file_operations amdgpu_debugfs_sensors_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_sensor_read,
- .llseek = default_llseek
-};
-
-static const struct file_operations amdgpu_debugfs_wave_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_wave_read,
- .llseek = default_llseek
-};
-static const struct file_operations amdgpu_debugfs_gpr_fops = {
- .owner = THIS_MODULE,
- .read = amdgpu_debugfs_gpr_read,
- .llseek = default_llseek
-};
-
-static const struct file_operations *debugfs_regs[] = {
- &amdgpu_debugfs_regs_fops,
- &amdgpu_debugfs_regs_didt_fops,
- &amdgpu_debugfs_regs_pcie_fops,
- &amdgpu_debugfs_regs_smc_fops,
- &amdgpu_debugfs_gca_config_fops,
- &amdgpu_debugfs_sensors_fops,
- &amdgpu_debugfs_wave_fops,
- &amdgpu_debugfs_gpr_fops,
-};
-
-static const char *debugfs_regs_names[] = {
- "amdgpu_regs",
- "amdgpu_regs_didt",
- "amdgpu_regs_pcie",
- "amdgpu_regs_smc",
- "amdgpu_gca_config",
- "amdgpu_sensors",
- "amdgpu_wave",
- "amdgpu_gpr",
-};
-
-static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
-{
- struct drm_minor *minor = adev->ddev->primary;
- struct dentry *ent, *root = minor->debugfs_root;
- unsigned i, j;
-
- for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
- ent = debugfs_create_file(debugfs_regs_names[i],
- S_IFREG | S_IRUGO, root,
- adev, debugfs_regs[i]);
- if (IS_ERR(ent)) {
- for (j = 0; j < i; j++) {
- debugfs_remove(adev->debugfs_regs[i]);
- adev->debugfs_regs[i] = NULL;
- }
- return PTR_ERR(ent);
- }
-
- if (!i)
- i_size_write(ent->d_inode, adev->rmmio_size);
- adev->debugfs_regs[i] = ent;
- }
-
- return 0;
-}
-
-static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
- if (adev->debugfs_regs[i]) {
- debugfs_remove(adev->debugfs_regs[i]);
- adev->debugfs_regs[i] = NULL;
- }
- }
-}
-
-static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
-{
- struct drm_info_node *node = (struct drm_info_node *) m->private;
- struct drm_device *dev = node->minor->dev;
- struct amdgpu_device *adev = dev->dev_private;
- int r = 0, i;
-
- /* hold on the scheduler */
- for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
- struct amdgpu_ring *ring = adev->rings[i];
-
- if (!ring || !ring->sched.thread)
- continue;
- kthread_park(ring->sched.thread);
- }
-
- seq_printf(m, "run ib test:\n");
- r = amdgpu_ib_ring_tests(adev);
- if (r)
- seq_printf(m, "ib ring tests failed (%d).\n", r);
- else
- seq_printf(m, "ib ring tests passed.\n");
-
- /* go on the scheduler */
- for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
- struct amdgpu_ring *ring = adev->rings[i];
-
- if (!ring || !ring->sched.thread)
- continue;
- kthread_unpark(ring->sched.thread);
- }
-
- return 0;
-}
-
-static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
- {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
-};
-
-static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
-{
- return amdgpu_debugfs_add_files(adev,
- amdgpu_debugfs_test_ib_ring_list, 1);
-}
-
-int amdgpu_debugfs_init(struct drm_minor *minor)
-{
- return 0;
-}
-
-static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
-{
- struct drm_info_node *node = (struct drm_info_node *) m->private;
- struct drm_device *dev = node->minor->dev;
- struct amdgpu_device *adev = dev->dev_private;
-
- seq_write(m, adev->bios, adev->bios_size);
- return 0;
-}
-
-static const struct drm_info_list amdgpu_vbios_dump_list[] = {
- {"amdgpu_vbios",
- amdgpu_debugfs_get_vbios_dump,
- 0, NULL},
-};
-
-static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
-{
- return amdgpu_debugfs_add_files(adev,
- amdgpu_vbios_dump_list, 1);
-}
-#else
-static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
-{
- return 0;
-}
-static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
-{
- return 0;
-}
-static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
-{
- return 0;
-}
-static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
-#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index cc68acc..9f2cca1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -35,6 +35,7 @@
#include <linux/pm_runtime.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
+#include <drm/drm_fb_helper.h>
static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb)
{
@@ -571,15 +572,9 @@
return &amdgpu_fb->base;
}
-void amdgpu_output_poll_changed(struct drm_device *dev)
-{
- struct amdgpu_device *adev = dev->dev_private;
- amdgpu_fb_output_poll_changed(adev);
-}
-
const struct drm_mode_config_funcs amdgpu_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
- .output_poll_changed = amdgpu_output_poll_changed
+ .output_poll_changed = drm_fb_helper_output_poll_changed,
};
static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
index 5ae19163..6f93668d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
@@ -26,9 +26,7 @@
uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
struct drm_framebuffer *
amdgpu_user_framebuffer_create(struct drm_device *dev,
- struct drm_file *file_priv,
- const struct drm_mode_fb_cmd2 *mode_cmd);
-
-void amdgpu_output_poll_changed(struct drm_device *dev);
+ struct drm_file *file_priv,
+ const struct drm_mode_fb_cmd2 *mode_cmd);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 56caaee..a8437a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -360,6 +360,12 @@
((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
(adev)->powerplay.pp_handle, msg_id))
+#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \
+ virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \
+ ((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \
+ (adev)->powerplay.pp_handle, virtual_addr_low, \
+ virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
+
struct amdgpu_dpm {
struct amdgpu_ps *ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 613008c..a668796 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -90,7 +90,7 @@
int amdgpu_hw_i2c = 0;
int amdgpu_pcie_gen2 = -1;
int amdgpu_msi = -1;
-int amdgpu_lockup_timeout = 0;
+int amdgpu_lockup_timeout = 10000;
int amdgpu_dpm = -1;
int amdgpu_fw_load_type = -1;
int amdgpu_aspm = -1;
@@ -128,6 +128,7 @@
int amdgpu_job_hang_limit = 0;
int amdgpu_lbpw = -1;
int amdgpu_compute_multipipe = -1;
+int amdgpu_gpu_recovery = -1; /* auto */
MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -165,7 +166,7 @@
MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(msi, amdgpu_msi, int, 0444);
-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
+MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
@@ -216,7 +217,7 @@
MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
module_param_named(dc, amdgpu_dc, int, 0444);
-MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty");
+MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty");
module_param_named(dc_log, amdgpu_dc_log, int, 0444);
MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
@@ -280,6 +281,9 @@
MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
+MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto");
+module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
+
#ifdef CONFIG_DRM_AMDGPU_SI
#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
@@ -570,7 +574,7 @@
{
struct drm_device *dev;
unsigned long flags = ent->driver_data;
- int ret;
+ int ret, retry = 0;
bool supports_atomic = false;
if (!amdgpu_virtual_display &&
@@ -615,8 +619,14 @@
pci_set_drvdata(pdev, dev);
+retry_init:
ret = drm_dev_register(dev, ent->driver_data);
- if (ret)
+ if (ret == -EAGAIN && ++retry <= 3) {
+ DRM_INFO("retry init %d\n", retry);
+ /* Don't request EX mode too frequently which is attacking */
+ msleep(5000);
+ goto retry_init;
+ } else if (ret)
goto err_pci;
return 0;
@@ -650,7 +660,7 @@
* unfortunately we can't detect certain
* hypervisors so just do this all the time.
*/
- amdgpu_suspend(adev);
+ amdgpu_device_ip_suspend(adev);
}
static int amdgpu_pmops_suspend(struct device *dev)
@@ -855,9 +865,6 @@
.disable_vblank = amdgpu_disable_vblank_kms,
.get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
.get_scanout_position = amdgpu_get_crtc_scanout_position,
-#if defined(CONFIG_DEBUG_FS)
- .debugfs_init = amdgpu_debugfs_init,
-#endif
.irq_preinstall = amdgpu_irq_preinstall,
.irq_postinstall = amdgpu_irq_postinstall,
.irq_uninstall = amdgpu_irq_uninstall,
@@ -917,10 +924,6 @@
if (r)
goto error_fence;
- r = amd_sched_fence_slab_init();
- if (r)
- goto error_sched;
-
if (vgacon_text_force()) {
DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
return -EINVAL;
@@ -933,9 +936,6 @@
/* let modprobe override vga console setting */
return pci_register_driver(pdriver);
-error_sched:
- amdgpu_fence_slab_fini();
-
error_fence:
amdgpu_sync_fini();
@@ -949,7 +949,6 @@
pci_unregister_driver(pdriver);
amdgpu_unregister_atpx_handler();
amdgpu_sync_fini();
- amd_sched_fence_slab_fini();
amdgpu_fence_slab_fini();
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4ca4813..6dd77d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -285,12 +285,6 @@
return ret;
}
-void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
-{
- if (adev->mode_info.rfbdev)
- drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
-}
-
static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
{
struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
@@ -395,24 +389,3 @@
return true;
return false;
}
-
-void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
-{
- struct amdgpu_fbdev *afbdev;
- struct drm_fb_helper *fb_helper;
- int ret;
-
- if (!adev)
- return;
-
- afbdev = adev->mode_info.rfbdev;
-
- if (!afbdev)
- return;
-
- fb_helper = &afbdev->helper;
-
- ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
- if (ret)
- DRM_DEBUG("failed to restore crtc mode\n");
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d0e5aeb..9e2c225 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -187,7 +187,7 @@
seq = ++ring->fence_drv.sync_seq;
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
- seq, AMDGPU_FENCE_FLAG_INT);
+ seq, 0);
*s = seq;
@@ -409,7 +409,6 @@
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
unsigned num_hw_submission)
{
- long timeout;
int r;
/* Check that num_hw_submission is a power of two */
@@ -434,20 +433,9 @@
/* No need to setup the GPU scheduler for KIQ ring */
if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
- timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
- if (timeout == 0) {
- /*
- * FIXME:
- * Delayed workqueue cannot use it directly,
- * so the scheduler will not use delayed workqueue if
- * MAX_SCHEDULE_TIMEOUT is set.
- * Currently keep it simple and silly.
- */
- timeout = MAX_SCHEDULE_TIMEOUT;
- }
- r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
+ r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
num_hw_submission, amdgpu_job_hang_limit,
- timeout, ring->name);
+ msecs_to_jiffies(amdgpu_lockup_timeout), ring->name);
if (r) {
DRM_ERROR("Failed to create scheduler on ring %s.\n",
ring->name);
@@ -503,7 +491,7 @@
}
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
ring->fence_drv.irq_type);
- amd_sched_fini(&ring->sched);
+ drm_sched_fini(&ring->sched);
del_timer_sync(&ring->fence_drv.fallback_timer);
for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
dma_fence_put(ring->fence_drv.fences[j]);
@@ -705,7 +693,7 @@
struct amdgpu_device *adev = dev->dev_private;
seq_printf(m, "gpu recover\n");
- amdgpu_gpu_recover(adev, NULL);
+ amdgpu_device_gpu_recover(adev, NULL, true);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index fe81850..0a4f34a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -57,60 +57,48 @@
*/
/**
- * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
+ * amdgpu_dummy_page_init - init dummy page used by the driver
*
* @adev: amdgpu_device pointer
*
- * Allocate system memory for GART page table
- * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
- * gart table to be in system memory.
- * Returns 0 for success, -ENOMEM for failure.
+ * Allocate the dummy page used by the driver (all asics).
+ * This dummy page is used by the driver as a filler for gart entries
+ * when pages are taken out of the GART
+ * Returns 0 on sucess, -ENOMEM on failure.
*/
-int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
+static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
{
- void *ptr;
-
- ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
- &adev->gart.table_addr);
- if (ptr == NULL) {
+ if (adev->dummy_page.page)
+ return 0;
+ adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
+ if (adev->dummy_page.page == NULL)
+ return -ENOMEM;
+ adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
+ 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
+ dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
+ __free_page(adev->dummy_page.page);
+ adev->dummy_page.page = NULL;
return -ENOMEM;
}
-#ifdef CONFIG_X86
- if (0) {
- set_memory_uc((unsigned long)ptr,
- adev->gart.table_size >> PAGE_SHIFT);
- }
-#endif
- adev->gart.ptr = ptr;
- memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
return 0;
}
/**
- * amdgpu_gart_table_ram_free - free system ram for gart page table
+ * amdgpu_dummy_page_fini - free dummy page used by the driver
*
* @adev: amdgpu_device pointer
*
- * Free system memory for GART page table
- * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
- * gart table to be in system memory.
+ * Frees the dummy page used by the driver (all asics).
*/
-void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
+static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
- if (adev->gart.ptr == NULL) {
+ if (adev->dummy_page.page == NULL)
return;
- }
-#ifdef CONFIG_X86
- if (0) {
- set_memory_wb((unsigned long)adev->gart.ptr,
- adev->gart.table_size >> PAGE_SHIFT);
- }
-#endif
- pci_free_consistent(adev->pdev, adev->gart.table_size,
- (void *)adev->gart.ptr,
- adev->gart.table_addr);
- adev->gart.ptr = NULL;
- adev->gart.table_addr = 0;
+ pci_unmap_page(adev->pdev, adev->dummy_page.addr,
+ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ __free_page(adev->dummy_page.page);
+ adev->dummy_page.page = NULL;
}
/**
@@ -365,7 +353,7 @@
DRM_ERROR("Page size is smaller than GPU page size!\n");
return -EINVAL;
}
- r = amdgpu_dummy_page_init(adev);
+ r = amdgpu_gart_dummy_page_init(adev);
if (r)
return r;
/* Compute table size */
@@ -377,10 +365,8 @@
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
/* Allocate pages table */
adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
- if (adev->gart.pages == NULL) {
- amdgpu_gart_fini(adev);
+ if (adev->gart.pages == NULL)
return -ENOMEM;
- }
#endif
return 0;
@@ -395,14 +381,9 @@
*/
void amdgpu_gart_fini(struct amdgpu_device *adev)
{
- if (adev->gart.ready) {
- /* unbind pages */
- amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
- }
- adev->gart.ready = false;
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
vfree(adev->gart.pages);
adev->gart.pages = NULL;
#endif
- amdgpu_dummy_page_fini(adev);
+ amdgpu_gart_dummy_page_fini(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index afbe803..d4a4330 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -39,7 +39,7 @@
#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
struct amdgpu_gart {
- dma_addr_t table_addr;
+ u64 table_addr;
struct amdgpu_bo *robj;
void *ptr;
unsigned num_gpu_pages;
@@ -56,8 +56,6 @@
const struct amdgpu_gart_funcs *gart_funcs;
};
-int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
-void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 974b599..239a868 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -71,7 +71,7 @@
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
goto retry;
}
- DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
+ DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
size, initial_domain, alignment, r);
}
return r;
@@ -281,6 +281,7 @@
int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_gem_userptr *args = data;
struct drm_gem_object *gobj;
@@ -334,7 +335,7 @@
goto free_pages;
amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
amdgpu_bo_unreserve(bo);
if (r)
goto free_pages;
@@ -516,10 +517,6 @@
if (!amdgpu_vm_ready(vm))
return;
- r = amdgpu_vm_update_directories(adev, vm);
- if (r)
- goto error;
-
r = amdgpu_vm_clear_freed(adev, vm, NULL);
if (r)
goto error;
@@ -528,6 +525,10 @@
operation == AMDGPU_VA_OP_REPLACE)
r = amdgpu_vm_bo_update(adev, bo_va, false);
+ r = amdgpu_vm_update_directories(adev, vm);
+ if (r)
+ goto error;
+
error:
if (r && r != -ERESTARTSYS)
DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
@@ -556,7 +557,7 @@
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
- dev_err(&dev->pdev->dev,
+ dev_dbg(&dev->pdev->dev,
"va_address 0x%LX is in reserved area 0x%LX\n",
args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
@@ -574,7 +575,7 @@
args->va_address &= AMDGPU_VA_HOLE_MASK;
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
- dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+ dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
return -EINVAL;
}
@@ -586,7 +587,7 @@
case AMDGPU_VA_OP_REPLACE:
break;
default:
- dev_err(&dev->pdev->dev, "unsupported operation %d\n",
+ dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
args->operation);
return -EINVAL;
}
@@ -850,7 +851,7 @@
};
#endif
-int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
+int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index bb40d252..239bf2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -179,8 +179,12 @@
amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
- /* Using pipes 2/3 from MEC 2 seems cause problems */
- if (mec == 1 && pipe > 1)
+ /*
+ * 1. Using pipes 2/3 from MEC 2 seems cause problems.
+ * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
+ * only can be issued on queue 0.
+ */
+ if ((mec == 1 && pipe > 1) || queue != 0)
continue;
ring->me = mec + 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 00e0ce1..7c2be32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -31,6 +31,11 @@
atomic64_t available;
};
+struct amdgpu_gtt_node {
+ struct drm_mm_node node;
+ struct ttm_buffer_object *tbo;
+};
+
/**
* amdgpu_gtt_mgr_init - init GTT manager and DRM MM
*
@@ -70,7 +75,7 @@
static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
{
struct amdgpu_gtt_mgr *mgr = man->priv;
-
+ spin_lock(&mgr->lock);
drm_mm_takedown(&mgr->mm);
spin_unlock(&mgr->lock);
kfree(mgr);
@@ -79,17 +84,17 @@
}
/**
- * amdgpu_gtt_mgr_is_allocated - Check if mem has address space
+ * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space
*
* @mem: the mem object to check
*
* Check if a mem object has already address space allocated.
*/
-bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem)
+bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem)
{
- struct drm_mm_node *node = mem->mm_node;
+ struct amdgpu_gtt_node *node = mem->mm_node;
- return (node->start != AMDGPU_BO_INVALID_OFFSET);
+ return (node->node.start != AMDGPU_BO_INVALID_OFFSET);
}
/**
@@ -109,12 +114,12 @@
{
struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr = man->priv;
- struct drm_mm_node *node = mem->mm_node;
+ struct amdgpu_gtt_node *node = mem->mm_node;
enum drm_mm_insert_mode mode;
unsigned long fpfn, lpfn;
int r;
- if (amdgpu_gtt_mgr_is_allocated(mem))
+ if (amdgpu_gtt_mgr_has_gart_addr(mem))
return 0;
if (place)
@@ -132,13 +137,13 @@
mode = DRM_MM_INSERT_HIGH;
spin_lock(&mgr->lock);
- r = drm_mm_insert_node_in_range(&mgr->mm, node,
- mem->num_pages, mem->page_alignment, 0,
- fpfn, lpfn, mode);
+ r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages,
+ mem->page_alignment, 0, fpfn, lpfn,
+ mode);
spin_unlock(&mgr->lock);
if (!r)
- mem->start = node->start;
+ mem->start = node->node.start;
return r;
}
@@ -159,7 +164,7 @@
struct ttm_mem_reg *mem)
{
struct amdgpu_gtt_mgr *mgr = man->priv;
- struct drm_mm_node *node;
+ struct amdgpu_gtt_node *node;
int r;
spin_lock(&mgr->lock);
@@ -177,8 +182,9 @@
goto err_out;
}
- node->start = AMDGPU_BO_INVALID_OFFSET;
- node->size = mem->num_pages;
+ node->node.start = AMDGPU_BO_INVALID_OFFSET;
+ node->node.size = mem->num_pages;
+ node->tbo = tbo;
mem->mm_node = node;
if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
@@ -190,7 +196,7 @@
goto err_out;
}
} else {
- mem->start = node->start;
+ mem->start = node->node.start;
}
return 0;
@@ -214,14 +220,14 @@
struct ttm_mem_reg *mem)
{
struct amdgpu_gtt_mgr *mgr = man->priv;
- struct drm_mm_node *node = mem->mm_node;
+ struct amdgpu_gtt_node *node = mem->mm_node;
if (!node)
return;
spin_lock(&mgr->lock);
- if (node->start != AMDGPU_BO_INVALID_OFFSET)
- drm_mm_remove_node(node);
+ if (node->node.start != AMDGPU_BO_INVALID_OFFSET)
+ drm_mm_remove_node(&node->node);
spin_unlock(&mgr->lock);
atomic64_add(mem->num_pages, &mgr->available);
@@ -244,6 +250,25 @@
return (result > 0 ? result : 0) * PAGE_SIZE;
}
+int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man)
+{
+ struct amdgpu_gtt_mgr *mgr = man->priv;
+ struct amdgpu_gtt_node *node;
+ struct drm_mm_node *mm_node;
+ int r = 0;
+
+ spin_lock(&mgr->lock);
+ drm_mm_for_each_node(mm_node, &mgr->mm) {
+ node = container_of(mm_node, struct amdgpu_gtt_node, node);
+ r = amdgpu_ttm_recover_gart(node->tbo);
+ if (r)
+ break;
+ }
+ spin_unlock(&mgr->lock);
+
+ return r;
+}
+
/**
* amdgpu_gtt_mgr_debug - dump VRAM table
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index cd84bd0..d8779e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -149,7 +149,7 @@
return -EINVAL;
}
- if (vm && !job->vm_id) {
+ if (vm && !job->vmid) {
dev_err(adev->dev, "VM IB without ID\n");
return -EINVAL;
}
@@ -164,7 +164,7 @@
}
if (ring->funcs->emit_pipeline_sync && job &&
- ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
+ ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
amdgpu_vm_need_pipeline_sync(ring, job))) {
need_pipe_sync = true;
dma_fence_put(tmp);
@@ -181,7 +181,7 @@
}
}
- if (ring->funcs->init_cond_exec)
+ if (job && ring->funcs->init_cond_exec)
patch_offset = amdgpu_ring_init_cond_exec(ring);
if (ring->funcs->emit_hdp_flush
@@ -211,7 +211,7 @@
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
continue;
- amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
+ amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
need_ctx_switch);
need_ctx_switch = false;
}
@@ -229,9 +229,8 @@
r = amdgpu_fence_emit(ring, f);
if (r) {
dev_err(adev->dev, "failed to emit fence (%d)\n", r);
- if (job && job->vm_id)
- amdgpu_vm_reset_id(adev, ring->funcs->vmhub,
- job->vm_id);
+ if (job && job->vmid)
+ amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
amdgpu_ring_undo(ring);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
new file mode 100644
index 0000000..16884a0
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu_ids.h"
+
+#include <linux/idr.h>
+#include <linux/dma-fence-array.h>
+#include <drm/drmP.h>
+
+#include "amdgpu.h"
+#include "amdgpu_trace.h"
+
+/*
+ * PASID manager
+ *
+ * PASIDs are global address space identifiers that can be shared
+ * between the GPU, an IOMMU and the driver. VMs on different devices
+ * may use the same PASID if they share the same address
+ * space. Therefore PASIDs are allocated using a global IDA. VMs are
+ * looked up from the PASID per amdgpu_device.
+ */
+static DEFINE_IDA(amdgpu_pasid_ida);
+
+/**
+ * amdgpu_pasid_alloc - Allocate a PASID
+ * @bits: Maximum width of the PASID in bits, must be at least 1
+ *
+ * Allocates a PASID of the given width while keeping smaller PASIDs
+ * available if possible.
+ *
+ * Returns a positive integer on success. Returns %-EINVAL if bits==0.
+ * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
+ * memory allocation failure.
+ */
+int amdgpu_pasid_alloc(unsigned int bits)
+{
+ int pasid = -EINVAL;
+
+ for (bits = min(bits, 31U); bits > 0; bits--) {
+ pasid = ida_simple_get(&amdgpu_pasid_ida,
+ 1U << (bits - 1), 1U << bits,
+ GFP_KERNEL);
+ if (pasid != -ENOSPC)
+ break;
+ }
+
+ return pasid;
+}
+
+/**
+ * amdgpu_pasid_free - Free a PASID
+ * @pasid: PASID to free
+ */
+void amdgpu_pasid_free(unsigned int pasid)
+{
+ ida_simple_remove(&amdgpu_pasid_ida, pasid);
+}
+
+/*
+ * VMID manager
+ *
+ * VMIDs are a per VMHUB identifier for page tables handling.
+ */
+
+/**
+ * amdgpu_vmid_had_gpu_reset - check if reset occured since last use
+ *
+ * @adev: amdgpu_device pointer
+ * @id: VMID structure
+ *
+ * Check if GPU reset occured since last use of the VMID.
+ */
+bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
+ struct amdgpu_vmid *id)
+{
+ return id->current_gpu_reset_count !=
+ atomic_read(&adev->gpu_reset_counter);
+}
+
+/* idr_mgr->lock must be held */
+static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
+ struct amdgpu_ring *ring,
+ struct amdgpu_sync *sync,
+ struct dma_fence *fence,
+ struct amdgpu_job *job)
+{
+ struct amdgpu_device *adev = ring->adev;
+ unsigned vmhub = ring->funcs->vmhub;
+ uint64_t fence_context = adev->fence_context + ring->idx;
+ struct amdgpu_vmid *id = vm->reserved_vmid[vmhub];
+ struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+ struct dma_fence *updates = sync->last_vm_update;
+ int r = 0;
+ struct dma_fence *flushed, *tmp;
+ bool needs_flush = vm->use_cpu_for_update;
+
+ flushed = id->flushed_updates;
+ if ((amdgpu_vmid_had_gpu_reset(adev, id)) ||
+ (atomic64_read(&id->owner) != vm->entity.fence_context) ||
+ (job->vm_pd_addr != id->pd_gpu_addr) ||
+ (updates && (!flushed || updates->context != flushed->context ||
+ dma_fence_is_later(updates, flushed))) ||
+ (!id->last_flush || (id->last_flush->context != fence_context &&
+ !dma_fence_is_signaled(id->last_flush)))) {
+ needs_flush = true;
+ /* to prevent one context starved by another context */
+ id->pd_gpu_addr = 0;
+ tmp = amdgpu_sync_peek_fence(&id->active, ring);
+ if (tmp) {
+ r = amdgpu_sync_fence(adev, sync, tmp, false);
+ return r;
+ }
+ }
+
+ /* Good we can use this VMID. Remember this submission as
+ * user of the VMID.
+ */
+ r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
+ if (r)
+ goto out;
+
+ if (updates && (!flushed || updates->context != flushed->context ||
+ dma_fence_is_later(updates, flushed))) {
+ dma_fence_put(id->flushed_updates);
+ id->flushed_updates = dma_fence_get(updates);
+ }
+ id->pd_gpu_addr = job->vm_pd_addr;
+ atomic64_set(&id->owner, vm->entity.fence_context);
+ job->vm_needs_flush = needs_flush;
+ if (needs_flush) {
+ dma_fence_put(id->last_flush);
+ id->last_flush = NULL;
+ }
+ job->vmid = id - id_mgr->ids;
+ trace_amdgpu_vm_grab_id(vm, ring, job);
+out:
+ return r;
+}
+
+/**
+ * amdgpu_vm_grab_id - allocate the next free VMID
+ *
+ * @vm: vm to allocate id for
+ * @ring: ring we want to submit job to
+ * @sync: sync object where we add dependencies
+ * @fence: fence protecting ID from reuse
+ *
+ * Allocate an id for the vm, adding fences to the sync obj as necessary.
+ */
+int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
+ struct amdgpu_sync *sync, struct dma_fence *fence,
+ struct amdgpu_job *job)
+{
+ struct amdgpu_device *adev = ring->adev;
+ unsigned vmhub = ring->funcs->vmhub;
+ struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+ uint64_t fence_context = adev->fence_context + ring->idx;
+ struct dma_fence *updates = sync->last_vm_update;
+ struct amdgpu_vmid *id, *idle;
+ struct dma_fence **fences;
+ unsigned i;
+ int r = 0;
+
+ mutex_lock(&id_mgr->lock);
+ if (vm->reserved_vmid[vmhub]) {
+ r = amdgpu_vmid_grab_reserved_locked(vm, ring, sync, fence, job);
+ mutex_unlock(&id_mgr->lock);
+ return r;
+ }
+ fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
+ if (!fences) {
+ mutex_unlock(&id_mgr->lock);
+ return -ENOMEM;
+ }
+ /* Check if we have an idle VMID */
+ i = 0;
+ list_for_each_entry(idle, &id_mgr->ids_lru, list) {
+ fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
+ if (!fences[i])
+ break;
+ ++i;
+ }
+
+ /* If we can't find a idle VMID to use, wait till one becomes available */
+ if (&idle->list == &id_mgr->ids_lru) {
+ u64 fence_context = adev->vm_manager.fence_context + ring->idx;
+ unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
+ struct dma_fence_array *array;
+ unsigned j;
+
+ for (j = 0; j < i; ++j)
+ dma_fence_get(fences[j]);
+
+ array = dma_fence_array_create(i, fences, fence_context,
+ seqno, true);
+ if (!array) {
+ for (j = 0; j < i; ++j)
+ dma_fence_put(fences[j]);
+ kfree(fences);
+ r = -ENOMEM;
+ goto error;
+ }
+
+
+ r = amdgpu_sync_fence(ring->adev, sync, &array->base, false);
+ dma_fence_put(&array->base);
+ if (r)
+ goto error;
+
+ mutex_unlock(&id_mgr->lock);
+ return 0;
+
+ }
+ kfree(fences);
+
+ job->vm_needs_flush = vm->use_cpu_for_update;
+ /* Check if we can use a VMID already assigned to this VM */
+ list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
+ struct dma_fence *flushed;
+ bool needs_flush = vm->use_cpu_for_update;
+
+ /* Check all the prerequisites to using this VMID */
+ if (amdgpu_vmid_had_gpu_reset(adev, id))
+ continue;
+
+ if (atomic64_read(&id->owner) != vm->entity.fence_context)
+ continue;
+
+ if (job->vm_pd_addr != id->pd_gpu_addr)
+ continue;
+
+ if (!id->last_flush ||
+ (id->last_flush->context != fence_context &&
+ !dma_fence_is_signaled(id->last_flush)))
+ needs_flush = true;
+
+ flushed = id->flushed_updates;
+ if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
+ needs_flush = true;
+
+ /* Concurrent flushes are only possible starting with Vega10 */
+ if (adev->asic_type < CHIP_VEGA10 && needs_flush)
+ continue;
+
+ /* Good we can use this VMID. Remember this submission as
+ * user of the VMID.
+ */
+ r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
+ if (r)
+ goto error;
+
+ if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
+ dma_fence_put(id->flushed_updates);
+ id->flushed_updates = dma_fence_get(updates);
+ }
+
+ if (needs_flush)
+ goto needs_flush;
+ else
+ goto no_flush_needed;
+
+ };
+
+ /* Still no ID to use? Then use the idle one found earlier */
+ id = idle;
+
+ /* Remember this submission as user of the VMID */
+ r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
+ if (r)
+ goto error;
+
+ id->pd_gpu_addr = job->vm_pd_addr;
+ dma_fence_put(id->flushed_updates);
+ id->flushed_updates = dma_fence_get(updates);
+ atomic64_set(&id->owner, vm->entity.fence_context);
+
+needs_flush:
+ job->vm_needs_flush = true;
+ dma_fence_put(id->last_flush);
+ id->last_flush = NULL;
+
+no_flush_needed:
+ list_move_tail(&id->list, &id_mgr->ids_lru);
+
+ job->vmid = id - id_mgr->ids;
+ trace_amdgpu_vm_grab_id(vm, ring, job);
+
+error:
+ mutex_unlock(&id_mgr->lock);
+ return r;
+}
+
+int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ unsigned vmhub)
+{
+ struct amdgpu_vmid_mgr *id_mgr;
+ struct amdgpu_vmid *idle;
+ int r = 0;
+
+ id_mgr = &adev->vm_manager.id_mgr[vmhub];
+ mutex_lock(&id_mgr->lock);
+ if (vm->reserved_vmid[vmhub])
+ goto unlock;
+ if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
+ AMDGPU_VM_MAX_RESERVED_VMID) {
+ DRM_ERROR("Over limitation of reserved vmid\n");
+ atomic_dec(&id_mgr->reserved_vmid_num);
+ r = -EINVAL;
+ goto unlock;
+ }
+ /* Select the first entry VMID */
+ idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, list);
+ list_del_init(&idle->list);
+ vm->reserved_vmid[vmhub] = idle;
+ mutex_unlock(&id_mgr->lock);
+
+ return 0;
+unlock:
+ mutex_unlock(&id_mgr->lock);
+ return r;
+}
+
+void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ unsigned vmhub)
+{
+ struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+
+ mutex_lock(&id_mgr->lock);
+ if (vm->reserved_vmid[vmhub]) {
+ list_add(&vm->reserved_vmid[vmhub]->list,
+ &id_mgr->ids_lru);
+ vm->reserved_vmid[vmhub] = NULL;
+ atomic_dec(&id_mgr->reserved_vmid_num);
+ }
+ mutex_unlock(&id_mgr->lock);
+}
+
+/**
+ * amdgpu_vmid_reset - reset VMID to zero
+ *
+ * @adev: amdgpu device structure
+ * @vmid: vmid number to use
+ *
+ * Reset saved GDW, GWS and OA to force switch on next flush.
+ */
+void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
+ unsigned vmid)
+{
+ struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+ struct amdgpu_vmid *id = &id_mgr->ids[vmid];
+
+ atomic64_set(&id->owner, 0);
+ id->gds_base = 0;
+ id->gds_size = 0;
+ id->gws_base = 0;
+ id->gws_size = 0;
+ id->oa_base = 0;
+ id->oa_size = 0;
+}
+
+/**
+ * amdgpu_vmid_reset_all - reset VMID to zero
+ *
+ * @adev: amdgpu device structure
+ *
+ * Reset VMID to force flush on next use
+ */
+void amdgpu_vmid_reset_all(struct amdgpu_device *adev)
+{
+ unsigned i, j;
+
+ for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+ struct amdgpu_vmid_mgr *id_mgr =
+ &adev->vm_manager.id_mgr[i];
+
+ for (j = 1; j < id_mgr->num_ids; ++j)
+ amdgpu_vmid_reset(adev, i, j);
+ }
+}
+
+/**
+ * amdgpu_vmid_mgr_init - init the VMID manager
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Initialize the VM manager structures
+ */
+void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
+{
+ unsigned i, j;
+
+ for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+ struct amdgpu_vmid_mgr *id_mgr =
+ &adev->vm_manager.id_mgr[i];
+
+ mutex_init(&id_mgr->lock);
+ INIT_LIST_HEAD(&id_mgr->ids_lru);
+ atomic_set(&id_mgr->reserved_vmid_num, 0);
+
+ /* skip over VMID 0, since it is the system VM */
+ for (j = 1; j < id_mgr->num_ids; ++j) {
+ amdgpu_vmid_reset(adev, i, j);
+ amdgpu_sync_create(&id_mgr->ids[i].active);
+ list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
+ }
+ }
+
+ adev->vm_manager.fence_context =
+ dma_fence_context_alloc(AMDGPU_MAX_RINGS);
+ for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
+ adev->vm_manager.seqno[i] = 0;
+}
+
+/**
+ * amdgpu_vmid_mgr_fini - cleanup VM manager
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Cleanup the VM manager and free resources.
+ */
+void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev)
+{
+ unsigned i, j;
+
+ for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+ struct amdgpu_vmid_mgr *id_mgr =
+ &adev->vm_manager.id_mgr[i];
+
+ mutex_destroy(&id_mgr->lock);
+ for (j = 0; j < AMDGPU_NUM_VMID; ++j) {
+ struct amdgpu_vmid *id = &id_mgr->ids[j];
+
+ amdgpu_sync_free(&id->active);
+ dma_fence_put(id->flushed_updates);
+ dma_fence_put(id->last_flush);
+ }
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
new file mode 100644
index 0000000..ad931fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __AMDGPU_IDS_H__
+#define __AMDGPU_IDS_H__
+
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/list.h>
+#include <linux/dma-fence.h>
+
+#include "amdgpu_sync.h"
+
+/* maximum number of VMIDs */
+#define AMDGPU_NUM_VMID 16
+
+struct amdgpu_device;
+struct amdgpu_vm;
+struct amdgpu_ring;
+struct amdgpu_sync;
+struct amdgpu_job;
+
+struct amdgpu_vmid {
+ struct list_head list;
+ struct amdgpu_sync active;
+ struct dma_fence *last_flush;
+ atomic64_t owner;
+
+ uint64_t pd_gpu_addr;
+ /* last flushed PD/PT update */
+ struct dma_fence *flushed_updates;
+
+ uint32_t current_gpu_reset_count;
+
+ uint32_t gds_base;
+ uint32_t gds_size;
+ uint32_t gws_base;
+ uint32_t gws_size;
+ uint32_t oa_base;
+ uint32_t oa_size;
+};
+
+struct amdgpu_vmid_mgr {
+ struct mutex lock;
+ unsigned num_ids;
+ struct list_head ids_lru;
+ struct amdgpu_vmid ids[AMDGPU_NUM_VMID];
+ atomic_t reserved_vmid_num;
+};
+
+int amdgpu_pasid_alloc(unsigned int bits);
+void amdgpu_pasid_free(unsigned int pasid);
+
+bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
+ struct amdgpu_vmid *id);
+int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ unsigned vmhub);
+void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ unsigned vmhub);
+int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
+ struct amdgpu_sync *sync, struct dma_fence *fence,
+ struct amdgpu_job *job);
+void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
+ unsigned vmid);
+void amdgpu_vmid_reset_all(struct amdgpu_device *adev);
+
+void amdgpu_vmid_mgr_init(struct amdgpu_device *adev);
+void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index ada89358..29cf109 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -105,8 +105,8 @@
unsigned client_id;
unsigned src_id;
unsigned ring_id;
- unsigned vm_id;
- unsigned vm_id_src;
+ unsigned vmid;
+ unsigned vmid_src;
uint64_t timestamp;
unsigned timestamp_src;
unsigned pas_id;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index c340774..36483e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -88,7 +88,7 @@
reset_work);
if (!amdgpu_sriov_vf(adev))
- amdgpu_gpu_recover(adev, NULL);
+ amdgpu_device_gpu_recover(adev, NULL, false);
}
/* Disable *all* interrupts */
@@ -257,7 +257,8 @@
r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
if (r) {
adev->irq.installed = false;
- flush_work(&adev->hotplug_work);
+ if (!amdgpu_device_has_dc_support(adev))
+ flush_work(&adev->hotplug_work);
cancel_work_sync(&adev->reset_work);
return r;
}
@@ -282,7 +283,8 @@
adev->irq.installed = false;
if (adev->irq.msi_enabled)
pci_disable_msi(adev->pdev);
- flush_work(&adev->hotplug_work);
+ if (!amdgpu_device_has_dc_support(adev))
+ flush_work(&adev->hotplug_work);
cancel_work_sync(&adev->reset_work);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index c6a9871..2bd5676 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -28,7 +28,7 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
-static void amdgpu_job_timedout(struct amd_sched_job *s_job)
+static void amdgpu_job_timedout(struct drm_sched_job *s_job)
{
struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
@@ -37,7 +37,7 @@
atomic_read(&job->ring->fence_drv.last_seq),
job->ring->fence_drv.sync_seq);
- amdgpu_gpu_recover(job->adev, job);
+ amdgpu_device_gpu_recover(job->adev, job, false);
}
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
@@ -60,7 +60,6 @@
(*job)->num_ibs = num_ibs;
amdgpu_sync_create(&(*job)->sync);
- amdgpu_sync_create(&(*job)->dep_sync);
amdgpu_sync_create(&(*job)->sched_sync);
(*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
@@ -97,14 +96,13 @@
amdgpu_ib_free(job->adev, &job->ibs[i], f);
}
-static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
+static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
{
struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
amdgpu_ring_priority_put(job->ring, s_job->s_priority);
dma_fence_put(job->fence);
amdgpu_sync_free(&job->sync);
- amdgpu_sync_free(&job->dep_sync);
amdgpu_sync_free(&job->sched_sync);
kfree(job);
}
@@ -115,13 +113,12 @@
dma_fence_put(job->fence);
amdgpu_sync_free(&job->sync);
- amdgpu_sync_free(&job->dep_sync);
amdgpu_sync_free(&job->sched_sync);
kfree(job);
}
int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
- struct amd_sched_entity *entity, void *owner,
+ struct drm_sched_entity *entity, void *owner,
struct dma_fence **f)
{
int r;
@@ -130,7 +127,7 @@
if (!f)
return -EINVAL;
- r = amd_sched_job_init(&job->base, &ring->sched, entity, owner);
+ r = drm_sched_job_init(&job->base, &ring->sched, entity, owner);
if (r)
return r;
@@ -139,45 +136,46 @@
*f = dma_fence_get(&job->base.s_fence->finished);
amdgpu_job_free_resources(job);
amdgpu_ring_priority_get(job->ring, job->base.s_priority);
- amd_sched_entity_push_job(&job->base, entity);
+ drm_sched_entity_push_job(&job->base, entity);
return 0;
}
-static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job,
- struct amd_sched_entity *s_entity)
+static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
+ struct drm_sched_entity *s_entity)
{
struct amdgpu_job *job = to_amdgpu_job(sched_job);
struct amdgpu_vm *vm = job->vm;
-
- struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync);
+ bool explicit = false;
int r;
+ struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit);
- if (amd_sched_dependency_optimized(fence, s_entity)) {
- r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence);
- if (r)
- DRM_ERROR("Error adding fence to sync (%d)\n", r);
+ if (fence && explicit) {
+ if (drm_sched_dependency_optimized(fence, s_entity)) {
+ r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false);
+ if (r)
+ DRM_ERROR("Error adding fence to sync (%d)\n", r);
+ }
}
- if (!fence)
- fence = amdgpu_sync_get_fence(&job->sync);
- while (fence == NULL && vm && !job->vm_id) {
+
+ while (fence == NULL && vm && !job->vmid) {
struct amdgpu_ring *ring = job->ring;
- r = amdgpu_vm_grab_id(vm, ring, &job->sync,
- &job->base.s_fence->finished,
- job);
+ r = amdgpu_vmid_grab(vm, ring, &job->sync,
+ &job->base.s_fence->finished,
+ job);
if (r)
DRM_ERROR("Error getting VM ID (%d)\n", r);
- fence = amdgpu_sync_get_fence(&job->sync);
+ fence = amdgpu_sync_get_fence(&job->sync, NULL);
}
return fence;
}
-static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
+static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
{
- struct dma_fence *fence = NULL;
+ struct dma_fence *fence = NULL, *finished;
struct amdgpu_device *adev;
struct amdgpu_job *job;
int r;
@@ -187,15 +185,18 @@
return NULL;
}
job = to_amdgpu_job(sched_job);
+ finished = &job->base.s_fence->finished;
adev = job->adev;
BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
trace_amdgpu_sched_run_job(job);
- /* skip ib schedule when vram is lost */
- if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) {
- dma_fence_set_error(&job->base.s_fence->finished, -ECANCELED);
- DRM_ERROR("Skip scheduling IBs!\n");
+
+ if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
+ dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
+
+ if (finished->error < 0) {
+ DRM_INFO("Skip scheduling IBs!\n");
} else {
r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
&fence);
@@ -210,7 +211,7 @@
return fence;
}
-const struct amd_sched_backend_ops amdgpu_sched_ops = {
+const struct drm_sched_backend_ops amdgpu_sched_ops = {
.dependency = amdgpu_job_dependency,
.run_job = amdgpu_job_run,
.timedout_job = amdgpu_job_timedout,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index b8522e7..bfdeacb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -63,8 +63,6 @@
pm_runtime_forbid(dev->dev);
}
- amdgpu_amdkfd_device_fini(adev);
-
amdgpu_acpi_fini(adev);
amdgpu_device_fini(adev);
@@ -159,9 +157,6 @@
"Error during ACPI methods call\n");
}
- amdgpu_amdkfd_device_probe(adev);
- amdgpu_amdkfd_device_init(adev);
-
if (amdgpu_device_is_px(dev)) {
pm_runtime_use_autosuspend(dev->dev);
pm_runtime_set_autosuspend_delay(dev->dev, 5000);
@@ -171,9 +166,6 @@
pm_runtime_put_autosuspend(dev->dev);
}
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_release_full_gpu(adev, true);
-
out:
if (r) {
/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
@@ -799,9 +791,7 @@
*/
void amdgpu_driver_lastclose_kms(struct drm_device *dev)
{
- struct amdgpu_device *adev = dev->dev_private;
-
- amdgpu_fbdev_restore_mode(adev);
+ drm_fb_helper_lastclose(dev);
vga_switcheroo_process_delayed_switch();
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index ffde1e9..2264c5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -89,7 +89,6 @@
AMDGPU_HPD_4,
AMDGPU_HPD_5,
AMDGPU_HPD_6,
- AMDGPU_HPD_LAST,
AMDGPU_HPD_NONE = 0xff,
};
@@ -106,7 +105,6 @@
AMDGPU_CRTC_IRQ_VLINE4,
AMDGPU_CRTC_IRQ_VLINE5,
AMDGPU_CRTC_IRQ_VLINE6,
- AMDGPU_CRTC_IRQ_LAST,
AMDGPU_CRTC_IRQ_NONE = 0xff
};
@@ -117,7 +115,6 @@
AMDGPU_PAGEFLIP_IRQ_D4,
AMDGPU_PAGEFLIP_IRQ_D5,
AMDGPU_PAGEFLIP_IRQ_D6,
- AMDGPU_PAGEFLIP_IRQ_LAST,
AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
};
@@ -355,6 +352,7 @@
u16 firmware_flags;
/* pointer to backlight encoder */
struct amdgpu_encoder *bl_encoder;
+ u8 bl_level; /* saved backlight level */
struct amdgpu_audio audio; /* audio stuff */
int num_crtc; /* number of crtcs */
int num_hpd; /* number of hpd pins */
@@ -661,10 +659,6 @@
void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
-void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
-
-void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
-
int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index b53f81b..d2dcd41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -37,6 +37,18 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
+static bool amdgpu_need_backup(struct amdgpu_device *adev)
+{
+ if (adev->flags & AMD_IS_APU)
+ return false;
+
+ if (amdgpu_gpu_recovery == 0 ||
+ (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))
+ return false;
+
+ return true;
+}
+
static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
@@ -283,6 +295,44 @@
*cpu_addr = NULL;
}
+/* Validate bo size is bit bigger then the request domain */
+static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
+ unsigned long size, u32 domain)
+{
+ struct ttm_mem_type_manager *man = NULL;
+
+ /*
+ * If GTT is part of requested domains the check must succeed to
+ * allow fall back to GTT
+ */
+ if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+ man = &adev->mman.bdev.man[TTM_PL_TT];
+
+ if (size < (man->size << PAGE_SHIFT))
+ return true;
+ else
+ goto fail;
+ }
+
+ if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
+ man = &adev->mman.bdev.man[TTM_PL_VRAM];
+
+ if (size < (man->size << PAGE_SHIFT))
+ return true;
+ else
+ goto fail;
+ }
+
+
+ /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
+ return true;
+
+fail:
+ DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
+ man->size << PAGE_SHIFT);
+ return false;
+}
+
static int amdgpu_bo_do_create(struct amdgpu_device *adev,
unsigned long size, int byte_align,
bool kernel, u32 domain, u64 flags,
@@ -291,16 +341,24 @@
uint64_t init_value,
struct amdgpu_bo **bo_ptr)
{
+ struct ttm_operation_ctx ctx = {
+ .interruptible = !kernel,
+ .no_wait_gpu = false,
+ .allow_reserved_eviction = true,
+ .resv = resv
+ };
struct amdgpu_bo *bo;
enum ttm_bo_type type;
unsigned long page_align;
- u64 initial_bytes_moved, bytes_moved;
size_t acc_size;
int r;
page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
size = ALIGN(size, PAGE_SIZE);
+ if (!amdgpu_bo_validate_size(adev, size, domain))
+ return -ENOMEM;
+
if (kernel) {
type = ttm_bo_type_kernel;
} else if (sg) {
@@ -366,22 +424,19 @@
bo->tbo.bdev = &adev->mman.bdev;
amdgpu_ttm_placement_from_domain(bo, domain);
- initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
- /* Kernel allocation are uninterruptible */
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
- &bo->placement, page_align, !kernel, NULL,
+ &bo->placement, page_align, &ctx, NULL,
acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
if (unlikely(r != 0))
return r;
- bytes_moved = atomic64_read(&adev->num_bytes_moved) -
- initial_bytes_moved;
if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
bo->tbo.mem.mem_type == TTM_PL_VRAM &&
bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
- amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved);
+ amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
+ ctx.bytes_moved);
else
- amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0);
+ amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
if (kernel)
bo->tbo.priority = 1;
@@ -513,6 +568,7 @@
int amdgpu_bo_validate(struct amdgpu_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
uint32_t domain;
int r;
@@ -523,7 +579,7 @@
retry:
amdgpu_ttm_placement_from_domain(bo, domain);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
domain = bo->allowed_domains;
goto retry;
@@ -634,6 +690,7 @@
u64 *gpu_addr)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct ttm_operation_ctx ctx = { false, false };
int r, i;
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
@@ -658,7 +715,7 @@
if (bo->pin_count) {
uint32_t mem_type = bo->tbo.mem.mem_type;
- if (domain != amdgpu_mem_type_to_domain(mem_type))
+ if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
return -EINVAL;
bo->pin_count++;
@@ -693,25 +750,26 @@
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
}
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (unlikely(r)) {
dev_err(adev->dev, "%p pin failed\n", bo);
goto error;
}
- bo->pin_count = 1;
- if (gpu_addr != NULL) {
- r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
- if (unlikely(r)) {
- dev_err(adev->dev, "%p bind failed\n", bo);
- goto error;
- }
- *gpu_addr = amdgpu_bo_gpu_offset(bo);
+ r = amdgpu_ttm_alloc_gart(&bo->tbo);
+ if (unlikely(r)) {
+ dev_err(adev->dev, "%p bind failed\n", bo);
+ goto error;
}
+
+ bo->pin_count = 1;
+ if (gpu_addr != NULL)
+ *gpu_addr = amdgpu_bo_gpu_offset(bo);
+
+ domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
adev->vram_pin_size += amdgpu_bo_size(bo);
- if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
- adev->invisible_pin_size += amdgpu_bo_size(bo);
+ adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo);
} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
adev->gart_pin_size += amdgpu_bo_size(bo);
}
@@ -728,6 +786,7 @@
int amdgpu_bo_unpin(struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct ttm_operation_ctx ctx = { false, false };
int r, i;
if (!bo->pin_count) {
@@ -741,7 +800,7 @@
bo->placements[i].lpfn = 0;
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
}
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (unlikely(r)) {
dev_err(adev->dev, "%p validate failed for unpin\n", bo);
goto error;
@@ -749,8 +808,7 @@
if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
adev->vram_pin_size -= amdgpu_bo_size(bo);
- if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
- adev->invisible_pin_size -= amdgpu_bo_size(bo);
+ adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo);
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
adev->gart_pin_size -= amdgpu_bo_size(bo);
}
@@ -913,6 +971,7 @@
int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
+ struct ttm_operation_ctx ctx = { false, false };
struct amdgpu_bo *abo;
unsigned long offset, size;
int r;
@@ -946,7 +1005,7 @@
abo->placement.num_busy_placement = 1;
abo->placement.busy_placement = &abo->placements[1];
- r = ttm_bo_validate(bo, &abo->placement, false, false);
+ r = ttm_bo_validate(bo, &abo->placement, &ctx);
if (unlikely(r != 0))
return r;
@@ -991,7 +1050,7 @@
{
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
- !amdgpu_ttm_is_bound(bo->tbo.ttm));
+ !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
!bo->pin_count);
WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 868de77..b6c4471 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -187,7 +187,7 @@
static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
{
switch (bo->tbo.mem.mem_type) {
- case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm);
+ case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem);
case TTM_PL_VRAM: return true;
default: return false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index f8edf54..01a996c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -32,7 +32,6 @@
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
-#include "amd_powerplay.h"
static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
@@ -1279,16 +1278,16 @@
/* XXX select vce level based on ring/task */
adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
mutex_unlock(&adev->pm.mutex);
- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_CG_STATE_UNGATE);
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_UNGATE);
amdgpu_pm_compute_clocks(adev);
} else {
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_CG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_GATE);
mutex_lock(&adev->pm.mutex);
adev->pm.dpm.vce_active = false;
mutex_unlock(&adev->pm.mutex);
@@ -1585,7 +1584,7 @@
struct drm_device *ddev = adev->ddev;
u32 flags = 0;
- amdgpu_get_clockgating_state(adev, &flags);
+ amdgpu_device_ip_get_clockgating_state(adev, &flags);
seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
amdgpu_parse_cg_state(m, flags);
seq_printf(m, "\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 86c4fd57..03f108c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -168,9 +168,6 @@
ret = adev->powerplay.ip_funcs->hw_fini(
adev->powerplay.pp_handle);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_fini_bo(adev);
-
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 5e365b7..ac71aed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -170,6 +170,7 @@
{
struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct ttm_operation_ctx ctx = { true, false };
u32 domain = amdgpu_display_supported_domains(adev);
int ret;
bool reads = (direction == DMA_BIDIRECTIONAL ||
@@ -185,7 +186,7 @@
if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
- ret = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
}
amdgpu_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 447d446..2157d45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -264,7 +264,7 @@
struct amdgpu_device *adev = psp->adev;
int ret;
- if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
+ if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
ret = psp_bootloader_load_sysdrv(psp);
if (ret)
return ret;
@@ -334,23 +334,26 @@
int ret;
struct psp_context *psp = &adev->psp;
+ if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
+ goto skip_memalloc;
+
psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
if (!psp->cmd)
return -ENOMEM;
ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
- AMDGPU_GEM_DOMAIN_GTT,
- &psp->fw_pri_bo,
- &psp->fw_pri_mc_addr,
- &psp->fw_pri_buf);
+ AMDGPU_GEM_DOMAIN_GTT,
+ &psp->fw_pri_bo,
+ &psp->fw_pri_mc_addr,
+ &psp->fw_pri_buf);
if (ret)
goto failed;
ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &psp->fence_buf_bo,
- &psp->fence_buf_mc_addr,
- &psp->fence_buf);
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &psp->fence_buf_bo,
+ &psp->fence_buf_mc_addr,
+ &psp->fence_buf);
if (ret)
goto failed_mem2;
@@ -375,6 +378,7 @@
if (ret)
goto failed_mem;
+skip_memalloc:
ret = psp_hw_start(psp);
if (ret)
goto failed_mem;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 93d86619..262c126 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -225,7 +225,7 @@
/* Right now all IPs have only one instance - multiple rings. */
if (instance != 0) {
- DRM_ERROR("invalid ip instance: %d\n", instance);
+ DRM_DEBUG("invalid ip instance: %d\n", instance);
return -EINVAL;
}
@@ -255,13 +255,13 @@
ip_num_rings = adev->vcn.num_enc_rings;
break;
default:
- DRM_ERROR("unknown ip type: %d\n", hw_ip);
+ DRM_DEBUG("unknown ip type: %d\n", hw_ip);
return -EINVAL;
}
if (ring >= ip_num_rings) {
- DRM_ERROR("Ring index:%d exceeds maximum:%d for ip:%d\n",
- ring, ip_num_rings, hw_ip);
+ DRM_DEBUG("Ring index:%d exceeds maximum:%d for ip:%d\n",
+ ring, ip_num_rings, hw_ip);
return -EINVAL;
}
@@ -292,7 +292,7 @@
default:
*out_ring = NULL;
r = -EINVAL;
- DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
+ DRM_DEBUG("unknown HW IP type: %d\n", mapper->hw_ip);
}
out_unlock:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 098f268..561d331 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -164,7 +164,7 @@
* Release a request for executing at @priority
*/
void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
- enum amd_sched_priority priority)
+ enum drm_sched_priority priority)
{
int i;
@@ -175,7 +175,7 @@
return;
/* no need to restore if the job is already at the lowest priority */
- if (priority == AMD_SCHED_PRIORITY_NORMAL)
+ if (priority == DRM_SCHED_PRIORITY_NORMAL)
return;
mutex_lock(&ring->priority_mutex);
@@ -184,8 +184,8 @@
goto out_unlock;
/* decay priority to the next level with a job available */
- for (i = priority; i >= AMD_SCHED_PRIORITY_MIN; i--) {
- if (i == AMD_SCHED_PRIORITY_NORMAL
+ for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) {
+ if (i == DRM_SCHED_PRIORITY_NORMAL
|| atomic_read(&ring->num_jobs[i])) {
ring->priority = i;
ring->funcs->set_priority(ring, i);
@@ -206,7 +206,7 @@
* Request a ring's priority to be raised to @priority (refcounted).
*/
void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
- enum amd_sched_priority priority)
+ enum drm_sched_priority priority)
{
if (!ring->funcs->set_priority)
return;
@@ -317,12 +317,12 @@
}
ring->max_dw = max_dw;
- ring->priority = AMD_SCHED_PRIORITY_NORMAL;
+ ring->priority = DRM_SCHED_PRIORITY_NORMAL;
mutex_init(&ring->priority_mutex);
INIT_LIST_HEAD(&ring->lru_list);
amdgpu_ring_lru_touch(adev, ring);
- for (i = 0; i < AMD_SCHED_PRIORITY_MAX; ++i)
+ for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
atomic_set(&ring->num_jobs[i], 0);
if (amdgpu_debugfs_ring_init(adev, ring)) {
@@ -481,7 +481,7 @@
result = 0;
if (*pos < 12) {
- early[0] = amdgpu_ring_get_rptr(ring);
+ early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
early[2] = ring->wptr & ring->buf_mask;
for (i = *pos / 4; i < 3 && size; i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index a6b89e3..102dad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -25,7 +25,7 @@
#define __AMDGPU_RING_H__
#include <drm/amdgpu_drm.h>
-#include "gpu_scheduler.h"
+#include <drm/gpu_scheduler.h>
/* max number of rings */
#define AMDGPU_MAX_RINGS 18
@@ -121,11 +121,11 @@
/* command emit functions */
void (*emit_ib)(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch);
+ unsigned vmid, bool ctx_switch);
void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
uint64_t seq, unsigned flags);
void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
- void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
+ void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
uint64_t pd_addr);
void (*emit_hdp_flush)(struct amdgpu_ring *ring);
void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
@@ -154,14 +154,14 @@
void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
/* priority functions */
void (*set_priority) (struct amdgpu_ring *ring,
- enum amd_sched_priority priority);
+ enum drm_sched_priority priority);
};
struct amdgpu_ring {
struct amdgpu_device *adev;
const struct amdgpu_ring_funcs *funcs;
struct amdgpu_fence_driver fence_drv;
- struct amd_gpu_scheduler sched;
+ struct drm_gpu_scheduler sched;
struct list_head lru_list;
struct amdgpu_bo *ring_obj;
@@ -186,6 +186,7 @@
uint64_t eop_gpu_addr;
u32 doorbell_index;
bool use_doorbell;
+ bool use_pollmem;
unsigned wptr_offs;
unsigned fence_offs;
uint64_t current_ctx;
@@ -196,7 +197,7 @@
unsigned vm_inv_eng;
bool has_compute_vm_bug;
- atomic_t num_jobs[AMD_SCHED_PRIORITY_MAX];
+ atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX];
struct mutex priority_mutex;
/* protected by priority_mutex */
int priority;
@@ -212,9 +213,9 @@
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
- enum amd_sched_priority priority);
+ enum drm_sched_priority priority);
void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
- enum amd_sched_priority priority);
+ enum drm_sched_priority priority);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
unsigned ring_size, struct amdgpu_irq_src *irq_src,
unsigned irq_type);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
index 290cc3f..86a0715 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
@@ -29,29 +29,29 @@
#include "amdgpu_vm.h"
-enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
+enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
{
switch (amdgpu_priority) {
case AMDGPU_CTX_PRIORITY_VERY_HIGH:
- return AMD_SCHED_PRIORITY_HIGH_HW;
+ return DRM_SCHED_PRIORITY_HIGH_HW;
case AMDGPU_CTX_PRIORITY_HIGH:
- return AMD_SCHED_PRIORITY_HIGH_SW;
+ return DRM_SCHED_PRIORITY_HIGH_SW;
case AMDGPU_CTX_PRIORITY_NORMAL:
- return AMD_SCHED_PRIORITY_NORMAL;
+ return DRM_SCHED_PRIORITY_NORMAL;
case AMDGPU_CTX_PRIORITY_LOW:
case AMDGPU_CTX_PRIORITY_VERY_LOW:
- return AMD_SCHED_PRIORITY_LOW;
+ return DRM_SCHED_PRIORITY_LOW;
case AMDGPU_CTX_PRIORITY_UNSET:
- return AMD_SCHED_PRIORITY_UNSET;
+ return DRM_SCHED_PRIORITY_UNSET;
default:
WARN(1, "Invalid context priority %d\n", amdgpu_priority);
- return AMD_SCHED_PRIORITY_INVALID;
+ return DRM_SCHED_PRIORITY_INVALID;
}
}
static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
int fd,
- enum amd_sched_priority priority)
+ enum drm_sched_priority priority)
{
struct file *filp = fcheck(fd);
struct drm_file *file;
@@ -86,11 +86,11 @@
{
union drm_amdgpu_sched *args = data;
struct amdgpu_device *adev = dev->dev_private;
- enum amd_sched_priority priority;
+ enum drm_sched_priority priority;
int r;
priority = amdgpu_to_sched_priority(args->in.priority);
- if (args->in.flags || priority == AMD_SCHED_PRIORITY_INVALID)
+ if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID)
return -EINVAL;
switch (args->in.op) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
index b28c067..2a1a0c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
@@ -27,7 +27,7 @@
#include <drm/drmP.h>
-enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority);
+enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority);
int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index a4bf21f..df65c66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -35,6 +35,7 @@
struct amdgpu_sync_entry {
struct hlist_node node;
struct dma_fence *fence;
+ bool explicit;
};
static struct kmem_cache *amdgpu_sync_slab;
@@ -63,7 +64,7 @@
static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
struct dma_fence *f)
{
- struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
+ struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
if (s_fence) {
struct amdgpu_ring *ring;
@@ -84,7 +85,7 @@
*/
static void *amdgpu_sync_get_owner(struct dma_fence *f)
{
- struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
+ struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
if (s_fence)
return s_fence->owner;
@@ -119,7 +120,7 @@
* Tries to add the fence to an existing hash entry. Returns true when an entry
* was found, false otherwise.
*/
-static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f)
+static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f, bool explicit)
{
struct amdgpu_sync_entry *e;
@@ -128,6 +129,10 @@
continue;
amdgpu_sync_keep_later(&e->fence, f);
+
+ /* Preserve eplicit flag to not loose pipe line sync */
+ e->explicit |= explicit;
+
return true;
}
return false;
@@ -141,24 +146,25 @@
*
*/
int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- struct dma_fence *f)
+ struct dma_fence *f, bool explicit)
{
struct amdgpu_sync_entry *e;
if (!f)
return 0;
-
if (amdgpu_sync_same_dev(adev, f) &&
amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
amdgpu_sync_keep_later(&sync->last_vm_update, f);
- if (amdgpu_sync_add_later(sync, f))
+ if (amdgpu_sync_add_later(sync, f, explicit))
return 0;
e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
if (!e)
return -ENOMEM;
+ e->explicit = explicit;
+
hash_add(sync->fences, &e->node, f->context);
e->fence = dma_fence_get(f);
return 0;
@@ -189,10 +195,7 @@
/* always sync to the exclusive fence */
f = reservation_object_get_excl(resv);
- r = amdgpu_sync_fence(adev, sync, f);
-
- if (explicit_sync)
- return r;
+ r = amdgpu_sync_fence(adev, sync, f, false);
flist = reservation_object_get_list(resv);
if (!flist || r)
@@ -212,15 +215,15 @@
(fence_owner == AMDGPU_FENCE_OWNER_VM)))
continue;
- /* Ignore fence from the same owner as
+ /* Ignore fence from the same owner and explicit one as
* long as it isn't undefined.
*/
if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
- fence_owner == owner)
+ (fence_owner == owner || explicit_sync))
continue;
}
- r = amdgpu_sync_fence(adev, sync, f);
+ r = amdgpu_sync_fence(adev, sync, f, false);
if (r)
break;
}
@@ -245,7 +248,7 @@
hash_for_each_safe(sync->fences, i, tmp, e, node) {
struct dma_fence *f = e->fence;
- struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
+ struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
if (dma_fence_is_signaled(f)) {
hash_del(&e->node);
@@ -275,19 +278,21 @@
* amdgpu_sync_get_fence - get the next fence from the sync object
*
* @sync: sync object to use
+ * @explicit: true if the next fence is explicit
*
* Get and removes the next fence from the sync object not signaled yet.
*/
-struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
+struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit)
{
struct amdgpu_sync_entry *e;
struct hlist_node *tmp;
struct dma_fence *f;
int i;
-
hash_for_each_safe(sync->fences, i, tmp, e, node) {
f = e->fence;
+ if (explicit)
+ *explicit = e->explicit;
hash_del(&e->node);
kmem_cache_free(amdgpu_sync_slab, e);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
index 70d7e3a..7aba38d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
@@ -41,7 +41,7 @@
void amdgpu_sync_create(struct amdgpu_sync *sync);
int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- struct dma_fence *f);
+ struct dma_fence *f, bool explicit);
int amdgpu_sync_resv(struct amdgpu_device *adev,
struct amdgpu_sync *sync,
struct reservation_object *resv,
@@ -49,7 +49,7 @@
bool explicit_sync);
struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
struct amdgpu_ring *ring);
-struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
+struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit);
int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
void amdgpu_sync_free(struct amdgpu_sync *sync);
int amdgpu_sync_init(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 06525f2..cace7a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -82,8 +82,8 @@
__field(unsigned, client_id)
__field(unsigned, src_id)
__field(unsigned, ring_id)
- __field(unsigned, vm_id)
- __field(unsigned, vm_id_src)
+ __field(unsigned, vmid)
+ __field(unsigned, vmid_src)
__field(uint64_t, timestamp)
__field(unsigned, timestamp_src)
__field(unsigned, pas_id)
@@ -93,8 +93,8 @@
__entry->client_id = iv->client_id;
__entry->src_id = iv->src_id;
__entry->ring_id = iv->ring_id;
- __entry->vm_id = iv->vm_id;
- __entry->vm_id_src = iv->vm_id_src;
+ __entry->vmid = iv->vmid;
+ __entry->vmid_src = iv->vmid_src;
__entry->timestamp = iv->timestamp;
__entry->timestamp_src = iv->timestamp_src;
__entry->pas_id = iv->pas_id;
@@ -103,9 +103,9 @@
__entry->src_data[2] = iv->src_data[2];
__entry->src_data[3] = iv->src_data[3];
),
- TP_printk("client_id:%u src_id:%u ring:%u vm_id:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n",
+ TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n",
__entry->client_id, __entry->src_id,
- __entry->ring_id, __entry->vm_id,
+ __entry->ring_id, __entry->vmid,
__entry->timestamp, __entry->pas_id,
__entry->src_data[0], __entry->src_data[1],
__entry->src_data[2], __entry->src_data[3])
@@ -219,7 +219,7 @@
TP_STRUCT__entry(
__field(struct amdgpu_vm *, vm)
__field(u32, ring)
- __field(u32, vm_id)
+ __field(u32, vmid)
__field(u32, vm_hub)
__field(u64, pd_addr)
__field(u32, needs_flush)
@@ -228,13 +228,13 @@
TP_fast_assign(
__entry->vm = vm;
__entry->ring = ring->idx;
- __entry->vm_id = job->vm_id;
+ __entry->vmid = job->vmid;
__entry->vm_hub = ring->funcs->vmhub,
__entry->pd_addr = job->vm_pd_addr;
__entry->needs_flush = job->vm_needs_flush;
),
TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u",
- __entry->vm, __entry->ring, __entry->vm_id,
+ __entry->vm, __entry->ring, __entry->vmid,
__entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
);
@@ -357,24 +357,24 @@
);
TRACE_EVENT(amdgpu_vm_flush,
- TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id,
+ TP_PROTO(struct amdgpu_ring *ring, unsigned vmid,
uint64_t pd_addr),
- TP_ARGS(ring, vm_id, pd_addr),
+ TP_ARGS(ring, vmid, pd_addr),
TP_STRUCT__entry(
__field(u32, ring)
- __field(u32, vm_id)
+ __field(u32, vmid)
__field(u32, vm_hub)
__field(u64, pd_addr)
),
TP_fast_assign(
__entry->ring = ring->idx;
- __entry->vm_id = vm_id;
+ __entry->vmid = vmid;
__entry->vm_hub = ring->funcs->vmhub;
__entry->pd_addr = pd_addr;
),
TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
- __entry->ring, __entry->vm_id,
+ __entry->ring, __entry->vmid,
__entry->vm_hub,__entry->pd_addr)
);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2c425a4..c0cd942 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -76,7 +76,7 @@
{
struct drm_global_reference *global_ref;
struct amdgpu_ring *ring;
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
int r;
adev->mman.mem_global_referenced = false;
@@ -108,8 +108,8 @@
mutex_init(&adev->mman.gtt_window_lock);
ring = adev->mman.buffer_funcs_ring;
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
- r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+ r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
rq, amdgpu_sched_jobs, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move run queue.\n");
@@ -131,7 +131,7 @@
static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
{
if (adev->mman.mem_global_referenced) {
- amd_sched_entity_fini(adev->mman.entity.sched,
+ drm_sched_entity_fini(adev->mman.entity.sched,
&adev->mman.entity);
mutex_destroy(&adev->mman.gtt_window_lock);
drm_global_item_unref(&adev->mman.bo_global_ref.ref);
@@ -282,8 +282,7 @@
{
uint64_t addr = 0;
- if (mem->mem_type != TTM_PL_TT ||
- amdgpu_gtt_mgr_is_allocated(mem)) {
+ if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
addr = mm_node->start << PAGE_SHIFT;
addr += bo->bdev->man[mem->mem_type].gpu_offset;
}
@@ -369,7 +368,7 @@
* dst to window 1
*/
if (src->mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_is_allocated(src->mem)) {
+ !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
r = amdgpu_map_buffer(src->bo, src->mem,
PFN_UP(cur_size + src_page_offset),
src_node_start, 0, ring,
@@ -383,7 +382,7 @@
}
if (dst->mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_is_allocated(dst->mem)) {
+ !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
r = amdgpu_map_buffer(dst->bo, dst->mem,
PFN_UP(cur_size + dst_page_offset),
dst_node_start, 1, ring,
@@ -467,9 +466,8 @@
return r;
}
-static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu,
+static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem)
{
struct amdgpu_device *adev;
@@ -489,8 +487,7 @@
placements.fpfn = 0;
placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
- interruptible, no_wait_gpu);
+ r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)) {
return r;
}
@@ -500,23 +497,22 @@
goto out_cleanup;
}
- r = ttm_tt_bind(bo->ttm, &tmp_mem);
+ r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
if (unlikely(r)) {
goto out_cleanup;
}
- r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
+ r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem);
if (unlikely(r)) {
goto out_cleanup;
}
- r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
+ r = ttm_bo_move_ttm(bo, ctx, new_mem);
out_cleanup:
ttm_bo_mem_put(bo, &tmp_mem);
return r;
}
-static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu,
+static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem)
{
struct amdgpu_device *adev;
@@ -536,16 +532,15 @@
placements.fpfn = 0;
placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
- interruptible, no_wait_gpu);
+ r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)) {
return r;
}
- r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
+ r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
if (unlikely(r)) {
goto out_cleanup;
}
- r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
+ r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
if (unlikely(r)) {
goto out_cleanup;
}
@@ -554,10 +549,9 @@
return r;
}
-static int amdgpu_bo_move(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu,
- struct ttm_mem_reg *new_mem)
+static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_mem)
{
struct amdgpu_device *adev;
struct amdgpu_bo *abo;
@@ -592,19 +586,18 @@
if (old_mem->mem_type == TTM_PL_VRAM &&
new_mem->mem_type == TTM_PL_SYSTEM) {
- r = amdgpu_move_vram_ram(bo, evict, interruptible,
- no_wait_gpu, new_mem);
+ r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
new_mem->mem_type == TTM_PL_VRAM) {
- r = amdgpu_move_ram_vram(bo, evict, interruptible,
- no_wait_gpu, new_mem);
+ r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
} else {
- r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
+ r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
+ new_mem, old_mem);
}
if (r) {
memcpy:
- r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
+ r = ttm_bo_move_memcpy(bo, ctx, new_mem);
if (r) {
return r;
}
@@ -690,7 +683,6 @@
struct list_head guptasks;
atomic_t mmu_invalidations;
uint32_t last_set_pages;
- struct list_head list;
};
int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
@@ -861,45 +853,36 @@
bo_mem->mem_type == AMDGPU_PL_OA)
return -EINVAL;
- if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
+ if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
+ gtt->offset = AMDGPU_BO_INVALID_OFFSET;
return 0;
+ }
- spin_lock(>t->adev->gtt_list_lock);
flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
ttm->pages, gtt->ttm.dma_address, flags);
- if (r) {
+ if (r)
DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
ttm->num_pages, gtt->offset);
- goto error_gart_bind;
- }
-
- list_add_tail(>t->list, >t->adev->gtt_list);
-error_gart_bind:
- spin_unlock(>t->adev->gtt_list_lock);
return r;
}
-bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
-{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
-
- return gtt && !list_empty(>t->list);
-}
-
-int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
+int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
- struct ttm_tt *ttm = bo->ttm;
+ struct ttm_operation_ctx ctx = { false, false };
+ struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
struct ttm_mem_reg tmp;
struct ttm_placement placement;
struct ttm_place placements;
+ uint64_t flags;
int r;
- if (!ttm || amdgpu_ttm_is_bound(ttm))
+ if (bo->mem.mem_type != TTM_PL_TT ||
+ amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
return 0;
tmp = bo->mem;
@@ -913,43 +896,44 @@
placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
+ r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
if (unlikely(r))
return r;
- r = ttm_bo_move_ttm(bo, true, false, &tmp);
- if (unlikely(r))
+ flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
+ gtt->offset = (u64)tmp.start << PAGE_SHIFT;
+ r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,
+ bo->ttm->pages, gtt->ttm.dma_address, flags);
+ if (unlikely(r)) {
ttm_bo_mem_put(bo, &tmp);
- else
- bo->offset = (bo->mem.start << PAGE_SHIFT) +
- bo->bdev->man[bo->mem.mem_type].gpu_offset;
+ return r;
+ }
- return r;
+ ttm_bo_mem_put(bo, &bo->mem);
+ bo->mem = tmp;
+ bo->offset = (bo->mem.start << PAGE_SHIFT) +
+ bo->bdev->man[bo->mem.mem_type].gpu_offset;
+
+ return 0;
}
-int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
+int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
{
- struct amdgpu_ttm_tt *gtt, *tmp;
- struct ttm_mem_reg bo_mem;
+ struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
+ struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm;
uint64_t flags;
int r;
- bo_mem.mem_type = TTM_PL_TT;
- spin_lock(&adev->gtt_list_lock);
- list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
- flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem);
- r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
- gtt->ttm.ttm.pages, gtt->ttm.dma_address,
- flags);
- if (r) {
- spin_unlock(&adev->gtt_list_lock);
- DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
- gtt->ttm.ttm.num_pages, gtt->offset);
- return r;
- }
- }
- spin_unlock(&adev->gtt_list_lock);
- return 0;
+ if (!gtt)
+ return 0;
+
+ flags = amdgpu_ttm_tt_pte_flags(adev, >t->ttm.ttm, &tbo->mem);
+ r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
+ gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);
+ if (r)
+ DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
+ gtt->ttm.ttm.num_pages, gtt->offset);
+ return r;
}
static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
@@ -960,20 +944,14 @@
if (gtt->userptr)
amdgpu_ttm_tt_unpin_userptr(ttm);
- if (!amdgpu_ttm_is_bound(ttm))
+ if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
return 0;
/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
- spin_lock(>t->adev->gtt_list_lock);
r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
- if (r) {
+ if (r)
DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
gtt->ttm.ttm.num_pages, gtt->offset);
- goto error_unbind;
- }
- list_del_init(>t->list);
-error_unbind:
- spin_unlock(>t->adev->gtt_list_lock);
return r;
}
@@ -1010,11 +988,11 @@
kfree(gtt);
return NULL;
}
- INIT_LIST_HEAD(>t->list);
return >t->ttm.ttm;
}
-static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
+static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -1042,11 +1020,11 @@
#ifdef CONFIG_SWIOTLB
if (swiotlb_nr_tbl()) {
- return ttm_dma_populate(>t->ttm, adev->dev);
+ return ttm_dma_populate(>t->ttm, adev->dev, ctx);
}
#endif
- return ttm_populate_and_map_pages(adev->dev, >t->ttm);
+ return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
}
static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -1293,6 +1271,101 @@
.access_memory = &amdgpu_ttm_access_memory
};
+/*
+ * Firmware Reservation functions
+ */
+/**
+ * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * free fw reserved vram if it has been reserved.
+ */
+static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
+{
+ amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
+ NULL, &adev->fw_vram_usage.va);
+}
+
+/**
+ * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * create bo vram reservation from fw.
+ */
+static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
+{
+ struct ttm_operation_ctx ctx = { false, false };
+ int r = 0;
+ int i;
+ u64 vram_size = adev->mc.visible_vram_size;
+ u64 offset = adev->fw_vram_usage.start_offset;
+ u64 size = adev->fw_vram_usage.size;
+ struct amdgpu_bo *bo;
+
+ adev->fw_vram_usage.va = NULL;
+ adev->fw_vram_usage.reserved_bo = NULL;
+
+ if (adev->fw_vram_usage.size > 0 &&
+ adev->fw_vram_usage.size <= vram_size) {
+
+ r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
+ PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
+ &adev->fw_vram_usage.reserved_bo);
+ if (r)
+ goto error_create;
+
+ r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
+ if (r)
+ goto error_reserve;
+
+ /* remove the original mem node and create a new one at the
+ * request position
+ */
+ bo = adev->fw_vram_usage.reserved_bo;
+ offset = ALIGN(offset, PAGE_SIZE);
+ for (i = 0; i < bo->placement.num_placement; ++i) {
+ bo->placements[i].fpfn = offset >> PAGE_SHIFT;
+ bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
+ }
+
+ ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
+ r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
+ &bo->tbo.mem, &ctx);
+ if (r)
+ goto error_pin;
+
+ r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ adev->fw_vram_usage.start_offset,
+ (adev->fw_vram_usage.start_offset +
+ adev->fw_vram_usage.size), NULL);
+ if (r)
+ goto error_pin;
+ r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
+ &adev->fw_vram_usage.va);
+ if (r)
+ goto error_kmap;
+
+ amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+ }
+ return r;
+
+error_kmap:
+ amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
+error_pin:
+ amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+error_reserve:
+ amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
+error_create:
+ adev->fw_vram_usage.va = NULL;
+ adev->fw_vram_usage.reserved_bo = NULL;
+ return r;
+}
+
int amdgpu_ttm_init(struct amdgpu_device *adev)
{
uint64_t gtt_size;
@@ -1335,7 +1408,7 @@
*The reserved vram for firmware must be pinned to the specified
*place on the VRAM, so reserve it early.
*/
- r = amdgpu_fw_reserve_vram_init(adev);
+ r = amdgpu_ttm_fw_reserve_vram_init(adev);
if (r) {
return r;
}
@@ -1349,9 +1422,14 @@
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
(unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
- if (amdgpu_gtt_size == -1)
- gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
- adev->mc.mc_vram_size);
+ if (amdgpu_gtt_size == -1) {
+ struct sysinfo si;
+
+ si_meminfo(&si);
+ gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+ adev->mc.mc_vram_size),
+ ((uint64_t)si.totalram * si.mem_unit * 3/4));
+ }
else
gtt_size = (uint64_t)amdgpu_gtt_size << 20;
r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
@@ -1411,19 +1489,13 @@
void amdgpu_ttm_fini(struct amdgpu_device *adev)
{
- int r;
-
if (!adev->mman.initialized)
return;
+
amdgpu_ttm_debugfs_fini(adev);
- if (adev->stolen_vga_memory) {
- r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
- if (r == 0) {
- amdgpu_bo_unpin(adev->stolen_vga_memory);
- amdgpu_bo_unreserve(adev->stolen_vga_memory);
- }
- amdgpu_bo_unref(&adev->stolen_vga_memory);
- }
+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
+ amdgpu_ttm_fw_reserve_vram_fini(adev);
+
ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
if (adev->gds.mem.total_size)
@@ -1433,7 +1505,6 @@
if (adev->gds.oa.total_size)
ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
ttm_bo_device_release(&adev->mman.bdev);
- amdgpu_gart_fini(adev);
amdgpu_ttm_global_fini(adev);
adev->mman.initialized = false;
DRM_INFO("amdgpu: ttm finalized\n");
@@ -1629,7 +1700,7 @@
}
if (bo->tbo.mem.mem_type == TTM_PL_TT) {
- r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
+ r = amdgpu_ttm_alloc_gart(&bo->tbo);
if (r)
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index abd4084..60fec521 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -25,7 +25,7 @@
#define __AMDGPU_TTM_H__
#include "amdgpu.h"
-#include "gpu_scheduler.h"
+#include <drm/gpu_scheduler.h>
#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
@@ -55,7 +55,7 @@
struct mutex gtt_window_lock;
/* Scheduler entity for buffer moves */
- struct amd_sched_entity entity;
+ struct drm_sched_entity entity;
};
struct amdgpu_copy_mem {
@@ -67,9 +67,11 @@
extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
-bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem);
+bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
+int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
+u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo);
uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
@@ -90,9 +92,8 @@
struct dma_fence **fence);
int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
-bool amdgpu_ttm_is_bound(struct ttm_tt *ttm);
-int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem);
-int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
+int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
+int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 6564902..474f88f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -359,7 +359,6 @@
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
- struct amdgpu_bo **bo = &adev->firmware.fw_buf;
uint64_t fw_offset = 0;
int i, err;
struct amdgpu_firmware_info *ucode = NULL;
@@ -370,36 +369,16 @@
return 0;
}
- if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
- err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
+ if (!adev->in_gpu_reset) {
+ err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
- NULL, NULL, 0, bo);
+ &adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
+ dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
goto failed;
}
-
- err = amdgpu_bo_reserve(*bo, false);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
- goto failed_reserve;
- }
-
- err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- &adev->firmware.fw_buf_mc);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
- goto failed_pin;
- }
-
- err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
- goto failed_kmap;
- }
-
- amdgpu_bo_unreserve(*bo);
}
memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
@@ -436,12 +415,6 @@
}
return 0;
-failed_kmap:
- amdgpu_bo_unpin(*bo);
-failed_pin:
- amdgpu_bo_unreserve(*bo);
-failed_reserve:
- amdgpu_bo_unref(bo);
failed:
if (err)
adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
@@ -464,8 +437,10 @@
ucode->kaddr = NULL;
}
}
- amdgpu_bo_unref(&adev->firmware.fw_buf);
- adev->firmware.fw_buf = NULL;
+
+ amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
+ &adev->firmware.fw_buf_mc,
+ &adev->firmware.fw_buf_ptr);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index af7e83d..c0c0ac2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -116,7 +116,7 @@
int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
unsigned long bo_size;
const char *fw_name;
const struct common_firmware_header *hdr;
@@ -230,8 +230,8 @@
}
ring = &adev->uvd.ring;
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+ r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity,
rq, amdgpu_sched_jobs, NULL);
if (r != 0) {
DRM_ERROR("Failed setting up UVD run queue.\n");
@@ -244,7 +244,7 @@
}
/* from uvd v5.0 HW addressing capacity increased to 64 bits */
- if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
+ if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
adev->uvd.address_64_bit = true;
switch (adev->asic_type) {
@@ -272,7 +272,7 @@
int i;
kfree(adev->uvd.saved_bo);
- amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
+ drm_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo,
&adev->uvd.gpu_addr,
@@ -297,18 +297,18 @@
if (adev->uvd.vcpu_bo == NULL)
return 0;
+ cancel_delayed_work_sync(&adev->uvd.idle_work);
+
/* only valid for physical mode */
if (adev->asic_type < CHIP_POLARIS10) {
for (i = 0; i < adev->uvd.max_handles; ++i)
if (atomic_read(&adev->uvd.handles[i]))
break;
- if (i == adev->uvd.max_handles)
+ if (i == adev->uvd.max_handles)
return 0;
}
- cancel_delayed_work_sync(&adev->uvd.idle_work);
-
size = amdgpu_bo_size(adev->uvd.vcpu_bo);
ptr = adev->uvd.cpu_addr;
@@ -349,6 +349,8 @@
ptr += le32_to_cpu(hdr->ucode_size_bytes);
}
memset_io(ptr, 0, size);
+ /* to restore uvd fence seq */
+ amdgpu_fence_driver_force_completion(&adev->uvd.ring);
}
return 0;
@@ -411,6 +413,7 @@
*/
static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
{
+ struct ttm_operation_ctx tctx = { false, false };
struct amdgpu_bo_va_mapping *mapping;
struct amdgpu_bo *bo;
uint32_t cmd;
@@ -433,7 +436,7 @@
}
amdgpu_uvd_force_into_uvd_segment(bo);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
}
return r;
@@ -952,6 +955,7 @@
static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
bool direct, struct dma_fence **fence)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct list_head head;
@@ -978,7 +982,7 @@
amdgpu_uvd_force_into_uvd_segment(bo);
}
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r)
goto err;
@@ -1154,10 +1158,10 @@
} else {
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_GATE);
}
} else {
schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
@@ -1177,10 +1181,10 @@
amdgpu_dpm_enable_uvd(adev, true);
} else {
amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_UNGATE);
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
}
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 3553b92..32ea20b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -31,6 +31,10 @@
#define AMDGPU_UVD_SESSION_SIZE (50*1024)
#define AMDGPU_UVD_FIRMWARE_OFFSET 256
+#define AMDGPU_UVD_FIRMWARE_SIZE(adev) \
+ (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
+ 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
+
struct amdgpu_uvd {
struct amdgpu_bo *vcpu_bo;
void *cpu_addr;
@@ -47,8 +51,8 @@
struct amdgpu_irq_src irq;
bool address_64_bit;
bool use_ctx_buf;
- struct amd_sched_entity entity;
- struct amd_sched_entity entity_enc;
+ struct drm_sched_entity entity;
+ struct drm_sched_entity entity_enc;
uint32_t srbm_soft_reset;
unsigned num_enc_rings;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 92477e6..d274ae5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -85,7 +85,7 @@
int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
{
struct amdgpu_ring *ring;
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
const char *fw_name;
const struct common_firmware_header *hdr;
unsigned ucode_version, version_major, version_minor, binary_id;
@@ -174,8 +174,8 @@
}
ring = &adev->vce.ring[0];
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+ r = drm_sched_entity_init(&ring->sched, &adev->vce.entity,
rq, amdgpu_sched_jobs, NULL);
if (r != 0) {
DRM_ERROR("Failed setting up VCE run queue.\n");
@@ -207,7 +207,7 @@
if (adev->vce.vcpu_bo == NULL)
return 0;
- amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
+ drm_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
(void **)&adev->vce.cpu_addr);
@@ -311,10 +311,10 @@
amdgpu_dpm_enable_vce(adev, false);
} else {
amdgpu_asic_set_vce_clocks(adev, 0, 0);
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_CG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_GATE);
}
} else {
schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
@@ -343,10 +343,10 @@
amdgpu_dpm_enable_vce(adev, true);
} else {
amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_CG_STATE_UNGATE);
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_UNGATE);
}
}
@@ -544,6 +544,55 @@
}
/**
+ * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
+ *
+ * @p: parser context
+ * @lo: address of lower dword
+ * @hi: address of higher dword
+ * @size: minimum size
+ * @index: bs/fb index
+ *
+ * Make sure that no BO cross a 4GB boundary.
+ */
+static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
+ int lo, int hi, unsigned size, int32_t index)
+{
+ int64_t offset = ((uint64_t)size) * ((int64_t)index);
+ struct ttm_operation_ctx ctx = { false, false };
+ struct amdgpu_bo_va_mapping *mapping;
+ unsigned i, fpfn, lpfn;
+ struct amdgpu_bo *bo;
+ uint64_t addr;
+ int r;
+
+ addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
+ ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
+ if (index >= 0) {
+ addr += offset;
+ fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
+ lpfn = 0x100000000ULL >> PAGE_SHIFT;
+ } else {
+ fpfn = 0;
+ lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
+ }
+
+ r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
+ if (r) {
+ DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
+ addr, lo, hi, size, index);
+ return r;
+ }
+
+ for (i = 0; i < bo->placement.num_placement; ++i) {
+ bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
+ bo->placements[i].lpfn = bo->placements[i].lpfn ?
+ min(bo->placements[i].lpfn, lpfn) : lpfn;
+ }
+ return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+}
+
+
+/**
* amdgpu_vce_cs_reloc - command submission relocation
*
* @p: parser context
@@ -648,12 +697,13 @@
uint32_t allocated = 0;
uint32_t tmp, handle = 0;
uint32_t *size = &tmp;
- int i, r = 0, idx = 0;
+ unsigned idx;
+ int i, r = 0;
p->job->vm = NULL;
ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
- while (idx < ib->length_dw) {
+ for (idx = 0; idx < ib->length_dw;) {
uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
@@ -664,6 +714,54 @@
}
switch (cmd) {
+ case 0x00000002: /* task info */
+ fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
+ bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
+ break;
+
+ case 0x03000001: /* encode */
+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
+ idx + 9, 0, 0);
+ if (r)
+ goto out;
+
+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
+ idx + 11, 0, 0);
+ if (r)
+ goto out;
+ break;
+
+ case 0x05000001: /* context buffer */
+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
+ idx + 2, 0, 0);
+ if (r)
+ goto out;
+ break;
+
+ case 0x05000004: /* video bitstream buffer */
+ tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
+ tmp, bs_idx);
+ if (r)
+ goto out;
+ break;
+
+ case 0x05000005: /* feedback buffer */
+ r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
+ 4096, fb_idx);
+ if (r)
+ goto out;
+ break;
+ }
+
+ idx += len / 4;
+ }
+
+ for (idx = 0; idx < ib->length_dw;) {
+ uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
+ uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
+
+ switch (cmd) {
case 0x00000001: /* session */
handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
session_idx = amdgpu_vce_validate_handle(p, handle,
@@ -893,7 +991,7 @@
*
*/
void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 5ce54cd..0fd378a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -46,7 +46,7 @@
struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
struct amdgpu_irq_src irq;
unsigned harvest_config;
- struct amd_sched_entity entity;
+ struct drm_sched_entity entity;
uint32_t srbm_soft_reset;
unsigned num_rings;
};
@@ -63,7 +63,7 @@
int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch);
+ unsigned vmid, bool ctx_switch);
void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
unsigned flags);
int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index dabaca4..c72e417d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -35,8 +35,7 @@
#include "soc15d.h"
#include "soc15_common.h"
-#include "vega10/soc15ip.h"
-#include "raven1/VCN/vcn_1_0_offset.h"
+#include "vcn/vcn_1_0_offset.h"
/* 1 second timeout */
#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
@@ -51,7 +50,7 @@
int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
unsigned long bo_size;
const char *fw_name;
const struct common_firmware_header *hdr;
@@ -85,6 +84,7 @@
}
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+ adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
@@ -104,8 +104,8 @@
}
ring = &adev->vcn.ring_dec;
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+ r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
rq, amdgpu_sched_jobs, NULL);
if (r != 0) {
DRM_ERROR("Failed setting up VCN dec run queue.\n");
@@ -113,8 +113,8 @@
}
ring = &adev->vcn.ring_enc[0];
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+ r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
rq, amdgpu_sched_jobs, NULL);
if (r != 0) {
DRM_ERROR("Failed setting up VCN enc run queue.\n");
@@ -130,9 +130,9 @@
kfree(adev->vcn.saved_bo);
- amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
+ drm_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
- amd_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc);
+ drm_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc);
amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
&adev->vcn.gpu_addr,
@@ -274,6 +274,7 @@
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
bool direct, struct dma_fence **fence)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct list_head head;
@@ -294,7 +295,7 @@
if (r)
return r;
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r)
goto err;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index d50ba06..2fd7db8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -56,8 +56,8 @@
struct amdgpu_ring ring_dec;
struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
struct amdgpu_irq_src irq;
- struct amd_sched_entity entity_dec;
- struct amd_sched_entity entity_enc;
+ struct drm_sched_entity entity_dec;
+ struct drm_sched_entity entity_enc;
unsigned num_enc_rings;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 6e44a94..e7dfb7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -24,6 +24,14 @@
#include "amdgpu.h"
#define MAX_KIQ_REG_WAIT 100000000 /* in usecs */
+bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
+{
+ /* By now all MMIO pages except mailbox are blocked */
+ /* if blocking is enabled in hypervisor. Choose the */
+ /* SCRATCH_REG0 to test. */
+ return RREG32_NO_KIQ(0xc040) == 0xffffffff;
+}
+
int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
{
int r;
@@ -39,6 +47,12 @@
return 0;
}
+void amdgpu_free_static_csa(struct amdgpu_device *adev) {
+ amdgpu_bo_free_kernel(&adev->virt.csa_obj,
+ &adev->virt.csa_vmid0_addr,
+ NULL);
+}
+
/*
* amdgpu_map_static_csa should be called during amdgpu_vm_init
* it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
@@ -107,8 +121,6 @@
adev->enable_virtual_display = true;
adev->cg_flags = 0;
adev->pg_flags = 0;
-
- mutex_init(&adev->virt.lock_reset);
}
uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
@@ -312,7 +324,6 @@
void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
{
- uint32_t pf2vf_ver = 0;
uint32_t pf2vf_size = 0;
uint32_t checksum = 0;
uint32_t checkval;
@@ -325,9 +336,9 @@
adev->virt.fw_reserve.p_pf2vf =
(struct amdgim_pf2vf_info_header *)(
adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
- pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version;
AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
+ AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);
/* pf2vf message must be in 4K */
if (pf2vf_size > 0 && pf2vf_size < 4096) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 0be2545..6a83425 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -81,6 +81,8 @@
AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
/* GIM supports feature of loading uCodes */
AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
+ /* VRAM LOST by GIM */
+ AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
};
struct amdgim_pf2vf_info_header {
@@ -239,7 +241,6 @@
uint64_t csa_vmid0_addr;
bool chained_ib_support;
uint32_t reg_val_offs;
- struct mutex lock_reset;
struct amdgpu_irq_src ack_irq;
struct amdgpu_irq_src rcv_irq;
struct work_struct flr_work;
@@ -247,6 +248,7 @@
const struct amdgpu_virt_ops *ops;
struct amdgpu_vf_error_buffer vf_errors;
struct amdgpu_virt_fw_reserve fw_reserve;
+ uint32_t gim_feature;
};
#define AMDGPU_CSA_SIZE (8 * 1024)
@@ -277,9 +279,11 @@
}
struct amdgpu_vm;
+bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev);
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo_va **bo_va);
+void amdgpu_free_static_csa(struct amdgpu_device *adev);
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1e727da..5afbc5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,52 +34,6 @@
#include "amdgpu_trace.h"
/*
- * PASID manager
- *
- * PASIDs are global address space identifiers that can be shared
- * between the GPU, an IOMMU and the driver. VMs on different devices
- * may use the same PASID if they share the same address
- * space. Therefore PASIDs are allocated using a global IDA. VMs are
- * looked up from the PASID per amdgpu_device.
- */
-static DEFINE_IDA(amdgpu_vm_pasid_ida);
-
-/**
- * amdgpu_vm_alloc_pasid - Allocate a PASID
- * @bits: Maximum width of the PASID in bits, must be at least 1
- *
- * Allocates a PASID of the given width while keeping smaller PASIDs
- * available if possible.
- *
- * Returns a positive integer on success. Returns %-EINVAL if bits==0.
- * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
- * memory allocation failure.
- */
-int amdgpu_vm_alloc_pasid(unsigned int bits)
-{
- int pasid = -EINVAL;
-
- for (bits = min(bits, 31U); bits > 0; bits--) {
- pasid = ida_simple_get(&amdgpu_vm_pasid_ida,
- 1U << (bits - 1), 1U << bits,
- GFP_KERNEL);
- if (pasid != -ENOSPC)
- break;
- }
-
- return pasid;
-}
-
-/**
- * amdgpu_vm_free_pasid - Free a PASID
- * @pasid: PASID to free
- */
-void amdgpu_vm_free_pasid(unsigned int pasid)
-{
- ida_simple_remove(&amdgpu_vm_pasid_ida, pasid);
-}
-
-/*
* GPUVM
* GPUVM is similar to the legacy gart on older asics, however
* rather than there being a single global gart table
@@ -139,6 +93,35 @@
};
/**
+ * amdgpu_vm_level_shift - return the addr shift for each level
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns the number of bits the pfn needs to be right shifted for a level.
+ */
+static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
+ unsigned level)
+{
+ unsigned shift = 0xff;
+
+ switch (level) {
+ case AMDGPU_VM_PDB2:
+ case AMDGPU_VM_PDB1:
+ case AMDGPU_VM_PDB0:
+ shift = 9 * (AMDGPU_VM_PDB0 - level) +
+ adev->vm_manager.block_size;
+ break;
+ case AMDGPU_VM_PTB:
+ shift = 0;
+ break;
+ default:
+ dev_err(adev->dev, "the level%d isn't supported.\n", level);
+ }
+
+ return shift;
+}
+
+/**
* amdgpu_vm_num_entries - return the number of entries in a PD/PT
*
* @adev: amdgpu_device pointer
@@ -148,17 +131,18 @@
static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
unsigned level)
{
- if (level == 0)
+ unsigned shift = amdgpu_vm_level_shift(adev,
+ adev->vm_manager.root_level);
+
+ if (level == adev->vm_manager.root_level)
/* For the root directory */
- return adev->vm_manager.max_pfn >>
- (adev->vm_manager.block_size *
- adev->vm_manager.num_level);
- else if (level == adev->vm_manager.num_level)
+ return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
+ else if (level != AMDGPU_VM_PTB)
+ /* Everything in between */
+ return 512;
+ else
/* For the page tables on the leaves */
return AMDGPU_VM_PTE_COUNT(adev);
- else
- /* Everything in between */
- return 1 << adev->vm_manager.block_size;
}
/**
@@ -288,8 +272,7 @@
uint64_t saddr, uint64_t eaddr,
unsigned level)
{
- unsigned shift = (adev->vm_manager.num_level - level) *
- adev->vm_manager.block_size;
+ unsigned shift = amdgpu_vm_level_shift(adev, level);
unsigned pt_idx, from, to;
int r;
u64 flags;
@@ -312,9 +295,6 @@
to >= amdgpu_vm_num_entries(adev, level))
return -EINVAL;
- if (to > parent->last_entry_used)
- parent->last_entry_used = to;
-
++level;
saddr = saddr & ((1 << shift) - 1);
eaddr = eaddr & ((1 << shift) - 1);
@@ -329,7 +309,7 @@
if (vm->pte_support_ats) {
init_value = AMDGPU_PTE_DEFAULT_ATC;
- if (level != adev->vm_manager.num_level - 1)
+ if (level != AMDGPU_VM_PTB)
init_value |= AMDGPU_PDE_PTE;
}
@@ -369,10 +349,9 @@
spin_lock(&vm->status_lock);
list_add(&entry->base.vm_status, &vm->relocated);
spin_unlock(&vm->status_lock);
- entry->addr = 0;
}
- if (level < adev->vm_manager.num_level) {
+ if (level < AMDGPU_VM_PTB) {
uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
((1 << shift) - 1);
@@ -418,287 +397,8 @@
saddr /= AMDGPU_GPU_PAGE_SIZE;
eaddr /= AMDGPU_GPU_PAGE_SIZE;
- return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
-}
-
-/**
- * amdgpu_vm_had_gpu_reset - check if reset occured since last use
- *
- * @adev: amdgpu_device pointer
- * @id: VMID structure
- *
- * Check if GPU reset occured since last use of the VMID.
- */
-static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
- struct amdgpu_vm_id *id)
-{
- return id->current_gpu_reset_count !=
- atomic_read(&adev->gpu_reset_counter);
-}
-
-static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub)
-{
- return !!vm->reserved_vmid[vmhub];
-}
-
-/* idr_mgr->lock must be held */
-static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm,
- struct amdgpu_ring *ring,
- struct amdgpu_sync *sync,
- struct dma_fence *fence,
- struct amdgpu_job *job)
-{
- struct amdgpu_device *adev = ring->adev;
- unsigned vmhub = ring->funcs->vmhub;
- uint64_t fence_context = adev->fence_context + ring->idx;
- struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub];
- struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
- struct dma_fence *updates = sync->last_vm_update;
- int r = 0;
- struct dma_fence *flushed, *tmp;
- bool needs_flush = vm->use_cpu_for_update;
-
- flushed = id->flushed_updates;
- if ((amdgpu_vm_had_gpu_reset(adev, id)) ||
- (atomic64_read(&id->owner) != vm->client_id) ||
- (job->vm_pd_addr != id->pd_gpu_addr) ||
- (updates && (!flushed || updates->context != flushed->context ||
- dma_fence_is_later(updates, flushed))) ||
- (!id->last_flush || (id->last_flush->context != fence_context &&
- !dma_fence_is_signaled(id->last_flush)))) {
- needs_flush = true;
- /* to prevent one context starved by another context */
- id->pd_gpu_addr = 0;
- tmp = amdgpu_sync_peek_fence(&id->active, ring);
- if (tmp) {
- r = amdgpu_sync_fence(adev, sync, tmp);
- return r;
- }
- }
-
- /* Good we can use this VMID. Remember this submission as
- * user of the VMID.
- */
- r = amdgpu_sync_fence(ring->adev, &id->active, fence);
- if (r)
- goto out;
-
- if (updates && (!flushed || updates->context != flushed->context ||
- dma_fence_is_later(updates, flushed))) {
- dma_fence_put(id->flushed_updates);
- id->flushed_updates = dma_fence_get(updates);
- }
- id->pd_gpu_addr = job->vm_pd_addr;
- atomic64_set(&id->owner, vm->client_id);
- job->vm_needs_flush = needs_flush;
- if (needs_flush) {
- dma_fence_put(id->last_flush);
- id->last_flush = NULL;
- }
- job->vm_id = id - id_mgr->ids;
- trace_amdgpu_vm_grab_id(vm, ring, job);
-out:
- return r;
-}
-
-/**
- * amdgpu_vm_grab_id - allocate the next free VMID
- *
- * @vm: vm to allocate id for
- * @ring: ring we want to submit job to
- * @sync: sync object where we add dependencies
- * @fence: fence protecting ID from reuse
- *
- * Allocate an id for the vm, adding fences to the sync obj as necessary.
- */
-int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- struct amdgpu_sync *sync, struct dma_fence *fence,
- struct amdgpu_job *job)
-{
- struct amdgpu_device *adev = ring->adev;
- unsigned vmhub = ring->funcs->vmhub;
- struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
- uint64_t fence_context = adev->fence_context + ring->idx;
- struct dma_fence *updates = sync->last_vm_update;
- struct amdgpu_vm_id *id, *idle;
- struct dma_fence **fences;
- unsigned i;
- int r = 0;
-
- mutex_lock(&id_mgr->lock);
- if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) {
- r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job);
- mutex_unlock(&id_mgr->lock);
- return r;
- }
- fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
- if (!fences) {
- mutex_unlock(&id_mgr->lock);
- return -ENOMEM;
- }
- /* Check if we have an idle VMID */
- i = 0;
- list_for_each_entry(idle, &id_mgr->ids_lru, list) {
- fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
- if (!fences[i])
- break;
- ++i;
- }
-
- /* If we can't find a idle VMID to use, wait till one becomes available */
- if (&idle->list == &id_mgr->ids_lru) {
- u64 fence_context = adev->vm_manager.fence_context + ring->idx;
- unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
- struct dma_fence_array *array;
- unsigned j;
-
- for (j = 0; j < i; ++j)
- dma_fence_get(fences[j]);
-
- array = dma_fence_array_create(i, fences, fence_context,
- seqno, true);
- if (!array) {
- for (j = 0; j < i; ++j)
- dma_fence_put(fences[j]);
- kfree(fences);
- r = -ENOMEM;
- goto error;
- }
-
-
- r = amdgpu_sync_fence(ring->adev, sync, &array->base);
- dma_fence_put(&array->base);
- if (r)
- goto error;
-
- mutex_unlock(&id_mgr->lock);
- return 0;
-
- }
- kfree(fences);
-
- job->vm_needs_flush = vm->use_cpu_for_update;
- /* Check if we can use a VMID already assigned to this VM */
- list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
- struct dma_fence *flushed;
- bool needs_flush = vm->use_cpu_for_update;
-
- /* Check all the prerequisites to using this VMID */
- if (amdgpu_vm_had_gpu_reset(adev, id))
- continue;
-
- if (atomic64_read(&id->owner) != vm->client_id)
- continue;
-
- if (job->vm_pd_addr != id->pd_gpu_addr)
- continue;
-
- if (!id->last_flush ||
- (id->last_flush->context != fence_context &&
- !dma_fence_is_signaled(id->last_flush)))
- needs_flush = true;
-
- flushed = id->flushed_updates;
- if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
- needs_flush = true;
-
- /* Concurrent flushes are only possible starting with Vega10 */
- if (adev->asic_type < CHIP_VEGA10 && needs_flush)
- continue;
-
- /* Good we can use this VMID. Remember this submission as
- * user of the VMID.
- */
- r = amdgpu_sync_fence(ring->adev, &id->active, fence);
- if (r)
- goto error;
-
- if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
- dma_fence_put(id->flushed_updates);
- id->flushed_updates = dma_fence_get(updates);
- }
-
- if (needs_flush)
- goto needs_flush;
- else
- goto no_flush_needed;
-
- };
-
- /* Still no ID to use? Then use the idle one found earlier */
- id = idle;
-
- /* Remember this submission as user of the VMID */
- r = amdgpu_sync_fence(ring->adev, &id->active, fence);
- if (r)
- goto error;
-
- id->pd_gpu_addr = job->vm_pd_addr;
- dma_fence_put(id->flushed_updates);
- id->flushed_updates = dma_fence_get(updates);
- atomic64_set(&id->owner, vm->client_id);
-
-needs_flush:
- job->vm_needs_flush = true;
- dma_fence_put(id->last_flush);
- id->last_flush = NULL;
-
-no_flush_needed:
- list_move_tail(&id->list, &id_mgr->ids_lru);
-
- job->vm_id = id - id_mgr->ids;
- trace_amdgpu_vm_grab_id(vm, ring, job);
-
-error:
- mutex_unlock(&id_mgr->lock);
- return r;
-}
-
-static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- unsigned vmhub)
-{
- struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
-
- mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub]) {
- list_add(&vm->reserved_vmid[vmhub]->list,
- &id_mgr->ids_lru);
- vm->reserved_vmid[vmhub] = NULL;
- atomic_dec(&id_mgr->reserved_vmid_num);
- }
- mutex_unlock(&id_mgr->lock);
-}
-
-static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- unsigned vmhub)
-{
- struct amdgpu_vm_id_manager *id_mgr;
- struct amdgpu_vm_id *idle;
- int r = 0;
-
- id_mgr = &adev->vm_manager.id_mgr[vmhub];
- mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub])
- goto unlock;
- if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
- AMDGPU_VM_MAX_RESERVED_VMID) {
- DRM_ERROR("Over limitation of reserved vmid\n");
- atomic_dec(&id_mgr->reserved_vmid_num);
- r = -EINVAL;
- goto unlock;
- }
- /* Select the first entry VMID */
- idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list);
- list_del_init(&idle->list);
- vm->reserved_vmid[vmhub] = idle;
- mutex_unlock(&id_mgr->lock);
-
- return 0;
-unlock:
- mutex_unlock(&id_mgr->lock);
- return r;
+ return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
+ adev->vm_manager.root_level);
}
/**
@@ -715,7 +415,7 @@
has_compute_vm_bug = false;
- ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
+ ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
if (ip_block) {
/* Compute has a VM bug for GFX version < 7.
Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
@@ -741,14 +441,14 @@
{
struct amdgpu_device *adev = ring->adev;
unsigned vmhub = ring->funcs->vmhub;
- struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
- struct amdgpu_vm_id *id;
+ struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+ struct amdgpu_vmid *id;
bool gds_switch_needed;
bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
- if (job->vm_id == 0)
+ if (job->vmid == 0)
return false;
- id = &id_mgr->ids[job->vm_id];
+ id = &id_mgr->ids[job->vmid];
gds_switch_needed = ring->funcs->emit_gds_switch && (
id->gds_base != job->gds_base ||
id->gds_size != job->gds_size ||
@@ -757,7 +457,7 @@
id->oa_base != job->oa_base ||
id->oa_size != job->oa_size);
- if (amdgpu_vm_had_gpu_reset(adev, id))
+ if (amdgpu_vmid_had_gpu_reset(adev, id))
return true;
return vm_flush_needed || gds_switch_needed;
@@ -772,7 +472,7 @@
* amdgpu_vm_flush - hardware flush the vm
*
* @ring: ring to use for flush
- * @vm_id: vmid number to use
+ * @vmid: vmid number to use
* @pd_addr: address of the page directory
*
* Emit a VM flush when it is necessary.
@@ -781,8 +481,8 @@
{
struct amdgpu_device *adev = ring->adev;
unsigned vmhub = ring->funcs->vmhub;
- struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
- struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
+ struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+ struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
bool gds_switch_needed = ring->funcs->emit_gds_switch && (
id->gds_base != job->gds_base ||
id->gds_size != job->gds_size ||
@@ -794,7 +494,7 @@
unsigned patch_offset = 0;
int r;
- if (amdgpu_vm_had_gpu_reset(adev, id)) {
+ if (amdgpu_vmid_had_gpu_reset(adev, id)) {
gds_switch_needed = true;
vm_flush_needed = true;
}
@@ -811,8 +511,8 @@
if (ring->funcs->emit_vm_flush && vm_flush_needed) {
struct dma_fence *fence;
- trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr);
- amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
+ trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
+ amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
r = amdgpu_fence_emit(ring, &fence);
if (r)
@@ -832,7 +532,7 @@
id->gws_size = job->gws_size;
id->oa_base = job->oa_base;
id->oa_size = job->oa_size;
- amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
+ amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
job->gds_size, job->gws_base,
job->gws_size, job->oa_base,
job->oa_size);
@@ -850,49 +550,6 @@
}
/**
- * amdgpu_vm_reset_id - reset VMID to zero
- *
- * @adev: amdgpu device structure
- * @vm_id: vmid number to use
- *
- * Reset saved GDW, GWS and OA to force switch on next flush.
- */
-void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
- unsigned vmid)
-{
- struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
- struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
-
- atomic64_set(&id->owner, 0);
- id->gds_base = 0;
- id->gds_size = 0;
- id->gws_base = 0;
- id->gws_size = 0;
- id->oa_base = 0;
- id->oa_size = 0;
-}
-
-/**
- * amdgpu_vm_reset_all_id - reset VMID to zero
- *
- * @adev: amdgpu device structure
- *
- * Reset VMID to force flush on next use
- */
-void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
-{
- unsigned i, j;
-
- for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
- struct amdgpu_vm_id_manager *id_mgr =
- &adev->vm_manager.id_mgr[i];
-
- for (j = 1; j < id_mgr->num_ids; ++j)
- amdgpu_vm_reset_id(adev, i, j);
- }
-}
-
-/**
* amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
*
* @vm: requested vm
@@ -1043,162 +700,52 @@
}
/*
- * amdgpu_vm_update_level - update a single level in the hierarchy
+ * amdgpu_vm_update_pde - update a single level in the hierarchy
*
- * @adev: amdgpu_device pointer
+ * @param: parameters for the update
* @vm: requested vm
* @parent: parent directory
+ * @entry: entry to update
*
- * Makes sure all entries in @parent are up to date.
- * Returns 0 for success, error for failure.
+ * Makes sure the requested entry in parent is up to date.
*/
-static int amdgpu_vm_update_level(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct amdgpu_vm_pt *parent)
+static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
+ struct amdgpu_vm *vm,
+ struct amdgpu_vm_pt *parent,
+ struct amdgpu_vm_pt *entry)
{
- struct amdgpu_bo *shadow;
- struct amdgpu_ring *ring = NULL;
+ struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL, *pbo;
uint64_t pd_addr, shadow_addr = 0;
- uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
- unsigned count = 0, pt_idx, ndw = 0;
- struct amdgpu_job *job;
- struct amdgpu_pte_update_params params;
- struct dma_fence *fence = NULL;
- uint32_t incr;
+ uint64_t pde, pt, flags;
+ unsigned level;
- int r;
-
- if (!parent->entries)
- return 0;
-
- memset(¶ms, 0, sizeof(params));
- params.adev = adev;
- shadow = parent->base.bo->shadow;
+ /* Don't update huge pages here */
+ if (entry->huge)
+ return;
if (vm->use_cpu_for_update) {
pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
- r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
- if (unlikely(r))
- return r;
-
- params.func = amdgpu_vm_cpu_set_ptes;
} else {
- ring = container_of(vm->entity.sched, struct amdgpu_ring,
- sched);
-
- /* padding, etc. */
- ndw = 64;
-
- /* assume the worst case */
- ndw += parent->last_entry_used * 6;
-
pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
-
- if (shadow) {
+ shadow = parent->base.bo->shadow;
+ if (shadow)
shadow_addr = amdgpu_bo_gpu_offset(shadow);
- ndw *= 2;
- } else {
- shadow_addr = 0;
- }
-
- r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
- if (r)
- return r;
-
- params.ib = &job->ibs[0];
- params.func = amdgpu_vm_do_set_ptes;
}
+ for (level = 0, pbo = parent->base.bo->parent; pbo; ++level)
+ pbo = pbo->parent;
- /* walk over the address space and update the directory */
- for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
- struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
- struct amdgpu_bo *bo = entry->base.bo;
- uint64_t pde, pt;
-
- if (bo == NULL)
- continue;
-
- spin_lock(&vm->status_lock);
- list_del_init(&entry->base.vm_status);
- spin_unlock(&vm->status_lock);
-
- pt = amdgpu_bo_gpu_offset(bo);
- pt = amdgpu_gart_get_vm_pde(adev, pt);
- /* Don't update huge pages here */
- if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) ||
- parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID))
- continue;
-
- parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID;
-
- pde = pd_addr + pt_idx * 8;
- incr = amdgpu_bo_size(bo);
- if (((last_pde + 8 * count) != pde) ||
- ((last_pt + incr * count) != pt) ||
- (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
-
- if (count) {
- if (shadow)
- params.func(¶ms,
- last_shadow,
- last_pt, count,
- incr,
- AMDGPU_PTE_VALID);
-
- params.func(¶ms, last_pde,
- last_pt, count, incr,
- AMDGPU_PTE_VALID);
- }
-
- count = 1;
- last_pde = pde;
- last_shadow = shadow_addr + pt_idx * 8;
- last_pt = pt;
- } else {
- ++count;
- }
+ level += params->adev->vm_manager.root_level;
+ pt = amdgpu_bo_gpu_offset(bo);
+ flags = AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags);
+ if (shadow) {
+ pde = shadow_addr + (entry - parent->entries) * 8;
+ params->func(params, pde, pt, 1, 0, flags);
}
- if (count) {
- if (vm->root.base.bo->shadow)
- params.func(¶ms, last_shadow, last_pt,
- count, incr, AMDGPU_PTE_VALID);
-
- params.func(¶ms, last_pde, last_pt,
- count, incr, AMDGPU_PTE_VALID);
- }
-
- if (!vm->use_cpu_for_update) {
- if (params.ib->length_dw == 0) {
- amdgpu_job_free(job);
- } else {
- amdgpu_ring_pad_ib(ring, params.ib);
- amdgpu_sync_resv(adev, &job->sync,
- parent->base.bo->tbo.resv,
- AMDGPU_FENCE_OWNER_VM, false);
- if (shadow)
- amdgpu_sync_resv(adev, &job->sync,
- shadow->tbo.resv,
- AMDGPU_FENCE_OWNER_VM, false);
-
- WARN_ON(params.ib->length_dw > ndw);
- r = amdgpu_job_submit(job, ring, &vm->entity,
- AMDGPU_FENCE_OWNER_VM, &fence);
- if (r)
- goto error_free;
-
- amdgpu_bo_fence(parent->base.bo, fence, true);
- dma_fence_put(vm->last_update);
- vm->last_update = fence;
- }
- }
-
- return 0;
-
-error_free:
- amdgpu_job_free(job);
- return r;
+ pde = pd_addr + (entry - parent->entries) * 8;
+ params->func(params, pde, pt, 1, 0, flags);
}
/*
@@ -1208,27 +755,29 @@
*
* Mark all PD level as invalid after an error.
*/
-static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm,
- struct amdgpu_vm_pt *parent)
+static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ struct amdgpu_vm_pt *parent,
+ unsigned level)
{
- unsigned pt_idx;
+ unsigned pt_idx, num_entries;
/*
* Recurse into the subdirectories. This recursion is harmless because
* we only have a maximum of 5 layers.
*/
- for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
+ num_entries = amdgpu_vm_num_entries(adev, level);
+ for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
if (!entry->base.bo)
continue;
- entry->addr = ~0ULL;
spin_lock(&vm->status_lock);
if (list_empty(&entry->base.vm_status))
list_add(&entry->base.vm_status, &vm->relocated);
spin_unlock(&vm->status_lock);
- amdgpu_vm_invalidate_level(vm, entry);
+ amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
}
}
@@ -1244,38 +793,63 @@
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
{
+ struct amdgpu_pte_update_params params;
+ struct amdgpu_job *job;
+ unsigned ndw = 0;
int r = 0;
+ if (list_empty(&vm->relocated))
+ return 0;
+
+restart:
+ memset(¶ms, 0, sizeof(params));
+ params.adev = adev;
+
+ if (vm->use_cpu_for_update) {
+ r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
+ if (unlikely(r))
+ return r;
+
+ params.func = amdgpu_vm_cpu_set_ptes;
+ } else {
+ ndw = 512 * 8;
+ r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
+ if (r)
+ return r;
+
+ params.ib = &job->ibs[0];
+ params.func = amdgpu_vm_do_set_ptes;
+ }
+
spin_lock(&vm->status_lock);
while (!list_empty(&vm->relocated)) {
- struct amdgpu_vm_bo_base *bo_base;
+ struct amdgpu_vm_bo_base *bo_base, *parent;
+ struct amdgpu_vm_pt *pt, *entry;
struct amdgpu_bo *bo;
bo_base = list_first_entry(&vm->relocated,
struct amdgpu_vm_bo_base,
vm_status);
+ list_del_init(&bo_base->vm_status);
spin_unlock(&vm->status_lock);
bo = bo_base->bo->parent;
- if (bo) {
- struct amdgpu_vm_bo_base *parent;
- struct amdgpu_vm_pt *pt;
-
- parent = list_first_entry(&bo->va,
- struct amdgpu_vm_bo_base,
- bo_list);
- pt = container_of(parent, struct amdgpu_vm_pt, base);
-
- r = amdgpu_vm_update_level(adev, vm, pt);
- if (r) {
- amdgpu_vm_invalidate_level(vm, &vm->root);
- return r;
- }
+ if (!bo) {
spin_lock(&vm->status_lock);
- } else {
- spin_lock(&vm->status_lock);
- list_del_init(&bo_base->vm_status);
+ continue;
}
+
+ parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
+ bo_list);
+ pt = container_of(parent, struct amdgpu_vm_pt, base);
+ entry = container_of(bo_base, struct amdgpu_vm_pt, base);
+
+ amdgpu_vm_update_pde(¶ms, vm, pt, entry);
+
+ spin_lock(&vm->status_lock);
+ if (!vm->use_cpu_for_update &&
+ (ndw - params.ib->length_dw) < 32)
+ break;
}
spin_unlock(&vm->status_lock);
@@ -1283,8 +857,44 @@
/* Flush HDP */
mb();
amdgpu_gart_flush_gpu_tlb(adev, 0);
+ } else if (params.ib->length_dw == 0) {
+ amdgpu_job_free(job);
+ } else {
+ struct amdgpu_bo *root = vm->root.base.bo;
+ struct amdgpu_ring *ring;
+ struct dma_fence *fence;
+
+ ring = container_of(vm->entity.sched, struct amdgpu_ring,
+ sched);
+
+ amdgpu_ring_pad_ib(ring, params.ib);
+ amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
+ AMDGPU_FENCE_OWNER_VM, false);
+ if (root->shadow)
+ amdgpu_sync_resv(adev, &job->sync,
+ root->shadow->tbo.resv,
+ AMDGPU_FENCE_OWNER_VM, false);
+
+ WARN_ON(params.ib->length_dw > ndw);
+ r = amdgpu_job_submit(job, ring, &vm->entity,
+ AMDGPU_FENCE_OWNER_VM, &fence);
+ if (r)
+ goto error;
+
+ amdgpu_bo_fence(root, fence, true);
+ dma_fence_put(vm->last_update);
+ vm->last_update = fence;
}
+ if (!list_empty(&vm->relocated))
+ goto restart;
+
+ return 0;
+
+error:
+ amdgpu_vm_invalidate_level(adev, vm, &vm->root,
+ adev->vm_manager.root_level);
+ amdgpu_job_free(job);
return r;
}
@@ -1302,18 +912,19 @@
struct amdgpu_vm_pt **entry,
struct amdgpu_vm_pt **parent)
{
- unsigned idx, level = p->adev->vm_manager.num_level;
+ unsigned level = p->adev->vm_manager.root_level;
*parent = NULL;
*entry = &p->vm->root;
while ((*entry)->entries) {
- idx = addr >> (p->adev->vm_manager.block_size * level--);
- idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
+ unsigned shift = amdgpu_vm_level_shift(p->adev, level++);
+
*parent = *entry;
- *entry = &(*entry)->entries[idx];
+ *entry = &(*entry)->entries[addr >> shift];
+ addr &= (1ULL << shift) - 1;
}
- if (level)
+ if (level != AMDGPU_VM_PTB)
*entry = NULL;
}
@@ -1335,56 +946,42 @@
unsigned nptes, uint64_t dst,
uint64_t flags)
{
- bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes);
uint64_t pd_addr, pde;
/* In the case of a mixed PT the PDE must point to it*/
- if (p->adev->asic_type < CHIP_VEGA10 ||
- nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
- p->src ||
- !(flags & AMDGPU_PTE_VALID)) {
-
- dst = amdgpu_bo_gpu_offset(entry->base.bo);
- dst = amdgpu_gart_get_vm_pde(p->adev, dst);
- flags = AMDGPU_PTE_VALID;
- } else {
+ if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
+ nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
/* Set the huge page flag to stop scanning at this PDE */
flags |= AMDGPU_PDE_PTE;
}
- if (entry->addr == (dst | flags))
+ if (!(flags & AMDGPU_PDE_PTE)) {
+ if (entry->huge) {
+ /* Add the entry to the relocated list to update it. */
+ entry->huge = false;
+ spin_lock(&p->vm->status_lock);
+ list_move(&entry->base.vm_status, &p->vm->relocated);
+ spin_unlock(&p->vm->status_lock);
+ }
return;
+ }
- entry->addr = (dst | flags);
+ entry->huge = true;
+ amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0,
+ &dst, &flags);
- if (use_cpu_update) {
- /* In case a huge page is replaced with a system
- * memory mapping, p->pages_addr != NULL and
- * amdgpu_vm_cpu_set_ptes would try to translate dst
- * through amdgpu_vm_map_gart. But dst is already a
- * GPU address (of the page table). Disable
- * amdgpu_vm_map_gart temporarily.
- */
- dma_addr_t *tmp;
-
- tmp = p->pages_addr;
- p->pages_addr = NULL;
-
+ if (p->func == amdgpu_vm_cpu_set_ptes) {
pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
- pde = pd_addr + (entry - parent->entries) * 8;
- amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
-
- p->pages_addr = tmp;
} else {
if (parent->base.bo->shadow) {
pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
pde = pd_addr + (entry - parent->entries) * 8;
- amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
+ p->func(p, pde, dst, 1, 0, flags);
}
pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
- pde = pd_addr + (entry - parent->entries) * 8;
- amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
}
+ pde = pd_addr + (entry - parent->entries) * 8;
+ p->func(p, pde, dst, 1, 0, flags);
}
/**
@@ -1429,7 +1026,7 @@
amdgpu_vm_handle_huge_pages(params, entry, parent,
nptes, dst, flags);
/* We don't need to update PTEs for huge pages */
- if (entry->addr & AMDGPU_PDE_PTE)
+ if (entry->huge)
continue;
pt = entry->base.bo;
@@ -1588,14 +1185,14 @@
*
* The second command is for the shadow pagetables.
*/
- ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
+ if (vm->root.base.bo->shadow)
+ ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
+ else
+ ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
/* padding, etc. */
ndw = 64;
- /* one PDE write for each huge page */
- ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
-
if (pages_addr) {
/* copy commands needed */
ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
@@ -1639,7 +1236,7 @@
addr = 0;
}
- r = amdgpu_sync_fence(adev, &job->sync, exclusive);
+ r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
if (r)
goto error_free;
@@ -1670,7 +1267,6 @@
error_free:
amdgpu_job_free(job);
- amdgpu_vm_invalidate_level(vm, &vm->root);
return r;
}
@@ -2081,18 +1677,31 @@
spin_lock(&vm->status_lock);
while (!list_empty(&vm->moved)) {
struct amdgpu_bo_va *bo_va;
+ struct reservation_object *resv;
bo_va = list_first_entry(&vm->moved,
struct amdgpu_bo_va, base.vm_status);
spin_unlock(&vm->status_lock);
+ resv = bo_va->base.bo->tbo.resv;
+
/* Per VM BOs never need to bo cleared in the page tables */
- clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv;
+ if (resv == vm->root.base.bo->tbo.resv)
+ clear = false;
+ /* Try to reserve the BO to avoid clearing its ptes */
+ else if (!amdgpu_vm_debug && reservation_object_trylock(resv))
+ clear = false;
+ /* Somebody else is using the BO right now */
+ else
+ clear = true;
r = amdgpu_vm_bo_update(adev, bo_va, clear);
if (r)
return r;
+ if (!clear && resv != vm->root.base.bo->tbo.resv)
+ reservation_object_unlock(resv);
+
spin_lock(&vm->status_lock);
}
spin_unlock(&vm->status_lock);
@@ -2132,8 +1741,26 @@
INIT_LIST_HEAD(&bo_va->valids);
INIT_LIST_HEAD(&bo_va->invalids);
- if (bo)
- list_add_tail(&bo_va->base.bo_list, &bo->va);
+ if (!bo)
+ return bo_va;
+
+ list_add_tail(&bo_va->base.bo_list, &bo->va);
+
+ if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
+ return bo_va;
+
+ if (bo->preferred_domains &
+ amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
+ return bo_va;
+
+ /*
+ * We checked all the prerequisites, but it looks like this per VM BO
+ * is currently evicted. add the BO to the evicted list to make sure it
+ * is validated on next VM use to avoid fault.
+ * */
+ spin_lock(&vm->status_lock);
+ list_move_tail(&bo_va->base.vm_status, &vm->evicted);
+ spin_unlock(&vm->status_lock);
return bo_va;
}
@@ -2556,47 +2183,69 @@
}
/**
- * amdgpu_vm_set_fragment_size - adjust fragment size in PTE
- *
- * @adev: amdgpu_device pointer
- * @fragment_size_default: the default fragment size if it's set auto
- */
-void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
- uint32_t fragment_size_default)
-{
- if (amdgpu_vm_fragment_size == -1)
- adev->vm_manager.fragment_size = fragment_size_default;
- else
- adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
-}
-
-/**
* amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
*
* @adev: amdgpu_device pointer
* @vm_size: the default vm size if it's set auto
*/
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
- uint32_t fragment_size_default)
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+ uint32_t fragment_size_default, unsigned max_level,
+ unsigned max_bits)
{
- /* adjust vm size firstly */
- if (amdgpu_vm_size == -1)
- adev->vm_manager.vm_size = vm_size;
- else
- adev->vm_manager.vm_size = amdgpu_vm_size;
+ uint64_t tmp;
- /* block size depends on vm size */
- if (amdgpu_vm_block_size == -1)
+ /* adjust vm size first */
+ if (amdgpu_vm_size != -1) {
+ unsigned max_size = 1 << (max_bits - 30);
+
+ vm_size = amdgpu_vm_size;
+ if (vm_size > max_size) {
+ dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
+ amdgpu_vm_size, max_size);
+ vm_size = max_size;
+ }
+ }
+
+ adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
+
+ tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
+ if (amdgpu_vm_block_size != -1)
+ tmp >>= amdgpu_vm_block_size - 9;
+ tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
+ adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
+ switch (adev->vm_manager.num_level) {
+ case 3:
+ adev->vm_manager.root_level = AMDGPU_VM_PDB2;
+ break;
+ case 2:
+ adev->vm_manager.root_level = AMDGPU_VM_PDB1;
+ break;
+ case 1:
+ adev->vm_manager.root_level = AMDGPU_VM_PDB0;
+ break;
+ default:
+ dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
+ }
+ /* block size depends on vm size and hw setup*/
+ if (amdgpu_vm_block_size != -1)
adev->vm_manager.block_size =
- amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
+ min((unsigned)amdgpu_vm_block_size, max_bits
+ - AMDGPU_GPU_PAGE_SHIFT
+ - 9 * adev->vm_manager.num_level);
+ else if (adev->vm_manager.num_level > 1)
+ adev->vm_manager.block_size = 9;
else
- adev->vm_manager.block_size = amdgpu_vm_block_size;
+ adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
- amdgpu_vm_set_fragment_size(adev, fragment_size_default);
+ if (amdgpu_vm_fragment_size == -1)
+ adev->vm_manager.fragment_size = fragment_size_default;
+ else
+ adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
- DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
- adev->vm_manager.vm_size, adev->vm_manager.block_size,
- adev->vm_manager.fragment_size);
+ DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
+ vm_size, adev->vm_manager.num_level + 1,
+ adev->vm_manager.block_size,
+ adev->vm_manager.fragment_size);
}
/**
@@ -2613,15 +2262,14 @@
{
const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
AMDGPU_VM_PTE_COUNT(adev) * 8);
+ uint64_t init_pde_value = 0, flags;
unsigned ring_instance;
struct amdgpu_ring *ring;
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
+ unsigned long size;
int r, i;
- u64 flags;
- uint64_t init_pde_value = 0;
vm->va = RB_ROOT_CACHED;
- vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
vm->reserved_vmid[i] = NULL;
spin_lock_init(&vm->status_lock);
@@ -2635,8 +2283,8 @@
ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
ring_instance %= adev->vm_manager.vm_pte_num_rings;
ring = adev->vm_manager.vm_pte_rings[ring_instance];
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
- r = amd_sched_entity_init(&ring->sched, &vm->entity,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+ r = drm_sched_entity_init(&ring->sched, &vm->entity,
rq, amdgpu_sched_jobs, NULL);
if (r)
return r;
@@ -2670,27 +2318,21 @@
flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
AMDGPU_GEM_CREATE_SHADOW);
- r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
- AMDGPU_GEM_DOMAIN_VRAM,
- flags,
- NULL, NULL, init_pde_value, &vm->root.base.bo);
+ size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
+ r = amdgpu_bo_create(adev, size, align, true, AMDGPU_GEM_DOMAIN_VRAM,
+ flags, NULL, NULL, init_pde_value,
+ &vm->root.base.bo);
if (r)
goto error_free_sched_entity;
+ r = amdgpu_bo_reserve(vm->root.base.bo, true);
+ if (r)
+ goto error_free_root;
+
vm->root.base.vm = vm;
list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
- INIT_LIST_HEAD(&vm->root.base.vm_status);
-
- if (vm->use_cpu_for_update) {
- r = amdgpu_bo_reserve(vm->root.base.bo, false);
- if (r)
- goto error_free_root;
-
- r = amdgpu_bo_kmap(vm->root.base.bo, NULL);
- amdgpu_bo_unreserve(vm->root.base.bo);
- if (r)
- goto error_free_root;
- }
+ list_add_tail(&vm->root.base.vm_status, &vm->evicted);
+ amdgpu_bo_unreserve(vm->root.base.bo);
if (pasid) {
unsigned long flags;
@@ -2716,7 +2358,7 @@
vm->root.base.bo = NULL;
error_free_sched_entity:
- amd_sched_entity_fini(&ring->sched, &vm->entity);
+ drm_sched_entity_fini(&ring->sched, &vm->entity);
return r;
}
@@ -2724,26 +2366,31 @@
/**
* amdgpu_vm_free_levels - free PD/PT levels
*
- * @level: PD/PT starting level to free
+ * @adev: amdgpu device structure
+ * @parent: PD/PT starting level to free
+ * @level: level of parent structure
*
* Free the page directory or page table level and all sub levels.
*/
-static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
+static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
+ struct amdgpu_vm_pt *parent,
+ unsigned level)
{
- unsigned i;
+ unsigned i, num_entries = amdgpu_vm_num_entries(adev, level);
- if (level->base.bo) {
- list_del(&level->base.bo_list);
- list_del(&level->base.vm_status);
- amdgpu_bo_unref(&level->base.bo->shadow);
- amdgpu_bo_unref(&level->base.bo);
+ if (parent->base.bo) {
+ list_del(&parent->base.bo_list);
+ list_del(&parent->base.vm_status);
+ amdgpu_bo_unref(&parent->base.bo->shadow);
+ amdgpu_bo_unref(&parent->base.bo);
}
- if (level->entries)
- for (i = 0; i <= level->last_entry_used; i++)
- amdgpu_vm_free_levels(&level->entries[i]);
+ if (parent->entries)
+ for (i = 0; i < num_entries; i++)
+ amdgpu_vm_free_levels(adev, &parent->entries[i],
+ level + 1);
- kvfree(level->entries);
+ kvfree(parent->entries);
}
/**
@@ -2775,7 +2422,7 @@
spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
}
- amd_sched_entity_fini(vm->entity.sched, &vm->entity);
+ drm_sched_entity_fini(vm->entity.sched, &vm->entity);
if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
dev_err(adev->dev, "still active bo inside vm\n");
@@ -2801,13 +2448,14 @@
if (r) {
dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
} else {
- amdgpu_vm_free_levels(&vm->root);
+ amdgpu_vm_free_levels(adev, &vm->root,
+ adev->vm_manager.root_level);
amdgpu_bo_unreserve(root);
}
amdgpu_bo_unref(&root);
dma_fence_put(vm->last_update);
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
- amdgpu_vm_free_reserved_vmid(adev, vm, i);
+ amdgpu_vmid_free_reserved(adev, vm, i);
}
/**
@@ -2826,17 +2474,21 @@
spin_lock(&adev->vm_manager.pasid_lock);
vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
- spin_unlock(&adev->vm_manager.pasid_lock);
- if (!vm)
+ if (!vm) {
/* VM not found, can't track fault credit */
+ spin_unlock(&adev->vm_manager.pasid_lock);
return true;
+ }
/* No lock needed. only accessed by IRQ handler */
- if (!vm->fault_credit)
+ if (!vm->fault_credit) {
/* Too many faults in this VM */
+ spin_unlock(&adev->vm_manager.pasid_lock);
return false;
+ }
vm->fault_credit--;
+ spin_unlock(&adev->vm_manager.pasid_lock);
return true;
}
@@ -2849,23 +2501,9 @@
*/
void amdgpu_vm_manager_init(struct amdgpu_device *adev)
{
- unsigned i, j;
+ unsigned i;
- for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
- struct amdgpu_vm_id_manager *id_mgr =
- &adev->vm_manager.id_mgr[i];
-
- mutex_init(&id_mgr->lock);
- INIT_LIST_HEAD(&id_mgr->ids_lru);
- atomic_set(&id_mgr->reserved_vmid_num, 0);
-
- /* skip over VMID 0, since it is the system VM */
- for (j = 1; j < id_mgr->num_ids; ++j) {
- amdgpu_vm_reset_id(adev, i, j);
- amdgpu_sync_create(&id_mgr->ids[i].active);
- list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
- }
- }
+ amdgpu_vmid_mgr_init(adev);
adev->vm_manager.fence_context =
dma_fence_context_alloc(AMDGPU_MAX_RINGS);
@@ -2873,7 +2511,6 @@
adev->vm_manager.seqno[i] = 0;
atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
- atomic64_set(&adev->vm_manager.client_counter, 0);
spin_lock_init(&adev->vm_manager.prt_lock);
atomic_set(&adev->vm_manager.num_prt_users, 0);
@@ -2906,24 +2543,10 @@
*/
void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
{
- unsigned i, j;
-
WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
idr_destroy(&adev->vm_manager.pasid_idr);
- for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
- struct amdgpu_vm_id_manager *id_mgr =
- &adev->vm_manager.id_mgr[i];
-
- mutex_destroy(&id_mgr->lock);
- for (j = 0; j < AMDGPU_NUM_VM; ++j) {
- struct amdgpu_vm_id *id = &id_mgr->ids[j];
-
- amdgpu_sync_free(&id->active);
- dma_fence_put(id->flushed_updates);
- dma_fence_put(id->last_flush);
- }
- }
+ amdgpu_vmid_mgr_fini(adev);
}
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
@@ -2936,13 +2559,12 @@
switch (args->in.op) {
case AMDGPU_VM_OP_RESERVE_VMID:
/* current, we only have requirement to reserve vmid from gfxhub */
- r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm,
- AMDGPU_GFXHUB);
+ r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
if (r)
return r;
break;
case AMDGPU_VM_OP_UNRESERVE_VMID:
- amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB);
+ amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
break;
default:
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index aef9ae5..21a80f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -24,12 +24,14 @@
#ifndef __AMDGPU_VM_H__
#define __AMDGPU_VM_H__
-#include <linux/rbtree.h>
#include <linux/idr.h>
+#include <linux/kfifo.h>
+#include <linux/rbtree.h>
+#include <drm/gpu_scheduler.h>
-#include "gpu_scheduler.h"
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
+#include "amdgpu_ids.h"
struct amdgpu_bo_va;
struct amdgpu_job;
@@ -39,9 +41,6 @@
* GPUVM handling
*/
-/* maximum number of VMIDs */
-#define AMDGPU_NUM_VM 16
-
/* Maximum number of PTEs the hardware can write with one command */
#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
@@ -69,6 +68,12 @@
/* PDE is handled as PTE for VEGA10 */
#define AMDGPU_PDE_PTE (1ULL << 54)
+/* PTE is handled as PDE for VEGA10 (Translate Further) */
+#define AMDGPU_PTE_TF (1ULL << 56)
+
+/* PDE Block Fragment Size for VEGA10 */
+#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
+
/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
@@ -119,6 +124,16 @@
#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
+/* VMPT level enumerate, and the hiberachy is:
+ * PDB2->PDB1->PDB0->PTB
+ */
+enum amdgpu_vm_level {
+ AMDGPU_VM_PDB2,
+ AMDGPU_VM_PDB1,
+ AMDGPU_VM_PDB0,
+ AMDGPU_VM_PTB
+};
+
/* base structure for tracking BO usage in a VM */
struct amdgpu_vm_bo_base {
/* constant after initialization */
@@ -137,11 +152,10 @@
struct amdgpu_vm_pt {
struct amdgpu_vm_bo_base base;
- uint64_t addr;
+ bool huge;
/* array of page tables, one for each directory entry */
struct amdgpu_vm_pt *entries;
- unsigned last_entry_used;
};
#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
@@ -175,13 +189,11 @@
spinlock_t freed_lock;
/* Scheduler entity for page table updates */
- struct amd_sched_entity entity;
+ struct drm_sched_entity entity;
- /* client id and PASID (TODO: replace client_id with PASID) */
- u64 client_id;
unsigned int pasid;
/* dedicated to vm */
- struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS];
+ struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
bool use_cpu_for_update;
@@ -196,37 +208,9 @@
unsigned int fault_credit;
};
-struct amdgpu_vm_id {
- struct list_head list;
- struct amdgpu_sync active;
- struct dma_fence *last_flush;
- atomic64_t owner;
-
- uint64_t pd_gpu_addr;
- /* last flushed PD/PT update */
- struct dma_fence *flushed_updates;
-
- uint32_t current_gpu_reset_count;
-
- uint32_t gds_base;
- uint32_t gds_size;
- uint32_t gws_base;
- uint32_t gws_size;
- uint32_t oa_base;
- uint32_t oa_size;
-};
-
-struct amdgpu_vm_id_manager {
- struct mutex lock;
- unsigned num_ids;
- struct list_head ids_lru;
- struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
- atomic_t reserved_vmid_num;
-};
-
struct amdgpu_vm_manager {
/* Handling of VMIDs */
- struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS];
+ struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
/* Handling of VM fences */
u64 fence_context;
@@ -234,9 +218,9 @@
uint64_t max_pfn;
uint32_t num_level;
- uint64_t vm_size;
uint32_t block_size;
uint32_t fragment_size;
+ enum amdgpu_vm_level root_level;
/* vram base address for page table entry */
u64 vram_base_offset;
/* vm pte handling */
@@ -244,8 +228,6 @@
struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
unsigned vm_pte_num_rings;
atomic_t vm_pte_next_ring;
- /* client id counter */
- atomic64_t client_counter;
/* partial resident texture handling */
spinlock_t prt_lock;
@@ -264,8 +246,6 @@
spinlock_t pasid_lock;
};
-int amdgpu_vm_alloc_pasid(unsigned int bits);
-void amdgpu_vm_free_pasid(unsigned int pasid);
void amdgpu_vm_manager_init(struct amdgpu_device *adev);
void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -283,13 +263,7 @@
int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
uint64_t saddr, uint64_t size);
-int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- struct amdgpu_sync *sync, struct dma_fence *fence,
- struct amdgpu_job *job);
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
-void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
- unsigned vmid);
-void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
struct amdgpu_vm *vm);
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
@@ -325,10 +299,9 @@
uint64_t addr);
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va);
-void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
- uint32_t fragment_size_default);
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
- uint32_t fragment_size_default);
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+ uint32_t fragment_size_default, unsigned max_level,
+ unsigned max_bits);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
struct amdgpu_job *job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 4acca92..c9f3336 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -97,6 +97,22 @@
}
/**
+ * amdgpu_vram_mgr_bo_invisible_size - CPU invisible BO size
+ *
+ * @bo: &amdgpu_bo buffer object (must be in VRAM)
+ *
+ * Returns:
+ * How much of the given &amdgpu_bo buffer object lies in CPU invisible VRAM.
+ */
+u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo)
+{
+ if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
+ return amdgpu_bo_size(bo);
+
+ return 0;
+}
+
+/**
* amdgpu_vram_mgr_new - allocate new ranges
*
* @man: TTM memory type manager
@@ -135,7 +151,8 @@
num_nodes = DIV_ROUND_UP(mem->num_pages, pages_per_node);
}
- nodes = kcalloc(num_nodes, sizeof(*nodes), GFP_KERNEL);
+ nodes = kvmalloc_array(num_nodes, sizeof(*nodes),
+ GFP_KERNEL | __GFP_ZERO);
if (!nodes)
return -ENOMEM;
@@ -190,7 +207,7 @@
drm_mm_remove_node(&nodes[i]);
spin_unlock(&mgr->lock);
- kfree(nodes);
+ kvfree(nodes);
return r == -ENOSPC ? 0 : r;
}
@@ -229,7 +246,7 @@
atomic64_sub(usage, &mgr->usage);
atomic64_sub(vis_usage, &mgr->vis_usage);
- kfree(mem->mm_node);
+ kvfree(mem->mm_node);
mem->mm_node = NULL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 2af26d2d..d702fb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -34,7 +34,7 @@
#include <linux/backlight.h>
#include "bif/bif_4_1_d.h"
-static u8
+u8
amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
{
u8 backlight_level;
@@ -48,7 +48,7 @@
return backlight_level;
}
-static void
+void
amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
u8 backlight_level)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
index 2bdec40..f77cbde 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
@@ -25,6 +25,11 @@
#define __ATOMBIOS_ENCODER_H__
u8
+amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev);
+void
+amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
+ u8 backlight_level);
+u8
amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder);
void
amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
index b374653..f9b2ce9 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
@@ -65,8 +65,15 @@
args.ucRegIndex = buf[0];
if (num)
num--;
- if (num)
- memcpy(&out, &buf[1], num);
+ if (num) {
+ if (buf) {
+ memcpy(&out, &buf[1], num);
+ } else {
+ DRM_ERROR("hw i2c: missing buf with num > 1\n");
+ r = -EINVAL;
+ goto done;
+ }
+ }
args.lpI2CDataOut = cpu_to_le16(out);
} else {
if (num > ATOM_MAX_HW_I2C_READ) {
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 68b505c..a0943aa8 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -891,12 +891,12 @@
if (gate) {
/* stop the UVD block */
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_GATE);
ci_update_uvd_dpm(adev, gate);
} else {
- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
ci_update_uvd_dpm(adev, gate);
}
}
@@ -4540,9 +4540,9 @@
((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
}
j++;
+
if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
return -EINVAL;
-
temp_reg = RREG32(mmMC_PMG_CMD_MRS);
table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
@@ -4553,10 +4553,10 @@
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
}
j++;
- if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
+ if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
+ return -EINVAL;
table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
for (k = 0; k < table->num_entries; k++) {
@@ -4564,8 +4564,6 @@
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
}
j++;
- if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
}
break;
case mmMC_SEQ_RESERVE_M:
@@ -4577,8 +4575,6 @@
(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
}
j++;
- if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
break;
default:
break;
@@ -6625,9 +6621,9 @@
for (i = 0; i < pcie_table->count; i++)
size += sprintf(buf + size, "%d: %s %s\n", i,
- (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
- (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
- (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
+ (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" :
+ (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
+ (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
(i == now) ? "*" : "");
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a296f7bb..8e59e65 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -755,74 +755,74 @@
switch (adev->asic_type) {
case CHIP_BONAIRE:
- amdgpu_program_register_sequence(adev,
- bonaire_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- bonaire_golden_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_registers));
- amdgpu_program_register_sequence(adev,
- bonaire_golden_common_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
- amdgpu_program_register_sequence(adev,
- bonaire_golden_spm_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+ amdgpu_device_program_register_sequence(adev,
+ bonaire_mgcg_cgcg_init,
+ ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ bonaire_golden_registers,
+ ARRAY_SIZE(bonaire_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ bonaire_golden_common_registers,
+ ARRAY_SIZE(bonaire_golden_common_registers));
+ amdgpu_device_program_register_sequence(adev,
+ bonaire_golden_spm_registers,
+ ARRAY_SIZE(bonaire_golden_spm_registers));
break;
case CHIP_KABINI:
- amdgpu_program_register_sequence(adev,
- kalindi_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- kalindi_golden_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_registers));
- amdgpu_program_register_sequence(adev,
- kalindi_golden_common_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
- amdgpu_program_register_sequence(adev,
- kalindi_golden_spm_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_mgcg_cgcg_init,
+ ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_golden_registers,
+ ARRAY_SIZE(kalindi_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_golden_common_registers,
+ ARRAY_SIZE(kalindi_golden_common_registers));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_golden_spm_registers,
+ ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_MULLINS:
- amdgpu_program_register_sequence(adev,
- kalindi_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- godavari_golden_registers,
- (const u32)ARRAY_SIZE(godavari_golden_registers));
- amdgpu_program_register_sequence(adev,
- kalindi_golden_common_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
- amdgpu_program_register_sequence(adev,
- kalindi_golden_spm_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_mgcg_cgcg_init,
+ ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ godavari_golden_registers,
+ ARRAY_SIZE(godavari_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_golden_common_registers,
+ ARRAY_SIZE(kalindi_golden_common_registers));
+ amdgpu_device_program_register_sequence(adev,
+ kalindi_golden_spm_registers,
+ ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_KAVERI:
- amdgpu_program_register_sequence(adev,
- spectre_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- spectre_golden_registers,
- (const u32)ARRAY_SIZE(spectre_golden_registers));
- amdgpu_program_register_sequence(adev,
- spectre_golden_common_registers,
- (const u32)ARRAY_SIZE(spectre_golden_common_registers));
- amdgpu_program_register_sequence(adev,
- spectre_golden_spm_registers,
- (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
+ amdgpu_device_program_register_sequence(adev,
+ spectre_mgcg_cgcg_init,
+ ARRAY_SIZE(spectre_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ spectre_golden_registers,
+ ARRAY_SIZE(spectre_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ spectre_golden_common_registers,
+ ARRAY_SIZE(spectre_golden_common_registers));
+ amdgpu_device_program_register_sequence(adev,
+ spectre_golden_spm_registers,
+ ARRAY_SIZE(spectre_golden_spm_registers));
break;
case CHIP_HAWAII:
- amdgpu_program_register_sequence(adev,
- hawaii_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- hawaii_golden_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_registers));
- amdgpu_program_register_sequence(adev,
- hawaii_golden_common_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
- amdgpu_program_register_sequence(adev,
- hawaii_golden_spm_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
+ amdgpu_device_program_register_sequence(adev,
+ hawaii_mgcg_cgcg_init,
+ ARRAY_SIZE(hawaii_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ hawaii_golden_registers,
+ ARRAY_SIZE(hawaii_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ hawaii_golden_common_registers,
+ ARRAY_SIZE(hawaii_golden_common_registers));
+ amdgpu_device_program_register_sequence(adev,
+ hawaii_golden_spm_registers,
+ ARRAY_SIZE(hawaii_golden_spm_registers));
break;
default:
break;
@@ -1246,7 +1246,7 @@
/* disable BM */
pci_clear_master(adev->pdev);
/* reset */
- amdgpu_pci_config_reset(adev);
+ amdgpu_device_pci_config_reset(adev);
udelay(100);
@@ -1866,7 +1866,7 @@
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
- amdgpu_get_pcie_info(adev);
+ amdgpu_device_get_pcie_info(adev);
return 0;
}
@@ -1974,77 +1974,77 @@
switch (adev->asic_type) {
case CHIP_BONAIRE:
- amdgpu_ip_block_add(adev, &cik_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
- amdgpu_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
- amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
case CHIP_HAWAII:
- amdgpu_ip_block_add(adev, &cik_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
- amdgpu_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
- amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
case CHIP_KAVERI:
- amdgpu_ip_block_add(adev, &cik_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
- amdgpu_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
- amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
case CHIP_KABINI:
case CHIP_MULLINS:
- amdgpu_ip_block_add(adev, &cik_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
- amdgpu_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
- amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
default:
/* FIXME: not supported yet */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index a870b35..d5a05c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -280,7 +280,7 @@
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
- entry->vm_id = (dw[2] >> 8) & 0xff;
+ entry->vmid = (dw[2] >> 8) & 0xff;
entry->pas_id = (dw[2] >> 16) & 0xffff;
/* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 375ef27..0066da3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -221,9 +221,9 @@
*/
static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 extra_bits = vm_id & 0xf;
+ u32 extra_bits = vmid & 0xf;
/* IB packet must end on a 8 DW boundary */
cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
@@ -880,23 +880,23 @@
* using sDMA (CIK).
*/
static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
- if (vm_id < 8) {
- amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+ if (vmid < 8) {
+ amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
} else {
- amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+ amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
}
amdgpu_ring_write(ring, pd_addr >> 12);
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
index 6a9e38a..cee6e8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cikd.h
+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
@@ -562,7 +562,7 @@
#define PRIVATE_BASE(x) ((x) << 0) /* scratch */
#define SHARED_BASE(x) ((x) << 16) /* LDS */
-#define KFD_CIK_SDMA_QUEUE_OFFSET 0x200
+#define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL)
/* valid for both DEFAULT_MTYPE and APE1_MTYPE */
enum {
diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
index 003a131..567a904 100644
--- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
+++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
@@ -48,7 +48,7 @@
0x00000000, // DB_STENCIL_WRITE_BASE
0x00000000, // DB_STENCIL_WRITE_BASE_HI
0x00000000, // DB_DFSM_CONTROL
- 0x00000000, // DB_RENDER_FILTER
+ 0, // HOLE
0x00000000, // DB_Z_INFO2
0x00000000, // DB_STENCIL_INFO2
0, // HOLE
@@ -259,8 +259,8 @@
0x00000000, // PA_SC_RIGHT_VERT_GRID
0x00000000, // PA_SC_LEFT_VERT_GRID
0x00000000, // PA_SC_HORIZ_GRID
- 0x00000000, // PA_SC_FOV_WINDOW_LR
- 0x00000000, // PA_SC_FOV_WINDOW_TB
+ 0, // HOLE
+ 0, // HOLE
0, // HOLE
0, // HOLE
0, // HOLE
@@ -701,7 +701,7 @@
{
0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP
0x00000000, // VGT_DRAW_PAYLOAD_CNTL
- 0x00000000, // VGT_INDEX_PAYLOAD_CNTL
+ 0, // HOLE
0x00000000, // VGT_INSTANCE_STEP_RATE_0
0x00000000, // VGT_INSTANCE_STEP_RATE_1
0, // HOLE
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index fa61d64..f576e9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -259,7 +259,7 @@
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
- entry->vm_id = (dw[2] >> 8) & 0xff;
+ entry->vmid = (dw[2] >> 8) & 0xff;
entry->pas_id = (dw[2] >> 16) & 0xffff;
/* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 4e519dc..022f303 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -145,20 +145,20 @@
{
switch (adev->asic_type) {
case CHIP_FIJI:
- amdgpu_program_register_sequence(adev,
- fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ amdgpu_device_program_register_sequence(adev,
+ fiji_mgcg_cgcg_init,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_fiji_a10,
+ ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA:
- amdgpu_program_register_sequence(adev,
- tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ amdgpu_device_program_register_sequence(adev,
+ tonga_mgcg_cgcg_init,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_tonga_a11,
+ ARRAY_SIZE(golden_settings_tonga_a11));
break;
default:
break;
@@ -2773,7 +2773,6 @@
adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
dce_v10_0_set_display_funcs(adev);
- dce_v10_0_set_irq_funcs(adev);
adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
@@ -2788,6 +2787,8 @@
return -EINVAL;
}
+ dce_v10_0_set_irq_funcs(adev);
+
return 0;
}
@@ -2920,6 +2921,11 @@
static int dce_v10_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ adev->mode_info.bl_level =
+ amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
return dce_v10_0_hw_fini(handle);
}
@@ -2928,6 +2934,9 @@
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+ adev->mode_info.bl_level);
+
ret = dce_v10_0_hw_init(handle);
/* turn on the BL */
@@ -3635,13 +3644,16 @@
static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+ if (adev->mode_info.num_crtc > 0)
+ adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+ else
+ adev->crtc_irq.num_types = 0;
adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
- adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+ adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
- adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+ adev->hpd_irq.num_types = adev->mode_info.num_hpd;
adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 11edc75..800a9f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -154,28 +154,28 @@
{
switch (adev->asic_type) {
case CHIP_CARRIZO:
- amdgpu_program_register_sequence(adev,
- cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- cz_golden_settings_a11,
- (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ cz_mgcg_cgcg_init,
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ cz_golden_settings_a11,
+ ARRAY_SIZE(cz_golden_settings_a11));
break;
case CHIP_STONEY:
- amdgpu_program_register_sequence(adev,
- stoney_golden_settings_a11,
- (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_golden_settings_a11,
+ ARRAY_SIZE(stoney_golden_settings_a11));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
- amdgpu_program_register_sequence(adev,
- polaris11_golden_settings_a11,
- (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ polaris11_golden_settings_a11,
+ ARRAY_SIZE(polaris11_golden_settings_a11));
break;
case CHIP_POLARIS10:
- amdgpu_program_register_sequence(adev,
- polaris10_golden_settings_a11,
- (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ polaris10_golden_settings_a11,
+ ARRAY_SIZE(polaris10_golden_settings_a11));
break;
default:
break;
@@ -2876,7 +2876,6 @@
adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
dce_v11_0_set_display_funcs(adev);
- dce_v11_0_set_irq_funcs(adev);
adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
@@ -2903,6 +2902,8 @@
return -EINVAL;
}
+ dce_v11_0_set_irq_funcs(adev);
+
return 0;
}
@@ -3046,6 +3047,11 @@
static int dce_v11_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ adev->mode_info.bl_level =
+ amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
return dce_v11_0_hw_fini(handle);
}
@@ -3054,6 +3060,9 @@
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+ adev->mode_info.bl_level);
+
ret = dce_v11_0_hw_init(handle);
/* turn on the BL */
@@ -3759,13 +3768,16 @@
static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+ if (adev->mode_info.num_crtc > 0)
+ adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+ else
+ adev->crtc_irq.num_types = 0;
adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
- adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+ adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
- adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+ adev->hpd_irq.num_types = adev->mode_info.num_hpd;
adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index a51e35f..b8368f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2639,7 +2639,6 @@
adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
dce_v6_0_set_display_funcs(adev);
- dce_v6_0_set_irq_funcs(adev);
adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
@@ -2658,6 +2657,8 @@
return -EINVAL;
}
+ dce_v6_0_set_irq_funcs(adev);
+
return 0;
}
@@ -2786,6 +2787,11 @@
static int dce_v6_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ adev->mode_info.bl_level =
+ amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
return dce_v6_0_hw_fini(handle);
}
@@ -2794,6 +2800,9 @@
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+ adev->mode_info.bl_level);
+
ret = dce_v6_0_hw_init(handle);
/* turn on the BL */
@@ -3092,7 +3101,7 @@
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
schedule_work(&adev->hotplug_work);
- DRM_INFO("IH: HPD%d\n", hpd + 1);
+ DRM_DEBUG("IH: HPD%d\n", hpd + 1);
}
return 0;
@@ -3441,13 +3450,16 @@
static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+ if (adev->mode_info.num_crtc > 0)
+ adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+ else
+ adev->crtc_irq.num_types = 0;
adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
- adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+ adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
- adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+ adev->hpd_irq.num_types = adev->mode_info.num_hpd;
adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 9cf14b8..012e0a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2664,7 +2664,6 @@
adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
dce_v8_0_set_display_funcs(adev);
- dce_v8_0_set_irq_funcs(adev);
adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
@@ -2688,6 +2687,8 @@
return -EINVAL;
}
+ dce_v8_0_set_irq_funcs(adev);
+
return 0;
}
@@ -2818,6 +2819,11 @@
static int dce_v8_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ adev->mode_info.bl_level =
+ amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
return dce_v8_0_hw_fini(handle);
}
@@ -2826,6 +2832,9 @@
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+ adev->mode_info.bl_level);
+
ret = dce_v8_0_hw_init(handle);
/* turn on the BL */
@@ -3525,13 +3534,16 @@
static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+ if (adev->mode_info.num_crtc > 0)
+ adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+ else
+ adev->crtc_irq.num_types = 0;
adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
- adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+ adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
- adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+ adev->hpd_irq.num_types = adev->mode_info.num_hpd;
adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 39460eb..120dd3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -44,6 +44,9 @@
static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
int index);
+static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
+ int crtc,
+ enum amdgpu_interrupt_state state);
/**
* dce_virtual_vblank_wait - vblank wait asic callback.
@@ -491,6 +494,13 @@
static int dce_virtual_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i = 0;
+
+ for (i = 0; i<adev->mode_info.num_crtc; i++)
+ if (adev->mode_info.crtcs[i])
+ dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 9430d48..9870d83 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1874,7 +1874,7 @@
static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
u32 header, control = 0;
@@ -1889,7 +1889,7 @@
else
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- control |= ib->length_dw | (vm_id << 24);
+ control |= ib->length_dw | (vmid << 24);
amdgpu_ring_write(ring, header);
amdgpu_ring_write(ring,
@@ -2354,7 +2354,7 @@
}
static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
@@ -2362,10 +2362,10 @@
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
WRITE_DATA_DST_SEL(0)));
- if (vm_id < 8) {
- amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
+ if (vmid < 8) {
+ amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid ));
} else {
- amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
+ amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
}
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
@@ -2376,7 +2376,7 @@
WRITE_DATA_DST_SEL(0)));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
/* wait for the invalidate to complete */
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -2962,25 +2962,7 @@
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
-
- switch (adev->asic_type) {
- case CHIP_TAHITI:
- case CHIP_PITCAIRN:
- buffer[count++] = cpu_to_le32(0x2a00126a);
- break;
- case CHIP_VERDE:
- buffer[count++] = cpu_to_le32(0x0000124a);
- break;
- case CHIP_OLAND:
- buffer[count++] = cpu_to_le32(0x00000082);
- break;
- case CHIP_HAINAN:
- buffer[count++] = cpu_to_le32(0x00000000);
- break;
- default:
- buffer[count++] = cpu_to_le32(0x00000000);
- break;
- }
+ buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7bd6f64..a430969 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -48,6 +48,8 @@
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
+#define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
+
#define GFX7_NUM_GFX_RINGS 1
#define GFX7_MEC_HPD_SIZE 2048
@@ -2252,7 +2254,7 @@
*/
static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
u32 header, control = 0;
@@ -2267,7 +2269,7 @@
else
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- control |= ib->length_dw | (vm_id << 24);
+ control |= ib->length_dw | (vmid << 24);
amdgpu_ring_write(ring, header);
amdgpu_ring_write(ring,
@@ -2281,9 +2283,9 @@
static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
+ u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
amdgpu_ring_write(ring,
@@ -2551,29 +2553,8 @@
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
- switch (adev->asic_type) {
- case CHIP_BONAIRE:
- amdgpu_ring_write(ring, 0x16000012);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_KAVERI:
- amdgpu_ring_write(ring, 0x00000000); /* XXX */
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_KABINI:
- case CHIP_MULLINS:
- amdgpu_ring_write(ring, 0x00000000); /* XXX */
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_HAWAII:
- amdgpu_ring_write(ring, 0x3a00161a);
- amdgpu_ring_write(ring, 0x0000002e);
- break;
- default:
- amdgpu_ring_write(ring, 0x00000000);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- }
+ amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
+ amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
@@ -3258,19 +3239,19 @@
* using the CP (CIK).
*/
static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
WRITE_DATA_DST_SEL(0)));
- if (vm_id < 8) {
+ if (vmid < 8) {
amdgpu_ring_write(ring,
- (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+ (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
} else {
amdgpu_ring_write(ring,
- (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+ (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
}
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
@@ -3281,7 +3262,7 @@
WRITE_DATA_DST_SEL(0)));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
/* wait for the invalidate to complete */
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -5272,6 +5253,11 @@
cu_info->number = active_cu_number;
cu_info->ao_cu_mask = ao_cu_mask;
+ cu_info->simd_per_cu = NUM_SIMD_PER_CU;
+ cu_info->max_waves_per_simd = 10;
+ cu_info->max_scratch_slots_per_cu = 32;
+ cu_info->wave_front_size = 64;
+ cu_info->lds_size = 64;
}
const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0e4fadd..060dc955 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -679,55 +679,55 @@
{
switch (adev->asic_type) {
case CHIP_TOPAZ:
- amdgpu_program_register_sequence(adev,
- iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_iceland_a11,
- (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
- amdgpu_program_register_sequence(adev,
- iceland_golden_common_all,
- (const u32)ARRAY_SIZE(iceland_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ iceland_mgcg_cgcg_init,
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_iceland_a11,
+ ARRAY_SIZE(golden_settings_iceland_a11));
+ amdgpu_device_program_register_sequence(adev,
+ iceland_golden_common_all,
+ ARRAY_SIZE(iceland_golden_common_all));
break;
case CHIP_FIJI:
- amdgpu_program_register_sequence(adev,
- fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
- amdgpu_program_register_sequence(adev,
- fiji_golden_common_all,
- (const u32)ARRAY_SIZE(fiji_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ fiji_mgcg_cgcg_init,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_fiji_a10,
+ ARRAY_SIZE(golden_settings_fiji_a10));
+ amdgpu_device_program_register_sequence(adev,
+ fiji_golden_common_all,
+ ARRAY_SIZE(fiji_golden_common_all));
break;
case CHIP_TONGA:
- amdgpu_program_register_sequence(adev,
- tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
- amdgpu_program_register_sequence(adev,
- tonga_golden_common_all,
- (const u32)ARRAY_SIZE(tonga_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ tonga_mgcg_cgcg_init,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_tonga_a11,
+ ARRAY_SIZE(golden_settings_tonga_a11));
+ amdgpu_device_program_register_sequence(adev,
+ tonga_golden_common_all,
+ ARRAY_SIZE(tonga_golden_common_all));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
- amdgpu_program_register_sequence(adev,
- golden_settings_polaris11_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
- amdgpu_program_register_sequence(adev,
- polaris11_golden_common_all,
- (const u32)ARRAY_SIZE(polaris11_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_polaris11_a11,
+ ARRAY_SIZE(golden_settings_polaris11_a11));
+ amdgpu_device_program_register_sequence(adev,
+ polaris11_golden_common_all,
+ ARRAY_SIZE(polaris11_golden_common_all));
break;
case CHIP_POLARIS10:
- amdgpu_program_register_sequence(adev,
- golden_settings_polaris10_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
- amdgpu_program_register_sequence(adev,
- polaris10_golden_common_all,
- (const u32)ARRAY_SIZE(polaris10_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_polaris10_a11,
+ ARRAY_SIZE(golden_settings_polaris10_a11));
+ amdgpu_device_program_register_sequence(adev,
+ polaris10_golden_common_all,
+ ARRAY_SIZE(polaris10_golden_common_all));
WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
if (adev->pdev->revision == 0xc7 &&
((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
@@ -738,26 +738,26 @@
}
break;
case CHIP_CARRIZO:
- amdgpu_program_register_sequence(adev,
- cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- cz_golden_settings_a11,
- (const u32)ARRAY_SIZE(cz_golden_settings_a11));
- amdgpu_program_register_sequence(adev,
- cz_golden_common_all,
- (const u32)ARRAY_SIZE(cz_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ cz_mgcg_cgcg_init,
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ cz_golden_settings_a11,
+ ARRAY_SIZE(cz_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ cz_golden_common_all,
+ ARRAY_SIZE(cz_golden_common_all));
break;
case CHIP_STONEY:
- amdgpu_program_register_sequence(adev,
- stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- stoney_golden_settings_a11,
- (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
- amdgpu_program_register_sequence(adev,
- stoney_golden_common_all,
- (const u32)ARRAY_SIZE(stoney_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_mgcg_cgcg_init,
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_golden_settings_a11,
+ ARRAY_SIZE(stoney_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_golden_common_all,
+ ARRAY_SIZE(stoney_golden_common_all));
break;
default:
break;
@@ -2123,7 +2123,6 @@
amdgpu_gfx_compute_mqd_sw_fini(adev);
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
amdgpu_gfx_kiq_fini(adev);
- amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
gfx_v8_0_mec_fini(adev);
gfx_v8_0_rlc_fini(adev);
@@ -4322,37 +4321,8 @@
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
- switch (adev->asic_type) {
- case CHIP_TONGA:
- case CHIP_POLARIS10:
- amdgpu_ring_write(ring, 0x16000012);
- amdgpu_ring_write(ring, 0x0000002A);
- break;
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- amdgpu_ring_write(ring, 0x16000012);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_FIJI:
- amdgpu_ring_write(ring, 0x3a00161a);
- amdgpu_ring_write(ring, 0x0000002e);
- break;
- case CHIP_CARRIZO:
- amdgpu_ring_write(ring, 0x00000002);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_TOPAZ:
- amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ?
- 0x00000000 : 0x00000002);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_STONEY:
- amdgpu_ring_write(ring, 0x00000000);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- default:
- BUG();
- }
+ amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
+ amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
@@ -4833,7 +4803,7 @@
gfx_v8_0_kiq_setting(ring);
- if (adev->in_sriov_reset) { /* for GPU_RESET case */
+ if (adev->in_gpu_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
@@ -4870,7 +4840,7 @@
struct vi_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - &adev->gfx.compute_ring[0];
- if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
+ if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
@@ -4882,13 +4852,10 @@
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
- } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
+ } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
- /* reset ring buffer */
- ring->wptr = 0;
- amdgpu_ring_clear_ring(ring);
} else {
amdgpu_ring_clear_ring(ring);
}
@@ -4963,6 +4930,13 @@
/* Test KCQs */
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
+ if (adev->in_gpu_reset) {
+ /* move reset ring buffer to here to workaround
+ * compute ring test failed
+ */
+ ring->wptr = 0;
+ amdgpu_ring_clear_ring(ring);
+ }
ring->ready = true;
r = amdgpu_ring_test_ring(ring);
if (r)
@@ -5097,8 +5071,9 @@
gfx_v8_0_cp_enable(adev, false);
gfx_v8_0_rlc_stop(adev);
- amdgpu_set_powergating_state(adev,
- AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_PG_STATE_UNGATE);
return 0;
}
@@ -5515,8 +5490,9 @@
if (r)
return r;
- amdgpu_set_powergating_state(adev,
- AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_PG_STATE_GATE);
return 0;
}
@@ -5527,10 +5503,10 @@
if ((adev->asic_type == CHIP_POLARIS11) ||
(adev->asic_type == CHIP_POLARIS12))
/* Send msg to SMU via Powerplay */
- amdgpu_set_powergating_state(adev,
- AMD_IP_BLOCK_TYPE_SMC,
- enable ?
- AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_SMC,
+ enable ?
+ AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
}
@@ -6278,7 +6254,7 @@
static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
u32 header, control = 0;
@@ -6287,7 +6263,7 @@
else
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- control |= ib->length_dw | (vm_id << 24);
+ control |= ib->length_dw | (vmid << 24);
if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
control |= INDIRECT_BUFFER_PRE_ENB(1);
@@ -6308,9 +6284,9 @@
static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
+ u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
amdgpu_ring_write(ring,
@@ -6361,7 +6337,7 @@
}
static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
@@ -6369,12 +6345,12 @@
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
WRITE_DATA_DST_SEL(0)) |
WR_CONFIRM);
- if (vm_id < 8) {
+ if (vmid < 8) {
amdgpu_ring_write(ring,
- (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+ (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
} else {
amdgpu_ring_write(ring,
- (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+ (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
}
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
@@ -6386,7 +6362,7 @@
WRITE_DATA_DST_SEL(0)));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
/* wait for the invalidate to complete */
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -6507,10 +6483,10 @@
mutex_unlock(&adev->srbm_mutex);
}
static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
- enum amd_sched_priority priority)
+ enum drm_sched_priority priority)
{
struct amdgpu_device *adev = ring->adev;
- bool acquire = priority == AMD_SCHED_PRIORITY_HIGH_HW;
+ bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
return;
@@ -7149,6 +7125,11 @@
cu_info->number = active_cu_number;
cu_info->ao_cu_mask = ao_cu_mask;
+ cu_info->simd_per_cu = NUM_SIMD_PER_CU;
+ cu_info->max_waves_per_simd = 10;
+ cu_info->max_scratch_slots_per_cu = 32;
+ cu_info->wave_front_size = 64;
+ cu_info->lds_size = 64;
}
const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e9d1652..d7bbccd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -28,11 +28,10 @@
#include "soc15.h"
#include "soc15d.h"
-#include "vega10/soc15ip.h"
-#include "vega10/GC/gc_9_0_offset.h"
-#include "vega10/GC/gc_9_0_sh_mask.h"
-#include "vega10/vega10_enum.h"
-#include "vega10/HDP/hdp_4_0_offset.h"
+#include "gc/gc_9_0_offset.h"
+#include "gc/gc_9_0_sh_mask.h"
+#include "vega10_enum.h"
+#include "hdp/hdp_4_0_offset.h"
#include "soc15_common.h"
#include "clearstate_gfx9.h"
@@ -65,152 +64,84 @@
MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
-static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
+static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
- { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
};
-static const u32 golden_settings_gc_9_0[] =
+static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
{
- SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
- SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
- SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
- SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
- SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
- SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
- SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
- SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
- SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
- SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
- SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
- SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
};
-static const u32 golden_settings_gc_9_0_vg10[] =
+static const struct soc15_reg_golden golden_settings_gc_9_1[] =
{
- SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
- SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
- SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
- SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
- SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
- SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
};
-static const u32 golden_settings_gc_9_1[] =
+static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
{
- SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
- SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
- SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
- SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
- SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
- SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
- SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
- SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
- SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
- SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
- SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
};
-static const u32 golden_settings_gc_9_1_rv1[] =
+static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
{
- SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
- SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
- SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
- SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
- SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
- SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
-};
-
-static const u32 golden_settings_gc_9_x_common[] =
-{
- SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
- SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
};
#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
@@ -230,26 +161,26 @@
{
switch (adev->asic_type) {
case CHIP_VEGA10:
- amdgpu_program_register_sequence(adev,
+ soc15_program_register_sequence(adev,
golden_settings_gc_9_0,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
- amdgpu_program_register_sequence(adev,
+ ARRAY_SIZE(golden_settings_gc_9_0));
+ soc15_program_register_sequence(adev,
golden_settings_gc_9_0_vg10,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
+ ARRAY_SIZE(golden_settings_gc_9_0_vg10));
break;
case CHIP_RAVEN:
- amdgpu_program_register_sequence(adev,
+ soc15_program_register_sequence(adev,
golden_settings_gc_9_1,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
- amdgpu_program_register_sequence(adev,
+ ARRAY_SIZE(golden_settings_gc_9_1));
+ soc15_program_register_sequence(adev,
golden_settings_gc_9_1_rv1,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ ARRAY_SIZE(golden_settings_gc_9_1_rv1));
break;
default:
break;
}
- amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
+ soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
}
@@ -1137,8 +1068,8 @@
adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
- adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
- adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
+ adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
+ adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
/* Primitive Buffer */
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
@@ -1243,23 +1174,24 @@
}
gfx_v9_0_write_data_to_reg(ring, 0, false,
- amdgpu_gds_reg_offset[0].mem_size,
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
(adev->gds.mem.total_size +
adev->gfx.ngg.gds_reserve_size) >>
AMDGPU_GDS_SHIFT);
amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+ PACKET3_DMA_DATA_DST_SEL(1) |
PACKET3_DMA_DATA_SRC_SEL(2)));
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
-
+ amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
+ adev->gfx.ngg.gds_reserve_size);
gfx_v9_0_write_data_to_reg(ring, 0, false,
- amdgpu_gds_reg_offset[0].mem_size, 0);
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
amdgpu_ring_commit(ring);
@@ -1464,7 +1396,6 @@
amdgpu_gfx_compute_mqd_sw_fini(adev);
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
amdgpu_gfx_kiq_fini(adev);
- amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
gfx_v9_0_mec_fini(adev);
gfx_v9_0_ngg_fini(adev);
@@ -1596,14 +1527,21 @@
/* XXX SH_MEM regs */
/* where to put LDS, scratch, GPUVM in FSA64 space */
mutex_lock(&adev->srbm_mutex);
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
soc15_grbm_select(adev, 0, 0, 0, i);
/* CP and shaders */
- tmp = 0;
- tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
- WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
- WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
+ if (i == 0) {
+ tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
+ WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
+ } else {
+ tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
+ tmp = adev->mc.shared_aperture_start >> 48;
+ WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
+ }
}
soc15_grbm_select(adev, 0, 0, 0, 0);
@@ -2757,7 +2695,7 @@
gfx_v9_0_kiq_setting(ring);
- if (adev->in_sriov_reset) { /* for GPU_RESET case */
+ if (adev->in_gpu_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
@@ -2795,7 +2733,7 @@
struct v9_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - &adev->gfx.compute_ring[0];
- if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
+ if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
@@ -2807,7 +2745,7 @@
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
- } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
+ } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
@@ -3153,6 +3091,8 @@
uint32_t gws_base, uint32_t gws_size,
uint32_t oa_base, uint32_t oa_size)
{
+ struct amdgpu_device *adev = ring->adev;
+
gds_base = gds_base >> AMDGPU_GDS_SHIFT;
gds_size = gds_size >> AMDGPU_GDS_SHIFT;
@@ -3164,22 +3104,22 @@
/* GDS Base */
gfx_v9_0_write_data_to_reg(ring, 0, false,
- amdgpu_gds_reg_offset[vmid].mem_base,
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
gds_base);
/* GDS Size */
gfx_v9_0_write_data_to_reg(ring, 0, false,
- amdgpu_gds_reg_offset[vmid].mem_size,
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
gds_size);
/* GWS */
gfx_v9_0_write_data_to_reg(ring, 0, false,
- amdgpu_gds_reg_offset[vmid].gws,
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
/* OA */
gfx_v9_0_write_data_to_reg(ring, 0, false,
- amdgpu_gds_reg_offset[vmid].oa,
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
(1 << (oa_size + oa_base)) - (1 << oa_base));
}
@@ -3624,13 +3564,9 @@
static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
u32 ref_and_mask, reg_mem_engine;
- const struct nbio_hdp_flush_reg *nbio_hf_reg;
-
- if (ring->adev->flags & AMD_IS_APU)
- nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
- else
- nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
+ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
switch (ring->me) {
@@ -3650,20 +3586,22 @@
}
gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
- nbio_hf_reg->hdp_flush_req_offset,
- nbio_hf_reg->hdp_flush_done_offset,
+ adev->nbio_funcs->get_hdp_flush_req_offset(adev),
+ adev->nbio_funcs->get_hdp_flush_done_offset(adev),
ref_and_mask, ref_and_mask, 0x20);
}
static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
gfx_v9_0_write_data_to_reg(ring, 0, true,
SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
}
static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
u32 header, control = 0;
@@ -3672,7 +3610,7 @@
else
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- control |= ib->length_dw | (vm_id << 24);
+ control |= ib->length_dw | (vmid << 24);
if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
control |= INDIRECT_BUFFER_PRE_ENB(1);
@@ -3694,9 +3632,9 @@
static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
+ u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
@@ -3752,22 +3690,23 @@
}
static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
gfx_v9_0_write_data_to_reg(ring, usepfp, true,
- hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
+ hub->ctx0_ptb_addr_lo32 + (2 * vmid),
lower_32_bits(pd_addr));
gfx_v9_0_write_data_to_reg(ring, usepfp, true,
- hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
+ hub->ctx0_ptb_addr_hi32 + (2 * vmid),
upper_32_bits(pd_addr));
gfx_v9_0_write_data_to_reg(ring, usepfp, true,
@@ -3775,7 +3714,7 @@
/* wait for the invalidate to complete */
gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
- eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
+ eng, 0, 1 << vmid, 1 << vmid, 0x20);
/* compute doesn't have PFP */
if (usepfp) {
@@ -3818,6 +3757,8 @@
static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
u64 seq, unsigned int flags)
{
+ struct amdgpu_device *adev = ring->adev;
+
/* we only allocate 32bit for each seq wb address */
BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index c17996e..56f5fe4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -23,11 +23,10 @@
#include "amdgpu.h"
#include "gfxhub_v1_0.h"
-#include "vega10/soc15ip.h"
-#include "vega10/GC/gc_9_0_offset.h"
-#include "vega10/GC/gc_9_0_sh_mask.h"
-#include "vega10/GC/gc_9_0_default.h"
-#include "vega10/vega10_enum.h"
+#include "gc/gc_9_0_offset.h"
+#include "gc/gc_9_0_sh_mask.h"
+#include "gc/gc_9_0_default.h"
+#include "vega10_enum.h"
#include "soc15_common.h"
@@ -144,8 +143,15 @@
WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
tmp = mmVM_L2_CNTL3_DEFAULT;
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ if (adev->mc.translate_further) {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+ } else {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ }
WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
tmp = mmVM_L2_CNTL4_DEFAULT;
@@ -183,31 +189,40 @@
static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
{
- int i;
+ unsigned num_level, block_size;
uint32_t tmp;
+ int i;
+
+ num_level = adev->vm_manager.num_level;
+ block_size = adev->vm_manager.block_size;
+ if (adev->mc.translate_further)
+ num_level -= 1;
+ else
+ block_size -= 9;
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
- adev->vm_manager.num_level);
+ num_level);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
+ 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- PAGE_TABLE_BLOCK_SIZE,
- adev->vm_manager.block_size - 9);
+ PAGE_TABLE_BLOCK_SIZE,
+ block_size);
/* Send no-retry XNACK on fault to suppress VM fault storm. */
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index f4603a7..8e28270 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -222,13 +222,8 @@
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
base <<= 24;
- if (mc->mc_vram_size > 0xFFC0000000ULL) {
- dev_warn(adev->dev, "limiting VRAM\n");
- mc->real_vram_size = 0xFFC0000000ULL;
- mc->mc_vram_size = 0xFFC0000000ULL;
- }
- amdgpu_vram_location(adev, &adev->mc, base);
- amdgpu_gart_location(adev, mc);
+ amdgpu_device_vram_location(adev, &adev->mc, base);
+ amdgpu_device_gart_location(adev, mc);
}
static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
@@ -283,6 +278,7 @@
u32 tmp;
int chansize, numchan;
+ int r;
tmp = RREG32(mmMC_ARB_RAMCFG);
if (tmp & (1 << 11)) {
@@ -324,12 +320,17 @@
break;
}
adev->mc.vram_width = numchan * chansize;
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_device_resize_fb_bar(adev);
+ if (r)
+ return r;
+ }
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
adev->mc.visible_vram_size = adev->mc.aper_size;
/* set the gart size */
@@ -394,10 +395,10 @@
return pte_flag;
}
-static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
+static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ uint64_t *addr, uint64_t *flags)
{
- BUG_ON(addr & 0xFFFFFF0000000FFFULL);
- return addr;
+ BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
}
static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
@@ -831,8 +832,7 @@
if (r)
return r;
- amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
+ amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
adev->mc.mc_mask = 0xffffffffffULL;
@@ -877,7 +877,6 @@
* amdkfd will use VMIDs 8-15
*/
adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
- adev->vm_manager.num_level = 1;
amdgpu_vm_manager_init(adev);
/* base offset of vram pages */
@@ -897,9 +896,9 @@
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ amdgpu_gem_force_release(adev);
amdgpu_vm_manager_fini(adev);
gmc_v6_0_gart_fini(adev);
- amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
release_firmware(adev->mc.fw);
adev->mc.fw = NULL;
@@ -957,7 +956,7 @@
if (r)
return r;
- amdgpu_vm_reset_all_ids(adev);
+ amdgpu_vmid_reset_all(adev);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b0528ca..86e9d682 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -67,12 +67,12 @@
{
switch (adev->asic_type) {
case CHIP_TOPAZ:
- amdgpu_program_register_sequence(adev,
- iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_iceland_a11,
- (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+ amdgpu_device_program_register_sequence(adev,
+ iceland_mgcg_cgcg_init,
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_iceland_a11,
+ ARRAY_SIZE(golden_settings_iceland_a11));
break;
default:
break;
@@ -240,14 +240,8 @@
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
base <<= 24;
- if (mc->mc_vram_size > 0xFFC0000000ULL) {
- /* leave room for at least 1024M GTT */
- dev_warn(adev->dev, "limiting VRAM\n");
- mc->real_vram_size = 0xFFC0000000ULL;
- mc->mc_vram_size = 0xFFC0000000ULL;
- }
- amdgpu_vram_location(adev, &adev->mc, base);
- amdgpu_gart_location(adev, mc);
+ amdgpu_device_vram_location(adev, &adev->mc, base);
+ amdgpu_device_gart_location(adev, mc);
}
/**
@@ -322,6 +316,8 @@
*/
static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
{
+ int r;
+
adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
if (!adev->mc.vram_width) {
u32 tmp;
@@ -367,13 +363,18 @@
}
adev->mc.vram_width = numchan * chansize;
}
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_device_resize_fb_bar(adev);
+ if (r)
+ return r;
+ }
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
@@ -479,10 +480,10 @@
return pte_flag;
}
-static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
+static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ uint64_t *addr, uint64_t *flags)
{
- BUG_ON(addr & 0xFFFFFF0000000FFFULL);
- return addr;
+ BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
}
/**
@@ -970,8 +971,7 @@
* Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits.
*/
- amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
+ amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
/* Set the internal MC address mask
* This is the max address of the GPU's
@@ -1026,7 +1026,6 @@
* amdkfd will use VMIDs 8-15
*/
adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
- adev->vm_manager.num_level = 1;
amdgpu_vm_manager_init(adev);
/* base offset of vram pages */
@@ -1046,9 +1045,9 @@
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ amdgpu_gem_force_release(adev);
amdgpu_vm_manager_fini(adev);
gmc_v7_0_gart_fini(adev);
- amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
release_firmware(adev->mc.fw);
adev->mc.fw = NULL;
@@ -1108,7 +1107,7 @@
if (r)
return r;
- amdgpu_vm_reset_all_ids(adev);
+ amdgpu_vmid_reset_all(adev);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f368cfe..9a813d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -120,44 +120,44 @@
{
switch (adev->asic_type) {
case CHIP_FIJI:
- amdgpu_program_register_sequence(adev,
- fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ amdgpu_device_program_register_sequence(adev,
+ fiji_mgcg_cgcg_init,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_fiji_a10,
+ ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA:
- amdgpu_program_register_sequence(adev,
- tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ amdgpu_device_program_register_sequence(adev,
+ tonga_mgcg_cgcg_init,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_tonga_a11,
+ ARRAY_SIZE(golden_settings_tonga_a11));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
- amdgpu_program_register_sequence(adev,
- golden_settings_polaris11_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_polaris11_a11,
+ ARRAY_SIZE(golden_settings_polaris11_a11));
break;
case CHIP_POLARIS10:
- amdgpu_program_register_sequence(adev,
- golden_settings_polaris10_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_polaris10_a11,
+ ARRAY_SIZE(golden_settings_polaris10_a11));
break;
case CHIP_CARRIZO:
- amdgpu_program_register_sequence(adev,
- cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ cz_mgcg_cgcg_init,
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
break;
case CHIP_STONEY:
- amdgpu_program_register_sequence(adev,
- stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_stoney_common,
- (const u32)ARRAY_SIZE(golden_settings_stoney_common));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_mgcg_cgcg_init,
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_stoney_common,
+ ARRAY_SIZE(golden_settings_stoney_common));
break;
default:
break;
@@ -405,14 +405,8 @@
base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
base <<= 24;
- if (mc->mc_vram_size > 0xFFC0000000ULL) {
- /* leave room for at least 1024M GTT */
- dev_warn(adev->dev, "limiting VRAM\n");
- mc->real_vram_size = 0xFFC0000000ULL;
- mc->mc_vram_size = 0xFFC0000000ULL;
- }
- amdgpu_vram_location(adev, &adev->mc, base);
- amdgpu_gart_location(adev, mc);
+ amdgpu_device_vram_location(adev, &adev->mc, base);
+ amdgpu_device_gart_location(adev, mc);
}
/**
@@ -498,6 +492,8 @@
*/
static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
{
+ int r;
+
adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
if (!adev->mc.vram_width) {
u32 tmp;
@@ -543,13 +539,18 @@
}
adev->mc.vram_width = numchan * chansize;
}
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_device_resize_fb_bar(adev);
+ if (r)
+ return r;
+ }
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
@@ -676,10 +677,10 @@
return pte_flag;
}
-static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
+static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ uint64_t *addr, uint64_t *flags)
{
- BUG_ON(addr & 0xFFFFFF0000000FFFULL);
- return addr;
+ BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
}
/**
@@ -1067,8 +1068,7 @@
* Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits.
*/
- amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
+ amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
/* Set the internal MC address mask
* This is the max address of the GPU's
@@ -1123,7 +1123,6 @@
* amdkfd will use VMIDs 8-15
*/
adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
- adev->vm_manager.num_level = 1;
amdgpu_vm_manager_init(adev);
/* base offset of vram pages */
@@ -1143,9 +1142,9 @@
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ amdgpu_gem_force_release(adev);
amdgpu_vm_manager_fini(adev);
gmc_v8_0_gart_fini(adev);
- amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
release_firmware(adev->mc.fw);
adev->mc.fw = NULL;
@@ -1213,7 +1212,7 @@
if (r)
return r;
- amdgpu_vm_reset_all_ids(adev);
+ amdgpu_vmid_reset_all(adev);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 9737408b..3b7e7af 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -25,20 +25,19 @@
#include "gmc_v9_0.h"
#include "amdgpu_atomfirmware.h"
-#include "vega10/soc15ip.h"
-#include "vega10/HDP/hdp_4_0_offset.h"
-#include "vega10/HDP/hdp_4_0_sh_mask.h"
-#include "vega10/GC/gc_9_0_sh_mask.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/vega10_enum.h"
-#include "vega10/MMHUB/mmhub_1_0_offset.h"
-#include "vega10/ATHUB/athub_1_0_offset.h"
+#include "hdp/hdp_4_0_offset.h"
+#include "hdp/hdp_4_0_sh_mask.h"
+#include "gc/gc_9_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "vega10_enum.h"
+#include "mmhub/mmhub_1_0_offset.h"
+#include "athub/athub_1_0_offset.h"
+#include "soc15.h"
#include "soc15_common.h"
+#include "umc/umc_6_0_sh_mask.h"
-#include "nbio_v6_1.h"
-#include "nbio_v7_0.h"
#include "gfxhub_v1_0.h"
#include "mmhub_v1_0.h"
@@ -73,16 +72,131 @@
0xf6e, 0x0fffffff, 0x00000000,
};
-static const u32 golden_settings_mmhub_1_0_0[] =
+static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
{
- SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
- SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
+ SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
+ SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
};
-static const u32 golden_settings_athub_1_0_0[] =
+static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
{
- SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
- SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
+ SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
+};
+
+/* Ecc related register addresses, (BASE + reg offset) */
+/* Universal Memory Controller caps (may be fused). */
+/* UMCCH:UmcLocalCap */
+#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
+#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
+#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
+#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
+
+/* Universal Memory Controller Channel config. */
+/* UMCCH:UMC_CONFIG */
+#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
+#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
+#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
+#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
+
+/* Universal Memory Controller Channel Ecc config. */
+/* UMCCH:EccCtrl */
+#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
+#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
+#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
+#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
+
+static const uint32_t ecc_umclocalcap_addrs[] = {
+ UMCLOCALCAPS_ADDR0,
+ UMCLOCALCAPS_ADDR1,
+ UMCLOCALCAPS_ADDR2,
+ UMCLOCALCAPS_ADDR3,
+ UMCLOCALCAPS_ADDR4,
+ UMCLOCALCAPS_ADDR5,
+ UMCLOCALCAPS_ADDR6,
+ UMCLOCALCAPS_ADDR7,
+ UMCLOCALCAPS_ADDR8,
+ UMCLOCALCAPS_ADDR9,
+ UMCLOCALCAPS_ADDR10,
+ UMCLOCALCAPS_ADDR11,
+ UMCLOCALCAPS_ADDR12,
+ UMCLOCALCAPS_ADDR13,
+ UMCLOCALCAPS_ADDR14,
+ UMCLOCALCAPS_ADDR15,
+};
+
+static const uint32_t ecc_umcch_umc_config_addrs[] = {
+ UMCCH_UMC_CONFIG_ADDR0,
+ UMCCH_UMC_CONFIG_ADDR1,
+ UMCCH_UMC_CONFIG_ADDR2,
+ UMCCH_UMC_CONFIG_ADDR3,
+ UMCCH_UMC_CONFIG_ADDR4,
+ UMCCH_UMC_CONFIG_ADDR5,
+ UMCCH_UMC_CONFIG_ADDR6,
+ UMCCH_UMC_CONFIG_ADDR7,
+ UMCCH_UMC_CONFIG_ADDR8,
+ UMCCH_UMC_CONFIG_ADDR9,
+ UMCCH_UMC_CONFIG_ADDR10,
+ UMCCH_UMC_CONFIG_ADDR11,
+ UMCCH_UMC_CONFIG_ADDR12,
+ UMCCH_UMC_CONFIG_ADDR13,
+ UMCCH_UMC_CONFIG_ADDR14,
+ UMCCH_UMC_CONFIG_ADDR15,
+};
+
+static const uint32_t ecc_umcch_eccctrl_addrs[] = {
+ UMCCH_ECCCTRL_ADDR0,
+ UMCCH_ECCCTRL_ADDR1,
+ UMCCH_ECCCTRL_ADDR2,
+ UMCCH_ECCCTRL_ADDR3,
+ UMCCH_ECCCTRL_ADDR4,
+ UMCCH_ECCCTRL_ADDR5,
+ UMCCH_ECCCTRL_ADDR6,
+ UMCCH_ECCCTRL_ADDR7,
+ UMCCH_ECCCTRL_ADDR8,
+ UMCCH_ECCCTRL_ADDR9,
+ UMCCH_ECCCTRL_ADDR10,
+ UMCCH_ECCCTRL_ADDR11,
+ UMCCH_ECCCTRL_ADDR12,
+ UMCCH_ECCCTRL_ADDR13,
+ UMCCH_ECCCTRL_ADDR14,
+ UMCCH_ECCCTRL_ADDR15,
};
static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
@@ -134,7 +248,7 @@
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
- struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
+ struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
uint32_t status = 0;
u64 addr;
@@ -148,9 +262,9 @@
if (printk_ratelimit()) {
dev_err(adev->dev,
- "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
- entry->vm_id_src ? "mmhub" : "gfxhub",
- entry->src_id, entry->ring_id, entry->vm_id,
+ "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pas_id:%u)\n",
+ entry->vmid_src ? "mmhub" : "gfxhub",
+ entry->src_id, entry->ring_id, entry->vmid,
entry->pas_id);
dev_err(adev->dev, " at page 0x%016llx from %d\n",
addr, entry->client_id);
@@ -174,13 +288,13 @@
adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
}
-static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
+static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
{
u32 req = 0;
- /* invalidate using legacy mode on vm_id*/
+ /* invalidate using legacy mode on vmid*/
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- PER_VMID_INVALIDATE_REQ, 1 << vm_id);
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
@@ -216,10 +330,7 @@
unsigned i, j;
/* flush hdp cache */
- if (adev->flags & AMD_IS_APU)
- nbio_v7_0_hdp_flush(adev);
- else
- nbio_v6_1_hdp_flush(adev);
+ adev->nbio_funcs->hdp_flush(adev);
spin_lock(&adev->mc.invalidate_lock);
@@ -358,11 +469,28 @@
return pte_flag;
}
-static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
+static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ uint64_t *addr, uint64_t *flags)
{
- addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
- BUG_ON(addr & 0xFFFF00000000003FULL);
- return addr;
+ if (!(*flags & AMDGPU_PDE_PTE))
+ *addr = adev->vm_manager.vram_base_offset + *addr -
+ adev->mc.vram_start;
+ BUG_ON(*addr & 0xFFFF00000000003FULL);
+
+ if (!adev->mc.translate_further)
+ return;
+
+ if (level == AMDGPU_VM_PDB1) {
+ /* Set the block fragment size */
+ if (!(*flags & AMDGPU_PDE_PTE))
+ *flags |= AMDGPU_PDE_BFS(0x9);
+
+ } else if (level == AMDGPU_VM_PDB0) {
+ if (*flags & AMDGPU_PDE_PTE)
+ *flags &= ~AMDGPU_PDE_PTE;
+ else
+ *flags |= AMDGPU_PTE_TF;
+ }
}
static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
@@ -386,9 +514,96 @@
gmc_v9_0_set_gart_funcs(adev);
gmc_v9_0_set_irq_funcs(adev);
+ adev->mc.shared_aperture_start = 0x2000000000000000ULL;
+ adev->mc.shared_aperture_end =
+ adev->mc.shared_aperture_start + (4ULL << 30) - 1;
+ adev->mc.private_aperture_start =
+ adev->mc.shared_aperture_end + 1;
+ adev->mc.private_aperture_end =
+ adev->mc.private_aperture_start + (4ULL << 30) - 1;
+
return 0;
}
+static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
+{
+ uint32_t reg_val;
+ uint32_t reg_addr;
+ uint32_t field_val;
+ size_t i;
+ uint32_t fv2;
+ size_t lost_sheep;
+
+ DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
+
+ lost_sheep = 0;
+ for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
+ reg_addr = ecc_umclocalcap_addrs[i];
+ DRM_DEBUG("ecc: "
+ "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
+ i, reg_addr);
+ reg_val = RREG32(reg_addr);
+ field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
+ EccDis);
+ DRM_DEBUG("ecc: "
+ "reg_val: 0x%08x, "
+ "EccDis: 0x%08x, ",
+ reg_val, field_val);
+ if (field_val) {
+ DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
+ ++lost_sheep;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
+ reg_addr = ecc_umcch_umc_config_addrs[i];
+ DRM_DEBUG("ecc: "
+ "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
+ i, reg_addr);
+ reg_val = RREG32(reg_addr);
+ field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
+ DramReady);
+ DRM_DEBUG("ecc: "
+ "reg_val: 0x%08x, "
+ "DramReady: 0x%08x\n",
+ reg_val, field_val);
+
+ if (!field_val) {
+ DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
+ ++lost_sheep;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
+ reg_addr = ecc_umcch_eccctrl_addrs[i];
+ DRM_DEBUG("ecc: "
+ "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
+ i, reg_addr);
+ reg_val = RREG32(reg_addr);
+ field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
+ WrEccEn);
+ fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
+ RdEccEn);
+ DRM_DEBUG("ecc: "
+ "reg_val: 0x%08x, "
+ "WrEccEn: 0x%08x, "
+ "RdEccEn: 0x%08x\n",
+ reg_val, field_val, fv2);
+
+ if (!field_val) {
+ DRM_DEBUG("ecc: WrEccEn is not set\n");
+ ++lost_sheep;
+ }
+ if (!fv2) {
+ DRM_DEBUG("ecc: RdEccEn is not set\n");
+ ++lost_sheep;
+ }
+ }
+
+ DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
+ return lost_sheep == 0;
+}
+
static int gmc_v9_0_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -403,6 +618,7 @@
*/
unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
unsigned i;
+ int r;
for(i = 0; i < adev->num_rings; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
@@ -418,6 +634,18 @@
for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
BUG_ON(vm_inv_eng[i] > 16);
+ if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
+ r = gmc_v9_0_ecc_available(adev);
+ if (r == 1) {
+ DRM_INFO("ECC is active.\n");
+ } else if (r == 0) {
+ DRM_INFO("ECC is not present.\n");
+ } else {
+ DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
+ return r;
+ }
+ }
+
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
}
@@ -427,8 +655,8 @@
u64 base = 0;
if (!amdgpu_sriov_vf(adev))
base = mmhub_v1_0_get_fb_location(adev);
- amdgpu_vram_location(adev, &adev->mc, base);
- amdgpu_gart_location(adev, mc);
+ amdgpu_device_vram_location(adev, &adev->mc, base);
+ amdgpu_device_gart_location(adev, mc);
/* base offset of vram pages */
if (adev->flags & AMD_IS_APU)
adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
@@ -449,6 +677,7 @@
{
u32 tmp;
int chansize, numchan;
+ int r;
adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
if (!adev->mc.vram_width) {
@@ -494,17 +723,21 @@
adev->mc.vram_width = numchan * chansize;
}
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size =
- ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
- nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
+ adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = adev->mc.mc_vram_size;
- adev->mc.visible_vram_size = adev->mc.aper_size;
+
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_device_resize_fb_bar(adev);
+ if (r)
+ return r;
+ }
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* In case the PCI BAR is larger than the actual amount of vram */
+ adev->mc.visible_vram_size = adev->mc.aper_size;
if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
adev->mc.visible_vram_size = adev->mc.real_vram_size;
@@ -561,14 +794,12 @@
case CHIP_RAVEN:
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
- adev->vm_manager.vm_size = 1U << 18;
- adev->vm_manager.block_size = 9;
- adev->vm_manager.num_level = 3;
- amdgpu_vm_set_fragment_size(adev, 9);
+ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
} else {
- /* vm_size is 64GB for legacy 2-level page support */
- amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.num_level = 1;
+ /* vm_size is 128TB + 512GB for legacy 3-level page support */
+ amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
+ adev->mc.translate_further =
+ adev->vm_manager.num_level > 1;
}
break;
case CHIP_VEGA10:
@@ -579,20 +810,12 @@
* vm size is 256TB (48bit), maximum size of Vega10,
* block size 512 (9bit)
*/
- adev->vm_manager.vm_size = 1U << 18;
- adev->vm_manager.block_size = 9;
- adev->vm_manager.num_level = 3;
- amdgpu_vm_set_fragment_size(adev, 9);
+ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
break;
default:
break;
}
- DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
- adev->vm_manager.vm_size,
- adev->vm_manager.block_size,
- adev->vm_manager.fragment_size);
-
/* This interrupt is VMC page fault.*/
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
&adev->mc.vm_fault);
@@ -602,8 +825,6 @@
if (r)
return r;
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
-
/* Set the internal MC address mask
* This is the max address of the GPU's
* internal address space.
@@ -663,7 +884,7 @@
}
/**
- * gmc_v8_0_gart_fini - vm fini callback
+ * gmc_v9_0_gart_fini - vm fini callback
*
* @adev: amdgpu_device pointer
*
@@ -679,9 +900,9 @@
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ amdgpu_gem_force_release(adev);
amdgpu_vm_manager_fini(adev);
gmc_v9_0_gart_fini(adev);
- amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
return 0;
@@ -689,19 +910,20 @@
static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
{
+
switch (adev->asic_type) {
case CHIP_VEGA10:
- amdgpu_program_register_sequence(adev,
+ soc15_program_register_sequence(adev,
golden_settings_mmhub_1_0_0,
- (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
- amdgpu_program_register_sequence(adev,
+ ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+ soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0,
- (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+ ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
case CHIP_RAVEN:
- amdgpu_program_register_sequence(adev,
+ soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0,
- (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+ ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
default:
break;
@@ -719,9 +941,9 @@
bool value;
u32 tmp;
- amdgpu_program_register_sequence(adev,
- golden_settings_vega10_hdp,
- (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_vega10_hdp,
+ ARRAY_SIZE(golden_settings_vega10_hdp));
if (adev->gart.robj == NULL) {
dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
@@ -754,10 +976,7 @@
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
/* After HDP is initialized, flush HDP.*/
- if (adev->flags & AMD_IS_APU)
- nbio_v7_0_hdp_flush(adev);
- else
- nbio_v6_1_hdp_flush(adev);
+ adev->nbio_funcs->hdp_flush(adev);
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
value = false;
@@ -842,7 +1061,7 @@
if (r)
return r;
- amdgpu_vm_reset_all_ids(adev);
+ amdgpu_vmid_reset_all(adev);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index bd592cb..c4e4be3 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -259,7 +259,7 @@
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
- entry->vm_id = (dw[2] >> 8) & 0xff;
+ entry->vmid = (dw[2] >> 8) & 0xff;
entry->pas_id = (dw[2] >> 16) & 0xffff;
/* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index f33d1ff..d9e9e52 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -1682,8 +1682,8 @@
if (gate) {
/* stop the UVD block */
- ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_GATE);
kv_update_uvd_dpm(adev, gate);
if (pi->caps_uvd_pg)
/* power off the UVD block */
@@ -1695,8 +1695,8 @@
/* re-init the UVD block */
kv_update_uvd_dpm(adev, gate);
- ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index cc21c4b..ffd5b7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -23,14 +23,12 @@
#include "amdgpu.h"
#include "mmhub_v1_0.h"
-#include "vega10/soc15ip.h"
-#include "vega10/MMHUB/mmhub_1_0_offset.h"
-#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
-#include "vega10/MMHUB/mmhub_1_0_default.h"
-#include "vega10/ATHUB/athub_1_0_offset.h"
-#include "vega10/ATHUB/athub_1_0_sh_mask.h"
-#include "vega10/ATHUB/athub_1_0_default.h"
-#include "vega10/vega10_enum.h"
+#include "mmhub/mmhub_1_0_offset.h"
+#include "mmhub/mmhub_1_0_sh_mask.h"
+#include "mmhub/mmhub_1_0_default.h"
+#include "athub/athub_1_0_offset.h"
+#include "athub/athub_1_0_sh_mask.h"
+#include "vega10_enum.h"
#include "soc15_common.h"
@@ -157,10 +155,15 @@
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
- tmp = mmVM_L2_CNTL3_DEFAULT;
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
- WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
+ if (adev->mc.translate_further) {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+ } else {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ }
tmp = mmVM_L2_CNTL4_DEFAULT;
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
@@ -198,32 +201,40 @@
static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
{
- int i;
+ unsigned num_level, block_size;
uint32_t tmp;
+ int i;
+
+ num_level = adev->vm_manager.num_level;
+ block_size = adev->vm_manager.block_size;
+ if (adev->mc.translate_further)
+ num_level -= 1;
+ else
+ block_size -= 9;
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
+ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+ num_level);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- ENABLE_CONTEXT, 1);
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- PAGE_TABLE_DEPTH, adev->vm_manager.num_level);
+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
+ 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
- tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
- tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
- PAGE_TABLE_BLOCK_SIZE,
- adev->vm_manager.block_size - 9);
+ PAGE_TABLE_BLOCK_SIZE,
+ block_size);
/* Send no-retry XNACK on fault to suppress VM fault storm. */
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index a43cffb..271452d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -22,11 +22,10 @@
*/
#include "amdgpu.h"
-#include "vega10/soc15ip.h"
-#include "vega10/NBIO/nbio_6_1_offset.h"
-#include "vega10/NBIO/nbio_6_1_sh_mask.h"
-#include "vega10/GC/gc_9_0_offset.h"
-#include "vega10/GC/gc_9_0_sh_mask.h"
+#include "nbio/nbio_6_1_offset.h"
+#include "nbio/nbio_6_1_sh_mask.h"
+#include "gc/gc_9_0_offset.h"
+#include "gc/gc_9_0_sh_mask.h"
#include "soc15.h"
#include "vega10_ih.h"
#include "soc15_common.h"
@@ -254,7 +253,7 @@
}
/* Trigger recovery due to world switch failure */
- amdgpu_gpu_recover(adev, NULL);
+ amdgpu_device_gpu_recover(adev, NULL, false);
}
static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
@@ -278,7 +277,7 @@
int r;
/* trigger gpu-reset by hypervisor only if TDR disbaled */
- if (amdgpu_lockup_timeout == 0) {
+ if (!amdgpu_gpu_recovery) {
/* see what event we get */
r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
@@ -361,5 +360,6 @@
.req_full_gpu = xgpu_ai_request_full_gpu_access,
.rel_full_gpu = xgpu_ai_release_full_gpu_access,
.reset_gpu = xgpu_ai_request_reset,
+ .wait_reset = NULL,
.trans_msg = xgpu_ai_mailbox_trans_msg,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index dae6d3a..9fc1c37 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -279,32 +279,32 @@
{
switch (adev->asic_type) {
case CHIP_FIJI:
- amdgpu_program_register_sequence(adev,
- xgpu_fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(
- xgpu_fiji_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- xgpu_fiji_golden_settings_a10,
- (const u32)ARRAY_SIZE(
- xgpu_fiji_golden_settings_a10));
- amdgpu_program_register_sequence(adev,
- xgpu_fiji_golden_common_all,
- (const u32)ARRAY_SIZE(
- xgpu_fiji_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ xgpu_fiji_mgcg_cgcg_init,
+ ARRAY_SIZE(
+ xgpu_fiji_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ xgpu_fiji_golden_settings_a10,
+ ARRAY_SIZE(
+ xgpu_fiji_golden_settings_a10));
+ amdgpu_device_program_register_sequence(adev,
+ xgpu_fiji_golden_common_all,
+ ARRAY_SIZE(
+ xgpu_fiji_golden_common_all));
break;
case CHIP_TONGA:
- amdgpu_program_register_sequence(adev,
- xgpu_tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(
- xgpu_tonga_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- xgpu_tonga_golden_settings_a11,
- (const u32)ARRAY_SIZE(
- xgpu_tonga_golden_settings_a11));
- amdgpu_program_register_sequence(adev,
- xgpu_tonga_golden_common_all,
- (const u32)ARRAY_SIZE(
- xgpu_tonga_golden_common_all));
+ amdgpu_device_program_register_sequence(adev,
+ xgpu_tonga_mgcg_cgcg_init,
+ ARRAY_SIZE(
+ xgpu_tonga_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ xgpu_tonga_golden_settings_a11,
+ ARRAY_SIZE(
+ xgpu_tonga_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ xgpu_tonga_golden_common_all,
+ ARRAY_SIZE(
+ xgpu_tonga_golden_common_all));
break;
default:
BUG_ON("Doesn't support chip type.\n");
@@ -446,8 +446,10 @@
request == IDH_REQ_GPU_FINI_ACCESS ||
request == IDH_REQ_GPU_RESET_ACCESS) {
r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
- if (r)
- pr_err("Doesn't get ack from pf, continue\n");
+ if (r) {
+ pr_err("Doesn't get ack from pf, give up\n");
+ return r;
+ }
}
return 0;
@@ -458,6 +460,11 @@
return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
}
+static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev)
+{
+ return xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL);
+}
+
static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
bool init)
{
@@ -514,7 +521,7 @@
}
/* Trigger recovery due to world switch failure */
- amdgpu_gpu_recover(adev, NULL);
+ amdgpu_device_gpu_recover(adev, NULL, false);
}
static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
@@ -538,7 +545,7 @@
int r;
/* trigger gpu-reset by hypervisor only if TDR disbaled */
- if (amdgpu_lockup_timeout == 0) {
+ if (!amdgpu_gpu_recovery) {
/* see what event we get */
r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
@@ -613,5 +620,6 @@
.req_full_gpu = xgpu_vi_request_full_gpu_access,
.rel_full_gpu = xgpu_vi_release_full_gpu_access,
.reset_gpu = xgpu_vi_request_reset,
+ .wait_reset = xgpu_vi_wait_reset_cmpl,
.trans_msg = NULL, /* Does not need to trans VF errors to host. */
};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 904a1ba..d4da663d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -24,17 +24,16 @@
#include "amdgpu_atombios.h"
#include "nbio_v6_1.h"
-#include "vega10/soc15ip.h"
-#include "vega10/NBIO/nbio_6_1_default.h"
-#include "vega10/NBIO/nbio_6_1_offset.h"
-#include "vega10/NBIO/nbio_6_1_sh_mask.h"
-#include "vega10/vega10_enum.h"
+#include "nbio/nbio_6_1_default.h"
+#include "nbio/nbio_6_1_offset.h"
+#include "nbio/nbio_6_1_sh_mask.h"
+#include "vega10_enum.h"
#define smnCPM_CONTROL 0x11180460
#define smnPCIE_CNTL2 0x11180070
#define smnPCIE_CONFIG_CNTL 0x11180044
-u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -44,19 +43,7 @@
return tmp;
}
-u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx)
-{
- return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
-}
-
-void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx, uint32_t val)
-{
- WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
-}
-
-void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
+static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
{
if (enable)
WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
@@ -66,26 +53,23 @@
WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
}
-void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
+static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
{
WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
}
-u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
{
return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
}
-static const u32 nbio_sdma_doorbell_range_reg[] =
-{
- SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
- SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
-};
-
-void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
bool use_doorbell, int doorbell_index)
{
- u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
+ u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
+
+ u32 doorbell_range = RREG32(reg);
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
@@ -93,17 +77,18 @@
} else
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
- WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
+ WREG32(reg, doorbell_range);
+
}
-void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
- bool enable)
+static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
{
WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
}
-void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
- bool enable)
+static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+ bool enable)
{
u32 tmp = 0;
@@ -122,8 +107,8 @@
}
-void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
- bool use_doorbell, int doorbell_index)
+static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index)
{
u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
@@ -136,7 +121,7 @@
WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
}
-void nbio_v6_1_ih_control(struct amdgpu_device *adev)
+static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
{
u32 interrupt_cntl;
@@ -152,8 +137,8 @@
WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
}
-void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t def, data;
@@ -180,8 +165,8 @@
WREG32_PCIE(smnCPM_CONTROL, data);
}
-void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
- bool enable)
+static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t def, data;
@@ -200,7 +185,8 @@
WREG32_PCIE(smnPCIE_CNTL2, data);
}
-void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
+static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
+ u32 *flags)
{
int data;
@@ -215,9 +201,27 @@
*flags |= AMD_CG_SUPPORT_BIF_LS;
}
-const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
- .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
- .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
+static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
+}
+
+static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
+}
+
+static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
+}
+
+static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
+}
+
+static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
@@ -232,12 +236,7 @@
.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
};
-const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
- .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
- .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
-};
-
-void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
+static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
{
uint32_t reg;
@@ -254,7 +253,7 @@
}
}
-void nbio_v6_1_init_registers(struct amdgpu_device *adev)
+static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
{
uint32_t def, data;
@@ -265,3 +264,25 @@
if (def != data)
WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
}
+
+const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+ .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
+ .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
+ .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
+ .get_rev_id = nbio_v6_1_get_rev_id,
+ .mc_access_enable = nbio_v6_1_mc_access_enable,
+ .hdp_flush = nbio_v6_1_hdp_flush,
+ .get_memsize = nbio_v6_1_get_memsize,
+ .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
+ .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
+ .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
+ .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
+ .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
+ .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
+ .get_clockgating_state = nbio_v6_1_get_clockgating_state,
+ .ih_control = nbio_v6_1_ih_control,
+ .init_registers = nbio_v6_1_init_registers,
+ .detect_hw_virt = nbio_v6_1_detect_hw_virt,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index 14ca8d4..0743a6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -26,30 +26,6 @@
#include "soc15_common.h"
-extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
-int nbio_v6_1_init(struct amdgpu_device *adev);
-u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx);
-void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx, uint32_t val);
-void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable);
-void nbio_v6_1_hdp_flush(struct amdgpu_device *adev);
-u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev);
-void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index);
-void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
- bool enable);
-void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
- bool enable);
-void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
- bool use_doorbell, int doorbell_index);
-void nbio_v6_1_ih_control(struct amdgpu_device *adev);
-u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev);
-void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable);
-void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable);
-void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
-void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);
-void nbio_v6_1_init_registers(struct amdgpu_device *adev);
+extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index f802b97..17a9131 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -24,15 +24,17 @@
#include "amdgpu_atombios.h"
#include "nbio_v7_0.h"
-#include "vega10/soc15ip.h"
-#include "raven1/NBIO/nbio_7_0_default.h"
-#include "raven1/NBIO/nbio_7_0_offset.h"
-#include "raven1/NBIO/nbio_7_0_sh_mask.h"
-#include "vega10/vega10_enum.h"
+#include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
+#include "nbio/nbio_7_0_sh_mask.h"
+#include "vega10_enum.h"
#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
-u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
+#define smnCPM_CONTROL 0x11180460
+#define smnPCIE_CNTL2 0x11180070
+
+static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -42,19 +44,7 @@
return tmp;
}
-u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx)
-{
- return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
-}
-
-void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx, uint32_t val)
-{
- WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
-}
-
-void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
+static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
{
if (enable)
WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
@@ -63,26 +53,23 @@
WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
}
-void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
+static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
{
WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
}
-u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
+static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
{
return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
}
-static const u32 nbio_sdma_doorbell_range_reg[] =
+static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index)
{
- SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
- SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
-};
+ u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
-void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index)
-{
- u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
+ u32 doorbell_range = RREG32(reg);
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
@@ -90,17 +77,23 @@
} else
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
- WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
+ WREG32(reg, doorbell_range);
}
-void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
- bool enable)
+static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
{
WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
}
-void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
- bool use_doorbell, int doorbell_index)
+static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+ bool enable)
+{
+
+}
+
+static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index)
{
u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
@@ -130,8 +123,8 @@
WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
}
-void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t def, data;
@@ -169,7 +162,43 @@
nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
}
-void nbio_v7_0_ih_control(struct amdgpu_device *adev)
+static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_PCIE(smnPCIE_CNTL2);
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
+ data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+ PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+ PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+ } else {
+ data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+ PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+ PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+ }
+
+ if (def != data)
+ WREG32_PCIE(smnPCIE_CNTL2, data);
+}
+
+static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
+ u32 *flags)
+{
+ int data;
+
+ /* AMD_CG_SUPPORT_BIF_MGCG */
+ data = RREG32_PCIE(smnCPM_CONTROL);
+ if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_BIF_MGCG;
+
+ /* AMD_CG_SUPPORT_BIF_LS */
+ data = RREG32_PCIE(smnPCIE_CNTL2);
+ if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_BIF_LS;
+}
+
+static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
{
u32 interrupt_cntl;
@@ -185,9 +214,27 @@
WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
}
+static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
+}
+
+static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
+}
+
+static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
+}
+
+static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
+}
+
const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
- .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ),
- .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE),
.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
@@ -202,7 +249,35 @@
.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
};
-const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = {
- .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2),
- .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)
+static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
+{
+ if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
+ adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
+}
+
+static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
+{
+
+}
+
+const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+ .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
+ .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
+ .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
+ .get_rev_id = nbio_v7_0_get_rev_id,
+ .mc_access_enable = nbio_v7_0_mc_access_enable,
+ .hdp_flush = nbio_v7_0_hdp_flush,
+ .get_memsize = nbio_v7_0_get_memsize,
+ .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
+ .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
+ .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
+ .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
+ .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
+ .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
+ .get_clockgating_state = nbio_v7_0_get_clockgating_state,
+ .ih_control = nbio_v7_0_ih_control,
+ .init_registers = nbio_v7_0_init_registers,
+ .detect_hw_virt = nbio_v7_0_detect_hw_virt,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
index df8fa90..508d549 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -26,24 +26,6 @@
#include "soc15_common.h"
-extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
-extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
-int nbio_v7_0_init(struct amdgpu_device *adev);
-u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx);
-void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
- uint32_t idx, uint32_t val);
-void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable);
-void nbio_v7_0_hdp_flush(struct amdgpu_device *adev);
-u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev);
-void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index);
-void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
- bool enable);
-void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
- bool use_doorbell, int doorbell_index);
-void nbio_v7_0_ih_control(struct amdgpu_device *adev);
-u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev);
-void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable);
+extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 4e20d91..5a9fe24 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -30,10 +30,9 @@
#include "soc15_common.h"
#include "psp_v10_0.h"
-#include "vega10/soc15ip.h"
-#include "raven1/MP/mp_10_0_offset.h"
-#include "raven1/GC/gc_9_1_offset.h"
-#include "raven1/SDMA0/sdma0_4_1_offset.h"
+#include "mp/mp_10_0_offset.h"
+#include "gc/gc_9_1_offset.h"
+#include "sdma0/sdma0_4_1_offset.h"
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
@@ -298,9 +297,10 @@
}
static int
-psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
- unsigned int *sram_data_reg_offset,
- enum AMDGPU_UCODE_ID ucode_id)
+psp_v10_0_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+ unsigned int *sram_data_reg_offset,
+ enum AMDGPU_UCODE_ID ucode_id)
{
int ret = 0;
@@ -395,7 +395,7 @@
uint32_t *ucode_mem = NULL;
struct amdgpu_device *adev = psp->adev;
- err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
+ err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
&fw_sram_data_reg_offset, ucode_type);
if (err)
return false;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index c7bcfe8..19bd193 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -31,12 +31,11 @@
#include "soc15_common.h"
#include "psp_v3_1.h"
-#include "vega10/soc15ip.h"
-#include "vega10/MP/mp_9_0_offset.h"
-#include "vega10/MP/mp_9_0_sh_mask.h"
-#include "vega10/GC/gc_9_0_offset.h"
-#include "vega10/SDMA0/sdma0_4_0_offset.h"
-#include "vega10/NBIO/nbio_6_1_offset.h"
+#include "mp/mp_9_0_offset.h"
+#include "mp/mp_9_0_sh_mask.h"
+#include "gc/gc_9_0_offset.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "nbio/nbio_6_1_offset.h"
MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
@@ -410,9 +409,10 @@
}
static int
-psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
- unsigned int *sram_data_reg_offset,
- enum AMDGPU_UCODE_ID ucode_id)
+psp_v3_1_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+ unsigned int *sram_data_reg_offset,
+ enum AMDGPU_UCODE_ID ucode_id)
{
int ret = 0;
@@ -507,7 +507,7 @@
uint32_t *ucode_mem = NULL;
struct amdgpu_device *adev = psp->adev;
- err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
+ err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
&fw_sram_data_reg_offset, ucode_type);
if (err)
return false;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 400c645..bd844ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -93,12 +93,12 @@
{
switch (adev->asic_type) {
case CHIP_TOPAZ:
- amdgpu_program_register_sequence(adev,
- iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_iceland_a11,
- (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+ amdgpu_device_program_register_sequence(adev,
+ iceland_mgcg_cgcg_init,
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_iceland_a11,
+ ARRAY_SIZE(golden_settings_iceland_a11));
break;
default:
break;
@@ -246,15 +246,13 @@
*/
static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 vmid = vm_id & 0xf;
-
/* IB packet must end on a 8 DW boundary */
sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
- SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
+ SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
/* base must be 32 byte aligned */
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -861,14 +859,14 @@
* using sDMA (VI).
*/
static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- if (vm_id < 8) {
- amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+ if (vmid < 8) {
+ amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
} else {
- amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+ amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
}
amdgpu_ring_write(ring, pd_addr >> 12);
@@ -876,7 +874,7 @@
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
/* wait for flush */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 943cf67..1fa5911 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -192,47 +192,47 @@
{
switch (adev->asic_type) {
case CHIP_FIJI:
- amdgpu_program_register_sequence(adev,
- fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ amdgpu_device_program_register_sequence(adev,
+ fiji_mgcg_cgcg_init,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_fiji_a10,
+ ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA:
- amdgpu_program_register_sequence(adev,
- tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ amdgpu_device_program_register_sequence(adev,
+ tonga_mgcg_cgcg_init,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_tonga_a11,
+ ARRAY_SIZE(golden_settings_tonga_a11));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
- amdgpu_program_register_sequence(adev,
- golden_settings_polaris11_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_polaris11_a11,
+ ARRAY_SIZE(golden_settings_polaris11_a11));
break;
case CHIP_POLARIS10:
- amdgpu_program_register_sequence(adev,
- golden_settings_polaris10_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+ amdgpu_device_program_register_sequence(adev,
+ golden_settings_polaris10_a11,
+ ARRAY_SIZE(golden_settings_polaris10_a11));
break;
case CHIP_CARRIZO:
- amdgpu_program_register_sequence(adev,
- cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- cz_golden_settings_a11,
- (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ cz_mgcg_cgcg_init,
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ cz_golden_settings_a11,
+ ARRAY_SIZE(cz_golden_settings_a11));
break;
case CHIP_STONEY:
- amdgpu_program_register_sequence(adev,
- stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- stoney_golden_settings_a11,
- (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_mgcg_cgcg_init,
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_golden_settings_a11,
+ ARRAY_SIZE(stoney_golden_settings_a11));
break;
default:
break;
@@ -355,7 +355,7 @@
struct amdgpu_device *adev = ring->adev;
u32 wptr;
- if (ring->use_doorbell) {
+ if (ring->use_doorbell || ring->use_pollmem) {
/* XXX check if swapping is necessary on BE */
wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
} else {
@@ -380,10 +380,13 @@
if (ring->use_doorbell) {
u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
-
/* XXX check if swapping is necessary on BE */
WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
+ } else if (ring->use_pollmem) {
+ u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
+
+ WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
} else {
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
@@ -414,15 +417,13 @@
*/
static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 vmid = vm_id & 0xf;
-
/* IB packet must end on a 8 DW boundary */
sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
- SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
+ SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
/* base must be 32 byte aligned */
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -718,10 +719,17 @@
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
- if (amdgpu_sriov_vf(adev))
- wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
- else
- wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
+ if (ring->use_pollmem) {
+ /*wptr polling is not enogh fast, directly clean the wptr register */
+ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
+ SDMA0_GFX_RB_WPTR_POLL_CNTL,
+ ENABLE, 1);
+ } else {
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
+ SDMA0_GFX_RB_WPTR_POLL_CNTL,
+ ENABLE, 0);
+ }
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
/* enable DMA RB */
@@ -1120,14 +1128,14 @@
* using sDMA (VI).
*/
static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- if (vm_id < 8) {
- amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+ if (vmid < 8) {
+ amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
} else {
- amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+ amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
}
amdgpu_ring_write(ring, pd_addr >> 12);
@@ -1135,7 +1143,7 @@
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
/* wait for flush */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
@@ -1203,9 +1211,13 @@
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL;
- ring->use_doorbell = true;
- ring->doorbell_index = (i == 0) ?
- AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
+ if (!amdgpu_sriov_vf(adev)) {
+ ring->use_doorbell = true;
+ ring->doorbell_index = (i == 0) ?
+ AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
+ } else {
+ ring->use_pollmem = true;
+ }
sprintf(ring->name, "sdma%d", i);
r = amdgpu_ring_init(adev, ring, 1024,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4e7b008..036798b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -27,15 +27,14 @@
#include "amdgpu_ucode.h"
#include "amdgpu_trace.h"
-#include "vega10/soc15ip.h"
-#include "vega10/SDMA0/sdma0_4_0_offset.h"
-#include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
-#include "vega10/SDMA1/sdma1_4_0_offset.h"
-#include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
-#include "vega10/MMHUB/mmhub_1_0_offset.h"
-#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
-#include "vega10/HDP/hdp_4_0_offset.h"
-#include "raven1/SDMA0/sdma0_4_1_default.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma0/sdma0_4_0_sh_mask.h"
+#include "sdma1/sdma1_4_0_offset.h"
+#include "sdma1/sdma1_4_0_sh_mask.h"
+#include "mmhub/mmhub_1_0_offset.h"
+#include "mmhub/mmhub_1_0_sh_mask.h"
+#include "hdp/hdp_4_0_offset.h"
+#include "sdma0/sdma0_4_1_default.h"
#include "soc15_common.h"
#include "soc15.h"
@@ -53,97 +52,85 @@
static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static const u32 golden_settings_sdma_4[] = {
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
+static const struct soc15_reg_golden golden_settings_sdma_4[] = {
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
};
-static const u32 golden_settings_sdma_vg10[] = {
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
- SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
+static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
};
-static const u32 golden_settings_sdma_4_1[] =
+static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
{
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)
};
-static const u32 golden_settings_sdma_rv1[] =
+static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
{
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002,
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
};
-static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
+static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+ u32 instance, u32 offset)
{
- u32 base = 0;
-
- switch (instance) {
- case 0:
- base = SDMA0_BASE.instance[0].segment[0];
- break;
- case 1:
- base = SDMA1_BASE.instance[0].segment[0];
- break;
- default:
- BUG();
- break;
- }
-
- return base + internal_offset;
+ return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
+ (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
}
static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_VEGA10:
- amdgpu_program_register_sequence(adev,
+ soc15_program_register_sequence(adev,
golden_settings_sdma_4,
- (const u32)ARRAY_SIZE(golden_settings_sdma_4));
- amdgpu_program_register_sequence(adev,
+ ARRAY_SIZE(golden_settings_sdma_4));
+ soc15_program_register_sequence(adev,
golden_settings_sdma_vg10,
- (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
+ ARRAY_SIZE(golden_settings_sdma_vg10));
break;
case CHIP_RAVEN:
- amdgpu_program_register_sequence(adev,
+ soc15_program_register_sequence(adev,
golden_settings_sdma_4_1,
- (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
- amdgpu_program_register_sequence(adev,
+ ARRAY_SIZE(golden_settings_sdma_4_1));
+ soc15_program_register_sequence(adev,
golden_settings_sdma_rv1,
- (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
+ ARRAY_SIZE(golden_settings_sdma_rv1));
break;
default:
break;
@@ -251,31 +238,27 @@
static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- u64 *wptr = NULL;
- uint64_t local_wptr = 0;
+ u64 wptr;
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
- DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
- *wptr = (*wptr) >> 2;
- DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
+ wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
+ DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
u32 lowbit, highbit;
int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
- wptr = &local_wptr;
- lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;
- highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
+ lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
+ highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
me, highbit, lowbit);
- *wptr = highbit;
- *wptr = (*wptr) << 32;
- *wptr |= lowbit;
+ wptr = highbit;
+ wptr = wptr << 32;
+ wptr |= lowbit;
}
- return *wptr;
+ return wptr >> 2;
}
/**
@@ -315,8 +298,8 @@
lower_32_bits(ring->wptr << 2),
me,
upper_32_bits(ring->wptr << 2));
- WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
+ WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
+ WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
}
}
@@ -343,15 +326,13 @@
*/
static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
- u32 vmid = vm_id & 0xf;
-
/* IB packet must end on a 8 DW boundary */
sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
- SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
+ SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
/* base must be 32 byte aligned */
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -370,13 +351,9 @@
*/
static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
u32 ref_and_mask = 0;
- const struct nbio_hdp_flush_reg *nbio_hf_reg;
-
- if (ring->adev->flags & AMD_IS_APU)
- nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
- else
- nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
+ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
if (ring == &ring->adev->sdma.instance[0].ring)
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
@@ -386,8 +363,8 @@
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
- amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2);
- amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2);
+ amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
+ amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
amdgpu_ring_write(ring, ref_and_mask); /* reference */
amdgpu_ring_write(ring, ref_and_mask); /* mask */
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
@@ -396,6 +373,8 @@
static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
@@ -460,12 +439,12 @@
amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
for (i = 0; i < adev->sdma.num_instances; i++) {
- rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
- ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
}
sdma0->ready = false;
@@ -522,18 +501,18 @@
}
for (i = 0; i < adev->sdma.num_instances; i++) {
- f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
+ f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
AUTO_CTXSW_ENABLE, enable ? 1 : 0);
if (enable && amdgpu_sdma_phase_quantum) {
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE0_QUANTUM),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
phase_quantum);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE1_QUANTUM),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
phase_quantum);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE2_QUANTUM),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
phase_quantum);
}
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
}
}
@@ -557,9 +536,9 @@
}
for (i = 0; i < adev->sdma.num_instances; i++) {
- f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
+ f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
}
}
@@ -587,48 +566,48 @@
ring = &adev->sdma.instance[i].ring;
wb_offset = (ring->rptr_offs * 4);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4);
- rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
#ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
RPTR_WRITEBACK_SWAP_ENABLE, 1);
#endif
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
/* set the wb address whether it's enabled or not */
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update first */
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
}
- doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL));
- doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET));
+ doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
+ doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
if (ring->use_doorbell) {
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
@@ -637,55 +616,53 @@
} else {
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
}
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
- if (adev->flags & AMD_IS_APU)
- nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
- else
- nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+ adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
+ ring->doorbell_index);
if (amdgpu_sriov_vf(adev))
sdma_v4_0_ring_set_wptr(ring);
/* set minor_ptr_update to 0 after wptr programed */
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
/* set utc l1 enable flag always to 1 */
- temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
+ temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
if (!amdgpu_sriov_vf(adev)) {
/* unhalt engine */
- temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
+ temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
}
/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
lower_32_bits(wptr_gpu_addr));
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
- wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+ wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
if (amdgpu_sriov_vf(adev))
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
else
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
- ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
+ ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
#ifdef __BIG_ENDIAN
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
#endif
/* enable DMA IBs */
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
ring->ready = true;
@@ -816,12 +793,12 @@
(adev->sdma.instance[i].fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
for (j = 0; j < fw_size; j++)
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
- WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
+ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
}
return 0;
@@ -1152,23 +1129,24 @@
* using sDMA (VEGA10).
*/
static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
+ amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
+ amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
amdgpu_ring_write(ring, upper_32_bits(pd_addr));
/* flush TLB */
@@ -1183,8 +1161,8 @@
SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 1 << vm_id); /* reference */
- amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+ amdgpu_ring_write(ring, 1 << vmid); /* reference */
+ amdgpu_ring_write(ring, 1 << vmid); /* mask */
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
}
@@ -1317,7 +1295,7 @@
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
- u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));
+ u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
return false;
@@ -1333,8 +1311,8 @@
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
- sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));
- sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
+ sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
+ sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
return 0;
@@ -1358,8 +1336,8 @@
u32 sdma_cntl;
u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
- sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) :
- sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL);
+ sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
+ sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
sdma_cntl = RREG32(reg_offset);
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 40520a9..3598151 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1458,65 +1458,65 @@
{
switch (adev->asic_type) {
case CHIP_TAHITI:
- amdgpu_program_register_sequence(adev,
- tahiti_golden_registers,
- (const u32)ARRAY_SIZE(tahiti_golden_registers));
- amdgpu_program_register_sequence(adev,
- tahiti_golden_rlc_registers,
- (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
- amdgpu_program_register_sequence(adev,
- tahiti_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- tahiti_golden_registers2,
- (const u32)ARRAY_SIZE(tahiti_golden_registers2));
+ amdgpu_device_program_register_sequence(adev,
+ tahiti_golden_registers,
+ ARRAY_SIZE(tahiti_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ tahiti_golden_rlc_registers,
+ ARRAY_SIZE(tahiti_golden_rlc_registers));
+ amdgpu_device_program_register_sequence(adev,
+ tahiti_mgcg_cgcg_init,
+ ARRAY_SIZE(tahiti_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ tahiti_golden_registers2,
+ ARRAY_SIZE(tahiti_golden_registers2));
break;
case CHIP_PITCAIRN:
- amdgpu_program_register_sequence(adev,
- pitcairn_golden_registers,
- (const u32)ARRAY_SIZE(pitcairn_golden_registers));
- amdgpu_program_register_sequence(adev,
- pitcairn_golden_rlc_registers,
- (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
- amdgpu_program_register_sequence(adev,
- pitcairn_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ pitcairn_golden_registers,
+ ARRAY_SIZE(pitcairn_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ pitcairn_golden_rlc_registers,
+ ARRAY_SIZE(pitcairn_golden_rlc_registers));
+ amdgpu_device_program_register_sequence(adev,
+ pitcairn_mgcg_cgcg_init,
+ ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
break;
case CHIP_VERDE:
- amdgpu_program_register_sequence(adev,
- verde_golden_registers,
- (const u32)ARRAY_SIZE(verde_golden_registers));
- amdgpu_program_register_sequence(adev,
- verde_golden_rlc_registers,
- (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
- amdgpu_program_register_sequence(adev,
- verde_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
- amdgpu_program_register_sequence(adev,
- verde_pg_init,
- (const u32)ARRAY_SIZE(verde_pg_init));
+ amdgpu_device_program_register_sequence(adev,
+ verde_golden_registers,
+ ARRAY_SIZE(verde_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ verde_golden_rlc_registers,
+ ARRAY_SIZE(verde_golden_rlc_registers));
+ amdgpu_device_program_register_sequence(adev,
+ verde_mgcg_cgcg_init,
+ ARRAY_SIZE(verde_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ verde_pg_init,
+ ARRAY_SIZE(verde_pg_init));
break;
case CHIP_OLAND:
- amdgpu_program_register_sequence(adev,
- oland_golden_registers,
- (const u32)ARRAY_SIZE(oland_golden_registers));
- amdgpu_program_register_sequence(adev,
- oland_golden_rlc_registers,
- (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
- amdgpu_program_register_sequence(adev,
- oland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ oland_golden_registers,
+ ARRAY_SIZE(oland_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ oland_golden_rlc_registers,
+ ARRAY_SIZE(oland_golden_rlc_registers));
+ amdgpu_device_program_register_sequence(adev,
+ oland_mgcg_cgcg_init,
+ ARRAY_SIZE(oland_mgcg_cgcg_init));
break;
case CHIP_HAINAN:
- amdgpu_program_register_sequence(adev,
- hainan_golden_registers,
- (const u32)ARRAY_SIZE(hainan_golden_registers));
- amdgpu_program_register_sequence(adev,
- hainan_golden_registers2,
- (const u32)ARRAY_SIZE(hainan_golden_registers2));
- amdgpu_program_register_sequence(adev,
- hainan_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ hainan_golden_registers,
+ ARRAY_SIZE(hainan_golden_registers));
+ amdgpu_device_program_register_sequence(adev,
+ hainan_golden_registers2,
+ ARRAY_SIZE(hainan_golden_registers2));
+ amdgpu_device_program_register_sequence(adev,
+ hainan_mgcg_cgcg_init,
+ ARRAY_SIZE(hainan_mgcg_cgcg_init));
break;
@@ -2024,42 +2024,42 @@
case CHIP_VERDE:
case CHIP_TAHITI:
case CHIP_PITCAIRN:
- amdgpu_ip_block_add(adev, &si_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &si_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
- amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &si_dma_ip_block);
- /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
- /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
+ amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
+ /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
+ /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
case CHIP_OLAND:
- amdgpu_ip_block_add(adev, &si_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &si_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
- amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &si_dma_ip_block);
- /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
- /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
+ amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
+ /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
+ /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
case CHIP_HAINAN:
- amdgpu_ip_block_add(adev, &si_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &si_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &si_dma_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
break;
default:
BUG();
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 9adca5d..9a29c13 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -61,14 +61,14 @@
static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
* Pad as necessary with NOPs.
*/
while ((lower_32_bits(ring->wptr) & 7) != 5)
amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
- amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));
+ amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));
amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
@@ -473,25 +473,25 @@
* using sDMA (VI).
*/
static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
- if (vm_id < 8)
- amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+ if (vmid < 8)
+ amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
else
- amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
+ amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
amdgpu_ring_write(ring, pd_addr >> 12);
/* bits 0-7 are the VM contexts0-7 */
amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
amdgpu_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST));
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
/* wait for invalidate to complete */
amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
amdgpu_ring_write(ring, 0xff << 16); /* retry */
- amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+ amdgpu_ring_write(ring, 1 << vmid); /* mask */
amdgpu_ring_write(ring, 0); /* value */
amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
}
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index b8256566..b1a3ca5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -5829,9 +5829,9 @@
((temp_reg & 0xffff0000)) |
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
j++;
+
if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
return -EINVAL;
-
temp_reg = RREG32(MC_PMG_CMD_MRS);
table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
@@ -5843,18 +5843,16 @@
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
}
j++;
- if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
+ if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
+ return -EINVAL;
table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
for (k = 0; k < table->num_entries; k++)
table->mc_reg_table_entry[k].mc_data[j] =
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
j++;
- if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
}
break;
case MC_SEQ_RESERVE_M:
@@ -5866,8 +5864,6 @@
(temp_reg & 0xffff0000) |
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
j++;
- if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index d2c6b80..60dad63 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -146,7 +146,7 @@
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
- entry->vm_id = (dw[2] >> 8) & 0xff;
+ entry->vmid = (dw[2] >> 8) & 0xff;
adev->irq.ih.rptr += 16;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 40767fd..a04a033 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -34,18 +34,17 @@
#include "atom.h"
#include "amd_pcie.h"
-#include "vega10/soc15ip.h"
-#include "vega10/UVD/uvd_7_0_offset.h"
-#include "vega10/GC/gc_9_0_offset.h"
-#include "vega10/GC/gc_9_0_sh_mask.h"
-#include "vega10/SDMA0/sdma0_4_0_offset.h"
-#include "vega10/SDMA1/sdma1_4_0_offset.h"
-#include "vega10/HDP/hdp_4_0_offset.h"
-#include "vega10/HDP/hdp_4_0_sh_mask.h"
-#include "vega10/MP/mp_9_0_offset.h"
-#include "vega10/MP/mp_9_0_sh_mask.h"
-#include "vega10/SMUIO/smuio_9_0_offset.h"
-#include "vega10/SMUIO/smuio_9_0_sh_mask.h"
+#include "uvd/uvd_7_0_offset.h"
+#include "gc/gc_9_0_offset.h"
+#include "gc/gc_9_0_sh_mask.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
+#include "hdp/hdp_4_0_offset.h"
+#include "hdp/hdp_4_0_sh_mask.h"
+#include "mp/mp_9_0_offset.h"
+#include "mp/mp_9_0_sh_mask.h"
+#include "smuio/smuio_9_0_offset.h"
+#include "smuio/smuio_9_0_sh_mask.h"
#include "soc15.h"
#include "soc15_common.h"
@@ -101,15 +100,8 @@
{
unsigned long flags, address, data;
u32 r;
- const struct nbio_pcie_index_data *nbio_pcie_id;
-
- if (adev->flags & AMD_IS_APU)
- nbio_pcie_id = &nbio_v7_0_pcie_index_data;
- else
- nbio_pcie_id = &nbio_v6_1_pcie_index_data;
-
- address = nbio_pcie_id->index_offset;
- data = nbio_pcie_id->data_offset;
+ address = adev->nbio_funcs->get_pcie_index_offset(adev);
+ data = adev->nbio_funcs->get_pcie_data_offset(adev);
spin_lock_irqsave(&adev->pcie_idx_lock, flags);
WREG32(address, reg);
@@ -122,15 +114,9 @@
static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
unsigned long flags, address, data;
- const struct nbio_pcie_index_data *nbio_pcie_id;
- if (adev->flags & AMD_IS_APU)
- nbio_pcie_id = &nbio_v7_0_pcie_index_data;
- else
- nbio_pcie_id = &nbio_v6_1_pcie_index_data;
-
- address = nbio_pcie_id->index_offset;
- data = nbio_pcie_id->data_offset;
+ address = adev->nbio_funcs->get_pcie_index_offset(adev);
+ data = adev->nbio_funcs->get_pcie_data_offset(adev);
spin_lock_irqsave(&adev->pcie_idx_lock, flags);
WREG32(address, reg);
@@ -242,41 +228,9 @@
static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
{
- if (adev->flags & AMD_IS_APU)
- return nbio_v7_0_get_memsize(adev);
- else
- return nbio_v6_1_get_memsize(adev);
+ return adev->nbio_funcs->get_memsize(adev);
}
-static const u32 vega10_golden_init[] =
-{
-};
-
-static const u32 raven_golden_init[] =
-{
-};
-
-static void soc15_init_golden_registers(struct amdgpu_device *adev)
-{
- /* Some of the registers might be dependent on GRBM_GFX_INDEX */
- mutex_lock(&adev->grbm_idx_mutex);
-
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- amdgpu_program_register_sequence(adev,
- vega10_golden_init,
- (const u32)ARRAY_SIZE(vega10_golden_init));
- break;
- case CHIP_RAVEN:
- amdgpu_program_register_sequence(adev,
- raven_golden_init,
- (const u32)ARRAY_SIZE(raven_golden_init));
- break;
- default:
- break;
- }
- mutex_unlock(&adev->grbm_idx_mutex);
-}
static u32 soc15_get_xclk(struct amdgpu_device *adev)
{
return adev->clock.spll.reference_freq;
@@ -332,25 +286,34 @@
return true;
}
-static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
- { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
- { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
- { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)},
- { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)},
- { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)},
- { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)},
- { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)},
- { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)},
- { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)},
- { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)},
+struct soc15_allowed_register_entry {
+ uint32_t hwip;
+ uint32_t inst;
+ uint32_t seg;
+ uint32_t reg_offset;
+ bool grbm_indexed;
+};
+
+
+static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
+ { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
};
static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
@@ -377,12 +340,9 @@
if (indexed) {
return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
} else {
- switch (reg_offset) {
- case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
+ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
return adev->gfx.config.gb_addr_config;
- default:
- return RREG32(reg_offset);
- }
+ return RREG32(reg_offset);
}
}
@@ -390,10 +350,13 @@
u32 sh_num, u32 reg_offset, u32 *value)
{
uint32_t i;
+ struct soc15_allowed_register_entry *en;
*value = 0;
for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
- if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
+ en = &soc15_allowed_read_registers[i];
+ if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+ + en->reg_offset))
continue;
*value = soc15_get_register_value(adev,
@@ -404,6 +367,43 @@
return -EINVAL;
}
+
+/**
+ * soc15_program_register_sequence - program an array of registers.
+ *
+ * @adev: amdgpu_device pointer
+ * @regs: pointer to the register array
+ * @array_size: size of the register array
+ *
+ * Programs an array or registers with and and or masks.
+ * This is a helper for setting golden registers.
+ */
+
+void soc15_program_register_sequence(struct amdgpu_device *adev,
+ const struct soc15_reg_golden *regs,
+ const u32 array_size)
+{
+ const struct soc15_reg_golden *entry;
+ u32 tmp, reg;
+ int i;
+
+ for (i = 0; i < array_size; ++i) {
+ entry = ®s[i];
+ reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
+
+ if (entry->and_mask == 0xffffffff) {
+ tmp = entry->or_mask;
+ } else {
+ tmp = RREG32(reg);
+ tmp &= ~(entry->and_mask);
+ tmp |= entry->or_mask;
+ }
+ WREG32(reg, tmp);
+ }
+
+}
+
+
static int soc15_asic_reset(struct amdgpu_device *adev)
{
u32 i;
@@ -428,9 +428,8 @@
/* wait for asic to come out of reset */
for (i = 0; i < adev->usec_timeout; i++) {
- u32 memsize = (adev->flags & AMD_IS_APU) ?
- nbio_v7_0_get_memsize(adev) :
- nbio_v6_1_get_memsize(adev);
+ u32 memsize = adev->nbio_funcs->get_memsize(adev);
+
if (memsize != 0xffffffff)
break;
udelay(1);
@@ -495,14 +494,10 @@
}
static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
- if (adev->flags & AMD_IS_APU) {
- nbio_v7_0_enable_doorbell_aperture(adev, enable);
- } else {
- nbio_v6_1_enable_doorbell_aperture(adev, enable);
- nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
- }
+ adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
+ adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
}
static const struct amdgpu_ip_block_version vega10_common_ip_block =
@@ -516,50 +511,65 @@
int soc15_set_ip_blocks(struct amdgpu_device *adev)
{
- nbio_v6_1_detect_hw_virt(adev);
+ /* Set IP register base before any HW register access */
+ switch (adev->asic_type) {
+ case CHIP_VEGA10:
+ case CHIP_RAVEN:
+ vega10_reg_base_init(adev);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (adev->flags & AMD_IS_APU)
+ adev->nbio_funcs = &nbio_v7_0_funcs;
+ else
+ adev->nbio_funcs = &nbio_v6_1_funcs;
+
+ adev->nbio_funcs->detect_hw_virt(adev);
if (amdgpu_sriov_vf(adev))
adev->virt.ops = &xgpu_ai_virt_ops;
switch (adev->asic_type) {
case CHIP_VEGA10:
- amdgpu_ip_block_add(adev, &vega10_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
- amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
- amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
if (!amdgpu_sriov_vf(adev))
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
- amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
- amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
break;
case CHIP_RAVEN:
- amdgpu_ip_block_add(adev, &vega10_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
- amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
- amdgpu_ip_block_add(adev, &psp_v10_0_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
- amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
- amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
break;
default:
return -EINVAL;
@@ -570,10 +580,7 @@
static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
{
- if (adev->flags & AMD_IS_APU)
- return nbio_v7_0_get_rev_id(adev);
- else
- return nbio_v6_1_get_rev_id(adev);
+ return adev->nbio_funcs->get_rev_id(adev);
}
static const struct amdgpu_asic_funcs soc15_asic_funcs =
@@ -609,8 +616,8 @@
adev->asic_funcs = &soc15_asic_funcs;
- if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
- (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
+ (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
psp_enabled = true;
adev->rev_id = soc15_get_rev_id(adev);
@@ -675,7 +682,7 @@
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
- amdgpu_get_pcie_info(adev);
+ amdgpu_device_get_pcie_info(adev);
return 0;
}
@@ -709,15 +716,12 @@
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- /* move the golden regs per IP block */
- soc15_init_golden_registers(adev);
/* enable pcie gen2/3 link */
soc15_pcie_gen3_enable(adev);
/* enable aspm */
soc15_program_aspm(adev);
/* setup nbio registers */
- if (!(adev->flags & AMD_IS_APU))
- nbio_v6_1_init_registers(adev);
+ adev->nbio_funcs->init_registers(adev);
/* enable the doorbell aperture */
soc15_enable_doorbell_aperture(adev, true);
@@ -878,9 +882,9 @@
switch (adev->asic_type) {
case CHIP_VEGA10:
- nbio_v6_1_update_medium_grain_clock_gating(adev,
+ adev->nbio_funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
- nbio_v6_1_update_medium_grain_light_sleep(adev,
+ adev->nbio_funcs->update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
soc15_update_hdp_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
@@ -894,9 +898,9 @@
state == AMD_CG_STATE_GATE ? true : false);
break;
case CHIP_RAVEN:
- nbio_v7_0_update_medium_grain_clock_gating(adev,
+ adev->nbio_funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
- nbio_v6_1_update_medium_grain_light_sleep(adev,
+ adev->nbio_funcs->update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
soc15_update_hdp_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
@@ -921,7 +925,7 @@
if (amdgpu_sriov_vf(adev))
*flags = 0;
- nbio_v6_1_get_clockgating_state(adev, flags);
+ adev->nbio_funcs->get_clockgating_state(adev, flags);
/* AMD_CG_SUPPORT_HDP_LS */
data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index acb3cdb..26b3fea 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -29,8 +29,28 @@
extern const struct amd_ip_funcs soc15_common_ip_funcs;
+struct soc15_reg_golden {
+ u32 hwip;
+ u32 instance;
+ u32 segment;
+ u32 reg;
+ u32 and_mask;
+ u32 or_mask;
+};
+
+#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
+
+#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
+ { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
+
void soc15_grbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int soc15_set_ip_blocks(struct amdgpu_device *adev);
+void soc15_program_register_sequence(struct amdgpu_device *adev,
+ const struct soc15_reg_golden *registers,
+ const u32 array_size);
+
+int vega10_reg_base_init(struct amdgpu_device *adev);
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 7a8e4e2..def8650 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -24,72 +24,28 @@
#ifndef __SOC15_COMMON_H__
#define __SOC15_COMMON_H__
-struct nbio_hdp_flush_reg {
- u32 hdp_flush_req_offset;
- u32 hdp_flush_done_offset;
- u32 ref_and_mask_cp0;
- u32 ref_and_mask_cp1;
- u32 ref_and_mask_cp2;
- u32 ref_and_mask_cp3;
- u32 ref_and_mask_cp4;
- u32 ref_and_mask_cp5;
- u32 ref_and_mask_cp6;
- u32 ref_and_mask_cp7;
- u32 ref_and_mask_cp8;
- u32 ref_and_mask_cp9;
- u32 ref_and_mask_sdma0;
- u32 ref_and_mask_sdma1;
-};
-
-struct nbio_pcie_index_data {
- u32 index_offset;
- u32 data_offset;
-};
-
/* Register Access Macros */
-#define SOC15_REG_OFFSET(ip, inst, reg) (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
- (ip##_BASE__INST##inst##_SEG4 + reg)))))
+#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
#define WREG32_FIELD15(ip, idx, reg, field, val) \
- WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+ WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
+ (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
+ & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
#define RREG32_SOC15(ip, inst, reg) \
- RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
- (ip##_BASE__INST##inst##_SEG4 + reg))))))
+ RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
- RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
- (ip##_BASE__INST##inst##_SEG4 + reg))))) + offset)
+ RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
#define WREG32_SOC15(ip, inst, reg, value) \
- WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
- (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
+ WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
- WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
- (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
+ WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
- WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
- (ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value)
+ WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index aa4e320..5995ffc 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -270,7 +270,7 @@
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
- entry->vm_id = (dw[2] >> 8) & 0xff;
+ entry->vmid = (dw[2] >> 8) & 0xff;
entry->pas_id = (dw[2] >> 16) & 0xffff;
/* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 15771a53..8ab10c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -541,7 +541,7 @@
*/
static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
amdgpu_ring_write(ring, ib->gpu_addr);
@@ -563,7 +563,7 @@
/* programm the VCPU memory controller bits 0-27 */
addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
+ size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 3b29aaba..c1fe30c 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -258,7 +258,7 @@
upper_32_bits(adev->uvd.gpu_addr));
offset = AMDGPU_UVD_FIRMWARE_OFFSET;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+ size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
@@ -556,7 +556,7 @@
*/
static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 3956c64..4bc33b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -37,6 +37,9 @@
#include "gmc/gmc_8_1_d.h"
#include "vi.h"
+/* Polaris10/11/12 firmware version */
+#define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
+
static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@@ -58,7 +61,9 @@
*/
static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
{
- return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
+ return ((adev->asic_type >= CHIP_POLARIS10) &&
+ (adev->asic_type <= CHIP_POLARIS12) &&
+ (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
}
/**
@@ -411,11 +416,19 @@
if (r)
return r;
- if (uvd_v6_0_enc_support(adev)) {
- struct amd_sched_rq *rq;
+ if (!uvd_v6_0_enc_support(adev)) {
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+ adev->uvd.ring_enc[i].funcs = NULL;
+
+ adev->uvd.irq.num_types = 1;
+ adev->uvd.num_enc_rings = 0;
+
+ DRM_INFO("UVD ENC is disabled\n");
+ } else {
+ struct drm_sched_rq *rq;
ring = &adev->uvd.ring_enc[0];
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+ r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
rq, amdgpu_sched_jobs, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD ENC run queue.\n");
@@ -456,7 +469,7 @@
return r;
if (uvd_v6_0_enc_support(adev)) {
- amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
+ drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
for (i = 0; i < adev->uvd.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
@@ -603,7 +616,7 @@
upper_32_bits(adev->uvd.gpu_addr));
offset = AMDGPU_UVD_FIRMWARE_OFFSET;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+ size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
@@ -1028,10 +1041,10 @@
*/
static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
@@ -1050,24 +1063,24 @@
* Write enc ring commands to execute the indirect buffer
*/
static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+ struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
}
static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
uint32_t reg;
- if (vm_id < 8)
- reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
+ if (vmid < 8)
+ reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
else
- reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
+ reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
amdgpu_ring_write(ring, reg << 2);
@@ -1079,7 +1092,7 @@
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
amdgpu_ring_write(ring, 0x8);
@@ -1088,7 +1101,7 @@
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
- amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+ amdgpu_ring_write(ring, 1 << vmid); /* mask */
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
amdgpu_ring_write(ring, 0xC);
}
@@ -1127,14 +1140,14 @@
}
static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned int vm_id, uint64_t pd_addr)
+ unsigned int vmid, uint64_t pd_addr)
{
amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, pd_addr >> 12);
amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
}
static bool uvd_v6_0_is_idle(void *handle)
@@ -1605,7 +1618,7 @@
.set_wptr = uvd_v6_0_enc_ring_set_wptr,
.emit_frame_size =
4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
- 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
+ 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1, /* uvd_v6_0_enc_ring_insert_end */
.emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 7b77339..6b95f4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -29,16 +29,15 @@
#include "soc15_common.h"
#include "mmsch_v1_0.h"
-#include "vega10/soc15ip.h"
-#include "vega10/UVD/uvd_7_0_offset.h"
-#include "vega10/UVD/uvd_7_0_sh_mask.h"
-#include "vega10/VCE/vce_4_0_offset.h"
-#include "vega10/VCE/vce_4_0_default.h"
-#include "vega10/VCE/vce_4_0_sh_mask.h"
-#include "vega10/NBIF/nbif_6_1_offset.h"
-#include "vega10/HDP/hdp_4_0_offset.h"
-#include "vega10/MMHUB/mmhub_1_0_offset.h"
-#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
+#include "uvd/uvd_7_0_offset.h"
+#include "uvd/uvd_7_0_sh_mask.h"
+#include "vce/vce_4_0_offset.h"
+#include "vce/vce_4_0_default.h"
+#include "vce/vce_4_0_sh_mask.h"
+#include "nbif/nbif_6_1_offset.h"
+#include "hdp/hdp_4_0_offset.h"
+#include "mmhub/mmhub_1_0_offset.h"
+#include "mmhub/mmhub_1_0_sh_mask.h"
static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@@ -385,7 +384,7 @@
static int uvd_v7_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
- struct amd_sched_rq *rq;
+ struct drm_sched_rq *rq;
int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -416,8 +415,8 @@
}
ring = &adev->uvd.ring_enc[0];
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
+ rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+ r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
rq, amdgpu_sched_jobs, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD ENC run queue.\n");
@@ -472,7 +471,7 @@
if (r)
return r;
- amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
+ drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
for (i = 0; i < adev->uvd.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
@@ -616,7 +615,7 @@
*/
static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+ uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
uint32_t offset;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
@@ -1086,6 +1085,8 @@
static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
unsigned flags)
{
+ struct amdgpu_device *adev = ring->adev;
+
WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
amdgpu_ring_write(ring,
@@ -1123,6 +1124,7 @@
static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
u64 seq, unsigned flags)
{
+
WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
@@ -1141,6 +1143,8 @@
*/
static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
amdgpu_ring_write(ring, 0);
@@ -1155,6 +1159,8 @@
*/
static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
amdgpu_ring_write(ring, 1);
}
@@ -1212,11 +1218,13 @@
*/
static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -1238,10 +1246,10 @@
* Write enc ring commands to execute the indirect buffer
*/
static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+ struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
@@ -1250,6 +1258,8 @@
static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
uint32_t data0, uint32_t data1)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
amdgpu_ring_write(ring, data0);
@@ -1264,6 +1274,8 @@
static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
uint32_t data0, uint32_t data1, uint32_t mask)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
amdgpu_ring_write(ring, data0);
@@ -1279,25 +1291,26 @@
}
static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
- uint32_t data0, data1, mask;
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t data0, data1, mask;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
- data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
+ data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
data1 = upper_32_bits(pd_addr);
uvd_v7_0_vm_reg_write(ring, data0, data1);
- data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+ data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
uvd_v7_0_vm_reg_write(ring, data0, data1);
- data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+ data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
mask = 0xffffffff;
uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
@@ -1309,36 +1322,47 @@
/* wait for flush */
data0 = (hub->vm_inv_eng0_ack + eng) << 2;
- data1 = 1 << vm_id;
- mask = 1 << vm_id;
+ data1 = 1 << vmid;
+ mask = 1 << vmid;
uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
}
+static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+{
+ int i;
+ struct amdgpu_device *adev = ring->adev;
+
+ for (i = 0; i < count; i++)
+ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
+
+}
+
static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
{
amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
}
static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned int vm_id, uint64_t pd_addr)
+ unsigned int vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
- amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
amdgpu_ring_write(ring, upper_32_bits(pd_addr));
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
- amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
- amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0xffffffff);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
@@ -1350,8 +1374,8 @@
/* wait for flush */
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
- amdgpu_ring_write(ring, 1 << vm_id);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
+ amdgpu_ring_write(ring, 1 << vmid);
}
#if 0
@@ -1681,7 +1705,7 @@
static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_UVD,
.align_mask = 0xf,
- .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
+ .nop = PACKET0(0x81ff, 0),
.support_64bit_ptrs = false,
.vmhub = AMDGPU_MMHUB,
.get_rptr = uvd_v7_0_ring_get_rptr,
@@ -1700,7 +1724,7 @@
.emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
.test_ring = uvd_v7_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
- .insert_nop = amdgpu_ring_insert_nop,
+ .insert_nop = uvd_v7_0_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_uvd_ring_begin_use,
.end_use = amdgpu_uvd_ring_end_use,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5183b46..8622d25 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -834,24 +834,24 @@
}
static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+ struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB_VM);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
}
static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned int vm_id, uint64_t pd_addr)
+ unsigned int vmid, uint64_t pd_addr)
{
amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, pd_addr >> 12);
amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, VCE_CMD_END);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
old mode 100644
new mode 100755
index 7574554..7cf2eef
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -32,12 +32,11 @@
#include "soc15_common.h"
#include "mmsch_v1_0.h"
-#include "vega10/soc15ip.h"
-#include "vega10/VCE/vce_4_0_offset.h"
-#include "vega10/VCE/vce_4_0_default.h"
-#include "vega10/VCE/vce_4_0_sh_mask.h"
-#include "vega10/MMHUB/mmhub_1_0_offset.h"
-#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
+#include "vce/vce_4_0_offset.h"
+#include "vce/vce_4_0_default.h"
+#include "vce/vce_4_0_sh_mask.h"
+#include "mmhub/mmhub_1_0_offset.h"
+#include "mmhub/mmhub_1_0_sh_mask.h"
#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
@@ -243,37 +242,49 @@
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
- adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
- adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);
} else {
- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
adev->vce.gpu_addr >> 8);
- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
- adev->vce.gpu_addr >> 8);
- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
- adev->vce.gpu_addr >> 8);
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
+ (adev->vce.gpu_addr >> 40) & 0xff);
}
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
+ adev->vce.gpu_addr >> 8);
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_64BIT_BAR1),
+ (adev->vce.gpu_addr >> 40) & 0xff);
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
+ adev->vce.gpu_addr >> 8);
+ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+ mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),
+ (adev->vce.gpu_addr >> 40) & 0xff);
offset = AMDGPU_VCE_FIRMWARE_OFFSET;
size = VCE_V4_0_FW_SIZE;
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
- offset & 0x7FFFFFFF);
+ offset & ~0x0f000000);
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
- offset += size;
+ offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;
size = VCE_V4_0_STACK_SIZE;
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),
- offset & 0x7FFFFFFF);
+ (offset & ~0x0f000000) | (1 << 24));
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
offset += size;
size = VCE_V4_0_DATA_SIZE;
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),
- offset & 0x7FFFFFFF);
+ (offset & ~0x0f000000) | (2 << 24));
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);
@@ -412,7 +423,7 @@
if (r)
return r;
- size = (VCE_V4_0_STACK_SIZE + VCE_V4_0_DATA_SIZE) * 2;
+ size = VCE_V4_0_STACK_SIZE + VCE_V4_0_DATA_SIZE;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
size += VCE_V4_0_FW_SIZE;
@@ -927,10 +938,10 @@
#endif
static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+ struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB_VM);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
@@ -954,25 +965,26 @@
}
static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned int vm_id, uint64_t pd_addr)
+ unsigned int vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
- amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
amdgpu_ring_write(ring, upper_32_bits(pd_addr));
amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
- amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
- amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0xffffffff);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
@@ -984,8 +996,8 @@
/* wait for flush */
amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
- amdgpu_ring_write(ring, 1 << vm_id);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
+ amdgpu_ring_write(ring, 1 << vmid);
}
static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 0450ac5..b99e15c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -28,12 +28,11 @@
#include "soc15d.h"
#include "soc15_common.h"
-#include "vega10/soc15ip.h"
-#include "raven1/VCN/vcn_1_0_offset.h"
-#include "raven1/VCN/vcn_1_0_sh_mask.h"
-#include "vega10/HDP/hdp_4_0_offset.h"
-#include "raven1/MMHUB/mmhub_9_1_offset.h"
-#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
+#include "vcn/vcn_1_0_offset.h"
+#include "vcn/vcn_1_0_sh_mask.h"
+#include "hdp/hdp_4_0_offset.h"
+#include "mmhub/mmhub_9_1_offset.h"
+#include "mmhub/mmhub_9_1_sh_mask.h"
static int vcn_v1_0_start(struct amdgpu_device *adev);
static int vcn_v1_0_stop(struct amdgpu_device *adev);
@@ -744,6 +743,8 @@
*/
static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
amdgpu_ring_write(ring, 0);
@@ -761,6 +762,8 @@
*/
static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
@@ -777,6 +780,8 @@
static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
unsigned flags)
{
+ struct amdgpu_device *adev = ring->adev;
+
WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
amdgpu_ring_write(ring,
@@ -812,6 +817,8 @@
*/
static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
amdgpu_ring_write(ring, 1);
}
@@ -826,11 +833,13 @@
*/
static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+ unsigned vmid, bool ctx_switch)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -846,6 +855,8 @@
static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
uint32_t data0, uint32_t data1)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
amdgpu_ring_write(ring, data0);
@@ -860,6 +871,8 @@
static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
uint32_t data0, uint32_t data1, uint32_t mask)
{
+ struct amdgpu_device *adev = ring->adev;
+
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
amdgpu_ring_write(ring, data0);
@@ -875,25 +888,26 @@
}
static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
+ unsigned vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
- uint32_t data0, data1, mask;
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t data0, data1, mask;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
- data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
+ data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
data1 = upper_32_bits(pd_addr);
vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
- data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+ data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
- data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+ data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
mask = 0xffffffff;
vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
@@ -905,8 +919,8 @@
/* wait for flush */
data0 = (hub->vm_inv_eng0_ack + eng) << 2;
- data1 = 1 << vm_id;
- mask = 1 << vm_id;
+ data1 = 1 << vmid;
+ mask = 1 << vmid;
vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
}
@@ -997,38 +1011,39 @@
* Write enc ring commands to execute the indirect buffer
*/
static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+ struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
{
amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
- amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
}
static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned int vm_id, uint64_t pd_addr)
+ unsigned int vmid, uint64_t pd_addr)
{
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
- pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
- pd_addr |= AMDGPU_PTE_VALID;
+ amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
amdgpu_ring_write(ring,
- (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+ (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
amdgpu_ring_write(ring, upper_32_bits(pd_addr));
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
amdgpu_ring_write(ring,
- (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring,
- (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0xffffffff);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
@@ -1040,8 +1055,8 @@
/* wait for flush */
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
- amdgpu_ring_write(ring, 1 << vm_id);
- amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vmid);
+ amdgpu_ring_write(ring, 1 << vmid);
}
static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
@@ -1077,6 +1092,17 @@
return 0;
}
+static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+{
+ int i;
+ struct amdgpu_device *adev = ring->adev;
+
+ for (i = 0; i < count; i++)
+ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
+
+}
+
+
static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
.name = "vcn_v1_0",
.early_init = vcn_v1_0_early_init,
@@ -1100,7 +1126,7 @@
static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_VCN_DEC,
.align_mask = 0xf,
- .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
+ .nop = PACKET0(0x81ff, 0),
.support_64bit_ptrs = false,
.vmhub = AMDGPU_MMHUB,
.get_rptr = vcn_v1_0_dec_ring_get_rptr,
@@ -1118,7 +1144,7 @@
.emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate,
.test_ring = amdgpu_vcn_dec_ring_test_ring,
.test_ib = amdgpu_vcn_dec_ring_test_ib,
- .insert_nop = amdgpu_ring_insert_nop,
+ .insert_nop = vcn_v1_0_ring_insert_nop,
.insert_start = vcn_v1_0_dec_ring_insert_start,
.insert_end = vcn_v1_0_dec_ring_insert_end,
.pad_ib = amdgpu_ring_generic_pad_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 6973257..ee14d78 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -25,10 +25,8 @@
#include "amdgpu_ih.h"
#include "soc15.h"
-
-#include "vega10/soc15ip.h"
-#include "vega10/OSSSYS/osssys_4_0_offset.h"
-#include "vega10/OSSSYS/osssys_4_0_sh_mask.h"
+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
#include "soc15_common.h"
#include "vega10_ih.h"
@@ -46,11 +44,11 @@
*/
static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
{
- u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+ u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
adev->irq.ih.enabled = true;
}
@@ -63,14 +61,14 @@
*/
static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
{
- u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+ u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
/* set rptr, wptr to 0 */
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
adev->irq.ih.enabled = false;
adev->irq.ih.rptr = 0;
}
@@ -97,20 +95,17 @@
/* disable irqs */
vega10_ih_disable_interrupts(adev);
- if (adev->flags & AMD_IS_APU)
- nbio_v7_0_ih_control(adev);
- else
- nbio_v6_1_ih_control(adev);
+ adev->nbio_funcs->ih_control(adev);
- ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
if (adev->irq.ih.use_bus_addr) {
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
} else {
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
}
rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
@@ -126,21 +121,21 @@
if (adev->irq.msi_enabled)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
/* set the writeback address whether it's enabled or not */
if (adev->irq.ih.use_bus_addr)
wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
else
wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off));
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
/* set rptr, wptr to 0 */
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
- ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR));
+ ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
if (adev->irq.ih.use_doorbell) {
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
OFFSET, adev->irq.ih.doorbell_index);
@@ -150,20 +145,18 @@
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
ENABLE, 0);
}
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr);
- if (adev->flags & AMD_IS_APU)
- nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
- else
- nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
+ WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
+ adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
+ adev->irq.ih.doorbell_index);
- tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL));
+ tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
CLIENT18_IS_STORM_CLIENT, 1);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp);
+ WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
- tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL));
+ tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp);
+ WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
pci_set_master(adev->pdev);
@@ -285,9 +278,9 @@
/* Track retry faults in per-VM fault FIFO. */
spin_lock(&adev->vm_manager.pasid_lock);
vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
- spin_unlock(&adev->vm_manager.pasid_lock);
- if (WARN_ON_ONCE(!vm)) {
+ if (!vm) {
/* VM not found, process it normally */
+ spin_unlock(&adev->vm_manager.pasid_lock);
amdgpu_ih_clear_fault(adev, key);
return true;
}
@@ -295,9 +288,11 @@
r = kfifo_put(&vm->faults, key);
if (!r) {
/* FIFO is full. Ignore it until there is space */
+ spin_unlock(&adev->vm_manager.pasid_lock);
amdgpu_ih_clear_fault(adev, key);
goto ignore_iv;
}
+ spin_unlock(&adev->vm_manager.pasid_lock);
/* It's the first fault for this address, process it normally */
return true;
@@ -334,8 +329,8 @@
entry->client_id = dw[0] & 0xff;
entry->src_id = (dw[0] >> 8) & 0xff;
entry->ring_id = (dw[0] >> 16) & 0xff;
- entry->vm_id = (dw[0] >> 24) & 0xf;
- entry->vm_id_src = (dw[0] >> 31);
+ entry->vmid = (dw[0] >> 24) & 0xf;
+ entry->vmid_src = (dw[0] >> 31);
entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
entry->timestamp_src = dw[2] >> 31;
entry->pas_id = dw[3] & 0xffff;
@@ -367,7 +362,7 @@
adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
} else {
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
new file mode 100644
index 0000000..b7bdd04
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "soc15.h"
+
+#include "soc15_common.h"
+#include "soc15ip.h"
+
+int vega10_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke beend by our driver */
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
+ adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
+ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));
+ adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));
+
+ }
+ return 0;
+}
+
+
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 18bc16d..f5d714e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -282,29 +282,29 @@
switch (adev->asic_type) {
case CHIP_TOPAZ:
- amdgpu_program_register_sequence(adev,
- iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ iceland_mgcg_cgcg_init,
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
break;
case CHIP_FIJI:
- amdgpu_program_register_sequence(adev,
- fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ fiji_mgcg_cgcg_init,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
break;
case CHIP_TONGA:
- amdgpu_program_register_sequence(adev,
- tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ tonga_mgcg_cgcg_init,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
break;
case CHIP_CARRIZO:
- amdgpu_program_register_sequence(adev,
- cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ cz_mgcg_cgcg_init,
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
break;
case CHIP_STONEY:
- amdgpu_program_register_sequence(adev,
- stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ amdgpu_device_program_register_sequence(adev,
+ stoney_mgcg_cgcg_init,
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
@@ -455,11 +455,10 @@
adev->asic_type == CHIP_FIJI) {
reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
/* bit0: 0 means pf and 1 means vf */
- /* bit31: 0 means disable IOV and 1 means enable */
- if (reg & 1)
+ if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
-
- if (reg & 0x80000000)
+ /* bit31: 0 means disable IOV and 1 means enable */
+ if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
}
@@ -672,7 +671,7 @@
/* disable BM */
pci_clear_master(adev->pdev);
/* reset */
- amdgpu_pci_config_reset(adev);
+ amdgpu_device_pci_config_reset(adev);
udelay(100);
@@ -939,8 +938,8 @@
adev->asic_funcs = &vi_asic_funcs;
- if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
- (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
+ (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
smc_enabled = true;
adev->rev_id = vi_get_rev_id(adev);
@@ -1121,7 +1120,7 @@
/* vi use smc load by default */
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
- amdgpu_get_pcie_info(adev);
+ amdgpu_device_get_pcie_info(adev);
return 0;
}
@@ -1534,115 +1533,115 @@
switch (adev->asic_type) {
case CHIP_TOPAZ:
/* topaz has no DCE, UVD, VCE */
- amdgpu_ip_block_add(adev, &vi_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
- amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
+ amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
break;
case CHIP_FIJI:
- amdgpu_ip_block_add(adev, &vi_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
- amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
+ amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
- amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
}
break;
case CHIP_TONGA:
- amdgpu_ip_block_add(adev, &vi_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
- amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
- amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
}
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
- amdgpu_ip_block_add(adev, &vi_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
- amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
- amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
break;
case CHIP_CARRIZO:
- amdgpu_ip_block_add(adev, &vi_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &cz_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
- amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
#if defined(CONFIG_DRM_AMD_ACP)
- amdgpu_ip_block_add(adev, &acp_ip_block);
+ amdgpu_device_ip_block_add(adev, &acp_ip_block);
#endif
break;
case CHIP_STONEY:
- amdgpu_ip_block_add(adev, &vi_common_ip_block);
- amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
- amdgpu_ip_block_add(adev, &cz_ih_ip_block);
- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
- amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
- amdgpu_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
else
- amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
- amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
- amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
- amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
+ amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
#if defined(CONFIG_DRM_AMD_ACP)
- amdgpu_ip_block_add(adev, &acp_ip_block);
+ amdgpu_device_ip_block_add(adev, &acp_ip_block);
#endif
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index dbf3703..19ddd23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -27,6 +27,8 @@
#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
#define SDMA_MAX_INSTANCE 2
+#define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */
+
/* crtc instance offsets */
#define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
#define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
index 342c2d9..a317e76 100644
--- a/drivers/gpu/drm/amd/amdkfd/Makefile
+++ b/drivers/gpu/drm/amd/amdkfd/Makefile
@@ -35,6 +35,8 @@
kfd_process_queue_manager.o kfd_device_queue_manager.o \
kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \
kfd_interrupt.o kfd_events.o cik_event_interrupt.o \
- kfd_dbgdev.o kfd_dbgmgr.o
+ kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o
+
+amdkfd-$(CONFIG_DEBUG_FS) += kfd_debugfs.o
obj-$(CONFIG_HSA_AMD) += amdkfd.o
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
new file mode 100644
index 0000000..997a383d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
@@ -0,0 +1,1384 @@
+/*
+ * Copyright 2015-2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#if 0
+HW (VI) source code for CWSR trap handler
+#Version 18 + multiple trap handler
+
+// this performance-optimal version was originally from Seven Xu at SRDC
+
+// Revison #18 --...
+/* Rev History
+** #1. Branch from gc dv. //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV)
+** #4. SR Memory Layout:
+** 1. VGPR-SGPR-HWREG-{LDS}
+** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern..
+** #5. Update: 1. Accurate g8sr_ts_save_d timestamp
+** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation)
+** #7. Update: 1. don't barrier if noLDS
+** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version
+** 2. Fix SQ issue by s_sleep 2
+** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last
+** 2. optimize s_buffer save by burst 16sgprs...
+** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs.
+** #11. Update 1. Add 2 more timestamp for debug version
+** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance
+** #13. Integ 1. Always use MUBUF for PV trap shader...
+** #14. Update 1. s_buffer_store soft clause...
+** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot.
+** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree
+** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part]
+** 2. PERF - Save LDS before save VGPR to cover LDS save long latency...
+** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32
+** 2. FUNC - Handle non-CWSR traps
+*/
+
+var G8SR_WDMEM_HWREG_OFFSET = 0
+var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes
+
+// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore.
+
+var G8SR_DEBUG_TIMESTAMP = 0
+var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset
+var s_g8sr_ts_save_s = s[34:35] // save start
+var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi
+var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ
+var s_g8sr_ts_save_d = s[40:41] // save end
+var s_g8sr_ts_restore_s = s[42:43] // restore start
+var s_g8sr_ts_restore_d = s[44:45] // restore end
+
+var G8SR_VGPR_SR_IN_DWX4 = 0
+var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes
+var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4
+
+
+/*************************************************************************/
+/* control on how to run the shader */
+/*************************************************************************/
+//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run)
+var EMU_RUN_HACK = 0
+var EMU_RUN_HACK_RESTORE_NORMAL = 0
+var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0
+var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0
+var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK
+var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK
+var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK
+var SAVE_LDS = 1
+var WG_BASE_ADDR_LO = 0x9000a000
+var WG_BASE_ADDR_HI = 0x0
+var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem
+var CTX_SAVE_CONTROL = 0x0
+var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL
+var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run)
+var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write
+var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes
+var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing
+
+/**************************************************************************/
+/* variables */
+/**************************************************************************/
+var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23
+var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000
+var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006
+
+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12
+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9
+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8
+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6
+var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24
+var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
+
+var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400
+var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask
+var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10
+var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100
+var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8
+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF
+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0
+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10
+var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800
+var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11
+var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21
+
+var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME
+var SQ_WAVE_IB_STS_RCNT_SIZE = 4 //FIXME
+var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME
+var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME
+var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME
+
+var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24
+var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27
+
+
+/* Save */
+var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes
+var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
+
+var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit
+var S_SAVE_SPI_INIT_ATC_SHIFT = 27
+var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype
+var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28
+var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG
+var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26
+
+var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used
+var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME
+var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME
+var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME
+
+var s_save_spi_init_lo = exec_lo
+var s_save_spi_init_hi = exec_hi
+
+ //tba_lo and tba_hi need to be saved/restored
+var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3??h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
+var s_save_pc_hi = ttmp1
+var s_save_exec_lo = ttmp2
+var s_save_exec_hi = ttmp3
+var s_save_status = ttmp4
+var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine
+var s_save_xnack_mask_lo = ttmp6
+var s_save_xnack_mask_hi = ttmp7
+var s_save_buf_rsrc0 = ttmp8
+var s_save_buf_rsrc1 = ttmp9
+var s_save_buf_rsrc2 = ttmp10
+var s_save_buf_rsrc3 = ttmp11
+
+var s_save_mem_offset = tma_lo
+var s_save_alloc_size = s_save_trapsts //conflict
+var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time)
+var s_save_m0 = tma_hi
+
+/* Restore */
+var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE
+var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC
+
+var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit
+var S_RESTORE_SPI_INIT_ATC_SHIFT = 27
+var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype
+var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28
+var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG
+var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26
+
+var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT
+var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK
+var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK
+
+var s_restore_spi_init_lo = exec_lo
+var s_restore_spi_init_hi = exec_hi
+
+var s_restore_mem_offset = ttmp2
+var s_restore_alloc_size = ttmp3
+var s_restore_tmp = ttmp6 //tba_lo/hi need to be restored
+var s_restore_mem_offset_save = s_restore_tmp //no conflict
+
+var s_restore_m0 = s_restore_alloc_size //no conflict
+
+var s_restore_mode = ttmp7
+
+var s_restore_pc_lo = ttmp0
+var s_restore_pc_hi = ttmp1
+var s_restore_exec_lo = tma_lo //no conflict
+var s_restore_exec_hi = tma_hi //no conflict
+var s_restore_status = ttmp4
+var s_restore_trapsts = ttmp5
+var s_restore_xnack_mask_lo = xnack_mask_lo
+var s_restore_xnack_mask_hi = xnack_mask_hi
+var s_restore_buf_rsrc0 = ttmp8
+var s_restore_buf_rsrc1 = ttmp9
+var s_restore_buf_rsrc2 = ttmp10
+var s_restore_buf_rsrc3 = ttmp11
+
+/**************************************************************************/
+/* trap handler entry points */
+/**************************************************************************/
+/* Shader Main*/
+
+shader main
+ asic(VI)
+ type(CS)
+
+
+ if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore
+ //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC
+ s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC
+ s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
+ s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE
+ //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE
+ s_branch L_SKIP_RESTORE //NOT restore, SAVE actually
+ else
+ s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save
+ end
+
+L_JUMP_TO_RESTORE:
+ s_branch L_RESTORE //restore
+
+L_SKIP_RESTORE:
+
+ s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC
+ s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save
+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+ s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save
+ s_cbranch_scc1 L_SAVE //this is the operation for save
+
+ // ********* Handle non-CWSR traps *******************
+if (!EMU_RUN_HACK)
+ /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */
+ s_load_dwordx4 [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0
+ s_waitcnt lgkmcnt(0)
+ s_or_b32 ttmp7, ttmp8, ttmp9
+ s_cbranch_scc0 L_NO_NEXT_TRAP //next level trap handler not been set
+ s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //restore HW status(SCC)
+ s_setpc_b64 [ttmp8,ttmp9] //jump to next level trap handler
+
+L_NO_NEXT_TRAP:
+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+ s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception
+ s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly.
+ s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0
+ s_addc_u32 ttmp1, ttmp1, 0
+L_EXCP_CASE:
+ s_and_b32 ttmp1, ttmp1, 0xFFFF
+ s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //restore HW status(SCC)
+ s_rfe_b64 [ttmp0, ttmp1]
+end
+ // ********* End handling of non-CWSR traps *******************
+
+/**************************************************************************/
+/* save routine */
+/**************************************************************************/
+
+L_SAVE:
+
+if G8SR_DEBUG_TIMESTAMP
+ s_memrealtime s_g8sr_ts_save_s
+ s_waitcnt lgkmcnt(0) //FIXME, will cause xnack??
+end
+
+ //check whether there is mem_viol
+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+ s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
+ s_cbranch_scc0 L_NO_PC_REWIND
+
+ //if so, need rewind PC assuming GDS operation gets NACKed
+ s_mov_b32 s_save_tmp, 0 //clear mem_viol bit
+ s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp //clear mem_viol bit
+ s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32]
+ s_sub_u32 s_save_pc_lo, s_save_pc_lo, 8 //pc[31:0]-8
+ s_subb_u32 s_save_pc_hi, s_save_pc_hi, 0x0 // -scc
+
+L_NO_PC_REWIND:
+ s_mov_b32 s_save_tmp, 0 //clear saveCtx bit
+ s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit
+
+ s_mov_b32 s_save_xnack_mask_lo, xnack_mask_lo //save XNACK_MASK
+ s_mov_b32 s_save_xnack_mask_hi, xnack_mask_hi //save XNACK must before any memory operation
+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT
+ s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
+ s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp
+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY
+ s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+ s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp
+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS
+ s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
+
+ s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp
+
+ /* inform SPI the readiness and wait for SPI's go signal */
+ s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI
+ s_mov_b32 s_save_exec_hi, exec_hi
+ s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive
+
+if G8SR_DEBUG_TIMESTAMP
+ s_memrealtime s_g8sr_ts_sq_save_msg
+ s_waitcnt lgkmcnt(0)
+end
+
+ if (EMU_RUN_HACK)
+
+ else
+ s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC
+ end
+
+ L_SLEEP:
+ s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
+
+ if (EMU_RUN_HACK)
+
+ else
+ s_cbranch_execz L_SLEEP
+ end
+
+if G8SR_DEBUG_TIMESTAMP
+ s_memrealtime s_g8sr_ts_spi_wrexec
+ s_waitcnt lgkmcnt(0)
+end
+
+ /* setup Resource Contants */
+ if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+ //calculate wd_addr using absolute thread id
+ v_readlane_b32 s_save_tmp, v9, 0
+ s_lshr_b32 s_save_tmp, s_save_tmp, 6
+ s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
+ s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+ s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+ s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+ else
+ end
+ if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+ s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+ s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+ s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+ else
+ end
+
+
+ s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo
+ s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi
+ s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE
+ s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
+ s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC
+ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK
+ s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position
+ s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC
+ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK
+ s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position
+ s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE
+
+ //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?)
+ s_mov_b32 s_save_m0, m0 //save M0
+
+ /* global mem offset */
+ s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0
+
+
+
+
+ /* save HW registers */
+ //////////////////////////////
+
+ L_SAVE_HWREG:
+ // HWREG SR memory offset : size(VGPR)+size(SGPR)
+ get_vgpr_size_bytes(s_save_mem_offset)
+ get_sgpr_size_bytes(s_save_tmp)
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp
+
+
+ s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes
+ if (SWIZZLE_EN)
+ s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+
+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0
+
+ if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
+ s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4
+ s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over
+ s_mov_b32 tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO
+ s_mov_b32 tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI
+ end
+
+ write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC
+ write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
+ write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC
+ write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)
+ write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS
+
+ //s_save_trapsts conflicts with s_save_alloc_size
+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+ write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS
+
+ write_hwreg_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO
+ write_hwreg_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI
+
+ //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
+ s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE
+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
+ write_hwreg_to_mem(tba_lo, s_save_buf_rsrc0, s_save_mem_offset) //TBA_LO
+ write_hwreg_to_mem(tba_hi, s_save_buf_rsrc0, s_save_mem_offset) //TBA_HI
+
+
+
+ /* the first wave in the threadgroup */
+ // save fist_wave bits in tba_hi unused bit.26
+ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit
+ //s_or_b32 tba_hi, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[26]
+ s_mov_b32 s_save_exec_hi, 0x0
+ s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26]
+
+
+ /* save SGPRs */
+ // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...
+ //////////////////////////////
+
+ // SGPR SR memory offset : size(VGPR)
+ get_vgpr_size_bytes(s_save_mem_offset)
+ // TODO, change RSRC word to rearrange memory layout for SGPRS
+
+ s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size
+ s_add_u32 s_save_alloc_size, s_save_alloc_size, 1
+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value)
+
+ if (SGPR_SAVE_USE_SQC)
+ s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes
+ else
+ s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads)
+ end
+
+ if (SWIZZLE_EN)
+ s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+
+ // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
+ //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0
+ s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0
+ s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset
+ s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0
+
+ s_mov_b32 m0, 0x0 //SGPR initial index value =0
+ L_SAVE_SGPR_LOOP:
+ // SGPR is allocated in 16 SGPR granularity
+ s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0]
+ s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0]
+ s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0]
+ s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0]
+ s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0]
+ s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0]
+ s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0]
+ s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0]
+
+ write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4
+ s_add_u32 m0, m0, 16 //next sgpr index
+ s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0
+ s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete?
+ // restore s_save_buf_rsrc0,1
+ //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo
+ s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo
+
+
+
+
+ /* save first 4 VGPR, then LDS save could use */
+ // each wave will alloc 4 vgprs at least...
+ /////////////////////////////////////////////////////////////////////////////////////
+
+ s_mov_b32 s_save_mem_offset, 0
+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on
+ s_mov_b32 exec_hi, 0xFFFFFFFF
+
+ if (SWIZZLE_EN)
+ s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+
+ // VGPR Allocated in 4-GPR granularity
+
+if G8SR_VGPR_SR_IN_DWX4
+ // the const stride for DWx4 is 4*4 bytes
+ s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0
+ s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes
+
+ buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+
+ s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0
+ s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes
+else
+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
+end
+
+
+
+ /* save LDS */
+ //////////////////////////////
+
+ L_SAVE_LDS:
+
+ // Change EXEC to all threads...
+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on
+ s_mov_b32 exec_hi, 0xFFFFFFFF
+
+ s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size
+ s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero?
+ s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE
+
+ s_barrier //LDS is used? wait for other waves in the same TG
+ //s_and_b32 s_save_tmp, tba_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here
+ s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here
+ s_cbranch_scc0 L_SAVE_LDS_DONE
+
+ // first wave do LDS save;
+
+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw
+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes
+ s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes
+
+ // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)
+ //
+ get_vgpr_size_bytes(s_save_mem_offset)
+ get_sgpr_size_bytes(s_save_tmp)
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
+
+
+ if (SWIZZLE_EN)
+ s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+ s_mov_b32 m0, 0x0 //lds_offset initial value = 0
+
+
+var LDS_DMA_ENABLE = 0
+var UNROLL = 0
+if UNROLL==0 && LDS_DMA_ENABLE==1
+ s_mov_b32 s3, 256*2
+ s_nop 0
+ s_nop 0
+ s_nop 0
+ L_SAVE_LDS_LOOP:
+ //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.???
+ if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity
+ buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW
+ buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW
+ end
+
+ s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes
+ s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0
+ s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete?
+
+elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss
+ // store from higest LDS address to lowest
+ s_mov_b32 s3, 256*2
+ s_sub_u32 m0, s_save_alloc_size, s3
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, m0
+ s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks...
+ s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest
+ s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction
+ s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc
+ s_nop 0
+ s_nop 0
+ s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes
+ s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved
+ s_add_u32 s0, s0,s_save_alloc_size
+ s_addc_u32 s1, s1, 0
+ s_setpc_b64 s[0:1]
+
+
+ for var i =0; i< 128; i++
+ // be careful to make here a 64Byte aligned address, which could improve performance...
+ buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW
+ buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW
+
+ if i!=127
+ s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline
+ s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3
+ end
+ end
+
+else // BUFFER_STORE
+ v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
+ v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid
+ v_mul_i32_i24 v2, v3, 8 // tid*8
+ v_mov_b32 v3, 256*2
+ s_mov_b32 m0, 0x10000
+ s_mov_b32 s0, s_save_buf_rsrc3
+ s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid
+ s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT
+
+L_SAVE_LDS_LOOP_VECTOR:
+ ds_read_b64 v[0:1], v2 //x =LDS[a], byte address
+ s_waitcnt lgkmcnt(0)
+ buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
+// s_waitcnt vmcnt(0)
+ v_add_u32 v2, vcc[0:1], v2, v3
+ v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size
+ s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR
+
+ // restore rsrc3
+ s_mov_b32 s_save_buf_rsrc3, s0
+
+end
+
+L_SAVE_LDS_DONE:
+
+
+ /* save VGPRs - set the Rest VGPRs */
+ //////////////////////////////////////////////////////////////////////////////////////
+ L_SAVE_VGPR:
+ // VGPR SR memory offset: 0
+ // TODO rearrange the RSRC words to use swizzle for VGPR save...
+
+ s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs
+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on
+ s_mov_b32 exec_hi, 0xFFFFFFFF
+
+ s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size
+ s_add_u32 s_save_alloc_size, s_save_alloc_size, 1
+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible
+ s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4)
+ if (SWIZZLE_EN)
+ s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+
+ // VGPR Allocated in 4-GPR granularity
+
+if G8SR_VGPR_SR_IN_DWX4
+ // the const stride for DWx4 is 4*4 bytes
+ s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0
+ s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes
+
+ s_mov_b32 m0, 4 // skip first 4 VGPRs
+ s_cmp_lt_u32 m0, s_save_alloc_size
+ s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs
+
+ s_set_gpr_idx_on m0, 0x1 // This will change M0
+ s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0
+L_SAVE_VGPR_LOOP:
+ v_mov_b32 v0, v0 // v0 = v[0+m0]
+ v_mov_b32 v1, v1
+ v_mov_b32 v2, v2
+ v_mov_b32 v3, v3
+
+
+ buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+ s_add_u32 m0, m0, 4
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4
+ s_cmp_lt_u32 m0, s_save_alloc_size
+ s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete?
+ s_set_gpr_idx_off
+L_SAVE_VGPR_LOOP_END:
+
+ s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0
+ s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes
+else
+ // VGPR store using dw burst
+ s_mov_b32 m0, 0x4 //VGPR initial index value =0
+ s_cmp_lt_u32 m0, s_save_alloc_size
+ s_cbranch_scc0 L_SAVE_VGPR_END
+
+
+ s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
+ s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later
+
+ L_SAVE_VGPR_LOOP:
+ v_mov_b32 v0, v0 //v0 = v[0+m0]
+ v_mov_b32 v1, v1 //v0 = v[0+m0]
+ v_mov_b32 v2, v2 //v0 = v[0+m0]
+ v_mov_b32 v3, v3 //v0 = v[0+m0]
+
+ if(USE_MTBUF_INSTEAD_OF_MUBUF)
+ tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+ else
+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
+ end
+
+ s_add_u32 m0, m0, 4 //next vgpr index
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes
+ s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0
+ s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete?
+ s_set_gpr_idx_off
+end
+
+L_SAVE_VGPR_END:
+
+
+
+
+
+
+ /* S_PGM_END_SAVED */ //FIXME graphics ONLY
+ if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
+ s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32]
+ s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4
+ s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over
+ s_rfe_b64 s_save_pc_lo //Return to the main shader program
+ else
+ end
+
+// Save Done timestamp
+if G8SR_DEBUG_TIMESTAMP
+ s_memrealtime s_g8sr_ts_save_d
+ // SGPR SR memory offset : size(VGPR)
+ get_vgpr_size_bytes(s_save_mem_offset)
+ s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET
+ s_waitcnt lgkmcnt(0) //FIXME, will cause xnack??
+ // Need reset rsrc2??
+ s_mov_b32 m0, s_save_mem_offset
+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1
+end
+
+
+ s_branch L_END_PGM
+
+
+
+/**************************************************************************/
+/* restore routine */
+/**************************************************************************/
+
+L_RESTORE:
+ /* Setup Resource Contants */
+ if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+ //calculate wd_addr using absolute thread id
+ v_readlane_b32 s_restore_tmp, v9, 0
+ s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
+ s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
+ s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
+ s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
+ s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
+ else
+ end
+
+if G8SR_DEBUG_TIMESTAMP
+ s_memrealtime s_g8sr_ts_restore_s
+ s_waitcnt lgkmcnt(0) //FIXME, will cause xnack??
+ // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case...
+ s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0]
+ s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored..
+end
+
+
+
+ s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo
+ s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi
+ s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE
+ s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes)
+ s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC
+ s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK
+ s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position
+ s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC
+ s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK
+ s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position
+ s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE
+
+ /* global mem offset */
+// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0
+
+ /* the first wave in the threadgroup */
+ s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
+ s_cbranch_scc0 L_RESTORE_VGPR
+
+ /* restore LDS */
+ //////////////////////////////
+ L_RESTORE_LDS:
+
+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead
+ s_mov_b32 exec_hi, 0xFFFFFFFF
+
+ s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size
+ s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero?
+ s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR
+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw
+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes
+ s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes
+
+ // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)
+ //
+ get_vgpr_size_bytes(s_restore_mem_offset)
+ get_sgpr_size_bytes(s_restore_tmp)
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow???
+
+
+ if (SWIZZLE_EN)
+ s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+ s_mov_b32 m0, 0x0 //lds_offset initial value = 0
+
+ L_RESTORE_LDS_LOOP:
+ if (SAVE_LDS)
+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW
+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW
+ end
+ s_add_u32 m0, m0, 256*2 // 128 DW
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW
+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0
+ s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete?
+
+
+ /* restore VGPRs */
+ //////////////////////////////
+ L_RESTORE_VGPR:
+ // VGPR SR memory offset : 0
+ s_mov_b32 s_restore_mem_offset, 0x0
+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead
+ s_mov_b32 exec_hi, 0xFFFFFFFF
+
+ s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size
+ s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1
+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value)
+ s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4)
+ if (SWIZZLE_EN)
+ s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+if G8SR_VGPR_SR_IN_DWX4
+ get_vgpr_size_bytes(s_restore_mem_offset)
+ s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4
+
+ // the const stride for DWx4 is 4*4 bytes
+ s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0
+ s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes
+
+ s_mov_b32 m0, s_restore_alloc_size
+ s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0
+
+L_RESTORE_VGPR_LOOP:
+ buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
+ s_waitcnt vmcnt(0)
+ s_sub_u32 m0, m0, 4
+ v_mov_b32 v0, v0 // v[0+m0] = v0
+ v_mov_b32 v1, v1
+ v_mov_b32 v2, v2
+ v_mov_b32 v3, v3
+ s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4
+ s_cmp_eq_u32 m0, 0x8000
+ s_cbranch_scc0 L_RESTORE_VGPR_LOOP
+ s_set_gpr_idx_off
+
+ s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0
+ s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes
+
+else
+ // VGPR load using dw burst
+ s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4
+ s_mov_b32 m0, 4 //VGPR initial index value = 1
+ s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8
+ s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later
+
+ L_RESTORE_VGPR_LOOP:
+ if(USE_MTBUF_INSTEAD_OF_MUBUF)
+ tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+ else
+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
+ end
+ s_waitcnt vmcnt(0) //ensure data ready
+ v_mov_b32 v0, v0 //v[0+m0] = v0
+ v_mov_b32 v1, v1
+ v_mov_b32 v2, v2
+ v_mov_b32 v3, v3
+ s_add_u32 m0, m0, 4 //next vgpr index
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes
+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0
+ s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete?
+ s_set_gpr_idx_off
+ /* VGPR restore on v0 */
+ if(USE_MTBUF_INSTEAD_OF_MUBUF)
+ tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+ else
+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1
+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256
+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2
+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3
+ end
+
+end
+
+ /* restore SGPRs */
+ //////////////////////////////
+
+ // SGPR SR memory offset : size(VGPR)
+ get_vgpr_size_bytes(s_restore_mem_offset)
+ get_sgpr_size_bytes(s_restore_tmp)
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
+ s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group
+ // TODO, change RSRC word to rearrange memory layout for SGPRS
+
+ s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size
+ s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1
+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value)
+
+ if (SGPR_SAVE_USE_SQC)
+ s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes
+ else
+ s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads)
+ end
+ if (SWIZZLE_EN)
+ s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+ /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111),
+ However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG
+ */
+ s_mov_b32 m0, s_restore_alloc_size
+
+ L_RESTORE_SGPR_LOOP:
+ read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made
+ s_waitcnt lgkmcnt(0) //ensure data ready
+
+ s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0]
+
+ s_movreld_b64 s0, s0 //s[0+m0] = s0
+ s_movreld_b64 s2, s2
+ s_movreld_b64 s4, s4
+ s_movreld_b64 s6, s6
+ s_movreld_b64 s8, s8
+ s_movreld_b64 s10, s10
+ s_movreld_b64 s12, s12
+ s_movreld_b64 s14, s14
+
+ s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0
+ s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete?
+
+ /* restore HW registers */
+ //////////////////////////////
+ L_RESTORE_HWREG:
+
+
+if G8SR_DEBUG_TIMESTAMP
+ s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo
+ s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi
+end
+
+ // HWREG SR memory offset : size(VGPR)+size(SGPR)
+ get_vgpr_size_bytes(s_restore_mem_offset)
+ get_sgpr_size_bytes(s_restore_tmp)
+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
+
+
+ s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes
+ if (SWIZZLE_EN)
+ s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking?
+ else
+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes
+ end
+
+ read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0
+ read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC
+ read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
+ read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC
+ read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
+ read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS
+ read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS
+ read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO
+ read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI
+ read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE
+ read_hwreg_from_mem(tba_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_LO
+ read_hwreg_from_mem(tba_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_HI
+
+ s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS
+
+ s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS
+
+ //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
+ if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+ s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore)
+ s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over
+ end
+ if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
+ s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal
+ s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over
+ end
+
+ s_mov_b32 m0, s_restore_m0
+ s_mov_b32 exec_lo, s_restore_exec_lo
+ s_mov_b32 exec_hi, s_restore_exec_hi
+
+ s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
+ s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
+ s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
+ s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
+ s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
+ //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
+ s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode
+ //reuse s_restore_m0 as a temp register
+ s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK
+ s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
+ s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
+ s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero
+ s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0
+ s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK
+ s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+ s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
+ s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0
+ s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK
+ s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
+ s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp
+
+ s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32
+ s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32
+ s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu
+
+ s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
+
+if G8SR_DEBUG_TIMESTAMP
+ s_memrealtime s_g8sr_ts_restore_d
+ s_waitcnt lgkmcnt(0)
+end
+
+// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution
+ s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc
+
+
+/**************************************************************************/
+/* the END */
+/**************************************************************************/
+L_END_PGM:
+ s_endpgm
+
+end
+
+
+/**************************************************************************/
+/* the helper functions */
+/**************************************************************************/
+
+//Only for save hwreg to mem
+function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)
+ s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on
+ s_mov_b32 m0, s_mem_offset
+ s_buffer_store_dword s, s_rsrc, m0 glc:1
+ s_add_u32 s_mem_offset, s_mem_offset, 4
+ s_mov_b32 m0, exec_lo
+end
+
+
+// HWREG are saved before SGPRs, so all HWREG could be use.
+function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)
+
+ s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1
+ s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1
+ s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1
+ s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1
+ s_add_u32 s_rsrc[0], s_rsrc[0], 4*16
+ s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc
+end
+
+
+function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)
+ s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1
+ s_add_u32 s_mem_offset, s_mem_offset, 4
+end
+
+function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)
+ s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1
+ s_sub_u32 s_mem_offset, s_mem_offset, 4*16
+end
+
+
+
+function get_lds_size_bytes(s_lds_size_byte)
+ // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW
+ s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size
+ s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW
+end
+
+function get_vgpr_size_bytes(s_vgpr_size_byte)
+ s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size
+ s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1
+ s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible
+end
+
+function get_sgpr_size_bytes(s_sgpr_size_byte)
+ s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size
+ s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1
+ s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value)
+end
+
+function get_hwreg_size_bytes
+ return 128 //HWREG size 128 bytes
+end
+
+
+#endif
+
+static const uint32_t cwsr_trap_gfx8_hex[] = {
+ 0xbf820001, 0xbf820123,
+ 0xb8f4f802, 0x89748674,
+ 0xb8f5f803, 0x8675ff75,
+ 0x00000400, 0xbf850011,
+ 0xc00a1e37, 0x00000000,
+ 0xbf8c007f, 0x87777978,
+ 0xbf840002, 0xb974f802,
+ 0xbe801d78, 0xb8f5f803,
+ 0x8675ff75, 0x000001ff,
+ 0xbf850002, 0x80708470,
+ 0x82718071, 0x8671ff71,
+ 0x0000ffff, 0xb974f802,
+ 0xbe801f70, 0xb8f5f803,
+ 0x8675ff75, 0x00000100,
+ 0xbf840006, 0xbefa0080,
+ 0xb97a0203, 0x8671ff71,
+ 0x0000ffff, 0x80f08870,
+ 0x82f18071, 0xbefa0080,
+ 0xb97a0283, 0xbef60068,
+ 0xbef70069, 0xb8fa1c07,
+ 0x8e7a9c7a, 0x87717a71,
+ 0xb8fa03c7, 0x8e7a9b7a,
+ 0x87717a71, 0xb8faf807,
+ 0x867aff7a, 0x00007fff,
+ 0xb97af807, 0xbef2007e,
+ 0xbef3007f, 0xbefe0180,
+ 0xbf900004, 0xbf8e0002,
+ 0xbf88fffe, 0xbef8007e,
+ 0x8679ff7f, 0x0000ffff,
+ 0x8779ff79, 0x00040000,
+ 0xbefa0080, 0xbefb00ff,
+ 0x00807fac, 0x867aff7f,
+ 0x08000000, 0x8f7a837a,
+ 0x877b7a7b, 0x867aff7f,
+ 0x70000000, 0x8f7a817a,
+ 0x877b7a7b, 0xbeef007c,
+ 0xbeee0080, 0xb8ee2a05,
+ 0x806e816e, 0x8e6e8a6e,
+ 0xb8fa1605, 0x807a817a,
+ 0x8e7a867a, 0x806e7a6e,
+ 0xbefa0084, 0xbefa00ff,
+ 0x01000000, 0xbefe007c,
+ 0xbefc006e, 0xc0611bfc,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611c3c,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611c7c,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611cbc,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611cfc,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611d3c,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xb8f5f803,
+ 0xbefe007c, 0xbefc006e,
+ 0xc0611d7c, 0x0000007c,
+ 0x806e846e, 0xbefc007e,
+ 0xbefe007c, 0xbefc006e,
+ 0xc0611dbc, 0x0000007c,
+ 0x806e846e, 0xbefc007e,
+ 0xbefe007c, 0xbefc006e,
+ 0xc0611dfc, 0x0000007c,
+ 0x806e846e, 0xbefc007e,
+ 0xb8eff801, 0xbefe007c,
+ 0xbefc006e, 0xc0611bfc,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611b3c,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0xbefe007c,
+ 0xbefc006e, 0xc0611b7c,
+ 0x0000007c, 0x806e846e,
+ 0xbefc007e, 0x867aff7f,
+ 0x04000000, 0xbef30080,
+ 0x8773737a, 0xb8ee2a05,
+ 0x806e816e, 0x8e6e8a6e,
+ 0xb8f51605, 0x80758175,
+ 0x8e758475, 0x8e7a8275,
+ 0xbefa00ff, 0x01000000,
+ 0xbef60178, 0x80786e78,
+ 0x82798079, 0xbefc0080,
+ 0xbe802b00, 0xbe822b02,
+ 0xbe842b04, 0xbe862b06,
+ 0xbe882b08, 0xbe8a2b0a,
+ 0xbe8c2b0c, 0xbe8e2b0e,
+ 0xc06b003c, 0x00000000,
+ 0xc06b013c, 0x00000010,
+ 0xc06b023c, 0x00000020,
+ 0xc06b033c, 0x00000030,
+ 0x8078c078, 0x82798079,
+ 0x807c907c, 0xbf0a757c,
+ 0xbf85ffeb, 0xbef80176,
+ 0xbeee0080, 0xbefe00c1,
+ 0xbeff00c1, 0xbefa00ff,
+ 0x01000000, 0xe0724000,
+ 0x6e1e0000, 0xe0724100,
+ 0x6e1e0100, 0xe0724200,
+ 0x6e1e0200, 0xe0724300,
+ 0x6e1e0300, 0xbefe00c1,
+ 0xbeff00c1, 0xb8f54306,
+ 0x8675c175, 0xbf84002c,
+ 0xbf8a0000, 0x867aff73,
+ 0x04000000, 0xbf840028,
+ 0x8e758675, 0x8e758275,
+ 0xbefa0075, 0xb8ee2a05,
+ 0x806e816e, 0x8e6e8a6e,
+ 0xb8fa1605, 0x807a817a,
+ 0x8e7a867a, 0x806e7a6e,
+ 0x806eff6e, 0x00000080,
+ 0xbefa00ff, 0x01000000,
+ 0xbefc0080, 0xd28c0002,
+ 0x000100c1, 0xd28d0003,
+ 0x000204c1, 0xd1060002,
+ 0x00011103, 0x7e0602ff,
+ 0x00000200, 0xbefc00ff,
+ 0x00010000, 0xbe80007b,
+ 0x867bff7b, 0xff7fffff,
+ 0x877bff7b, 0x00058000,
+ 0xd8ec0000, 0x00000002,
+ 0xbf8c007f, 0xe0765000,
+ 0x6e1e0002, 0x32040702,
+ 0xd0c9006a, 0x0000eb02,
+ 0xbf87fff7, 0xbefb0000,
+ 0xbeee00ff, 0x00000400,
+ 0xbefe00c1, 0xbeff00c1,
+ 0xb8f52a05, 0x80758175,
+ 0x8e758275, 0x8e7a8875,
+ 0xbefa00ff, 0x01000000,
+ 0xbefc0084, 0xbf0a757c,
+ 0xbf840015, 0xbf11017c,
+ 0x8075ff75, 0x00001000,
+ 0x7e000300, 0x7e020301,
+ 0x7e040302, 0x7e060303,
+ 0xe0724000, 0x6e1e0000,
+ 0xe0724100, 0x6e1e0100,
+ 0xe0724200, 0x6e1e0200,
+ 0xe0724300, 0x6e1e0300,
+ 0x807c847c, 0x806eff6e,
+ 0x00000400, 0xbf0a757c,
+ 0xbf85ffef, 0xbf9c0000,
+ 0xbf8200ca, 0xbef8007e,
+ 0x8679ff7f, 0x0000ffff,
+ 0x8779ff79, 0x00040000,
+ 0xbefa0080, 0xbefb00ff,
+ 0x00807fac, 0x8676ff7f,
+ 0x08000000, 0x8f768376,
+ 0x877b767b, 0x8676ff7f,
+ 0x70000000, 0x8f768176,
+ 0x877b767b, 0x8676ff7f,
+ 0x04000000, 0xbf84001e,
+ 0xbefe00c1, 0xbeff00c1,
+ 0xb8f34306, 0x8673c173,
+ 0xbf840019, 0x8e738673,
+ 0x8e738273, 0xbefa0073,
+ 0xb8f22a05, 0x80728172,
+ 0x8e728a72, 0xb8f61605,
+ 0x80768176, 0x8e768676,
+ 0x80727672, 0x8072ff72,
+ 0x00000080, 0xbefa00ff,
+ 0x01000000, 0xbefc0080,
+ 0xe0510000, 0x721e0000,
+ 0xe0510100, 0x721e0000,
+ 0x807cff7c, 0x00000200,
+ 0x8072ff72, 0x00000200,
+ 0xbf0a737c, 0xbf85fff6,
+ 0xbef20080, 0xbefe00c1,
+ 0xbeff00c1, 0xb8f32a05,
+ 0x80738173, 0x8e738273,
+ 0x8e7a8873, 0xbefa00ff,
+ 0x01000000, 0xbef60072,
+ 0x8072ff72, 0x00000400,
+ 0xbefc0084, 0xbf11087c,
+ 0x8073ff73, 0x00008000,
+ 0xe0524000, 0x721e0000,
+ 0xe0524100, 0x721e0100,
+ 0xe0524200, 0x721e0200,
+ 0xe0524300, 0x721e0300,
+ 0xbf8c0f70, 0x7e000300,
+ 0x7e020301, 0x7e040302,
+ 0x7e060303, 0x807c847c,
+ 0x8072ff72, 0x00000400,
+ 0xbf0a737c, 0xbf85ffee,
+ 0xbf9c0000, 0xe0524000,
+ 0x761e0000, 0xe0524100,
+ 0x761e0100, 0xe0524200,
+ 0x761e0200, 0xe0524300,
+ 0x761e0300, 0xb8f22a05,
+ 0x80728172, 0x8e728a72,
+ 0xb8f61605, 0x80768176,
+ 0x8e768676, 0x80727672,
+ 0x80f2c072, 0xb8f31605,
+ 0x80738173, 0x8e738473,
+ 0x8e7a8273, 0xbefa00ff,
+ 0x01000000, 0xbefc0073,
+ 0xc031003c, 0x00000072,
+ 0x80f2c072, 0xbf8c007f,
+ 0x80fc907c, 0xbe802d00,
+ 0xbe822d02, 0xbe842d04,
+ 0xbe862d06, 0xbe882d08,
+ 0xbe8a2d0a, 0xbe8c2d0c,
+ 0xbe8e2d0e, 0xbf06807c,
+ 0xbf84fff1, 0xb8f22a05,
+ 0x80728172, 0x8e728a72,
+ 0xb8f61605, 0x80768176,
+ 0x8e768676, 0x80727672,
+ 0xbefa0084, 0xbefa00ff,
+ 0x01000000, 0xc0211cfc,
+ 0x00000072, 0x80728472,
+ 0xc0211c3c, 0x00000072,
+ 0x80728472, 0xc0211c7c,
+ 0x00000072, 0x80728472,
+ 0xc0211bbc, 0x00000072,
+ 0x80728472, 0xc0211bfc,
+ 0x00000072, 0x80728472,
+ 0xc0211d3c, 0x00000072,
+ 0x80728472, 0xc0211d7c,
+ 0x00000072, 0x80728472,
+ 0xc0211a3c, 0x00000072,
+ 0x80728472, 0xc0211a7c,
+ 0x00000072, 0x80728472,
+ 0xc0211dfc, 0x00000072,
+ 0x80728472, 0xc0211b3c,
+ 0x00000072, 0x80728472,
+ 0xc0211b7c, 0x00000072,
+ 0x80728472, 0xbf8c007f,
+ 0x8671ff71, 0x0000ffff,
+ 0xbefc0073, 0xbefe006e,
+ 0xbeff006f, 0x867375ff,
+ 0x000003ff, 0xb9734803,
+ 0x867375ff, 0xfffff800,
+ 0x8f738b73, 0xb973a2c3,
+ 0xb977f801, 0x8673ff71,
+ 0xf0000000, 0x8f739c73,
+ 0x8e739073, 0xbef60080,
+ 0x87767376, 0x8673ff71,
+ 0x08000000, 0x8f739b73,
+ 0x8e738f73, 0x87767376,
+ 0x8673ff74, 0x00800000,
+ 0x8f739773, 0xb976f807,
+ 0x86fe7e7e, 0x86ea6a6a,
+ 0xb974f802, 0xbf8a0000,
+ 0x95807370, 0xbf810000,
+};
+
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 87eea5f..0492aff 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -117,7 +117,7 @@
return -EPERM;
}
- process = kfd_create_process(current);
+ process = kfd_create_process(filep);
if (IS_ERR(process))
return PTR_ERR(process);
@@ -206,6 +206,7 @@
q_properties->ctx_save_restore_area_address =
args->ctx_save_restore_address;
q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
+ q_properties->ctl_stack_size = args->ctl_stack_size;
if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
@@ -431,6 +432,38 @@
return err;
}
+static int kfd_ioctl_set_trap_handler(struct file *filep,
+ struct kfd_process *p, void *data)
+{
+ struct kfd_ioctl_set_trap_handler_args *args = data;
+ struct kfd_dev *dev;
+ int err = 0;
+ struct kfd_process_device *pdd;
+
+ dev = kfd_device_by_id(args->gpu_id);
+ if (dev == NULL)
+ return -EINVAL;
+
+ mutex_lock(&p->mutex);
+
+ pdd = kfd_bind_process_to_device(dev, p);
+ if (IS_ERR(pdd)) {
+ err = -ESRCH;
+ goto out;
+ }
+
+ if (dev->dqm->ops.set_trap_handler(dev->dqm,
+ &pdd->qpd,
+ args->tba_addr,
+ args->tma_addr))
+ err = -EINVAL;
+
+out:
+ mutex_unlock(&p->mutex);
+
+ return err;
+}
+
static int kfd_ioctl_dbg_register(struct file *filep,
struct kfd_process *p, void *data)
{
@@ -493,7 +526,7 @@
long status;
dev = kfd_device_by_id(args->gpu_id);
- if (!dev)
+ if (!dev || !dev->dbgmgr)
return -EINVAL;
if (dev->device_info->asic_family == CHIP_CARRIZO) {
@@ -980,7 +1013,10 @@
kfd_ioctl_set_scratch_backing_va, 0),
AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
- kfd_ioctl_get_tile_config, 0)
+ kfd_ioctl_get_tile_config, 0),
+
+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
+ kfd_ioctl_set_trap_handler, 0),
};
#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
@@ -1089,6 +1125,10 @@
KFD_MMAP_EVENTS_MASK) {
vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_EVENTS_MASK;
return kfd_event_mmap(process, vma);
+ } else if ((vma->vm_pgoff & KFD_MMAP_RESERVED_MEM_MASK) ==
+ KFD_MMAP_RESERVED_MEM_MASK) {
+ vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_RESERVED_MEM_MASK;
+ return kfd_reserved_mem_mmap(process, vma);
}
return -EFAULT;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
new file mode 100644
index 0000000..2bc2816
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -0,0 +1,1267 @@
+/*
+ * Copyright 2015-2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/pci.h>
+#include <linux/acpi.h>
+#include <linux/amd-iommu.h>
+#include "kfd_crat.h"
+#include "kfd_priv.h"
+#include "kfd_topology.h"
+
+/* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
+ * GPU processor ID are expressed with Bit[31]=1.
+ * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
+ * used in the CRAT.
+ */
+static uint32_t gpu_processor_id_low = 0x80001000;
+
+/* Return the next available gpu_processor_id and increment it for next GPU
+ * @total_cu_count - Total CUs present in the GPU including ones
+ * masked off
+ */
+static inline unsigned int get_and_inc_gpu_processor_id(
+ unsigned int total_cu_count)
+{
+ int current_id = gpu_processor_id_low;
+
+ gpu_processor_id_low += total_cu_count;
+ return current_id;
+}
+
+/* Static table to describe GPU Cache information */
+struct kfd_gpu_cache_info {
+ uint32_t cache_size;
+ uint32_t cache_level;
+ uint32_t flags;
+ /* Indicates how many Compute Units share this cache
+ * Value = 1 indicates the cache is not shared
+ */
+ uint32_t num_cu_shared;
+};
+
+static struct kfd_gpu_cache_info kaveri_cache_info[] = {
+ {
+ /* TCP L1 Cache per CU */
+ .cache_size = 16,
+ .cache_level = 1,
+ .flags = (CRAT_CACHE_FLAGS_ENABLED |
+ CRAT_CACHE_FLAGS_DATA_CACHE |
+ CRAT_CACHE_FLAGS_SIMD_CACHE),
+ .num_cu_shared = 1,
+
+ },
+ {
+ /* Scalar L1 Instruction Cache (in SQC module) per bank */
+ .cache_size = 16,
+ .cache_level = 1,
+ .flags = (CRAT_CACHE_FLAGS_ENABLED |
+ CRAT_CACHE_FLAGS_INST_CACHE |
+ CRAT_CACHE_FLAGS_SIMD_CACHE),
+ .num_cu_shared = 2,
+ },
+ {
+ /* Scalar L1 Data Cache (in SQC module) per bank */
+ .cache_size = 8,
+ .cache_level = 1,
+ .flags = (CRAT_CACHE_FLAGS_ENABLED |
+ CRAT_CACHE_FLAGS_DATA_CACHE |
+ CRAT_CACHE_FLAGS_SIMD_CACHE),
+ .num_cu_shared = 2,
+ },
+
+ /* TODO: Add L2 Cache information */
+};
+
+
+static struct kfd_gpu_cache_info carrizo_cache_info[] = {
+ {
+ /* TCP L1 Cache per CU */
+ .cache_size = 16,
+ .cache_level = 1,
+ .flags = (CRAT_CACHE_FLAGS_ENABLED |
+ CRAT_CACHE_FLAGS_DATA_CACHE |
+ CRAT_CACHE_FLAGS_SIMD_CACHE),
+ .num_cu_shared = 1,
+ },
+ {
+ /* Scalar L1 Instruction Cache (in SQC module) per bank */
+ .cache_size = 8,
+ .cache_level = 1,
+ .flags = (CRAT_CACHE_FLAGS_ENABLED |
+ CRAT_CACHE_FLAGS_INST_CACHE |
+ CRAT_CACHE_FLAGS_SIMD_CACHE),
+ .num_cu_shared = 4,
+ },
+ {
+ /* Scalar L1 Data Cache (in SQC module) per bank. */
+ .cache_size = 4,
+ .cache_level = 1,
+ .flags = (CRAT_CACHE_FLAGS_ENABLED |
+ CRAT_CACHE_FLAGS_DATA_CACHE |
+ CRAT_CACHE_FLAGS_SIMD_CACHE),
+ .num_cu_shared = 4,
+ },
+
+ /* TODO: Add L2 Cache information */
+};
+
+/* NOTE: In future if more information is added to struct kfd_gpu_cache_info
+ * the following ASICs may need a separate table.
+ */
+#define hawaii_cache_info kaveri_cache_info
+#define tonga_cache_info carrizo_cache_info
+#define fiji_cache_info carrizo_cache_info
+#define polaris10_cache_info carrizo_cache_info
+#define polaris11_cache_info carrizo_cache_info
+
+static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
+ struct crat_subtype_computeunit *cu)
+{
+ dev->node_props.cpu_cores_count = cu->num_cpu_cores;
+ dev->node_props.cpu_core_id_base = cu->processor_id_low;
+ if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
+ dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
+
+ pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
+ cu->processor_id_low);
+}
+
+static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
+ struct crat_subtype_computeunit *cu)
+{
+ dev->node_props.simd_id_base = cu->processor_id_low;
+ dev->node_props.simd_count = cu->num_simd_cores;
+ dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
+ dev->node_props.max_waves_per_simd = cu->max_waves_simd;
+ dev->node_props.wave_front_size = cu->wave_front_size;
+ dev->node_props.array_count = cu->array_count;
+ dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
+ dev->node_props.simd_per_cu = cu->num_simd_per_cu;
+ dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
+ if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
+ dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
+ pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low);
+}
+
+/* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct
+ * topology device present in the device_list
+ */
+static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu,
+ struct list_head *device_list)
+{
+ struct kfd_topology_device *dev;
+
+ pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
+ cu->proximity_domain, cu->hsa_capability);
+ list_for_each_entry(dev, device_list, list) {
+ if (cu->proximity_domain == dev->proximity_domain) {
+ if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
+ kfd_populated_cu_info_cpu(dev, cu);
+
+ if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
+ kfd_populated_cu_info_gpu(dev, cu);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+/* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
+ * topology device present in the device_list
+ */
+static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem,
+ struct list_head *device_list)
+{
+ struct kfd_mem_properties *props;
+ struct kfd_topology_device *dev;
+
+ pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
+ mem->proximity_domain);
+ list_for_each_entry(dev, device_list, list) {
+ if (mem->proximity_domain == dev->proximity_domain) {
+ props = kfd_alloc_struct(props);
+ if (!props)
+ return -ENOMEM;
+
+ /* We're on GPU node */
+ if (dev->node_props.cpu_cores_count == 0) {
+ /* APU */
+ if (mem->visibility_type == 0)
+ props->heap_type =
+ HSA_MEM_HEAP_TYPE_FB_PRIVATE;
+ /* dGPU */
+ else
+ props->heap_type = mem->visibility_type;
+ } else
+ props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
+
+ if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
+ props->flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
+ if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
+ props->flags |= HSA_MEM_FLAGS_NON_VOLATILE;
+
+ props->size_in_bytes =
+ ((uint64_t)mem->length_high << 32) +
+ mem->length_low;
+ props->width = mem->width;
+
+ dev->node_props.mem_banks_count++;
+ list_add_tail(&props->list, &dev->mem_props);
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+/* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct
+ * topology device present in the device_list
+ */
+static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache,
+ struct list_head *device_list)
+{
+ struct kfd_cache_properties *props;
+ struct kfd_topology_device *dev;
+ uint32_t id;
+ uint32_t total_num_of_cu;
+
+ id = cache->processor_id_low;
+
+ pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
+ list_for_each_entry(dev, device_list, list) {
+ total_num_of_cu = (dev->node_props.array_count *
+ dev->node_props.cu_per_simd_array);
+
+ /* Cache infomration in CRAT doesn't have proximity_domain
+ * information as it is associated with a CPU core or GPU
+ * Compute Unit. So map the cache using CPU core Id or SIMD
+ * (GPU) ID.
+ * TODO: This works because currently we can safely assume that
+ * Compute Units are parsed before caches are parsed. In
+ * future, remove this dependency
+ */
+ if ((id >= dev->node_props.cpu_core_id_base &&
+ id <= dev->node_props.cpu_core_id_base +
+ dev->node_props.cpu_cores_count) ||
+ (id >= dev->node_props.simd_id_base &&
+ id < dev->node_props.simd_id_base +
+ total_num_of_cu)) {
+ props = kfd_alloc_struct(props);
+ if (!props)
+ return -ENOMEM;
+
+ props->processor_id_low = id;
+ props->cache_level = cache->cache_level;
+ props->cache_size = cache->cache_size;
+ props->cacheline_size = cache->cache_line_size;
+ props->cachelines_per_tag = cache->lines_per_tag;
+ props->cache_assoc = cache->associativity;
+ props->cache_latency = cache->cache_latency;
+ memcpy(props->sibling_map, cache->sibling_map,
+ sizeof(props->sibling_map));
+
+ if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
+ props->cache_type |= HSA_CACHE_TYPE_DATA;
+ if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
+ props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
+ if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
+ props->cache_type |= HSA_CACHE_TYPE_CPU;
+ if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
+ props->cache_type |= HSA_CACHE_TYPE_HSACU;
+
+ dev->cache_count++;
+ dev->node_props.caches_count++;
+ list_add_tail(&props->list, &dev->cache_props);
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+/* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct
+ * topology device present in the device_list
+ */
+static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
+ struct list_head *device_list)
+{
+ struct kfd_iolink_properties *props = NULL, *props2;
+ struct kfd_topology_device *dev, *cpu_dev;
+ uint32_t id_from;
+ uint32_t id_to;
+
+ id_from = iolink->proximity_domain_from;
+ id_to = iolink->proximity_domain_to;
+
+ pr_debug("Found IO link entry in CRAT table with id_from=%d\n",
+ id_from);
+ list_for_each_entry(dev, device_list, list) {
+ if (id_from == dev->proximity_domain) {
+ props = kfd_alloc_struct(props);
+ if (!props)
+ return -ENOMEM;
+
+ props->node_from = id_from;
+ props->node_to = id_to;
+ props->ver_maj = iolink->version_major;
+ props->ver_min = iolink->version_minor;
+ props->iolink_type = iolink->io_interface_type;
+
+ if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
+ props->weight = 20;
+ else
+ props->weight = node_distance(id_from, id_to);
+
+ props->min_latency = iolink->minimum_latency;
+ props->max_latency = iolink->maximum_latency;
+ props->min_bandwidth = iolink->minimum_bandwidth_mbs;
+ props->max_bandwidth = iolink->maximum_bandwidth_mbs;
+ props->rec_transfer_size =
+ iolink->recommended_transfer_size;
+
+ dev->io_link_count++;
+ dev->node_props.io_links_count++;
+ list_add_tail(&props->list, &dev->io_link_props);
+ break;
+ }
+ }
+
+ /* CPU topology is created before GPUs are detected, so CPU->GPU
+ * links are not built at that time. If a PCIe type is discovered, it
+ * means a GPU is detected and we are adding GPU->CPU to the topology.
+ * At this time, also add the corresponded CPU->GPU link.
+ */
+ if (props && props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS) {
+ cpu_dev = kfd_topology_device_by_proximity_domain(id_to);
+ if (!cpu_dev)
+ return -ENODEV;
+ /* same everything but the other direction */
+ props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL);
+ props2->node_from = id_to;
+ props2->node_to = id_from;
+ props2->kobj = NULL;
+ cpu_dev->io_link_count++;
+ cpu_dev->node_props.io_links_count++;
+ list_add_tail(&props2->list, &cpu_dev->io_link_props);
+ }
+
+ return 0;
+}
+
+/* kfd_parse_subtype - parse subtypes and attach it to correct topology device
+ * present in the device_list
+ * @sub_type_hdr - subtype section of crat_image
+ * @device_list - list of topology devices present in this crat_image
+ */
+static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr,
+ struct list_head *device_list)
+{
+ struct crat_subtype_computeunit *cu;
+ struct crat_subtype_memory *mem;
+ struct crat_subtype_cache *cache;
+ struct crat_subtype_iolink *iolink;
+ int ret = 0;
+
+ switch (sub_type_hdr->type) {
+ case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
+ cu = (struct crat_subtype_computeunit *)sub_type_hdr;
+ ret = kfd_parse_subtype_cu(cu, device_list);
+ break;
+ case CRAT_SUBTYPE_MEMORY_AFFINITY:
+ mem = (struct crat_subtype_memory *)sub_type_hdr;
+ ret = kfd_parse_subtype_mem(mem, device_list);
+ break;
+ case CRAT_SUBTYPE_CACHE_AFFINITY:
+ cache = (struct crat_subtype_cache *)sub_type_hdr;
+ ret = kfd_parse_subtype_cache(cache, device_list);
+ break;
+ case CRAT_SUBTYPE_TLB_AFFINITY:
+ /*
+ * For now, nothing to do here
+ */
+ pr_debug("Found TLB entry in CRAT table (not processing)\n");
+ break;
+ case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
+ /*
+ * For now, nothing to do here
+ */
+ pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n");
+ break;
+ case CRAT_SUBTYPE_IOLINK_AFFINITY:
+ iolink = (struct crat_subtype_iolink *)sub_type_hdr;
+ ret = kfd_parse_subtype_iolink(iolink, device_list);
+ break;
+ default:
+ pr_warn("Unknown subtype %d in CRAT\n",
+ sub_type_hdr->type);
+ }
+
+ return ret;
+}
+
+/* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT
+ * create a kfd_topology_device and add in to device_list. Also parse
+ * CRAT subtypes and attach it to appropriate kfd_topology_device
+ * @crat_image - input image containing CRAT
+ * @device_list - [OUT] list of kfd_topology_device generated after
+ * parsing crat_image
+ * @proximity_domain - Proximity domain of the first device in the table
+ *
+ * Return - 0 if successful else -ve value
+ */
+int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
+ uint32_t proximity_domain)
+{
+ struct kfd_topology_device *top_dev = NULL;
+ struct crat_subtype_generic *sub_type_hdr;
+ uint16_t node_id;
+ int ret = 0;
+ struct crat_header *crat_table = (struct crat_header *)crat_image;
+ uint16_t num_nodes;
+ uint32_t image_len;
+
+ if (!crat_image)
+ return -EINVAL;
+
+ if (!list_empty(device_list)) {
+ pr_warn("Error device list should be empty\n");
+ return -EINVAL;
+ }
+
+ num_nodes = crat_table->num_domains;
+ image_len = crat_table->length;
+
+ pr_info("Parsing CRAT table with %d nodes\n", num_nodes);
+
+ for (node_id = 0; node_id < num_nodes; node_id++) {
+ top_dev = kfd_create_topology_device(device_list);
+ if (!top_dev)
+ break;
+ top_dev->proximity_domain = proximity_domain++;
+ }
+
+ if (!top_dev) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH);
+ memcpy(top_dev->oem_table_id, crat_table->oem_table_id,
+ CRAT_OEMTABLEID_LENGTH);
+ top_dev->oem_revision = crat_table->oem_revision;
+
+ sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
+ while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
+ ((char *)crat_image) + image_len) {
+ if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
+ ret = kfd_parse_subtype(sub_type_hdr, device_list);
+ if (ret)
+ break;
+ }
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ sub_type_hdr->length);
+ }
+
+err:
+ if (ret)
+ kfd_release_topology_device_list(device_list);
+
+ return ret;
+}
+
+/* Helper function. See kfd_fill_gpu_cache_info for parameter description */
+static int fill_in_pcache(struct crat_subtype_cache *pcache,
+ struct kfd_gpu_cache_info *pcache_info,
+ struct kfd_cu_info *cu_info,
+ int mem_available,
+ int cu_bitmask,
+ int cache_type, unsigned int cu_processor_id,
+ int cu_block)
+{
+ unsigned int cu_sibling_map_mask;
+ int first_active_cu;
+
+ /* First check if enough memory is available */
+ if (sizeof(struct crat_subtype_cache) > mem_available)
+ return -ENOMEM;
+
+ cu_sibling_map_mask = cu_bitmask;
+ cu_sibling_map_mask >>= cu_block;
+ cu_sibling_map_mask &=
+ ((1 << pcache_info[cache_type].num_cu_shared) - 1);
+ first_active_cu = ffs(cu_sibling_map_mask);
+
+ /* CU could be inactive. In case of shared cache find the first active
+ * CU. and incase of non-shared cache check if the CU is inactive. If
+ * inactive active skip it
+ */
+ if (first_active_cu) {
+ memset(pcache, 0, sizeof(struct crat_subtype_cache));
+ pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY;
+ pcache->length = sizeof(struct crat_subtype_cache);
+ pcache->flags = pcache_info[cache_type].flags;
+ pcache->processor_id_low = cu_processor_id
+ + (first_active_cu - 1);
+ pcache->cache_level = pcache_info[cache_type].cache_level;
+ pcache->cache_size = pcache_info[cache_type].cache_size;
+
+ /* Sibling map is w.r.t processor_id_low, so shift out
+ * inactive CU
+ */
+ cu_sibling_map_mask =
+ cu_sibling_map_mask >> (first_active_cu - 1);
+
+ pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
+ pcache->sibling_map[1] =
+ (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
+ pcache->sibling_map[2] =
+ (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
+ pcache->sibling_map[3] =
+ (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
+ return 0;
+ }
+ return 1;
+}
+
+/* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info
+ * tables
+ *
+ * @kdev - [IN] GPU device
+ * @gpu_processor_id - [IN] GPU processor ID to which these caches
+ * associate
+ * @available_size - [IN] Amount of memory available in pcache
+ * @cu_info - [IN] Compute Unit info obtained from KGD
+ * @pcache - [OUT] memory into which cache data is to be filled in.
+ * @size_filled - [OUT] amount of data used up in pcache.
+ * @num_of_entries - [OUT] number of caches added
+ */
+static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ int gpu_processor_id,
+ int available_size,
+ struct kfd_cu_info *cu_info,
+ struct crat_subtype_cache *pcache,
+ int *size_filled,
+ int *num_of_entries)
+{
+ struct kfd_gpu_cache_info *pcache_info;
+ int num_of_cache_types = 0;
+ int i, j, k;
+ int ct = 0;
+ int mem_available = available_size;
+ unsigned int cu_processor_id;
+ int ret;
+
+ switch (kdev->device_info->asic_family) {
+ case CHIP_KAVERI:
+ pcache_info = kaveri_cache_info;
+ num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
+ break;
+ case CHIP_HAWAII:
+ pcache_info = hawaii_cache_info;
+ num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
+ break;
+ case CHIP_CARRIZO:
+ pcache_info = carrizo_cache_info;
+ num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);
+ break;
+ case CHIP_TONGA:
+ pcache_info = tonga_cache_info;
+ num_of_cache_types = ARRAY_SIZE(tonga_cache_info);
+ break;
+ case CHIP_FIJI:
+ pcache_info = fiji_cache_info;
+ num_of_cache_types = ARRAY_SIZE(fiji_cache_info);
+ break;
+ case CHIP_POLARIS10:
+ pcache_info = polaris10_cache_info;
+ num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);
+ break;
+ case CHIP_POLARIS11:
+ pcache_info = polaris11_cache_info;
+ num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *size_filled = 0;
+ *num_of_entries = 0;
+
+ /* For each type of cache listed in the kfd_gpu_cache_info table,
+ * go through all available Compute Units.
+ * The [i,j,k] loop will
+ * if kfd_gpu_cache_info.num_cu_shared = 1
+ * will parse through all available CU
+ * If (kfd_gpu_cache_info.num_cu_shared != 1)
+ * then it will consider only one CU from
+ * the shared unit
+ */
+
+ for (ct = 0; ct < num_of_cache_types; ct++) {
+ cu_processor_id = gpu_processor_id;
+ for (i = 0; i < cu_info->num_shader_engines; i++) {
+ for (j = 0; j < cu_info->num_shader_arrays_per_engine;
+ j++) {
+ for (k = 0; k < cu_info->num_cu_per_sh;
+ k += pcache_info[ct].num_cu_shared) {
+
+ ret = fill_in_pcache(pcache,
+ pcache_info,
+ cu_info,
+ mem_available,
+ cu_info->cu_bitmap[i][j],
+ ct,
+ cu_processor_id,
+ k);
+
+ if (ret < 0)
+ break;
+
+ if (!ret) {
+ pcache++;
+ (*num_of_entries)++;
+ mem_available -=
+ sizeof(*pcache);
+ (*size_filled) +=
+ sizeof(*pcache);
+ }
+
+ /* Move to next CU block */
+ cu_processor_id +=
+ pcache_info[ct].num_cu_shared;
+ }
+ }
+ }
+ }
+
+ pr_debug("Added [%d] GPU cache entries\n", *num_of_entries);
+
+ return 0;
+}
+
+/*
+ * kfd_create_crat_image_acpi - Allocates memory for CRAT image and
+ * copies CRAT from ACPI (if available).
+ * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
+ *
+ * @crat_image: CRAT read from ACPI. If no CRAT in ACPI then
+ * crat_image will be NULL
+ * @size: [OUT] size of crat_image
+ *
+ * Return 0 if successful else return error code
+ */
+int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
+{
+ struct acpi_table_header *crat_table;
+ acpi_status status;
+ void *pcrat_image;
+
+ if (!crat_image)
+ return -EINVAL;
+
+ *crat_image = NULL;
+
+ /* Fetch the CRAT table from ACPI */
+ status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
+ if (status == AE_NOT_FOUND) {
+ pr_warn("CRAT table not found\n");
+ return -ENODATA;
+ } else if (ACPI_FAILURE(status)) {
+ const char *err = acpi_format_exception(status);
+
+ pr_err("CRAT table error: %s\n", err);
+ return -EINVAL;
+ }
+
+ if (ignore_crat) {
+ pr_info("CRAT table disabled by module option\n");
+ return -ENODATA;
+ }
+
+ pcrat_image = kmalloc(crat_table->length, GFP_KERNEL);
+ if (!pcrat_image)
+ return -ENOMEM;
+
+ memcpy(pcrat_image, crat_table, crat_table->length);
+
+ *crat_image = pcrat_image;
+ *size = crat_table->length;
+
+ return 0;
+}
+
+/* Memory required to create Virtual CRAT.
+ * Since there is no easy way to predict the amount of memory required, the
+ * following amount are allocated for CPU and GPU Virtual CRAT. This is
+ * expected to cover all known conditions. But to be safe additional check
+ * is put in the code to ensure we don't overwrite.
+ */
+#define VCRAT_SIZE_FOR_CPU (2 * PAGE_SIZE)
+#define VCRAT_SIZE_FOR_GPU (3 * PAGE_SIZE)
+
+/* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
+ *
+ * @numa_node_id: CPU NUMA node id
+ * @avail_size: Available size in the memory
+ * @sub_type_hdr: Memory into which compute info will be filled in
+ *
+ * Return 0 if successful else return -ve value
+ */
+static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size,
+ int proximity_domain,
+ struct crat_subtype_computeunit *sub_type_hdr)
+{
+ const struct cpumask *cpumask;
+
+ *avail_size -= sizeof(struct crat_subtype_computeunit);
+ if (*avail_size < 0)
+ return -ENOMEM;
+
+ memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
+
+ /* Fill in subtype header data */
+ sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
+ sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
+ sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
+
+ cpumask = cpumask_of_node(numa_node_id);
+
+ /* Fill in CU data */
+ sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
+ sub_type_hdr->proximity_domain = proximity_domain;
+ sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id);
+ if (sub_type_hdr->processor_id_low == -1)
+ return -EINVAL;
+
+ sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask);
+
+ return 0;
+}
+
+/* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node
+ *
+ * @numa_node_id: CPU NUMA node id
+ * @avail_size: Available size in the memory
+ * @sub_type_hdr: Memory into which compute info will be filled in
+ *
+ * Return 0 if successful else return -ve value
+ */
+static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
+ int proximity_domain,
+ struct crat_subtype_memory *sub_type_hdr)
+{
+ uint64_t mem_in_bytes = 0;
+ pg_data_t *pgdat;
+ int zone_type;
+
+ *avail_size -= sizeof(struct crat_subtype_memory);
+ if (*avail_size < 0)
+ return -ENOMEM;
+
+ memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
+
+ /* Fill in subtype header data */
+ sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
+ sub_type_hdr->length = sizeof(struct crat_subtype_memory);
+ sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
+
+ /* Fill in Memory Subunit data */
+
+ /* Unlike si_meminfo, si_meminfo_node is not exported. So
+ * the following lines are duplicated from si_meminfo_node
+ * function
+ */
+ pgdat = NODE_DATA(numa_node_id);
+ for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
+ mem_in_bytes += pgdat->node_zones[zone_type].managed_pages;
+ mem_in_bytes <<= PAGE_SHIFT;
+
+ sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
+ sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
+ sub_type_hdr->proximity_domain = proximity_domain;
+
+ return 0;
+}
+
+static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
+ uint32_t *num_entries,
+ struct crat_subtype_iolink *sub_type_hdr)
+{
+ int nid;
+ struct cpuinfo_x86 *c = &cpu_data(0);
+ uint8_t link_type;
+
+ if (c->x86_vendor == X86_VENDOR_AMD)
+ link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT;
+ else
+ link_type = CRAT_IOLINK_TYPE_QPI_1_1;
+
+ *num_entries = 0;
+
+ /* Create IO links from this node to other CPU nodes */
+ for_each_online_node(nid) {
+ if (nid == numa_node_id) /* node itself */
+ continue;
+
+ *avail_size -= sizeof(struct crat_subtype_iolink);
+ if (*avail_size < 0)
+ return -ENOMEM;
+
+ memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
+
+ /* Fill in subtype header data */
+ sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
+ sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
+ sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
+
+ /* Fill in IO link data */
+ sub_type_hdr->proximity_domain_from = numa_node_id;
+ sub_type_hdr->proximity_domain_to = nid;
+ sub_type_hdr->io_interface_type = link_type;
+
+ (*num_entries)++;
+ sub_type_hdr++;
+ }
+
+ return 0;
+}
+
+/* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
+ *
+ * @pcrat_image: Fill in VCRAT for CPU
+ * @size: [IN] allocated size of crat_image.
+ * [OUT] actual size of data filled in crat_image
+ */
+static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
+{
+ struct crat_header *crat_table = (struct crat_header *)pcrat_image;
+ struct acpi_table_header *acpi_table;
+ acpi_status status;
+ struct crat_subtype_generic *sub_type_hdr;
+ int avail_size = *size;
+ int numa_node_id;
+ uint32_t entries = 0;
+ int ret = 0;
+
+ if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_CPU)
+ return -EINVAL;
+
+ /* Fill in CRAT Header.
+ * Modify length and total_entries as subunits are added.
+ */
+ avail_size -= sizeof(struct crat_header);
+ if (avail_size < 0)
+ return -ENOMEM;
+
+ memset(crat_table, 0, sizeof(struct crat_header));
+ memcpy(&crat_table->signature, CRAT_SIGNATURE,
+ sizeof(crat_table->signature));
+ crat_table->length = sizeof(struct crat_header);
+
+ status = acpi_get_table("DSDT", 0, &acpi_table);
+ if (status == AE_NOT_FOUND)
+ pr_warn("DSDT table not found for OEM information\n");
+ else {
+ crat_table->oem_revision = acpi_table->revision;
+ memcpy(crat_table->oem_id, acpi_table->oem_id,
+ CRAT_OEMID_LENGTH);
+ memcpy(crat_table->oem_table_id, acpi_table->oem_table_id,
+ CRAT_OEMTABLEID_LENGTH);
+ }
+ crat_table->total_entries = 0;
+ crat_table->num_domains = 0;
+
+ sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
+
+ for_each_online_node(numa_node_id) {
+ if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
+ continue;
+
+ /* Fill in Subtype: Compute Unit */
+ ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
+ crat_table->num_domains,
+ (struct crat_subtype_computeunit *)sub_type_hdr);
+ if (ret < 0)
+ return ret;
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ sub_type_hdr->length);
+
+ /* Fill in Subtype: Memory */
+ ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size,
+ crat_table->num_domains,
+ (struct crat_subtype_memory *)sub_type_hdr);
+ if (ret < 0)
+ return ret;
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ sub_type_hdr->length);
+
+ /* Fill in Subtype: IO Link */
+ ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
+ &entries,
+ (struct crat_subtype_iolink *)sub_type_hdr);
+ if (ret < 0)
+ return ret;
+ crat_table->length += (sub_type_hdr->length * entries);
+ crat_table->total_entries += entries;
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ sub_type_hdr->length * entries);
+
+ crat_table->num_domains++;
+ }
+
+ /* TODO: Add cache Subtype for CPU.
+ * Currently, CPU cache information is available in function
+ * detect_cache_attributes(cpu) defined in the file
+ * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not
+ * exported and to get the same information the code needs to be
+ * duplicated.
+ */
+
+ *size = crat_table->length;
+ pr_info("Virtual CRAT table created for CPU\n");
+
+ return 0;
+}
+
+static int kfd_fill_gpu_memory_affinity(int *avail_size,
+ struct kfd_dev *kdev, uint8_t type, uint64_t size,
+ struct crat_subtype_memory *sub_type_hdr,
+ uint32_t proximity_domain,
+ const struct kfd_local_mem_info *local_mem_info)
+{
+ *avail_size -= sizeof(struct crat_subtype_memory);
+ if (*avail_size < 0)
+ return -ENOMEM;
+
+ memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
+ sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
+ sub_type_hdr->length = sizeof(struct crat_subtype_memory);
+ sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
+
+ sub_type_hdr->proximity_domain = proximity_domain;
+
+ pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n",
+ type, size);
+
+ sub_type_hdr->length_low = lower_32_bits(size);
+ sub_type_hdr->length_high = upper_32_bits(size);
+
+ sub_type_hdr->width = local_mem_info->vram_width;
+ sub_type_hdr->visibility_type = type;
+
+ return 0;
+}
+
+/* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
+ * to its NUMA node
+ * @avail_size: Available size in the memory
+ * @kdev - [IN] GPU device
+ * @sub_type_hdr: Memory into which io link info will be filled in
+ * @proximity_domain - proximity domain of the GPU node
+ *
+ * Return 0 if successful else return -ve value
+ */
+static int kfd_fill_gpu_direct_io_link(int *avail_size,
+ struct kfd_dev *kdev,
+ struct crat_subtype_iolink *sub_type_hdr,
+ uint32_t proximity_domain)
+{
+ *avail_size -= sizeof(struct crat_subtype_iolink);
+ if (*avail_size < 0)
+ return -ENOMEM;
+
+ memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
+
+ /* Fill in subtype header data */
+ sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
+ sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
+ sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
+
+ /* Fill in IOLINK subtype.
+ * TODO: Fill-in other fields of iolink subtype
+ */
+ sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
+ sub_type_hdr->proximity_domain_from = proximity_domain;
+#ifdef CONFIG_NUMA
+ if (kdev->pdev->dev.numa_node == NUMA_NO_NODE)
+ sub_type_hdr->proximity_domain_to = 0;
+ else
+ sub_type_hdr->proximity_domain_to = kdev->pdev->dev.numa_node;
+#else
+ sub_type_hdr->proximity_domain_to = 0;
+#endif
+ return 0;
+}
+
+/* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU
+ *
+ * @pcrat_image: Fill in VCRAT for GPU
+ * @size: [IN] allocated size of crat_image.
+ * [OUT] actual size of data filled in crat_image
+ */
+static int kfd_create_vcrat_image_gpu(void *pcrat_image,
+ size_t *size, struct kfd_dev *kdev,
+ uint32_t proximity_domain)
+{
+ struct crat_header *crat_table = (struct crat_header *)pcrat_image;
+ struct crat_subtype_generic *sub_type_hdr;
+ struct crat_subtype_computeunit *cu;
+ struct kfd_cu_info cu_info;
+ struct amd_iommu_device_info iommu_info;
+ int avail_size = *size;
+ uint32_t total_num_of_cu;
+ int num_of_cache_entries = 0;
+ int cache_mem_filled = 0;
+ int ret = 0;
+ const u32 required_iommu_flags = AMD_IOMMU_DEVICE_FLAG_ATS_SUP |
+ AMD_IOMMU_DEVICE_FLAG_PRI_SUP |
+ AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
+ struct kfd_local_mem_info local_mem_info;
+
+ if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
+ return -EINVAL;
+
+ /* Fill the CRAT Header.
+ * Modify length and total_entries as subunits are added.
+ */
+ avail_size -= sizeof(struct crat_header);
+ if (avail_size < 0)
+ return -ENOMEM;
+
+ memset(crat_table, 0, sizeof(struct crat_header));
+
+ memcpy(&crat_table->signature, CRAT_SIGNATURE,
+ sizeof(crat_table->signature));
+ /* Change length as we add more subtypes*/
+ crat_table->length = sizeof(struct crat_header);
+ crat_table->num_domains = 1;
+ crat_table->total_entries = 0;
+
+ /* Fill in Subtype: Compute Unit
+ * First fill in the sub type header and then sub type data
+ */
+ avail_size -= sizeof(struct crat_subtype_computeunit);
+ if (avail_size < 0)
+ return -ENOMEM;
+
+ sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
+ memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
+
+ sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
+ sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
+ sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
+
+ /* Fill CU subtype data */
+ cu = (struct crat_subtype_computeunit *)sub_type_hdr;
+ cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
+ cu->proximity_domain = proximity_domain;
+
+ kdev->kfd2kgd->get_cu_info(kdev->kgd, &cu_info);
+ cu->num_simd_per_cu = cu_info.simd_per_cu;
+ cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number;
+ cu->max_waves_simd = cu_info.max_waves_per_simd;
+
+ cu->wave_front_size = cu_info.wave_front_size;
+ cu->array_count = cu_info.num_shader_arrays_per_engine *
+ cu_info.num_shader_engines;
+ total_num_of_cu = (cu->array_count * cu_info.num_cu_per_sh);
+ cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu);
+ cu->num_cu_per_array = cu_info.num_cu_per_sh;
+ cu->max_slots_scatch_cu = cu_info.max_scratch_slots_per_cu;
+ cu->num_banks = cu_info.num_shader_engines;
+ cu->lds_size_in_kb = cu_info.lds_size;
+
+ cu->hsa_capability = 0;
+
+ /* Check if this node supports IOMMU. During parsing this flag will
+ * translate to HSA_CAP_ATS_PRESENT
+ */
+ iommu_info.flags = 0;
+ if (amd_iommu_device_info(kdev->pdev, &iommu_info) == 0) {
+ if ((iommu_info.flags & required_iommu_flags) ==
+ required_iommu_flags)
+ cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT;
+ }
+
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
+
+ /* Fill in Subtype: Memory. Only on systems with large BAR (no
+ * private FB), report memory as public. On other systems
+ * report the total FB size (public+private) as a single
+ * private heap.
+ */
+ kdev->kfd2kgd->get_local_mem_info(kdev->kgd, &local_mem_info);
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ sub_type_hdr->length);
+
+ if (local_mem_info.local_mem_size_private == 0)
+ ret = kfd_fill_gpu_memory_affinity(&avail_size,
+ kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
+ local_mem_info.local_mem_size_public,
+ (struct crat_subtype_memory *)sub_type_hdr,
+ proximity_domain,
+ &local_mem_info);
+ else
+ ret = kfd_fill_gpu_memory_affinity(&avail_size,
+ kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE,
+ local_mem_info.local_mem_size_public +
+ local_mem_info.local_mem_size_private,
+ (struct crat_subtype_memory *)sub_type_hdr,
+ proximity_domain,
+ &local_mem_info);
+ if (ret < 0)
+ return ret;
+
+ crat_table->length += sizeof(struct crat_subtype_memory);
+ crat_table->total_entries++;
+
+ /* TODO: Fill in cache information. This information is NOT readily
+ * available in KGD
+ */
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ sub_type_hdr->length);
+ ret = kfd_fill_gpu_cache_info(kdev, cu->processor_id_low,
+ avail_size,
+ &cu_info,
+ (struct crat_subtype_cache *)sub_type_hdr,
+ &cache_mem_filled,
+ &num_of_cache_entries);
+
+ if (ret < 0)
+ return ret;
+
+ crat_table->length += cache_mem_filled;
+ crat_table->total_entries += num_of_cache_entries;
+ avail_size -= cache_mem_filled;
+
+ /* Fill in Subtype: IO_LINKS
+ * Only direct links are added here which is Link from GPU to
+ * to its NUMA node. Indirect links are added by userspace.
+ */
+ sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+ cache_mem_filled);
+ ret = kfd_fill_gpu_direct_io_link(&avail_size, kdev,
+ (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain);
+
+ if (ret < 0)
+ return ret;
+
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
+
+ *size = crat_table->length;
+ pr_info("Virtual CRAT table created for GPU\n");
+
+ return ret;
+}
+
+/* kfd_create_crat_image_virtual - Allocates memory for CRAT image and
+ * creates a Virtual CRAT (VCRAT) image
+ *
+ * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
+ *
+ * @crat_image: VCRAT image created because ACPI does not have a
+ * CRAT for this device
+ * @size: [OUT] size of virtual crat_image
+ * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device
+ * COMPUTE_UNIT_GPU - Create VCRAT for GPU
+ * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU
+ * -- this option is not currently implemented.
+ * The assumption is that all AMD APUs will have CRAT
+ * @kdev: Valid kfd_device required if flags contain COMPUTE_UNIT_GPU
+ *
+ * Return 0 if successful else return -ve value
+ */
+int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
+ int flags, struct kfd_dev *kdev,
+ uint32_t proximity_domain)
+{
+ void *pcrat_image = NULL;
+ int ret = 0;
+
+ if (!crat_image)
+ return -EINVAL;
+
+ *crat_image = NULL;
+
+ /* Allocate one VCRAT_SIZE_FOR_CPU for CPU virtual CRAT image and
+ * VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image. This should cover
+ * all the current conditions. A check is put not to overwrite beyond
+ * allocated size
+ */
+ switch (flags) {
+ case COMPUTE_UNIT_CPU:
+ pcrat_image = kmalloc(VCRAT_SIZE_FOR_CPU, GFP_KERNEL);
+ if (!pcrat_image)
+ return -ENOMEM;
+ *size = VCRAT_SIZE_FOR_CPU;
+ ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
+ break;
+ case COMPUTE_UNIT_GPU:
+ if (!kdev)
+ return -EINVAL;
+ pcrat_image = kmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL);
+ if (!pcrat_image)
+ return -ENOMEM;
+ *size = VCRAT_SIZE_FOR_GPU;
+ ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev,
+ proximity_domain);
+ break;
+ case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU):
+ /* TODO: */
+ ret = -EINVAL;
+ pr_err("VCRAT not implemented for APU\n");
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ if (!ret)
+ *crat_image = pcrat_image;
+ else
+ kfree(pcrat_image);
+
+ return ret;
+}
+
+
+/* kfd_destroy_crat_image
+ *
+ * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..)
+ *
+ */
+void kfd_destroy_crat_image(void *crat_image)
+{
+ kfree(crat_image);
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h
index a374fa3..b5cd182 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h
@@ -44,6 +44,10 @@
#define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
+/* Compute Unit flags */
+#define COMPUTE_UNIT_CPU (1 << 0) /* Create Virtual CRAT for CPU */
+#define COMPUTE_UNIT_GPU (1 << 1) /* Create Virtual CRAT for GPU */
+
struct crat_header {
uint32_t signature;
uint32_t length;
@@ -105,7 +109,7 @@
uint8_t wave_front_size;
uint8_t num_banks;
uint16_t micro_engine_id;
- uint8_t num_arrays;
+ uint8_t array_count;
uint8_t num_cu_per_array;
uint8_t num_simd_per_cu;
uint8_t max_slots_scatch_cu;
@@ -127,13 +131,14 @@
uint8_t length;
uint16_t reserved;
uint32_t flags;
- uint32_t promixity_domain;
+ uint32_t proximity_domain;
uint32_t base_addr_low;
uint32_t base_addr_high;
uint32_t length_low;
uint32_t length_high;
uint32_t width;
- uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH];
+ uint8_t visibility_type; /* for virtual (dGPU) CRAT */
+ uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
};
/*
@@ -222,9 +227,12 @@
/*
* HSA IO Link Affinity structure and definitions
*/
-#define CRAT_IOLINK_FLAGS_ENABLED 0x00000001
-#define CRAT_IOLINK_FLAGS_COHERENCY 0x00000002
-#define CRAT_IOLINK_FLAGS_RESERVED 0xfffffffc
+#define CRAT_IOLINK_FLAGS_ENABLED (1 << 0)
+#define CRAT_IOLINK_FLAGS_NON_COHERENT (1 << 1)
+#define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2)
+#define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3)
+#define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4)
+#define CRAT_IOLINK_FLAGS_RESERVED_MASK 0xffffffe0
/*
* IO interface types
@@ -232,10 +240,18 @@
#define CRAT_IOLINK_TYPE_UNDEFINED 0
#define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1
#define CRAT_IOLINK_TYPE_PCIEXPRESS 2
-#define CRAT_IOLINK_TYPE_OTHER 3
+#define CRAT_IOLINK_TYPE_AMBA 3
+#define CRAT_IOLINK_TYPE_MIPI 4
+#define CRAT_IOLINK_TYPE_QPI_1_1 5
+#define CRAT_IOLINK_TYPE_RESERVED1 6
+#define CRAT_IOLINK_TYPE_RESERVED2 7
+#define CRAT_IOLINK_TYPE_RAPID_IO 8
+#define CRAT_IOLINK_TYPE_INFINIBAND 9
+#define CRAT_IOLINK_TYPE_RESERVED3 10
+#define CRAT_IOLINK_TYPE_OTHER 11
#define CRAT_IOLINK_TYPE_MAX 255
-#define CRAT_IOLINK_RESERVED_LENGTH 24
+#define CRAT_IOLINK_RESERVED_LENGTH 24
struct crat_subtype_iolink {
uint8_t type;
@@ -291,4 +307,14 @@
#pragma pack()
+struct kfd_dev;
+
+int kfd_create_crat_image_acpi(void **crat_image, size_t *size);
+void kfd_destroy_crat_image(void *crat_image);
+int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
+ uint32_t proximity_domain);
+int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
+ int flags, struct kfd_dev *kdev,
+ uint32_t proximity_domain);
+
#endif /* KFD_CRAT_H_INCLUDED */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
index c407f6b..afb26f2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
@@ -95,7 +95,7 @@
ib_packet->bitfields3.ib_base_hi = largep->u.high_part;
ib_packet->control = (1 << 23) | (1 << 31) |
- ((size_in_bytes / sizeof(uint32_t)) & 0xfffff);
+ ((size_in_bytes / 4) & 0xfffff);
ib_packet->bitfields5.pasid = pasid;
@@ -126,8 +126,7 @@
rm_packet->header.opcode = IT_RELEASE_MEM;
rm_packet->header.type = PM4_TYPE_3;
- rm_packet->header.count = sizeof(struct pm4__release_mem) /
- sizeof(unsigned int) - 2;
+ rm_packet->header.count = sizeof(struct pm4__release_mem) / 4 - 2;
rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
rm_packet->bitfields2.event_index =
@@ -652,8 +651,7 @@
packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;
packets_vec[0].header.type = PM4_TYPE_3;
packets_vec[0].bitfields2.reg_offset =
- GRBM_GFX_INDEX / (sizeof(uint32_t)) -
- USERCONFIG_REG_BASE;
+ GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
packets_vec[0].bitfields2.insert_vmid = 0;
packets_vec[0].reg_data[0] = reg_gfx_index.u32All;
@@ -661,8 +659,7 @@
packets_vec[1].header.count = 1;
packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
packets_vec[1].header.type = PM4_TYPE_3;
- packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
- AMD_CONFIG_REG_BASE;
+ packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE;
packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
packets_vec[1].bitfields2.insert_vmid = 1;
@@ -678,8 +675,7 @@
packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
packets_vec[2].bitfields2.reg_offset =
- GRBM_GFX_INDEX / (sizeof(uint32_t)) -
- USERCONFIG_REG_BASE;
+ GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
packets_vec[2].bitfields2.insert_vmid = 0;
packets_vec[2].reg_data[0] = reg_gfx_index.u32All;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
new file mode 100644
index 0000000..4bd6ebf
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2016-2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include "kfd_priv.h"
+
+static struct dentry *debugfs_root;
+
+static int kfd_debugfs_open(struct inode *inode, struct file *file)
+{
+ int (*show)(struct seq_file *, void *) = inode->i_private;
+
+ return single_open(file, show, NULL);
+}
+
+static const struct file_operations kfd_debugfs_fops = {
+ .owner = THIS_MODULE,
+ .open = kfd_debugfs_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+void kfd_debugfs_init(void)
+{
+ struct dentry *ent;
+
+ debugfs_root = debugfs_create_dir("kfd", NULL);
+ if (!debugfs_root || debugfs_root == ERR_PTR(-ENODEV)) {
+ pr_warn("Failed to create kfd debugfs dir\n");
+ return;
+ }
+
+ ent = debugfs_create_file("mqds", S_IFREG | 0444, debugfs_root,
+ kfd_debugfs_mqds_by_process,
+ &kfd_debugfs_fops);
+ if (!ent)
+ pr_warn("Failed to create mqds in kfd debugfs\n");
+
+ ent = debugfs_create_file("hqds", S_IFREG | 0444, debugfs_root,
+ kfd_debugfs_hqds_by_device,
+ &kfd_debugfs_fops);
+ if (!ent)
+ pr_warn("Failed to create hqds in kfd debugfs\n");
+
+ ent = debugfs_create_file("rls", S_IFREG | 0444, debugfs_root,
+ kfd_debugfs_rls_by_device,
+ &kfd_debugfs_fops);
+ if (!ent)
+ pr_warn("Failed to create rls in kfd debugfs\n");
+}
+
+void kfd_debugfs_fini(void)
+{
+ debugfs_remove_recursive(debugfs_root);
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 621a3b5..a8fa33a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -27,6 +27,7 @@
#include "kfd_priv.h"
#include "kfd_device_queue_manager.h"
#include "kfd_pm4_headers_vi.h"
+#include "cwsr_trap_handler_gfx8.asm"
#define MQD_SIZE_ALIGNED 768
@@ -38,7 +39,8 @@
.ih_ring_entry_size = 4 * sizeof(uint32_t),
.event_interrupt_class = &event_interrupt_class_cik,
.num_of_watch_points = 4,
- .mqd_size_aligned = MQD_SIZE_ALIGNED
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .supports_cwsr = false,
};
static const struct kfd_device_info carrizo_device_info = {
@@ -49,7 +51,8 @@
.ih_ring_entry_size = 4 * sizeof(uint32_t),
.event_interrupt_class = &event_interrupt_class_cik,
.num_of_watch_points = 4,
- .mqd_size_aligned = MQD_SIZE_ALIGNED
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .supports_cwsr = true,
};
struct kfd_deviceid {
@@ -212,6 +215,17 @@
return AMD_IOMMU_INV_PRI_RSP_INVALID;
}
+static void kfd_cwsr_init(struct kfd_dev *kfd)
+{
+ if (cwsr_enable && kfd->device_info->supports_cwsr) {
+ BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
+
+ kfd->cwsr_isa = cwsr_trap_gfx8_hex;
+ kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
+ kfd->cwsr_enabled = true;
+ }
+}
+
bool kgd2kfd_device_init(struct kfd_dev *kfd,
const struct kgd2kfd_shared_resources *gpu_resources)
{
@@ -224,6 +238,17 @@
kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
- kfd->vm_info.first_vmid_kfd + 1;
+ /* Verify module parameters regarding mapped process number*/
+ if ((hws_max_conc_proc < 0)
+ || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
+ dev_err(kfd_device,
+ "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
+ hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
+ kfd->vm_info.vmid_num_kfd);
+ kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
+ } else
+ kfd->max_proc_per_quantum = hws_max_conc_proc;
+
/* calculate max size of mqds needed for queues */
size = max_num_of_queues_per_device *
kfd->device_info->mqd_size_aligned;
@@ -286,6 +311,8 @@
goto device_iommu_pasid_error;
}
+ kfd_cwsr_init(kfd);
+
if (kfd_resume(kfd))
goto kfd_resume_error;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index e202921..1bd5f26 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -149,8 +149,7 @@
static int create_queue_nocpsch(struct device_queue_manager *dqm,
struct queue *q,
- struct qcm_process_device *qpd,
- int *allocated_vmid)
+ struct qcm_process_device *qpd)
{
int retval;
@@ -170,9 +169,11 @@
if (retval)
goto out_unlock;
}
- *allocated_vmid = qpd->vmid;
q->properties.vmid = qpd->vmid;
+ q->properties.tba_addr = qpd->tba_addr;
+ q->properties.tma_addr = qpd->tma_addr;
+
if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
retval = create_compute_queue_nocpsch(dqm, q, qpd);
else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
@@ -181,10 +182,8 @@
retval = -EINVAL;
if (retval) {
- if (list_empty(&qpd->queues_list)) {
+ if (list_empty(&qpd->queues_list))
deallocate_vmid(dqm, qpd, q);
- *allocated_vmid = 0;
- }
goto out_unlock;
}
@@ -809,29 +808,26 @@
}
static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
- struct qcm_process_device *qpd, int *allocate_vmid)
+ struct qcm_process_device *qpd)
{
int retval;
struct mqd_manager *mqd;
retval = 0;
- if (allocate_vmid)
- *allocate_vmid = 0;
-
mutex_lock(&dqm->lock);
if (dqm->total_queue_count >= max_num_of_queues_per_device) {
pr_warn("Can't create new usermode queue because %d queues were already created\n",
dqm->total_queue_count);
retval = -EPERM;
- goto out;
+ goto out_unlock;
}
if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
retval = allocate_sdma_queue(dqm, &q->sdma_id);
if (retval)
- goto out;
+ goto out_unlock;
q->properties.sdma_queue_id =
q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
q->properties.sdma_engine_id =
@@ -842,14 +838,17 @@
if (!mqd) {
retval = -ENOMEM;
- goto out;
+ goto out_deallocate_sdma_queue;
}
dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
+
+ q->properties.tba_addr = qpd->tba_addr;
+ q->properties.tma_addr = qpd->tma_addr;
retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
&q->gart_mqd_addr, &q->properties);
if (retval)
- goto out;
+ goto out_deallocate_sdma_queue;
list_add(&q->list, &qpd->queues_list);
qpd->queue_count++;
@@ -870,7 +869,13 @@
pr_debug("Total of %d queues are accountable so far\n",
dqm->total_queue_count);
-out:
+ mutex_unlock(&dqm->lock);
+ return retval;
+
+out_deallocate_sdma_queue:
+ if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
+ deallocate_sdma_queue(dqm, q->sdma_id);
+out_unlock:
mutex_unlock(&dqm->lock);
return retval;
}
@@ -1014,13 +1019,13 @@
list_del(&q->list);
qpd->queue_count--;
- if (q->properties.is_active)
+ if (q->properties.is_active) {
dqm->queue_count--;
-
- retval = execute_queues_cpsch(dqm,
+ retval = execute_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
- if (retval == -ETIME)
- qpd->reset_wavefronts = true;
+ if (retval == -ETIME)
+ qpd->reset_wavefronts = true;
+ }
mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
@@ -1034,7 +1039,7 @@
mutex_unlock(&dqm->lock);
- return 0;
+ return retval;
failed:
failed_try_destroy_debugged_queue:
@@ -1110,6 +1115,26 @@
return retval;
}
+static int set_trap_handler(struct device_queue_manager *dqm,
+ struct qcm_process_device *qpd,
+ uint64_t tba_addr,
+ uint64_t tma_addr)
+{
+ uint64_t *tma;
+
+ if (dqm->dev->cwsr_enabled) {
+ /* Jump from CWSR trap handler to user trap */
+ tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
+ tma[0] = tba_addr;
+ tma[1] = tma_addr;
+ } else {
+ qpd->tba_addr = tba_addr;
+ qpd->tma_addr = tma_addr;
+ }
+
+ return 0;
+}
+
static int process_termination_nocpsch(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
@@ -1169,8 +1194,10 @@
/* Clear all user mode queues */
list_for_each_entry(q, &qpd->queues_list, list) {
- if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
+ if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
dqm->sdma_queue_count--;
+ deallocate_sdma_queue(dqm, q->sdma_id);
+ }
if (q->properties.is_active)
dqm->queue_count--;
@@ -1241,6 +1268,7 @@
dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
+ dqm->ops.set_trap_handler = set_trap_handler;
dqm->ops.process_termination = process_termination_cpsch;
break;
case KFD_SCHED_POLICY_NO_HWS:
@@ -1256,6 +1284,7 @@
dqm->ops.initialize = initialize_nocpsch;
dqm->ops.uninitialize = uninitialize;
dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
+ dqm->ops.set_trap_handler = set_trap_handler;
dqm->ops.process_termination = process_termination_nocpsch;
break;
default:
@@ -1290,3 +1319,74 @@
dqm->ops.uninitialize(dqm);
kfree(dqm);
}
+
+#if defined(CONFIG_DEBUG_FS)
+
+static void seq_reg_dump(struct seq_file *m,
+ uint32_t (*dump)[2], uint32_t n_regs)
+{
+ uint32_t i, count;
+
+ for (i = 0, count = 0; i < n_regs; i++) {
+ if (count == 0 ||
+ dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
+ seq_printf(m, "%s %08x: %08x",
+ i ? "\n" : "",
+ dump[i][0], dump[i][1]);
+ count = 7;
+ } else {
+ seq_printf(m, " %08x", dump[i][1]);
+ count--;
+ }
+ }
+
+ seq_puts(m, "\n");
+}
+
+int dqm_debugfs_hqds(struct seq_file *m, void *data)
+{
+ struct device_queue_manager *dqm = data;
+ uint32_t (*dump)[2], n_regs;
+ int pipe, queue;
+ int r = 0;
+
+ for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
+ int pipe_offset = pipe * get_queues_per_pipe(dqm);
+
+ for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
+ if (!test_bit(pipe_offset + queue,
+ dqm->dev->shared_resources.queue_bitmap))
+ continue;
+
+ r = dqm->dev->kfd2kgd->hqd_dump(
+ dqm->dev->kgd, pipe, queue, &dump, &n_regs);
+ if (r)
+ break;
+
+ seq_printf(m, " CP Pipe %d, Queue %d\n",
+ pipe, queue);
+ seq_reg_dump(m, dump, n_regs);
+
+ kfree(dump);
+ }
+ }
+
+ for (pipe = 0; pipe < CIK_SDMA_ENGINE_NUM; pipe++) {
+ for (queue = 0; queue < CIK_SDMA_QUEUES_PER_ENGINE; queue++) {
+ r = dqm->dev->kfd2kgd->hqd_sdma_dump(
+ dqm->dev->kgd, pipe, queue, &dump, &n_regs);
+ if (r)
+ break;
+
+ seq_printf(m, " SDMA Engine %d, RLC %d\n",
+ pipe, queue);
+ seq_reg_dump(m, dump, n_regs);
+
+ kfree(dump);
+ }
+ }
+
+ return r;
+}
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index 5b77cb69..c61b693b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -84,8 +84,7 @@
struct device_queue_manager_ops {
int (*create_queue)(struct device_queue_manager *dqm,
struct queue *q,
- struct qcm_process_device *qpd,
- int *allocate_vmid);
+ struct qcm_process_device *qpd);
int (*destroy_queue)(struct device_queue_manager *dqm,
struct qcm_process_device *qpd,
@@ -123,6 +122,11 @@
void __user *alternate_aperture_base,
uint64_t alternate_aperture_size);
+ int (*set_trap_handler)(struct device_queue_manager *dqm,
+ struct qcm_process_device *qpd,
+ uint64_t tba_addr,
+ uint64_t tma_addr);
+
int (*process_termination)(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
};
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
index feb76c235..ebb4da14 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
@@ -116,8 +116,7 @@
pr_debug("doorbell aperture size == 0x%08lX\n",
kfd->shared_resources.doorbell_aperture_size);
- pr_debug("doorbell kernel address == 0x%08lX\n",
- (uintptr_t)kfd->doorbell_kernel_ptr);
+ pr_debug("doorbell kernel address == %p\n", kfd->doorbell_kernel_ptr);
return 0;
}
@@ -194,8 +193,8 @@
pr_debug("Get kernel queue doorbell\n"
" doorbell offset == 0x%08X\n"
- " kernel address == 0x%08lX\n",
- *doorbell_off, (uintptr_t)(kfd->doorbell_kernel_ptr + inx));
+ " kernel address == %p\n",
+ *doorbell_off, (kfd->doorbell_kernel_ptr + inx));
return kfd->doorbell_kernel_ptr + inx;
}
@@ -215,7 +214,7 @@
{
if (db) {
writel(value, db);
- pr_debug("Writing %d to doorbell address 0x%p\n", value, db);
+ pr_debug("Writing %d to doorbell address %p\n", value, db);
}
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index cb92d4b..93aae5c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -441,7 +441,7 @@
/*
* Because we are called from arbitrary context (workqueue) as opposed
* to process context, kfd_process could attempt to exit while we are
- * running so the lookup function returns a locked process.
+ * running so the lookup function increments the process ref count.
*/
struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
@@ -493,7 +493,7 @@
}
mutex_unlock(&p->event_mutex);
- mutex_unlock(&p->mutex);
+ kfd_unref_process(p);
}
static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events)
@@ -847,7 +847,7 @@
/*
* Because we are called from arbitrary context (workqueue) as opposed
* to process context, kfd_process could attempt to exit while we are
- * running so the lookup function returns a locked process.
+ * running so the lookup function increments the process ref count.
*/
struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
struct mm_struct *mm;
@@ -860,7 +860,7 @@
*/
mm = get_task_mm(p->lead_thread);
if (!mm) {
- mutex_unlock(&p->mutex);
+ kfd_unref_process(p);
return; /* Process is exiting */
}
@@ -903,7 +903,7 @@
&memory_exception_data);
mutex_unlock(&p->event_mutex);
- mutex_unlock(&p->mutex);
+ kfd_unref_process(p);
}
void kfd_signal_hw_exception_event(unsigned int pasid)
@@ -911,7 +911,7 @@
/*
* Because we are called from arbitrary context (workqueue) as opposed
* to process context, kfd_process could attempt to exit while we are
- * running so the lookup function returns a locked process.
+ * running so the lookup function increments the process ref count.
*/
struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
@@ -924,5 +924,5 @@
lookup_events_by_type_and_signal(p, KFD_EVENT_TYPE_HW_EXCEPTION, NULL);
mutex_unlock(&p->event_mutex);
- mutex_unlock(&p->mutex);
+ kfd_unref_process(p);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index c59384b..7377513 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -300,9 +300,14 @@
struct kfd_process_device *pdd;
/*Iterating over all devices*/
- while ((dev = kfd_topology_enum_kfd_devices(id)) != NULL &&
+ while (kfd_topology_enum_kfd_devices(id, &dev) == 0 &&
id < NUM_OF_SUPPORTED_GPUS) {
+ if (!dev) {
+ id++; /* Skip non GPU devices */
+ continue;
+ }
+
pdd = kfd_create_process_device_data(dev, process);
if (!pdd) {
pr_err("Failed to create process device data\n");
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 8b0c064..5dc6567 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -218,7 +218,7 @@
rptr = *kq->rptr_kernel;
wptr = *kq->wptr_kernel;
queue_address = (unsigned int *)kq->pq_kernel_addr;
- queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t);
+ queue_size_dwords = kq->queue->properties.queue_size / 4;
pr_debug("rptr: %d\n", rptr);
pr_debug("wptr: %d\n", wptr);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index f744cae..3ac72be 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -50,6 +50,15 @@
MODULE_PARM_DESC(sched_policy,
"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
+int hws_max_conc_proc = 8;
+module_param(hws_max_conc_proc, int, 0444);
+MODULE_PARM_DESC(hws_max_conc_proc,
+ "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
+
+int cwsr_enable = 1;
+module_param(cwsr_enable, int, 0444);
+MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
+
int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
module_param(max_num_of_queues_per_device, int, 0444);
MODULE_PARM_DESC(max_num_of_queues_per_device,
@@ -60,6 +69,11 @@
MODULE_PARM_DESC(send_sigterm,
"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
+int ignore_crat;
+module_param(ignore_crat, int, 0444);
+MODULE_PARM_DESC(ignore_crat,
+ "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
+
static int amdkfd_init_completed;
int kgd2kfd_init(unsigned int interface_version,
@@ -114,6 +128,8 @@
kfd_process_create_wq();
+ kfd_debugfs_init();
+
amdkfd_init_completed = 1;
dev_info(kfd_device, "Initialized module\n");
@@ -130,6 +146,7 @@
{
amdkfd_init_completed = 0;
+ kfd_debugfs_fini();
kfd_process_destroy_wq();
kfd_topology_shutdown();
kfd_chardev_exit();
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
index 1f3a6ba..8972bcf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
@@ -85,6 +85,10 @@
uint64_t queue_address, uint32_t pipe_id,
uint32_t queue_id);
+#if defined(CONFIG_DEBUG_FS)
+ int (*debugfs_show_mqd)(struct seq_file *m, void *data);
+#endif
+
struct mutex mqd_mutex;
struct kfd_dev *dev;
};
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 4728fad..f8ef4a0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -36,6 +36,11 @@
return (struct cik_mqd *)mqd;
}
+static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
+{
+ return (struct cik_sdma_rlc_registers *)mqd;
+}
+
static int init_mqd(struct mqd_manager *mm, void **mqd,
struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
struct queue_properties *q)
@@ -149,7 +154,7 @@
{
/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
- uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1);
+ uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
(uint32_t __user *)p->write_ptr,
@@ -160,7 +165,9 @@
uint32_t pipe_id, uint32_t queue_id,
struct queue_properties *p, struct mm_struct *mms)
{
- return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd);
+ return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
+ (uint32_t __user *)p->write_ptr,
+ mms);
}
static int update_mqd(struct mqd_manager *mm, void *mqd,
@@ -176,8 +183,7 @@
* Calculating queue size which is log base 2 of actual queue size -1
* dwords and another -1 for ffs
*/
- m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
- - 1 - 1;
+ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
@@ -202,7 +208,7 @@
struct cik_sdma_rlc_registers *m;
m = get_sdma_mqd(mqd);
- m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+ m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
@@ -343,8 +349,7 @@
* Calculating queue size which is log base 2 of actual queue
* size -1 dwords
*/
- m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
- - 1 - 1;
+ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
@@ -360,15 +365,25 @@
return 0;
}
-struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
+#if defined(CONFIG_DEBUG_FS)
+
+static int debugfs_show_mqd(struct seq_file *m, void *data)
{
- struct cik_sdma_rlc_registers *m;
-
- m = (struct cik_sdma_rlc_registers *)mqd;
-
- return m;
+ seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
+ data, sizeof(struct cik_mqd), false);
+ return 0;
}
+static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
+{
+ seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
+ data, sizeof(struct cik_sdma_rlc_registers), false);
+ return 0;
+}
+
+#endif
+
+
struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
struct kfd_dev *dev)
{
@@ -392,6 +407,9 @@
mqd->update_mqd = update_mqd;
mqd->destroy_mqd = destroy_mqd;
mqd->is_occupied = is_occupied;
+#if defined(CONFIG_DEBUG_FS)
+ mqd->debugfs_show_mqd = debugfs_show_mqd;
+#endif
break;
case KFD_MQD_TYPE_HIQ:
mqd->init_mqd = init_mqd_hiq;
@@ -400,6 +418,9 @@
mqd->update_mqd = update_mqd_hiq;
mqd->destroy_mqd = destroy_mqd;
mqd->is_occupied = is_occupied;
+#if defined(CONFIG_DEBUG_FS)
+ mqd->debugfs_show_mqd = debugfs_show_mqd;
+#endif
break;
case KFD_MQD_TYPE_SDMA:
mqd->init_mqd = init_mqd_sdma;
@@ -408,6 +429,9 @@
mqd->update_mqd = update_mqd_sdma;
mqd->destroy_mqd = destroy_mqd_sdma;
mqd->is_occupied = is_occupied_sdma;
+#if defined(CONFIG_DEBUG_FS)
+ mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
+#endif
break;
default:
kfree(mqd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index 4ea854f..971aec0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -30,7 +30,7 @@
#include "vi_structs.h"
#include "gca/gfx_8_0_sh_mask.h"
#include "gca/gfx_8_0_enum.h"
-
+#include "oss/oss_3_0_sh_mask.h"
#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
static inline struct vi_mqd *get_mqd(void *mqd)
@@ -38,6 +38,11 @@
return (struct vi_mqd *)mqd;
}
+static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
+{
+ return (struct vi_sdma_mqd *)mqd;
+}
+
static int init_mqd(struct mqd_manager *mm, void **mqd,
struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
struct queue_properties *q)
@@ -84,6 +89,28 @@
if (q->format == KFD_QUEUE_FORMAT_AQL)
m->cp_hqd_iq_rptr = 1;
+ if (q->tba_addr) {
+ m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
+ m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
+ m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
+ m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
+ m->compute_pgm_rsrc2 |=
+ (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
+ }
+
+ if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
+ m->cp_hqd_persistent_state |=
+ (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
+ m->cp_hqd_ctx_save_base_addr_lo =
+ lower_32_bits(q->ctx_save_restore_area_address);
+ m->cp_hqd_ctx_save_base_addr_hi =
+ upper_32_bits(q->ctx_save_restore_area_address);
+ m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
+ m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
+ m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
+ m->cp_hqd_wg_state_offset = q->ctl_stack_size;
+ }
+
*mqd = m;
if (gart_addr)
*gart_addr = addr;
@@ -98,7 +125,7 @@
{
/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
- uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1);
+ uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
(uint32_t __user *)p->write_ptr,
@@ -116,8 +143,7 @@
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
- m->cp_hqd_pq_control |=
- ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
+ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
@@ -147,7 +173,7 @@
* is safe, giving a maximum field value of 0xA.
*/
m->cp_hqd_eop_control |= min(0xA,
- ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
+ order_base_2(q->eop_ring_buffer_size / 4) - 1);
m->cp_hqd_eop_base_addr_lo =
lower_32_bits(q->eop_ring_buffer_address >> 8);
m->cp_hqd_eop_base_addr_hi =
@@ -163,6 +189,11 @@
2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
}
+ if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
+ m->cp_hqd_ctx_save_control =
+ atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
+ mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
+
q->is_active = (q->queue_size > 0 &&
q->queue_address != 0 &&
q->queue_percent > 0);
@@ -234,6 +265,117 @@
return retval;
}
+static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+ struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
+ struct queue_properties *q)
+{
+ int retval;
+ struct vi_sdma_mqd *m;
+
+
+ retval = kfd_gtt_sa_allocate(mm->dev,
+ sizeof(struct vi_sdma_mqd),
+ mqd_mem_obj);
+
+ if (retval != 0)
+ return -ENOMEM;
+
+ m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
+
+ memset(m, 0, sizeof(struct vi_sdma_mqd));
+
+ *mqd = m;
+ if (gart_addr != NULL)
+ *gart_addr = (*mqd_mem_obj)->gpu_addr;
+
+ retval = mm->update_mqd(mm, m, q);
+
+ return retval;
+}
+
+static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
+ struct kfd_mem_obj *mqd_mem_obj)
+{
+ kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
+}
+
+static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
+ uint32_t pipe_id, uint32_t queue_id,
+ struct queue_properties *p, struct mm_struct *mms)
+{
+ return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
+ (uint32_t __user *)p->write_ptr,
+ mms);
+}
+
+static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
+ struct queue_properties *q)
+{
+ struct vi_sdma_mqd *m;
+
+ m = get_sdma_mqd(mqd);
+ m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
+ << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
+ q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
+ 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
+ 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
+
+ m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
+ m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
+ m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
+ m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
+ m->sdmax_rlcx_doorbell =
+ q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
+
+ m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
+
+ m->sdma_engine_id = q->sdma_engine_id;
+ m->sdma_queue_id = q->sdma_queue_id;
+
+ q->is_active = (q->queue_size > 0 &&
+ q->queue_address != 0 &&
+ q->queue_percent > 0);
+
+ return 0;
+}
+
+/*
+ * * preempt type here is ignored because there is only one way
+ * * to preempt sdma queue
+ */
+static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
+ enum kfd_preempt_type type,
+ unsigned int timeout, uint32_t pipe_id,
+ uint32_t queue_id)
+{
+ return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
+}
+
+static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
+ uint64_t queue_address, uint32_t pipe_id,
+ uint32_t queue_id)
+{
+ return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
+}
+
+#if defined(CONFIG_DEBUG_FS)
+
+static int debugfs_show_mqd(struct seq_file *m, void *data)
+{
+ seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
+ data, sizeof(struct vi_mqd), false);
+ return 0;
+}
+
+static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
+{
+ seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
+ data, sizeof(struct vi_sdma_mqd), false);
+ return 0;
+}
+
+#endif
+
struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
struct kfd_dev *dev)
{
@@ -257,6 +399,9 @@
mqd->update_mqd = update_mqd;
mqd->destroy_mqd = destroy_mqd;
mqd->is_occupied = is_occupied;
+#if defined(CONFIG_DEBUG_FS)
+ mqd->debugfs_show_mqd = debugfs_show_mqd;
+#endif
break;
case KFD_MQD_TYPE_HIQ:
mqd->init_mqd = init_mqd_hiq;
@@ -265,8 +410,20 @@
mqd->update_mqd = update_mqd_hiq;
mqd->destroy_mqd = destroy_mqd;
mqd->is_occupied = is_occupied;
+#if defined(CONFIG_DEBUG_FS)
+ mqd->debugfs_show_mqd = debugfs_show_mqd;
+#endif
break;
case KFD_MQD_TYPE_SDMA:
+ mqd->init_mqd = init_mqd_sdma;
+ mqd->uninit_mqd = uninit_mqd_sdma;
+ mqd->load_mqd = load_mqd_sdma;
+ mqd->update_mqd = update_mqd_sdma;
+ mqd->destroy_mqd = destroy_mqd_sdma;
+ mqd->is_occupied = is_occupied_sdma;
+#if defined(CONFIG_DEBUG_FS)
+ mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
+#endif
break;
default:
kfree(mqd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 55f0a85..0c3bc00 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -45,7 +45,7 @@
header.u32All = 0;
header.opcode = opcode;
- header.count = packet_size/sizeof(uint32_t) - 2;
+ header.count = packet_size / 4 - 2;
header.type = PM4_TYPE_3;
return header.u32All;
@@ -55,15 +55,27 @@
unsigned int *rlib_size,
bool *over_subscription)
{
- unsigned int process_count, queue_count;
+ unsigned int process_count, queue_count, compute_queue_count;
unsigned int map_queue_size;
+ unsigned int max_proc_per_quantum = 1;
+ struct kfd_dev *dev = pm->dqm->dev;
process_count = pm->dqm->processes_count;
queue_count = pm->dqm->queue_count;
+ compute_queue_count = queue_count - pm->dqm->sdma_queue_count;
- /* check if there is over subscription*/
+ /* check if there is over subscription
+ * Note: the arbitration between the number of VMIDs and
+ * hws_max_conc_proc has been done in
+ * kgd2kfd_device_init().
+ */
*over_subscription = false;
- if ((process_count > 1) || queue_count > get_queues_num(pm->dqm)) {
+
+ if (dev->max_proc_per_quantum > 1)
+ max_proc_per_quantum = dev->max_proc_per_quantum;
+
+ if ((process_count > max_proc_per_quantum) ||
+ compute_queue_count > get_queues_num(pm->dqm)) {
*over_subscription = true;
pr_debug("Over subscribed runlist\n");
}
@@ -116,10 +128,24 @@
uint64_t ib, size_t ib_size_in_dwords, bool chain)
{
struct pm4_mes_runlist *packet;
+ int concurrent_proc_cnt = 0;
+ struct kfd_dev *kfd = pm->dqm->dev;
if (WARN_ON(!ib))
return -EFAULT;
+ /* Determine the number of processes to map together to HW:
+ * it can not exceed the number of VMIDs available to the
+ * scheduler, and it is determined by the smaller of the number
+ * of processes in the runlist and kfd module parameter
+ * hws_max_conc_proc.
+ * Note: the arbitration between the number of VMIDs and
+ * hws_max_conc_proc has been done in
+ * kgd2kfd_device_init().
+ */
+ concurrent_proc_cnt = min(pm->dqm->processes_count,
+ kfd->max_proc_per_quantum);
+
packet = (struct pm4_mes_runlist *)buffer;
memset(buffer, 0, sizeof(struct pm4_mes_runlist));
@@ -130,6 +156,7 @@
packet->bitfields4.chain = chain ? 1 : 0;
packet->bitfields4.offload_polling = 0;
packet->bitfields4.valid = 1;
+ packet->bitfields4.process_cnt = concurrent_proc_cnt;
packet->ordinal2 = lower_32_bits(ib);
packet->bitfields3.ib_base_hi = upper_32_bits(ib);
@@ -250,6 +277,7 @@
return retval;
*rl_size_bytes = alloc_size_bytes;
+ pm->ib_size_bytes = alloc_size_bytes;
pr_debug("Building runlist ib process count: %d queues count %d\n",
pm->dqm->processes_count, pm->dqm->queue_count);
@@ -563,3 +591,26 @@
}
mutex_unlock(&pm->lock);
}
+
+#if defined(CONFIG_DEBUG_FS)
+
+int pm_debugfs_runlist(struct seq_file *m, void *data)
+{
+ struct packet_manager *pm = data;
+
+ mutex_lock(&pm->lock);
+
+ if (!pm->allocated) {
+ seq_puts(m, " No active runlist\n");
+ goto out;
+ }
+
+ seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
+ pm->ib_buffer_obj->cpu_ptr, pm->ib_size_bytes, false);
+
+out:
+ mutex_unlock(&pm->lock);
+ return 0;
+}
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
index d6a7961..15fff44 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
@@ -59,7 +59,7 @@
struct kfd_dev *dev = NULL;
unsigned int i = 0;
- while ((dev = kfd_topology_enum_kfd_devices(i)) != NULL) {
+ while ((kfd_topology_enum_kfd_devices(i, &dev)) == 0) {
if (dev && dev->kfd2kgd) {
kfd2kgd = dev->kfd2kgd;
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 9e4134c..0bedcf9c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -33,14 +33,17 @@
#include <linux/kfd_ioctl.h>
#include <linux/idr.h>
#include <linux/kfifo.h>
+#include <linux/seq_file.h>
+#include <linux/kref.h>
#include <kgd_kfd_interface.h>
#include "amd_shared.h"
#define KFD_SYSFS_FILE_MODE 0444
-#define KFD_MMAP_DOORBELL_MASK 0x8000000000000
-#define KFD_MMAP_EVENTS_MASK 0x4000000000000
+#define KFD_MMAP_DOORBELL_MASK 0x8000000000000ull
+#define KFD_MMAP_EVENTS_MASK 0x4000000000000ull
+#define KFD_MMAP_RESERVED_MEM_MASK 0x2000000000000ull
/*
* When working with cp scheduler we should assign the HIQ manually or via
@@ -63,6 +66,15 @@
#define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
/*
+ * Size of the per-process TBA+TMA buffer: 2 pages
+ *
+ * The first page is the TBA used for the CWSR ISA code. The second
+ * page is used as TMA for daisy changing a user-mode trap handler.
+ */
+#define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2)
+#define KFD_CWSR_TMA_OFFSET PAGE_SIZE
+
+/*
* Kernel module parameter to specify maximum number of supported queues per
* device
*/
@@ -79,11 +91,25 @@
extern int sched_policy;
/*
+ * Kernel module parameter to specify the maximum process
+ * number per HW scheduler
+ */
+extern int hws_max_conc_proc;
+
+extern int cwsr_enable;
+
+/*
* Kernel module parameter to specify whether to send sigterm to HSA process on
* unhandled exception
*/
extern int send_sigterm;
+/*
+ * Ignore CRAT table during KFD initialization, can be used to work around
+ * broken CRAT tables on some AMD systems
+ */
+extern int ignore_crat;
+
/**
* enum kfd_sched_policy
*
@@ -131,6 +157,7 @@
size_t ih_ring_entry_size;
uint8_t num_of_watch_points;
uint16_t mqd_size_aligned;
+ bool supports_cwsr;
};
struct kfd_mem_obj {
@@ -200,6 +227,14 @@
/* Debug manager */
struct kfd_dbgmgr *dbgmgr;
+
+ /* Maximum process number mapped to HW scheduler */
+ unsigned int max_proc_per_quantum;
+
+ /* CWSR */
+ bool cwsr_enabled;
+ const void *cwsr_isa;
+ unsigned int cwsr_isa_size;
};
/* KGD2KFD callbacks */
@@ -332,6 +367,9 @@
uint32_t eop_ring_buffer_size;
uint64_t ctx_save_restore_area_address;
uint32_t ctx_save_restore_area_size;
+ uint32_t ctl_stack_size;
+ uint64_t tba_addr;
+ uint64_t tma_addr;
};
/**
@@ -439,6 +477,11 @@
uint32_t num_gws;
uint32_t num_oac;
uint32_t sh_hidden_private_base;
+
+ /* CWSR memory */
+ void *cwsr_kaddr;
+ uint64_t tba_addr;
+ uint64_t tma_addr;
};
@@ -501,6 +544,9 @@
*/
void *mm;
+ struct kref ref;
+ struct work_struct release_work;
+
struct mutex mutex;
/*
@@ -563,9 +609,10 @@
void kfd_process_create_wq(void);
void kfd_process_destroy_wq(void);
-struct kfd_process *kfd_create_process(const struct task_struct *);
+struct kfd_process *kfd_create_process(struct file *filep);
struct kfd_process *kfd_get_process(const struct task_struct *);
struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid);
+void kfd_unref_process(struct kfd_process *p);
struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
struct kfd_process *p);
@@ -577,6 +624,9 @@
struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
struct kfd_process *p);
+int kfd_reserved_mem_mmap(struct kfd_process *process,
+ struct vm_area_struct *vma);
+
/* Process device data iterator */
struct kfd_process_device *kfd_get_first_process_device_data(
struct kfd_process *p);
@@ -624,9 +674,12 @@
void kfd_topology_shutdown(void);
int kfd_topology_add_device(struct kfd_dev *gpu);
int kfd_topology_remove_device(struct kfd_dev *gpu);
+struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
+ uint32_t proximity_domain);
struct kfd_dev *kfd_device_by_id(uint32_t gpu_id);
struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev);
-struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx);
+int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev);
+int kfd_numa_node_to_apic_id(int numa_node_id);
/* Interrupts */
int kfd_interrupt_init(struct kfd_dev *dev);
@@ -643,8 +696,6 @@
int kfd_init_apertures(struct kfd_process *process);
/* Queue Context Management */
-struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd);
-
int init_queue(struct queue **q, const struct queue_properties *properties);
void uninit_queue(struct queue *q);
void print_queue_properties(struct queue_properties *q);
@@ -699,6 +750,7 @@
struct mutex lock;
bool allocated;
struct kfd_mem_obj *ib_buffer_obj;
+ unsigned int ib_size_bytes;
};
int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
@@ -745,4 +797,23 @@
int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p);
+/* Debugfs */
+#if defined(CONFIG_DEBUG_FS)
+
+void kfd_debugfs_init(void);
+void kfd_debugfs_fini(void);
+int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
+int pqm_debugfs_mqds(struct seq_file *m, void *data);
+int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data);
+int dqm_debugfs_hqds(struct seq_file *m, void *data);
+int kfd_debugfs_rls_by_device(struct seq_file *m, void *data);
+int pm_debugfs_runlist(struct seq_file *m, void *data);
+
+#else
+
+static inline void kfd_debugfs_init(void) {}
+static inline void kfd_debugfs_fini(void) {}
+
+#endif
+
#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 1f5ccd28..4ff5f0f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -24,10 +24,12 @@
#include <linux/log2.h>
#include <linux/sched.h>
#include <linux/sched/mm.h>
+#include <linux/sched/task.h>
#include <linux/slab.h>
#include <linux/amd-iommu.h>
#include <linux/notifier.h>
#include <linux/compat.h>
+#include <linux/mman.h>
struct mm_struct;
@@ -46,13 +48,12 @@
static struct workqueue_struct *kfd_process_wq;
-struct kfd_process_release_work {
- struct work_struct kfd_work;
- struct kfd_process *p;
-};
-
static struct kfd_process *find_process(const struct task_struct *thread);
-static struct kfd_process *create_process(const struct task_struct *thread);
+static void kfd_process_ref_release(struct kref *ref);
+static struct kfd_process *create_process(const struct task_struct *thread,
+ struct file *filep);
+static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep);
+
void kfd_process_create_wq(void)
{
@@ -68,9 +69,10 @@
}
}
-struct kfd_process *kfd_create_process(const struct task_struct *thread)
+struct kfd_process *kfd_create_process(struct file *filep)
{
struct kfd_process *process;
+ struct task_struct *thread = current;
if (!thread->mm)
return ERR_PTR(-EINVAL);
@@ -79,9 +81,6 @@
if (thread->group_leader->mm != thread->mm)
return ERR_PTR(-EINVAL);
- /* Take mmap_sem because we call __mmu_notifier_register inside */
- down_write(&thread->mm->mmap_sem);
-
/*
* take kfd processes mutex before starting of process creation
* so there won't be a case where two threads of the same process
@@ -93,14 +92,11 @@
process = find_process(thread);
if (process)
pr_debug("Process already found\n");
-
- if (!process)
- process = create_process(thread);
+ else
+ process = create_process(thread, filep);
mutex_unlock(&kfd_processes_mutex);
- up_write(&thread->mm->mmap_sem);
-
return process;
}
@@ -144,63 +140,75 @@
return p;
}
-static void kfd_process_wq_release(struct work_struct *work)
+void kfd_unref_process(struct kfd_process *p)
{
- struct kfd_process_release_work *my_work;
+ kref_put(&p->ref, kfd_process_ref_release);
+}
+
+static void kfd_process_destroy_pdds(struct kfd_process *p)
+{
struct kfd_process_device *pdd, *temp;
- struct kfd_process *p;
-
- my_work = (struct kfd_process_release_work *) work;
-
- p = my_work->p;
-
- pr_debug("Releasing process (pasid %d) in workqueue\n",
- p->pasid);
-
- mutex_lock(&p->mutex);
list_for_each_entry_safe(pdd, temp, &p->per_device_data,
- per_device_list) {
- pr_debug("Releasing pdd (topology id %d) for process (pasid %d) in workqueue\n",
+ per_device_list) {
+ pr_debug("Releasing pdd (topology id %d) for process (pasid %d)\n",
pdd->dev->id, p->pasid);
- if (pdd->bound == PDD_BOUND)
- amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid);
-
list_del(&pdd->per_device_list);
+
+ if (pdd->qpd.cwsr_kaddr)
+ free_pages((unsigned long)pdd->qpd.cwsr_kaddr,
+ get_order(KFD_CWSR_TBA_TMA_SIZE));
+
kfree(pdd);
}
+}
+
+/* No process locking is needed in this function, because the process
+ * is not findable any more. We must assume that no other thread is
+ * using it any more, otherwise we couldn't safely free the process
+ * structure in the end.
+ */
+static void kfd_process_wq_release(struct work_struct *work)
+{
+ struct kfd_process *p = container_of(work, struct kfd_process,
+ release_work);
+ struct kfd_process_device *pdd;
+
+ pr_debug("Releasing process (pasid %d) in workqueue\n", p->pasid);
+
+ list_for_each_entry(pdd, &p->per_device_data, per_device_list) {
+ if (pdd->bound == PDD_BOUND)
+ amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid);
+ }
+
+ kfd_process_destroy_pdds(p);
kfd_event_free_process(p);
kfd_pasid_free(p->pasid);
kfd_free_process_doorbells(p);
- mutex_unlock(&p->mutex);
-
mutex_destroy(&p->mutex);
- kfree(p);
+ put_task_struct(p->lead_thread);
- kfree(work);
+ kfree(p);
+}
+
+static void kfd_process_ref_release(struct kref *ref)
+{
+ struct kfd_process *p = container_of(ref, struct kfd_process, ref);
+
+ INIT_WORK(&p->release_work, kfd_process_wq_release);
+ queue_work(kfd_process_wq, &p->release_work);
}
static void kfd_process_destroy_delayed(struct rcu_head *rcu)
{
- struct kfd_process_release_work *work;
- struct kfd_process *p;
+ struct kfd_process *p = container_of(rcu, struct kfd_process, rcu);
- p = container_of(rcu, struct kfd_process, rcu);
-
- mmdrop(p->mm);
-
- work = kmalloc(sizeof(struct kfd_process_release_work), GFP_ATOMIC);
-
- if (work) {
- INIT_WORK((struct work_struct *) work, kfd_process_wq_release);
- work->p = p;
- queue_work(kfd_process_wq, (struct work_struct *) work);
- }
+ kfd_unref_process(p);
}
static void kfd_process_notifier_release(struct mmu_notifier *mn,
@@ -244,15 +252,12 @@
kfd_process_dequeue_from_all_devices(p);
pqm_uninit(&p->pqm);
+ /* Indicate to other users that MM is no longer valid */
+ p->mm = NULL;
+
mutex_unlock(&p->mutex);
- /*
- * Because we drop mm_count inside kfd_process_destroy_delayed
- * and because the mmu_notifier_unregister function also drop
- * mm_count we need to take an extra count here.
- */
- mmgrab(p->mm);
- mmu_notifier_unregister_no_release(&p->mmu_notifier, p->mm);
+ mmu_notifier_unregister_no_release(&p->mmu_notifier, mm);
mmu_notifier_call_srcu(&p->rcu, &kfd_process_destroy_delayed);
}
@@ -260,7 +265,44 @@
.release = kfd_process_notifier_release,
};
-static struct kfd_process *create_process(const struct task_struct *thread)
+static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep)
+{
+ unsigned long offset;
+ struct kfd_process_device *pdd = NULL;
+ struct kfd_dev *dev = NULL;
+ struct qcm_process_device *qpd = NULL;
+
+ list_for_each_entry(pdd, &p->per_device_data, per_device_list) {
+ dev = pdd->dev;
+ qpd = &pdd->qpd;
+ if (!dev->cwsr_enabled || qpd->cwsr_kaddr)
+ continue;
+ offset = (dev->id | KFD_MMAP_RESERVED_MEM_MASK) << PAGE_SHIFT;
+ qpd->tba_addr = (int64_t)vm_mmap(filep, 0,
+ KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC,
+ MAP_SHARED, offset);
+
+ if (IS_ERR_VALUE(qpd->tba_addr)) {
+ int err = qpd->tba_addr;
+
+ pr_err("Failure to set tba address. error %d.\n", err);
+ qpd->tba_addr = 0;
+ qpd->cwsr_kaddr = NULL;
+ return err;
+ }
+
+ memcpy(qpd->cwsr_kaddr, dev->cwsr_isa, dev->cwsr_isa_size);
+
+ qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET;
+ pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n",
+ qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr);
+ }
+
+ return 0;
+}
+
+static struct kfd_process *create_process(const struct task_struct *thread,
+ struct file *filep)
{
struct kfd_process *process;
int err = -ENOMEM;
@@ -277,13 +319,15 @@
if (kfd_alloc_process_doorbells(process) < 0)
goto err_alloc_doorbells;
+ kref_init(&process->ref);
+
mutex_init(&process->mutex);
process->mm = thread->mm;
/* register notifier */
process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops;
- err = __mmu_notifier_register(&process->mmu_notifier, process->mm);
+ err = mmu_notifier_register(&process->mmu_notifier, process->mm);
if (err)
goto err_mmu_notifier;
@@ -291,6 +335,7 @@
(uintptr_t)process->mm);
process->lead_thread = thread->group_leader;
+ get_task_struct(process->lead_thread);
INIT_LIST_HEAD(&process->per_device_data);
@@ -306,8 +351,14 @@
if (err != 0)
goto err_init_apertures;
+ err = kfd_process_init_cwsr(process, filep);
+ if (err)
+ goto err_init_cwsr;
+
return process;
+err_init_cwsr:
+ kfd_process_destroy_pdds(process);
err_init_apertures:
pqm_uninit(&process->pqm);
err_process_pqm_init:
@@ -343,16 +394,18 @@
struct kfd_process_device *pdd = NULL;
pdd = kzalloc(sizeof(*pdd), GFP_KERNEL);
- if (pdd != NULL) {
- pdd->dev = dev;
- INIT_LIST_HEAD(&pdd->qpd.queues_list);
- INIT_LIST_HEAD(&pdd->qpd.priv_queue_list);
- pdd->qpd.dqm = dev->dqm;
- pdd->process = p;
- pdd->bound = PDD_UNBOUND;
- pdd->already_dequeued = false;
- list_add(&pdd->per_device_list, &p->per_device_data);
- }
+ if (!pdd)
+ return NULL;
+
+ pdd->dev = dev;
+ INIT_LIST_HEAD(&pdd->qpd.queues_list);
+ INIT_LIST_HEAD(&pdd->qpd.priv_queue_list);
+ pdd->qpd.dqm = dev->dqm;
+ pdd->qpd.pqm = &p->pqm;
+ pdd->process = p;
+ pdd->bound = PDD_UNBOUND;
+ pdd->already_dequeued = false;
+ list_add(&pdd->per_device_list, &p->per_device_data);
return pdd;
}
@@ -408,7 +461,8 @@
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
- if (pdd->bound != PDD_BOUND_SUSPENDED) {
+
+ if (WARN_ON(!pdd) || pdd->bound != PDD_BOUND_SUSPENDED) {
mutex_unlock(&p->mutex);
continue;
}
@@ -448,6 +502,11 @@
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+ if (WARN_ON(!pdd)) {
+ mutex_unlock(&p->mutex);
+ continue;
+ }
+
if (pdd->bound == PDD_BOUND)
pdd->bound = PDD_BOUND_SUSPENDED;
mutex_unlock(&p->mutex);
@@ -483,6 +542,8 @@
mutex_unlock(kfd_get_dbgmgr_mutex());
+ mutex_lock(&p->mutex);
+
pdd = kfd_get_process_device_data(dev, p);
if (pdd)
/* For GPU relying on IOMMU, we need to dequeue here
@@ -491,6 +552,8 @@
kfd_process_dequeue_from_device(pdd);
mutex_unlock(&p->mutex);
+
+ kfd_unref_process(p);
}
struct kfd_process_device *kfd_get_first_process_device_data(
@@ -515,22 +578,86 @@
return !(list_empty(&p->per_device_data));
}
-/* This returns with process->mutex locked. */
+/* This increments the process->ref counter. */
struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid)
{
- struct kfd_process *p;
+ struct kfd_process *p, *ret_p = NULL;
unsigned int temp;
int idx = srcu_read_lock(&kfd_processes_srcu);
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
if (p->pasid == pasid) {
- mutex_lock(&p->mutex);
+ kref_get(&p->ref);
+ ret_p = p;
break;
}
}
srcu_read_unlock(&kfd_processes_srcu, idx);
- return p;
+ return ret_p;
}
+
+int kfd_reserved_mem_mmap(struct kfd_process *process,
+ struct vm_area_struct *vma)
+{
+ struct kfd_dev *dev = kfd_device_by_id(vma->vm_pgoff);
+ struct kfd_process_device *pdd;
+ struct qcm_process_device *qpd;
+
+ if (!dev)
+ return -EINVAL;
+ if ((vma->vm_end - vma->vm_start) != KFD_CWSR_TBA_TMA_SIZE) {
+ pr_err("Incorrect CWSR mapping size.\n");
+ return -EINVAL;
+ }
+
+ pdd = kfd_get_process_device_data(dev, process);
+ if (!pdd)
+ return -EINVAL;
+ qpd = &pdd->qpd;
+
+ qpd->cwsr_kaddr = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
+ get_order(KFD_CWSR_TBA_TMA_SIZE));
+ if (!qpd->cwsr_kaddr) {
+ pr_err("Error allocating per process CWSR buffer.\n");
+ return -ENOMEM;
+ }
+
+ vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND
+ | VM_NORESERVE | VM_DONTDUMP | VM_PFNMAP;
+ /* Mapping pages to user process */
+ return remap_pfn_range(vma, vma->vm_start,
+ PFN_DOWN(__pa(qpd->cwsr_kaddr)),
+ KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot);
+}
+
+#if defined(CONFIG_DEBUG_FS)
+
+int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data)
+{
+ struct kfd_process *p;
+ unsigned int temp;
+ int r = 0;
+
+ int idx = srcu_read_lock(&kfd_processes_srcu);
+
+ hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
+ seq_printf(m, "Process %d PASID %d:\n",
+ p->lead_thread->tgid, p->pasid);
+
+ mutex_lock(&p->mutex);
+ r = pqm_debugfs_mqds(m, &p->pqm);
+ mutex_unlock(&p->mutex);
+
+ if (r)
+ break;
+ }
+
+ srcu_read_unlock(&kfd_processes_srcu, idx);
+
+ return r;
+}
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index a3f1e62..8763806 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -178,10 +178,8 @@
return retval;
if (list_empty(&pdd->qpd.queues_list) &&
- list_empty(&pdd->qpd.priv_queue_list)) {
- pdd->qpd.pqm = pqm;
+ list_empty(&pdd->qpd.priv_queue_list))
dev->dqm->ops.register_process(dev->dqm, &pdd->qpd);
- }
pqn = kzalloc(sizeof(*pqn), GFP_KERNEL);
if (!pqn) {
@@ -203,8 +201,7 @@
goto err_create_queue;
pqn->q = q;
pqn->kq = NULL;
- retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd,
- &q->properties.vmid);
+ retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd);
pr_debug("DQM returned %d for create_queue\n", retval);
print_queue(q);
break;
@@ -224,8 +221,7 @@
goto err_create_queue;
pqn->q = q;
pqn->kq = NULL;
- retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd,
- &q->properties.vmid);
+ retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd);
pr_debug("DQM returned %d for create_queue\n", retval);
print_queue(q);
break;
@@ -315,6 +311,10 @@
if (pqn->q) {
dqm = pqn->q->device->dqm;
retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
+ if (retval) {
+ pr_debug("Destroy queue failed, returned %d\n", retval);
+ goto err_destroy_queue;
+ }
uninit_queue(pqn->q);
}
@@ -326,6 +326,7 @@
list_empty(&pdd->qpd.priv_queue_list))
dqm->ops.unregister_process(dqm, &pdd->qpd);
+err_destroy_queue:
return retval;
}
@@ -367,4 +368,67 @@
return NULL;
}
+#if defined(CONFIG_DEBUG_FS)
+int pqm_debugfs_mqds(struct seq_file *m, void *data)
+{
+ struct process_queue_manager *pqm = data;
+ struct process_queue_node *pqn;
+ struct queue *q;
+ enum KFD_MQD_TYPE mqd_type;
+ struct mqd_manager *mqd_manager;
+ int r = 0;
+
+ list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
+ if (pqn->q) {
+ q = pqn->q;
+ switch (q->properties.type) {
+ case KFD_QUEUE_TYPE_SDMA:
+ seq_printf(m, " SDMA queue on device %x\n",
+ q->device->id);
+ mqd_type = KFD_MQD_TYPE_SDMA;
+ break;
+ case KFD_QUEUE_TYPE_COMPUTE:
+ seq_printf(m, " Compute queue on device %x\n",
+ q->device->id);
+ mqd_type = KFD_MQD_TYPE_CP;
+ break;
+ default:
+ seq_printf(m,
+ " Bad user queue type %d on device %x\n",
+ q->properties.type, q->device->id);
+ continue;
+ }
+ mqd_manager = q->device->dqm->ops.get_mqd_manager(
+ q->device->dqm, mqd_type);
+ } else if (pqn->kq) {
+ q = pqn->kq->queue;
+ mqd_manager = pqn->kq->mqd;
+ switch (q->properties.type) {
+ case KFD_QUEUE_TYPE_DIQ:
+ seq_printf(m, " DIQ on device %x\n",
+ pqn->kq->dev->id);
+ mqd_type = KFD_MQD_TYPE_HIQ;
+ break;
+ default:
+ seq_printf(m,
+ " Bad kernel queue type %d on device %x\n",
+ q->properties.type,
+ pqn->kq->dev->id);
+ continue;
+ }
+ } else {
+ seq_printf(m,
+ " Weird: Queue node with neither kernel nor user queue\n");
+ continue;
+ }
+
+ r = mqd_manager->debugfs_show_mqd(m, q->mqd);
+ if (r != 0)
+ break;
+ }
+
+ return r;
+}
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index e0b78fd..c6a7609 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -28,16 +28,39 @@
#include <linux/hash.h>
#include <linux/cpufreq.h>
#include <linux/log2.h>
+#include <linux/dmi.h>
+#include <linux/atomic.h>
#include "kfd_priv.h"
#include "kfd_crat.h"
#include "kfd_topology.h"
+#include "kfd_device_queue_manager.h"
+/* topology_device_list - Master list of all topology devices */
static struct list_head topology_device_list;
-static int topology_crat_parsed;
static struct kfd_system_properties sys_props;
static DECLARE_RWSEM(topology_lock);
+static atomic_t topology_crat_proximity_domain;
+
+struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
+ uint32_t proximity_domain)
+{
+ struct kfd_topology_device *top_dev;
+ struct kfd_topology_device *device = NULL;
+
+ down_read(&topology_lock);
+
+ list_for_each_entry(top_dev, &topology_device_list, list)
+ if (top_dev->proximity_domain == proximity_domain) {
+ device = top_dev;
+ break;
+ }
+
+ up_read(&topology_lock);
+
+ return device;
+}
struct kfd_dev *kfd_device_by_id(uint32_t gpu_id)
{
@@ -75,282 +98,13 @@
return device;
}
-static int kfd_topology_get_crat_acpi(void *crat_image, size_t *size)
-{
- struct acpi_table_header *crat_table;
- acpi_status status;
-
- if (!size)
- return -EINVAL;
-
- /*
- * Fetch the CRAT table from ACPI
- */
- status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
- if (status == AE_NOT_FOUND) {
- pr_warn("CRAT table not found\n");
- return -ENODATA;
- } else if (ACPI_FAILURE(status)) {
- const char *err = acpi_format_exception(status);
-
- pr_err("CRAT table error: %s\n", err);
- return -EINVAL;
- }
-
- if (*size >= crat_table->length && crat_image != NULL)
- memcpy(crat_image, crat_table, crat_table->length);
-
- *size = crat_table->length;
-
- return 0;
-}
-
-static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
- struct crat_subtype_computeunit *cu)
-{
- dev->node_props.cpu_cores_count = cu->num_cpu_cores;
- dev->node_props.cpu_core_id_base = cu->processor_id_low;
- if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
- dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
-
- pr_info("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
- cu->processor_id_low);
-}
-
-static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
- struct crat_subtype_computeunit *cu)
-{
- dev->node_props.simd_id_base = cu->processor_id_low;
- dev->node_props.simd_count = cu->num_simd_cores;
- dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
- dev->node_props.max_waves_per_simd = cu->max_waves_simd;
- dev->node_props.wave_front_size = cu->wave_front_size;
- dev->node_props.mem_banks_count = cu->num_banks;
- dev->node_props.array_count = cu->num_arrays;
- dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
- dev->node_props.simd_per_cu = cu->num_simd_per_cu;
- dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
- if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
- dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
- pr_info("CU GPU: simds=%d id_base=%d\n", cu->num_simd_cores,
- cu->processor_id_low);
-}
-
-/* kfd_parse_subtype_cu is called when the topology mutex is already acquired */
-static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu)
-{
- struct kfd_topology_device *dev;
- int i = 0;
-
- pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
- cu->proximity_domain, cu->hsa_capability);
- list_for_each_entry(dev, &topology_device_list, list) {
- if (cu->proximity_domain == i) {
- if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
- kfd_populated_cu_info_cpu(dev, cu);
-
- if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
- kfd_populated_cu_info_gpu(dev, cu);
- break;
- }
- i++;
- }
-
- return 0;
-}
-
-/*
- * kfd_parse_subtype_mem is called when the topology mutex is
- * already acquired
- */
-static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem)
-{
- struct kfd_mem_properties *props;
- struct kfd_topology_device *dev;
- int i = 0;
-
- pr_info("Found memory entry in CRAT table with proximity_domain=%d\n",
- mem->promixity_domain);
- list_for_each_entry(dev, &topology_device_list, list) {
- if (mem->promixity_domain == i) {
- props = kfd_alloc_struct(props);
- if (props == NULL)
- return -ENOMEM;
-
- if (dev->node_props.cpu_cores_count == 0)
- props->heap_type = HSA_MEM_HEAP_TYPE_FB_PRIVATE;
- else
- props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
-
- if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
- props->flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
- if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
- props->flags |= HSA_MEM_FLAGS_NON_VOLATILE;
-
- props->size_in_bytes =
- ((uint64_t)mem->length_high << 32) +
- mem->length_low;
- props->width = mem->width;
-
- dev->mem_bank_count++;
- list_add_tail(&props->list, &dev->mem_props);
-
- break;
- }
- i++;
- }
-
- return 0;
-}
-
-/*
- * kfd_parse_subtype_cache is called when the topology mutex
- * is already acquired
- */
-static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache)
-{
- struct kfd_cache_properties *props;
- struct kfd_topology_device *dev;
- uint32_t id;
-
- id = cache->processor_id_low;
-
- pr_info("Found cache entry in CRAT table with processor_id=%d\n", id);
- list_for_each_entry(dev, &topology_device_list, list)
- if (id == dev->node_props.cpu_core_id_base ||
- id == dev->node_props.simd_id_base) {
- props = kfd_alloc_struct(props);
- if (props == NULL)
- return -ENOMEM;
-
- props->processor_id_low = id;
- props->cache_level = cache->cache_level;
- props->cache_size = cache->cache_size;
- props->cacheline_size = cache->cache_line_size;
- props->cachelines_per_tag = cache->lines_per_tag;
- props->cache_assoc = cache->associativity;
- props->cache_latency = cache->cache_latency;
-
- if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
- props->cache_type |= HSA_CACHE_TYPE_DATA;
- if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
- props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
- if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
- props->cache_type |= HSA_CACHE_TYPE_CPU;
- if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
- props->cache_type |= HSA_CACHE_TYPE_HSACU;
-
- dev->cache_count++;
- dev->node_props.caches_count++;
- list_add_tail(&props->list, &dev->cache_props);
-
- break;
- }
-
- return 0;
-}
-
-/*
- * kfd_parse_subtype_iolink is called when the topology mutex
- * is already acquired
- */
-static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink)
-{
- struct kfd_iolink_properties *props;
- struct kfd_topology_device *dev;
- uint32_t i = 0;
- uint32_t id_from;
- uint32_t id_to;
-
- id_from = iolink->proximity_domain_from;
- id_to = iolink->proximity_domain_to;
-
- pr_info("Found IO link entry in CRAT table with id_from=%d\n", id_from);
- list_for_each_entry(dev, &topology_device_list, list) {
- if (id_from == i) {
- props = kfd_alloc_struct(props);
- if (props == NULL)
- return -ENOMEM;
-
- props->node_from = id_from;
- props->node_to = id_to;
- props->ver_maj = iolink->version_major;
- props->ver_min = iolink->version_minor;
-
- /*
- * weight factor (derived from CDIR), currently always 1
- */
- props->weight = 1;
-
- props->min_latency = iolink->minimum_latency;
- props->max_latency = iolink->maximum_latency;
- props->min_bandwidth = iolink->minimum_bandwidth_mbs;
- props->max_bandwidth = iolink->maximum_bandwidth_mbs;
- props->rec_transfer_size =
- iolink->recommended_transfer_size;
-
- dev->io_link_count++;
- dev->node_props.io_links_count++;
- list_add_tail(&props->list, &dev->io_link_props);
-
- break;
- }
- i++;
- }
-
- return 0;
-}
-
-static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr)
-{
- struct crat_subtype_computeunit *cu;
- struct crat_subtype_memory *mem;
- struct crat_subtype_cache *cache;
- struct crat_subtype_iolink *iolink;
- int ret = 0;
-
- switch (sub_type_hdr->type) {
- case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
- cu = (struct crat_subtype_computeunit *)sub_type_hdr;
- ret = kfd_parse_subtype_cu(cu);
- break;
- case CRAT_SUBTYPE_MEMORY_AFFINITY:
- mem = (struct crat_subtype_memory *)sub_type_hdr;
- ret = kfd_parse_subtype_mem(mem);
- break;
- case CRAT_SUBTYPE_CACHE_AFFINITY:
- cache = (struct crat_subtype_cache *)sub_type_hdr;
- ret = kfd_parse_subtype_cache(cache);
- break;
- case CRAT_SUBTYPE_TLB_AFFINITY:
- /*
- * For now, nothing to do here
- */
- pr_info("Found TLB entry in CRAT table (not processing)\n");
- break;
- case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
- /*
- * For now, nothing to do here
- */
- pr_info("Found CCOMPUTE entry in CRAT table (not processing)\n");
- break;
- case CRAT_SUBTYPE_IOLINK_AFFINITY:
- iolink = (struct crat_subtype_iolink *)sub_type_hdr;
- ret = kfd_parse_subtype_iolink(iolink);
- break;
- default:
- pr_warn("Unknown subtype (%d) in CRAT\n",
- sub_type_hdr->type);
- }
-
- return ret;
-}
-
+/* Called with write topology_lock acquired */
static void kfd_release_topology_device(struct kfd_topology_device *dev)
{
struct kfd_mem_properties *mem;
struct kfd_cache_properties *cache;
struct kfd_iolink_properties *iolink;
+ struct kfd_perf_properties *perf;
list_del(&dev->list);
@@ -375,25 +129,35 @@
kfree(iolink);
}
- kfree(dev);
+ while (dev->perf_props.next != &dev->perf_props) {
+ perf = container_of(dev->perf_props.next,
+ struct kfd_perf_properties, list);
+ list_del(&perf->list);
+ kfree(perf);
+ }
- sys_props.num_devices--;
+ kfree(dev);
+}
+
+void kfd_release_topology_device_list(struct list_head *device_list)
+{
+ struct kfd_topology_device *dev;
+
+ while (!list_empty(device_list)) {
+ dev = list_first_entry(device_list,
+ struct kfd_topology_device, list);
+ kfd_release_topology_device(dev);
+ }
}
static void kfd_release_live_view(void)
{
- struct kfd_topology_device *dev;
-
- while (topology_device_list.next != &topology_device_list) {
- dev = container_of(topology_device_list.next,
- struct kfd_topology_device, list);
- kfd_release_topology_device(dev);
-}
-
+ kfd_release_topology_device_list(&topology_device_list);
memset(&sys_props, 0, sizeof(sys_props));
}
-static struct kfd_topology_device *kfd_create_topology_device(void)
+struct kfd_topology_device *kfd_create_topology_device(
+ struct list_head *device_list)
{
struct kfd_topology_device *dev;
@@ -406,65 +170,13 @@
INIT_LIST_HEAD(&dev->mem_props);
INIT_LIST_HEAD(&dev->cache_props);
INIT_LIST_HEAD(&dev->io_link_props);
+ INIT_LIST_HEAD(&dev->perf_props);
- list_add_tail(&dev->list, &topology_device_list);
- sys_props.num_devices++;
+ list_add_tail(&dev->list, device_list);
return dev;
}
-static int kfd_parse_crat_table(void *crat_image)
-{
- struct kfd_topology_device *top_dev;
- struct crat_subtype_generic *sub_type_hdr;
- uint16_t node_id;
- int ret;
- struct crat_header *crat_table = (struct crat_header *)crat_image;
- uint16_t num_nodes;
- uint32_t image_len;
-
- if (!crat_image)
- return -EINVAL;
-
- num_nodes = crat_table->num_domains;
- image_len = crat_table->length;
-
- pr_info("Parsing CRAT table with %d nodes\n", num_nodes);
-
- for (node_id = 0; node_id < num_nodes; node_id++) {
- top_dev = kfd_create_topology_device();
- if (!top_dev) {
- kfd_release_live_view();
- return -ENOMEM;
- }
- }
-
- sys_props.platform_id =
- (*((uint64_t *)crat_table->oem_id)) & CRAT_OEMID_64BIT_MASK;
- sys_props.platform_oem = *((uint64_t *)crat_table->oem_table_id);
- sys_props.platform_rev = crat_table->revision;
-
- sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
- while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
- ((char *)crat_image) + image_len) {
- if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
- ret = kfd_parse_subtype(sub_type_hdr);
- if (ret != 0) {
- kfd_release_live_view();
- return ret;
- }
- }
-
- sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
- sub_type_hdr->length);
- }
-
- sys_props.generation_count++;
- topology_crat_parsed = 1;
-
- return 0;
-}
-
#define sysfs_show_gen_prop(buffer, fmt, ...) \
snprintf(buffer, PAGE_SIZE, "%s"fmt, buffer, __VA_ARGS__)
@@ -583,7 +295,7 @@
char *buffer)
{
ssize_t ret;
- uint32_t i;
+ uint32_t i, j;
struct kfd_cache_properties *cache;
/* Making sure that the buffer is an empty string */
@@ -601,12 +313,18 @@
sysfs_show_32bit_prop(buffer, "latency", cache->cache_latency);
sysfs_show_32bit_prop(buffer, "type", cache->cache_type);
snprintf(buffer, PAGE_SIZE, "%ssibling_map ", buffer);
- for (i = 0; i < KFD_TOPOLOGY_CPU_SIBLINGS; i++)
- ret = snprintf(buffer, PAGE_SIZE, "%s%d%s",
- buffer, cache->sibling_map[i],
- (i == KFD_TOPOLOGY_CPU_SIBLINGS-1) ?
- "\n" : ",");
-
+ for (i = 0; i < CRAT_SIBLINGMAP_SIZE; i++)
+ for (j = 0; j < sizeof(cache->sibling_map[0])*8; j++) {
+ /* Check each bit */
+ if (cache->sibling_map[i] & (1 << j))
+ ret = snprintf(buffer, PAGE_SIZE,
+ "%s%d%s", buffer, 1, ",");
+ else
+ ret = snprintf(buffer, PAGE_SIZE,
+ "%s%d%s", buffer, 0, ",");
+ }
+ /* Replace the last "," with end of line */
+ *(buffer + strlen(buffer) - 1) = 0xA;
return ret;
}
@@ -619,6 +337,39 @@
.sysfs_ops = &cache_ops,
};
+/****** Sysfs of Performance Counters ******/
+
+struct kfd_perf_attr {
+ struct kobj_attribute attr;
+ uint32_t data;
+};
+
+static ssize_t perf_show(struct kobject *kobj, struct kobj_attribute *attrs,
+ char *buf)
+{
+ struct kfd_perf_attr *attr;
+
+ buf[0] = 0;
+ attr = container_of(attrs, struct kfd_perf_attr, attr);
+ if (!attr->data) /* invalid data for PMC */
+ return 0;
+ else
+ return sysfs_show_32bit_val(buf, attr->data);
+}
+
+#define KFD_PERF_DESC(_name, _data) \
+{ \
+ .attr = __ATTR(_name, 0444, perf_show, NULL), \
+ .data = _data, \
+}
+
+static struct kfd_perf_attr perf_attr_iommu[] = {
+ KFD_PERF_DESC(max_concurrent, 0),
+ KFD_PERF_DESC(num_counters, 0),
+ KFD_PERF_DESC(counter_ids, 0),
+};
+/****************************************/
+
static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
char *buffer)
{
@@ -655,18 +406,8 @@
dev->node_props.cpu_cores_count);
sysfs_show_32bit_prop(buffer, "simd_count",
dev->node_props.simd_count);
-
- if (dev->mem_bank_count < dev->node_props.mem_banks_count) {
- pr_info_once("mem_banks_count truncated from %d to %d\n",
- dev->node_props.mem_banks_count,
- dev->mem_bank_count);
- sysfs_show_32bit_prop(buffer, "mem_banks_count",
- dev->mem_bank_count);
- } else {
- sysfs_show_32bit_prop(buffer, "mem_banks_count",
- dev->node_props.mem_banks_count);
- }
-
+ sysfs_show_32bit_prop(buffer, "mem_banks_count",
+ dev->node_props.mem_banks_count);
sysfs_show_32bit_prop(buffer, "caches_count",
dev->node_props.caches_count);
sysfs_show_32bit_prop(buffer, "io_links_count",
@@ -714,9 +455,12 @@
HSA_CAP_WATCH_POINTS_TOTALBITS_MASK);
}
+ if (dev->gpu->device_info->asic_family == CHIP_TONGA)
+ dev->node_props.capability |=
+ HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
+
sysfs_show_32bit_prop(buffer, "max_engine_clk_fcompute",
- dev->gpu->kfd2kgd->get_max_engine_clock_in_mhz(
- dev->gpu->kgd));
+ dev->node_props.max_engine_clk_fcompute);
sysfs_show_64bit_prop(buffer, "local_mem_size",
(unsigned long long int) 0);
@@ -754,6 +498,7 @@
struct kfd_iolink_properties *iolink;
struct kfd_cache_properties *cache;
struct kfd_mem_properties *mem;
+ struct kfd_perf_properties *perf;
if (dev->kobj_iolink) {
list_for_each_entry(iolink, &dev->io_link_props, list)
@@ -790,6 +535,16 @@
dev->kobj_mem = NULL;
}
+ if (dev->kobj_perf) {
+ list_for_each_entry(perf, &dev->perf_props, list) {
+ kfree(perf->attr_group);
+ perf->attr_group = NULL;
+ }
+ kobject_del(dev->kobj_perf);
+ kobject_put(dev->kobj_perf);
+ dev->kobj_perf = NULL;
+ }
+
if (dev->kobj_node) {
sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid);
sysfs_remove_file(dev->kobj_node, &dev->attr_name);
@@ -806,8 +561,10 @@
struct kfd_iolink_properties *iolink;
struct kfd_cache_properties *cache;
struct kfd_mem_properties *mem;
+ struct kfd_perf_properties *perf;
int ret;
- uint32_t i;
+ uint32_t i, num_attrs;
+ struct attribute **attrs;
if (WARN_ON(dev->kobj_node))
return -EEXIST;
@@ -836,6 +593,10 @@
if (!dev->kobj_iolink)
return -ENOMEM;
+ dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node);
+ if (!dev->kobj_perf)
+ return -ENOMEM;
+
/*
* Creating sysfs files for node properties
*/
@@ -913,11 +674,38 @@
if (ret < 0)
return ret;
i++;
-}
+ }
+
+ /* All hardware blocks have the same number of attributes. */
+ num_attrs = sizeof(perf_attr_iommu)/sizeof(struct kfd_perf_attr);
+ list_for_each_entry(perf, &dev->perf_props, list) {
+ perf->attr_group = kzalloc(sizeof(struct kfd_perf_attr)
+ * num_attrs + sizeof(struct attribute_group),
+ GFP_KERNEL);
+ if (!perf->attr_group)
+ return -ENOMEM;
+
+ attrs = (struct attribute **)(perf->attr_group + 1);
+ if (!strcmp(perf->block_name, "iommu")) {
+ /* Information of IOMMU's num_counters and counter_ids is shown
+ * under /sys/bus/event_source/devices/amd_iommu. We don't
+ * duplicate here.
+ */
+ perf_attr_iommu[0].data = perf->max_concurrent;
+ for (i = 0; i < num_attrs; i++)
+ attrs[i] = &perf_attr_iommu[i].attr.attr;
+ }
+ perf->attr_group->name = perf->block_name;
+ perf->attr_group->attrs = attrs;
+ ret = sysfs_create_group(dev->kobj_perf, perf->attr_group);
+ if (ret < 0)
+ return ret;
+ }
return 0;
}
+/* Called with write topology lock acquired */
static int kfd_build_sysfs_node_tree(void)
{
struct kfd_topology_device *dev;
@@ -934,6 +722,7 @@
return 0;
}
+/* Called with write topology lock acquired */
static void kfd_remove_sysfs_node_tree(void)
{
struct kfd_topology_device *dev;
@@ -1005,75 +794,246 @@
}
}
-int kfd_topology_init(void)
+/* Called with write topology_lock acquired */
+static void kfd_topology_update_device_list(struct list_head *temp_list,
+ struct list_head *master_list)
{
- void *crat_image = NULL;
- size_t image_size = 0;
- int ret;
-
- /*
- * Initialize the head for the topology device list
- */
- INIT_LIST_HEAD(&topology_device_list);
- init_rwsem(&topology_lock);
- topology_crat_parsed = 0;
-
- memset(&sys_props, 0, sizeof(sys_props));
-
- /*
- * Get the CRAT image from the ACPI
- */
- ret = kfd_topology_get_crat_acpi(crat_image, &image_size);
- if (ret == 0 && image_size > 0) {
- pr_info("Found CRAT image with size=%zd\n", image_size);
- crat_image = kmalloc(image_size, GFP_KERNEL);
- if (!crat_image) {
- ret = -ENOMEM;
- pr_err("No memory for allocating CRAT image\n");
- goto err;
- }
- ret = kfd_topology_get_crat_acpi(crat_image, &image_size);
-
- if (ret == 0) {
- down_write(&topology_lock);
- ret = kfd_parse_crat_table(crat_image);
- if (ret == 0)
- ret = kfd_topology_update_sysfs();
- up_write(&topology_lock);
- } else {
- pr_err("Couldn't get CRAT table size from ACPI\n");
- }
- kfree(crat_image);
- } else if (ret == -ENODATA) {
- ret = 0;
- } else {
- pr_err("Couldn't get CRAT table size from ACPI\n");
+ while (!list_empty(temp_list)) {
+ list_move_tail(temp_list->next, master_list);
+ sys_props.num_devices++;
}
-
-err:
- pr_info("Finished initializing topology ret=%d\n", ret);
- return ret;
-}
-
-void kfd_topology_shutdown(void)
-{
- kfd_topology_release_sysfs();
- kfd_release_live_view();
}
static void kfd_debug_print_topology(void)
{
struct kfd_topology_device *dev;
- uint32_t i = 0;
- pr_info("DEBUG PRINT OF TOPOLOGY:");
- list_for_each_entry(dev, &topology_device_list, list) {
- pr_info("Node: %d\n", i);
- pr_info("\tGPU assigned: %s\n", (dev->gpu ? "yes" : "no"));
- pr_info("\tCPU count: %d\n", dev->node_props.cpu_cores_count);
- pr_info("\tSIMD count: %d", dev->node_props.simd_count);
- i++;
+ down_read(&topology_lock);
+
+ dev = list_last_entry(&topology_device_list,
+ struct kfd_topology_device, list);
+ if (dev) {
+ if (dev->node_props.cpu_cores_count &&
+ dev->node_props.simd_count) {
+ pr_info("Topology: Add APU node [0x%0x:0x%0x]\n",
+ dev->node_props.device_id,
+ dev->node_props.vendor_id);
+ } else if (dev->node_props.cpu_cores_count)
+ pr_info("Topology: Add CPU node\n");
+ else if (dev->node_props.simd_count)
+ pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n",
+ dev->node_props.device_id,
+ dev->node_props.vendor_id);
}
+ up_read(&topology_lock);
+}
+
+/* Helper function for intializing platform_xx members of
+ * kfd_system_properties. Uses OEM info from the last CPU/APU node.
+ */
+static void kfd_update_system_properties(void)
+{
+ struct kfd_topology_device *dev;
+
+ down_read(&topology_lock);
+ dev = list_last_entry(&topology_device_list,
+ struct kfd_topology_device, list);
+ if (dev) {
+ sys_props.platform_id =
+ (*((uint64_t *)dev->oem_id)) & CRAT_OEMID_64BIT_MASK;
+ sys_props.platform_oem = *((uint64_t *)dev->oem_table_id);
+ sys_props.platform_rev = dev->oem_revision;
+ }
+ up_read(&topology_lock);
+}
+
+static void find_system_memory(const struct dmi_header *dm,
+ void *private)
+{
+ struct kfd_mem_properties *mem;
+ u16 mem_width, mem_clock;
+ struct kfd_topology_device *kdev =
+ (struct kfd_topology_device *)private;
+ const u8 *dmi_data = (const u8 *)(dm + 1);
+
+ if (dm->type == DMI_ENTRY_MEM_DEVICE && dm->length >= 0x15) {
+ mem_width = (u16)(*(const u16 *)(dmi_data + 0x6));
+ mem_clock = (u16)(*(const u16 *)(dmi_data + 0x11));
+ list_for_each_entry(mem, &kdev->mem_props, list) {
+ if (mem_width != 0xFFFF && mem_width != 0)
+ mem->width = mem_width;
+ if (mem_clock != 0)
+ mem->mem_clk_max = mem_clock;
+ }
+ }
+}
+
+/*
+ * Performance counters information is not part of CRAT but we would like to
+ * put them in the sysfs under topology directory for Thunk to get the data.
+ * This function is called before updating the sysfs.
+ */
+static int kfd_add_perf_to_topology(struct kfd_topology_device *kdev)
+{
+ struct kfd_perf_properties *props;
+
+ if (amd_iommu_pc_supported()) {
+ props = kfd_alloc_struct(props);
+ if (!props)
+ return -ENOMEM;
+ strcpy(props->block_name, "iommu");
+ props->max_concurrent = amd_iommu_pc_get_max_banks(0) *
+ amd_iommu_pc_get_max_counters(0); /* assume one iommu */
+ list_add_tail(&props->list, &kdev->perf_props);
+ }
+
+ return 0;
+}
+
+/* kfd_add_non_crat_information - Add information that is not currently
+ * defined in CRAT but is necessary for KFD topology
+ * @dev - topology device to which addition info is added
+ */
+static void kfd_add_non_crat_information(struct kfd_topology_device *kdev)
+{
+ /* Check if CPU only node. */
+ if (!kdev->gpu) {
+ /* Add system memory information */
+ dmi_walk(find_system_memory, kdev);
+ }
+ /* TODO: For GPU node, rearrange code from kfd_topology_add_device */
+}
+
+/* kfd_is_acpi_crat_invalid - CRAT from ACPI is valid only for AMD APU devices.
+ * Ignore CRAT for all other devices. AMD APU is identified if both CPU
+ * and GPU cores are present.
+ * @device_list - topology device list created by parsing ACPI CRAT table.
+ * @return - TRUE if invalid, FALSE is valid.
+ */
+static bool kfd_is_acpi_crat_invalid(struct list_head *device_list)
+{
+ struct kfd_topology_device *dev;
+
+ list_for_each_entry(dev, device_list, list) {
+ if (dev->node_props.cpu_cores_count &&
+ dev->node_props.simd_count)
+ return false;
+ }
+ pr_info("Ignoring ACPI CRAT on non-APU system\n");
+ return true;
+}
+
+int kfd_topology_init(void)
+{
+ void *crat_image = NULL;
+ size_t image_size = 0;
+ int ret;
+ struct list_head temp_topology_device_list;
+ int cpu_only_node = 0;
+ struct kfd_topology_device *kdev;
+ int proximity_domain;
+
+ /* topology_device_list - Master list of all topology devices
+ * temp_topology_device_list - temporary list created while parsing CRAT
+ * or VCRAT. Once parsing is complete the contents of list is moved to
+ * topology_device_list
+ */
+
+ /* Initialize the head for the both the lists */
+ INIT_LIST_HEAD(&topology_device_list);
+ INIT_LIST_HEAD(&temp_topology_device_list);
+ init_rwsem(&topology_lock);
+
+ memset(&sys_props, 0, sizeof(sys_props));
+
+ /* Proximity domains in ACPI CRAT tables start counting at
+ * 0. The same should be true for virtual CRAT tables created
+ * at this stage. GPUs added later in kfd_topology_add_device
+ * use a counter.
+ */
+ proximity_domain = 0;
+
+ /*
+ * Get the CRAT image from the ACPI. If ACPI doesn't have one
+ * or if ACPI CRAT is invalid create a virtual CRAT.
+ * NOTE: The current implementation expects all AMD APUs to have
+ * CRAT. If no CRAT is available, it is assumed to be a CPU
+ */
+ ret = kfd_create_crat_image_acpi(&crat_image, &image_size);
+ if (!ret) {
+ ret = kfd_parse_crat_table(crat_image,
+ &temp_topology_device_list,
+ proximity_domain);
+ if (ret ||
+ kfd_is_acpi_crat_invalid(&temp_topology_device_list)) {
+ kfd_release_topology_device_list(
+ &temp_topology_device_list);
+ kfd_destroy_crat_image(crat_image);
+ crat_image = NULL;
+ }
+ }
+
+ if (!crat_image) {
+ ret = kfd_create_crat_image_virtual(&crat_image, &image_size,
+ COMPUTE_UNIT_CPU, NULL,
+ proximity_domain);
+ cpu_only_node = 1;
+ if (ret) {
+ pr_err("Error creating VCRAT table for CPU\n");
+ return ret;
+ }
+
+ ret = kfd_parse_crat_table(crat_image,
+ &temp_topology_device_list,
+ proximity_domain);
+ if (ret) {
+ pr_err("Error parsing VCRAT table for CPU\n");
+ goto err;
+ }
+ }
+
+ kdev = list_first_entry(&temp_topology_device_list,
+ struct kfd_topology_device, list);
+ kfd_add_perf_to_topology(kdev);
+
+ down_write(&topology_lock);
+ kfd_topology_update_device_list(&temp_topology_device_list,
+ &topology_device_list);
+ atomic_set(&topology_crat_proximity_domain, sys_props.num_devices-1);
+ ret = kfd_topology_update_sysfs();
+ up_write(&topology_lock);
+
+ if (!ret) {
+ sys_props.generation_count++;
+ kfd_update_system_properties();
+ kfd_debug_print_topology();
+ pr_info("Finished initializing topology\n");
+ } else
+ pr_err("Failed to update topology in sysfs ret=%d\n", ret);
+
+ /* For nodes with GPU, this information gets added
+ * when GPU is detected (kfd_topology_add_device).
+ */
+ if (cpu_only_node) {
+ /* Add additional information to CPU only node created above */
+ down_write(&topology_lock);
+ kdev = list_first_entry(&topology_device_list,
+ struct kfd_topology_device, list);
+ up_write(&topology_lock);
+ kfd_add_non_crat_information(kdev);
+ }
+
+err:
+ kfd_destroy_crat_image(crat_image);
+ return ret;
+}
+
+void kfd_topology_shutdown(void)
+{
+ down_write(&topology_lock);
+ kfd_topology_release_sysfs();
+ kfd_release_live_view();
+ up_write(&topology_lock);
}
static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu)
@@ -1082,11 +1042,15 @@
uint32_t buf[7];
uint64_t local_mem_size;
int i;
+ struct kfd_local_mem_info local_mem_info;
if (!gpu)
return 0;
- local_mem_size = gpu->kfd2kgd->get_vmem_size(gpu->kgd);
+ gpu->kfd2kgd->get_local_mem_info(gpu->kgd, &local_mem_info);
+
+ local_mem_size = local_mem_info.local_mem_size_private +
+ local_mem_info.local_mem_size_public;
buf[0] = gpu->pdev->devfn;
buf[1] = gpu->pdev->subsystem_vendor;
@@ -1101,19 +1065,26 @@
return hashout;
}
-
+/* kfd_assign_gpu - Attach @gpu to the correct kfd topology device. If
+ * the GPU device is not already present in the topology device
+ * list then return NULL. This means a new topology device has to
+ * be created for this GPU.
+ * TODO: Rather than assiging @gpu to first topology device withtout
+ * gpu attached, it will better to have more stringent check.
+ */
static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
{
struct kfd_topology_device *dev;
struct kfd_topology_device *out_dev = NULL;
+ down_write(&topology_lock);
list_for_each_entry(dev, &topology_device_list, list)
if (!dev->gpu && (dev->node_props.simd_count > 0)) {
dev->gpu = gpu;
out_dev = dev;
break;
}
-
+ up_write(&topology_lock);
return out_dev;
}
@@ -1125,84 +1096,196 @@
*/
}
+/* kfd_fill_mem_clk_max_info - Since CRAT doesn't have memory clock info,
+ * patch this after CRAT parsing.
+ */
+static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev)
+{
+ struct kfd_mem_properties *mem;
+ struct kfd_local_mem_info local_mem_info;
+
+ if (!dev)
+ return;
+
+ /* Currently, amdgpu driver (amdgpu_mc) deals only with GPUs with
+ * single bank of VRAM local memory.
+ * for dGPUs - VCRAT reports only one bank of Local Memory
+ * for APUs - If CRAT from ACPI reports more than one bank, then
+ * all the banks will report the same mem_clk_max information
+ */
+ dev->gpu->kfd2kgd->get_local_mem_info(dev->gpu->kgd,
+ &local_mem_info);
+
+ list_for_each_entry(mem, &dev->mem_props, list)
+ mem->mem_clk_max = local_mem_info.mem_clk_max;
+}
+
+static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
+{
+ struct kfd_iolink_properties *link;
+
+ if (!dev || !dev->gpu)
+ return;
+
+ /* GPU only creates direck links so apply flags setting to all */
+ if (dev->gpu->device_info->asic_family == CHIP_HAWAII)
+ list_for_each_entry(link, &dev->io_link_props, list)
+ link->flags = CRAT_IOLINK_FLAGS_ENABLED |
+ CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
+ CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+}
+
int kfd_topology_add_device(struct kfd_dev *gpu)
{
uint32_t gpu_id;
struct kfd_topology_device *dev;
- int res;
+ struct kfd_cu_info cu_info;
+ int res = 0;
+ struct list_head temp_topology_device_list;
+ void *crat_image = NULL;
+ size_t image_size = 0;
+ int proximity_domain;
+
+ INIT_LIST_HEAD(&temp_topology_device_list);
gpu_id = kfd_generate_gpu_id(gpu);
pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id);
- down_write(&topology_lock);
- /*
- * Try to assign the GPU to existing topology device (generated from
- * CRAT table
+ proximity_domain = atomic_inc_return(&topology_crat_proximity_domain);
+
+ /* Check to see if this gpu device exists in the topology_device_list.
+ * If so, assign the gpu to that device,
+ * else create a Virtual CRAT for this gpu device and then parse that
+ * CRAT to create a new topology device. Once created assign the gpu to
+ * that topology device
*/
dev = kfd_assign_gpu(gpu);
if (!dev) {
- pr_info("GPU was not found in the current topology. Extending.\n");
- kfd_debug_print_topology();
- dev = kfd_create_topology_device();
- if (!dev) {
- res = -ENOMEM;
+ res = kfd_create_crat_image_virtual(&crat_image, &image_size,
+ COMPUTE_UNIT_GPU, gpu,
+ proximity_domain);
+ if (res) {
+ pr_err("Error creating VCRAT for GPU (ID: 0x%x)\n",
+ gpu_id);
+ return res;
+ }
+ res = kfd_parse_crat_table(crat_image,
+ &temp_topology_device_list,
+ proximity_domain);
+ if (res) {
+ pr_err("Error parsing VCRAT for GPU (ID: 0x%x)\n",
+ gpu_id);
goto err;
}
- dev->gpu = gpu;
- /*
- * TODO: Make a call to retrieve topology information from the
- * GPU vBIOS
- */
+ down_write(&topology_lock);
+ kfd_topology_update_device_list(&temp_topology_device_list,
+ &topology_device_list);
/* Update the SYSFS tree, since we added another topology
* device
*/
- if (kfd_topology_update_sysfs() < 0)
- kfd_topology_release_sysfs();
+ res = kfd_topology_update_sysfs();
+ up_write(&topology_lock);
+ if (!res)
+ sys_props.generation_count++;
+ else
+ pr_err("Failed to update GPU (ID: 0x%x) to sysfs topology. res=%d\n",
+ gpu_id, res);
+ dev = kfd_assign_gpu(gpu);
+ if (WARN_ON(!dev)) {
+ res = -ENODEV;
+ goto err;
+ }
}
dev->gpu_id = gpu_id;
gpu->id = gpu_id;
- dev->node_props.vendor_id = gpu->pdev->vendor;
- dev->node_props.device_id = gpu->pdev->device;
- dev->node_props.location_id = (gpu->pdev->bus->number << 24) +
- (gpu->pdev->devfn & 0xffffff);
- /*
- * TODO: Retrieve max engine clock values from KGD
+
+ /* TODO: Move the following lines to function
+ * kfd_add_non_crat_information
*/
- if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) {
- dev->node_props.capability |= HSA_CAP_DOORBELL_PACKET_TYPE;
- pr_info("Adding doorbell packet type capability\n");
+ /* Fill-in additional information that is not available in CRAT but
+ * needed for the topology
+ */
+
+ dev->gpu->kfd2kgd->get_cu_info(dev->gpu->kgd, &cu_info);
+ dev->node_props.simd_arrays_per_engine =
+ cu_info.num_shader_arrays_per_engine;
+
+ dev->node_props.vendor_id = gpu->pdev->vendor;
+ dev->node_props.device_id = gpu->pdev->device;
+ dev->node_props.location_id = PCI_DEVID(gpu->pdev->bus->number,
+ gpu->pdev->devfn);
+ dev->node_props.max_engine_clk_fcompute =
+ dev->gpu->kfd2kgd->get_max_engine_clock_in_mhz(dev->gpu->kgd);
+ dev->node_props.max_engine_clk_ccompute =
+ cpufreq_quick_get_max(0) / 1000;
+
+ kfd_fill_mem_clk_max_info(dev);
+ kfd_fill_iolink_non_crat_info(dev);
+
+ switch (dev->gpu->device_info->asic_family) {
+ case CHIP_KAVERI:
+ case CHIP_HAWAII:
+ case CHIP_TONGA:
+ dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
+ break;
+ case CHIP_CARRIZO:
+ case CHIP_FIJI:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
+ pr_debug("Adding doorbell packet type capability\n");
+ dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
+ break;
+ default:
+ WARN(1, "Unexpected ASIC family %u",
+ dev->gpu->device_info->asic_family);
}
- res = 0;
+ /* Fix errors in CZ CRAT.
+ * simd_count: Carrizo CRAT reports wrong simd_count, probably
+ * because it doesn't consider masked out CUs
+ * max_waves_per_simd: Carrizo reports wrong max_waves_per_simd
+ * capability flag: Carrizo CRAT doesn't report IOMMU flags
+ */
+ if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) {
+ dev->node_props.simd_count =
+ cu_info.simd_per_cu * cu_info.cu_active_number;
+ dev->node_props.max_waves_per_simd = 10;
+ dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
+ }
-err:
- up_write(&topology_lock);
+ kfd_debug_print_topology();
- if (res == 0)
+ if (!res)
kfd_notify_gpu_change(gpu_id, 1);
-
+err:
+ kfd_destroy_crat_image(crat_image);
return res;
}
int kfd_topology_remove_device(struct kfd_dev *gpu)
{
- struct kfd_topology_device *dev;
+ struct kfd_topology_device *dev, *tmp;
uint32_t gpu_id;
int res = -ENODEV;
down_write(&topology_lock);
- list_for_each_entry(dev, &topology_device_list, list)
+ list_for_each_entry_safe(dev, tmp, &topology_device_list, list)
if (dev->gpu == gpu) {
gpu_id = dev->gpu_id;
kfd_remove_sysfs_node_entry(dev);
kfd_release_topology_device(dev);
+ sys_props.num_devices--;
res = 0;
if (kfd_topology_update_sysfs() < 0)
kfd_topology_release_sysfs();
@@ -1211,28 +1294,32 @@
up_write(&topology_lock);
- if (res == 0)
+ if (!res)
kfd_notify_gpu_change(gpu_id, 0);
return res;
}
-/*
- * When idx is out of bounds, the function will return NULL
+/* kfd_topology_enum_kfd_devices - Enumerate through all devices in KFD
+ * topology. If GPU device is found @idx, then valid kfd_dev pointer is
+ * returned through @kdev
+ * Return - 0: On success (@kdev will be NULL for non GPU nodes)
+ * -1: If end of list
*/
-struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx)
+int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev)
{
struct kfd_topology_device *top_dev;
- struct kfd_dev *device = NULL;
uint8_t device_idx = 0;
+ *kdev = NULL;
down_read(&topology_lock);
list_for_each_entry(top_dev, &topology_device_list, list) {
if (device_idx == idx) {
- device = top_dev->gpu;
- break;
+ *kdev = top_dev->gpu;
+ up_read(&topology_lock);
+ return 0;
}
device_idx++;
@@ -1240,6 +1327,88 @@
up_read(&topology_lock);
- return device;
+ return -1;
}
+
+static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask)
+{
+ const struct cpuinfo_x86 *cpuinfo;
+ int first_cpu_of_numa_node;
+
+ if (!cpumask || cpumask == cpu_none_mask)
+ return -1;
+ first_cpu_of_numa_node = cpumask_first(cpumask);
+ if (first_cpu_of_numa_node >= nr_cpu_ids)
+ return -1;
+ cpuinfo = &cpu_data(first_cpu_of_numa_node);
+
+ return cpuinfo->apicid;
+}
+
+/* kfd_numa_node_to_apic_id - Returns the APIC ID of the first logical processor
+ * of the given NUMA node (numa_node_id)
+ * Return -1 on failure
+ */
+int kfd_numa_node_to_apic_id(int numa_node_id)
+{
+ if (numa_node_id == -1) {
+ pr_warn("Invalid NUMA Node. Use online CPU mask\n");
+ return kfd_cpumask_to_apic_id(cpu_online_mask);
+ }
+ return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id));
+}
+
+#if defined(CONFIG_DEBUG_FS)
+
+int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data)
+{
+ struct kfd_topology_device *dev;
+ unsigned int i = 0;
+ int r = 0;
+
+ down_read(&topology_lock);
+
+ list_for_each_entry(dev, &topology_device_list, list) {
+ if (!dev->gpu) {
+ i++;
+ continue;
+ }
+
+ seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
+ r = dqm_debugfs_hqds(m, dev->gpu->dqm);
+ if (r)
+ break;
+ }
+
+ up_read(&topology_lock);
+
+ return r;
+}
+
+int kfd_debugfs_rls_by_device(struct seq_file *m, void *data)
+{
+ struct kfd_topology_device *dev;
+ unsigned int i = 0;
+ int r = 0;
+
+ down_read(&topology_lock);
+
+ list_for_each_entry(dev, &topology_device_list, list) {
+ if (!dev->gpu) {
+ i++;
+ continue;
+ }
+
+ seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
+ r = pm_debugfs_runlist(m, &dev->gpu->dqm->packets);
+ if (r)
+ break;
+ }
+
+ up_read(&topology_lock);
+
+ return r;
+}
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index c3ddb9b..53fca1f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -39,8 +39,13 @@
#define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
-#define HSA_CAP_RESERVED 0xfffff000
-#define HSA_CAP_DOORBELL_PACKET_TYPE 0x00001000
+#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
+#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12
+#define HSA_CAP_RESERVED 0xffffc000
+
+#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0
+#define HSA_CAP_DOORBELL_TYPE_1_0 0x1
+#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000
struct kfd_node_properties {
uint32_t cpu_cores_count;
@@ -91,8 +96,6 @@
struct attribute attr;
};
-#define KFD_TOPOLOGY_CPU_SIBLINGS 256
-
#define HSA_CACHE_TYPE_DATA 0x00000001
#define HSA_CACHE_TYPE_INSTRUCTION 0x00000002
#define HSA_CACHE_TYPE_CPU 0x00000004
@@ -109,7 +112,7 @@
uint32_t cache_assoc;
uint32_t cache_latency;
uint32_t cache_type;
- uint8_t sibling_map[KFD_TOPOLOGY_CPU_SIBLINGS];
+ uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
struct kobject *kobj;
struct attribute attr;
};
@@ -132,24 +135,36 @@
struct attribute attr;
};
+struct kfd_perf_properties {
+ struct list_head list;
+ char block_name[16];
+ uint32_t max_concurrent;
+ struct attribute_group *attr_group;
+};
+
struct kfd_topology_device {
struct list_head list;
uint32_t gpu_id;
+ uint32_t proximity_domain;
struct kfd_node_properties node_props;
- uint32_t mem_bank_count;
struct list_head mem_props;
uint32_t cache_count;
struct list_head cache_props;
uint32_t io_link_count;
struct list_head io_link_props;
+ struct list_head perf_props;
struct kfd_dev *gpu;
struct kobject *kobj_node;
struct kobject *kobj_mem;
struct kobject *kobj_cache;
struct kobject *kobj_iolink;
+ struct kobject *kobj_perf;
struct attribute attr_gpuid;
struct attribute attr_name;
struct attribute attr_props;
+ uint8_t oem_id[CRAT_OEMID_LENGTH];
+ uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
+ uint32_t oem_revision;
};
struct kfd_system_properties {
@@ -164,6 +179,12 @@
struct attribute attr_props;
};
+struct kfd_topology_device *kfd_create_topology_device(
+ struct list_head *device_list);
+void kfd_release_topology_device_list(struct list_head *device_list);
+extern bool amd_iommu_pc_supported(void);
+extern u8 amd_iommu_pc_get_max_banks(u16 devid);
+extern u8 amd_iommu_pc_get_max_counters(u16 devid);
#endif /* __KFD_TOPOLOGY_H__ */
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index ec3285f..d5d4586 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -9,14 +9,6 @@
support for AMDGPU. This adds required support for Vega and
Raven ASICs.
-config DRM_AMD_DC_PRE_VEGA
- bool "DC support for Polaris and older ASICs"
- default n
- help
- Choose this option to enable the new DC support for older asics
- by default. This includes Polaris, Carrizo, Tonga, Bonaire,
- and Hawaii.
-
config DRM_AMD_DC_FBC
bool "AMD FBC - Enable Frame Buffer Compression"
depends on DRM_AMD_DC
diff --git a/drivers/gpu/drm/amd/display/TODO b/drivers/gpu/drm/amd/display/TODO
index 4646467..357d5964 100644
--- a/drivers/gpu/drm/amd/display/TODO
+++ b/drivers/gpu/drm/amd/display/TODO
@@ -105,3 +105,6 @@
20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI
retimer that we need to program to pass PHY compliance. Currently that's
bypassing the i2c device and goes directly to HW. This should be changed.
+
+21. Remove vector.c from dc/basics. It's used in DDC code which can probably
+be simplified enough to no longer need a vector implementation.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ac93128..f639429 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -59,9 +59,9 @@
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "ivsrcid/irqsrcs_dcn_1_0.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
+#include "soc15ip.h"
#include "soc15_common.h"
#endif
@@ -454,9 +454,9 @@
adev->dm.dc = dc_create(&init_data);
if (adev->dm.dc) {
- DRM_INFO("Display Core initialized!\n");
+ DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
} else {
- DRM_INFO("Display Core failed to initialize!\n");
+ DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
goto error;
}
@@ -652,11 +652,13 @@
{
struct amdgpu_device *adev = handle;
struct amdgpu_display_manager *dm = &adev->dm;
+ int ret = 0;
/* power on hardware */
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
- return 0;
+ ret = amdgpu_dm_display_resume(adev);
+ return ret;
}
int amdgpu_dm_display_resume(struct amdgpu_device *adev)
@@ -815,7 +817,7 @@
static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
- .output_poll_changed = amdgpu_output_poll_changed,
+ .output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = amdgpu_dm_atomic_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
@@ -1058,6 +1060,10 @@
!is_mst_root_connector) {
/* Downstream Port status changed. */
if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
+
+ if (aconnector->fake_enable)
+ aconnector->fake_enable = false;
+
amdgpu_dm_update_connector_after_detect(aconnector);
@@ -1413,7 +1419,7 @@
struct amdgpu_encoder *aencoder = NULL;
struct amdgpu_mode_info *mode_info = &adev->mode_info;
uint32_t link_cnt;
- int32_t total_overlay_planes, total_primary_planes;
+ int32_t total_primary_planes;
link_cnt = dm->dc->caps.max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
@@ -1422,17 +1428,8 @@
}
/* Identify the number of planes to be initialized */
- total_overlay_planes = dm->dc->caps.max_slave_planes;
total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
- /* First initialize overlay planes, index starting after primary planes */
- for (i = (total_overlay_planes - 1); i >= 0; i--) {
- if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
- DRM_ERROR("KMS: Failed to initialize overlay plane\n");
- goto fail;
- }
- }
-
/* Initialize primary planes */
for (i = (total_primary_planes - 1); i >= 0; i--) {
if (initialize_plane(dm, mode_info, i)) {
@@ -1641,7 +1638,6 @@
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- amdgpu_dm_set_irq_funcs(adev);
switch (adev->asic_type) {
case CHIP_BONAIRE:
case CHIP_HAWAII:
@@ -1714,6 +1710,8 @@
return -EINVAL;
}
+ amdgpu_dm_set_irq_funcs(adev);
+
if (adev->mode_info.funcs == NULL)
adev->mode_info.funcs = &dm_display_funcs;
@@ -1729,18 +1727,6 @@
return 0;
}
-struct dm_connector_state {
- struct drm_connector_state base;
-
- enum amdgpu_rmx_type scaling;
- uint8_t underscan_vborder;
- uint8_t underscan_hborder;
- bool underscan_enable;
-};
-
-#define to_dm_connector_state(x)\
- container_of((x), struct dm_connector_state, base)
-
static bool modeset_required(struct drm_crtc_state *crtc_state,
struct dc_stream_state *new_stream,
struct dc_stream_state *old_stream)
@@ -1823,8 +1809,7 @@
return true;
}
static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
- uint64_t *tiling_flags,
- uint64_t *fb_location)
+ uint64_t *tiling_flags)
{
struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
int r = amdgpu_bo_reserve(rbo, false);
@@ -1836,9 +1821,6 @@
return r;
}
- if (fb_location)
- *fb_location = amdgpu_bo_gpu_offset(rbo);
-
if (tiling_flags)
amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
@@ -1849,12 +1831,9 @@
static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
struct dc_plane_state *plane_state,
- const struct amdgpu_framebuffer *amdgpu_fb,
- bool addReq)
+ const struct amdgpu_framebuffer *amdgpu_fb)
{
uint64_t tiling_flags;
- uint64_t fb_location = 0;
- uint64_t chroma_addr = 0;
unsigned int awidth;
const struct drm_framebuffer *fb = &amdgpu_fb->base;
int ret = 0;
@@ -1862,8 +1841,7 @@
ret = get_fb_info(
amdgpu_fb,
- &tiling_flags,
- addReq == true ? &fb_location:NULL);
+ &tiling_flags);
if (ret)
return ret;
@@ -1901,8 +1879,6 @@
if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
- plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
- plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
plane_state->plane_size.grph.surface_size.x = 0;
plane_state->plane_size.grph.surface_size.y = 0;
plane_state->plane_size.grph.surface_size.width = fb->width;
@@ -1915,15 +1891,6 @@
} else {
awidth = ALIGN(fb->width, 64);
plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
- plane_state->address.video_progressive.luma_addr.low_part
- = lower_32_bits(fb_location);
- plane_state->address.video_progressive.luma_addr.high_part
- = upper_32_bits(fb_location);
- chroma_addr = fb_location + (u64)(awidth * fb->height);
- plane_state->address.video_progressive.chroma_addr.low_part
- = lower_32_bits(chroma_addr);
- plane_state->address.video_progressive.chroma_addr.high_part
- = upper_32_bits(chroma_addr);
plane_state->plane_size.video.luma_size.x = 0;
plane_state->plane_size.video.luma_size.y = 0;
plane_state->plane_size.video.luma_size.width = awidth;
@@ -2033,8 +2000,7 @@
static int fill_plane_attributes(struct amdgpu_device *adev,
struct dc_plane_state *dc_plane_state,
struct drm_plane_state *plane_state,
- struct drm_crtc_state *crtc_state,
- bool addrReq)
+ struct drm_crtc_state *crtc_state)
{
const struct amdgpu_framebuffer *amdgpu_fb =
to_amdgpu_framebuffer(plane_state->fb);
@@ -2048,8 +2014,7 @@
ret = fill_plane_attributes_from_fb(
crtc->dev->dev_private,
dc_plane_state,
- amdgpu_fb,
- addrReq);
+ amdgpu_fb);
if (ret)
return ret;
@@ -2092,30 +2057,32 @@
dst.width = stream->timing.h_addressable;
dst.height = stream->timing.v_addressable;
- rmx_type = dm_state->scaling;
- if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
- if (src.width * dst.height <
- src.height * dst.width) {
- /* height needs less upscaling/more downscaling */
- dst.width = src.width *
- dst.height / src.height;
- } else {
- /* width needs less upscaling/more downscaling */
- dst.height = src.height *
- dst.width / src.width;
+ if (dm_state) {
+ rmx_type = dm_state->scaling;
+ if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
+ if (src.width * dst.height <
+ src.height * dst.width) {
+ /* height needs less upscaling/more downscaling */
+ dst.width = src.width *
+ dst.height / src.height;
+ } else {
+ /* width needs less upscaling/more downscaling */
+ dst.height = src.height *
+ dst.width / src.width;
+ }
+ } else if (rmx_type == RMX_CENTER) {
+ dst = src;
}
- } else if (rmx_type == RMX_CENTER) {
- dst = src;
- }
- dst.x = (stream->timing.h_addressable - dst.width) / 2;
- dst.y = (stream->timing.v_addressable - dst.height) / 2;
+ dst.x = (stream->timing.h_addressable - dst.width) / 2;
+ dst.y = (stream->timing.v_addressable - dst.height) / 2;
- if (dm_state->underscan_enable) {
- dst.x += dm_state->underscan_hborder / 2;
- dst.y += dm_state->underscan_vborder / 2;
- dst.width -= dm_state->underscan_hborder;
- dst.height -= dm_state->underscan_vborder;
+ if (dm_state->underscan_enable) {
+ dst.x += dm_state->underscan_hborder / 2;
+ dst.y += dm_state->underscan_vborder / 2;
+ dst.width -= dm_state->underscan_hborder;
+ dst.height -= dm_state->underscan_vborder;
+ }
}
stream->src = src;
@@ -2131,12 +2098,6 @@
{
uint32_t bpc = connector->display_info.bpc;
- /* Limited color depth to 8bit
- * TODO: Still need to handle deep color
- */
- if (bpc > 8)
- bpc = 8;
-
switch (bpc) {
case 0:
/* Temporary Work around, DRM don't parse color depth for
@@ -2224,6 +2185,7 @@
const struct drm_connector *connector)
{
struct dc_crtc_timing *timing_out = &stream->timing;
+ struct dc_transfer_func *tf = dc_create_transfer_func();
memset(timing_out, 0, sizeof(struct dc_crtc_timing));
@@ -2267,13 +2229,9 @@
stream->output_color_space = get_output_color_space(timing_out);
- {
- struct dc_transfer_func *tf = dc_create_transfer_func();
-
- tf->type = TF_TYPE_PREDEFINED;
- tf->tf = TRANSFER_FUNCTION_SRGB;
- stream->out_transfer_func = tf;
- }
+ tf->type = TF_TYPE_PREDEFINED;
+ tf->tf = TRANSFER_FUNCTION_SRGB;
+ stream->out_transfer_func = tf;
}
static void fill_audio_info(struct audio_info *audio_info,
@@ -2380,6 +2338,56 @@
return 0;
}
+static void set_multisync_trigger_params(
+ struct dc_stream_state *stream)
+{
+ if (stream->triggered_crtc_reset.enabled) {
+ stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
+ stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
+ }
+}
+
+static void set_master_stream(struct dc_stream_state *stream_set[],
+ int stream_count)
+{
+ int j, highest_rfr = 0, master_stream = 0;
+
+ for (j = 0; j < stream_count; j++) {
+ if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
+ int refresh_rate = 0;
+
+ refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
+ (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
+ if (refresh_rate > highest_rfr) {
+ highest_rfr = refresh_rate;
+ master_stream = j;
+ }
+ }
+ }
+ for (j = 0; j < stream_count; j++) {
+ if (stream_set[j] && j != master_stream)
+ stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
+ }
+}
+
+static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
+{
+ int i = 0;
+
+ if (context->stream_count < 2)
+ return;
+ for (i = 0; i < context->stream_count ; i++) {
+ if (!context->streams[i])
+ continue;
+ /* TODO: add a function to read AMD VSDB bits and will set
+ * crtc_sync_master.multi_sync_enabled flag
+ * For now its set to false
+ */
+ set_multisync_trigger_params(context->streams[i]);
+ }
+ set_master_stream(context->streams, context->stream_count);
+}
+
static struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
const struct drm_display_mode *drm_mode,
@@ -2393,12 +2401,7 @@
if (aconnector == NULL) {
DRM_ERROR("aconnector is NULL!\n");
- goto drm_connector_null;
- }
-
- if (dm_state == NULL) {
- DRM_ERROR("dm_state is NULL!\n");
- goto dm_state_null;
+ return stream;
}
drm_connector = &aconnector->base;
@@ -2410,18 +2413,18 @@
*/
if (aconnector->mst_port) {
dm_dp_mst_dc_sink_create(drm_connector);
- goto mst_dc_sink_create_done;
+ return stream;
}
if (create_fake_sink(aconnector))
- goto stream_create_fail;
+ return stream;
}
stream = dc_create_stream_for_sink(aconnector->dc_sink);
if (stream == NULL) {
DRM_ERROR("Failed to create stream for sink!\n");
- goto stream_create_fail;
+ return stream;
}
list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
@@ -2447,9 +2450,12 @@
} else {
decide_crtc_timing_for_drm_display_mode(
&mode, preferred_mode,
- dm_state->scaling != RMX_OFF);
+ dm_state ? (dm_state->scaling != RMX_OFF) : false);
}
+ if (!dm_state)
+ drm_mode_set_crtcinfo(&mode, 0);
+
fill_stream_properties_from_drm_display_mode(stream,
&mode, &aconnector->base);
update_stream_scaling_settings(&mode, dm_state, stream);
@@ -2459,10 +2465,8 @@
drm_connector,
aconnector->dc_sink);
-stream_create_fail:
-dm_state_null:
-drm_connector_null:
-mst_dc_sink_create_done:
+ update_stream_signal(stream);
+
return stream;
}
@@ -2530,6 +2534,27 @@
return &state->base;
}
+
+static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
+{
+ enum dc_irq_source irq_source;
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ struct amdgpu_device *adev = crtc->dev->dev_private;
+
+ irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
+ return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
+}
+
+static int dm_enable_vblank(struct drm_crtc *crtc)
+{
+ return dm_set_vblank(crtc, true);
+}
+
+static void dm_disable_vblank(struct drm_crtc *crtc)
+{
+ dm_set_vblank(crtc, false);
+}
+
/* Implemented only the options currently availible for the driver */
static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
.reset = dm_crtc_reset_state,
@@ -2539,6 +2564,8 @@
.page_flip = drm_atomic_helper_page_flip,
.atomic_duplicate_state = dm_crtc_duplicate_state,
.atomic_destroy_state = dm_crtc_destroy_state,
+ .enable_vblank = dm_enable_vblank,
+ .disable_vblank = dm_disable_vblank,
};
static enum drm_connector_status
@@ -2833,7 +2860,7 @@
goto fail;
}
- stream = dc_create_stream_for_sink(dc_sink);
+ stream = create_stream_for_sink(aconnector, mode, NULL);
if (stream == NULL) {
DRM_ERROR("Failed to create stream for sink!\n");
goto fail;
@@ -3044,7 +3071,7 @@
= lower_32_bits(afb->address);
plane_state->address.video_progressive.luma_addr.high_part
= upper_32_bits(afb->address);
- chroma_addr = afb->address + (u64)(awidth * new_state->fb->height);
+ chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
plane_state->address.video_progressive.chroma_addr.low_part
= lower_32_bits(chroma_addr);
plane_state->address.video_progressive.chroma_addr.high_part
@@ -3088,6 +3115,9 @@
if (!dm_plane_state->dc_state)
return 0;
+ if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
+ return -EINVAL;
+
if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
return 0;
@@ -3134,8 +3164,6 @@
switch (aplane->base.type) {
case DRM_PLANE_TYPE_PRIMARY:
- aplane->base.format_default = true;
-
res = drm_universal_plane_init(
dm->adev->ddev,
&aplane->base,
@@ -4042,6 +4070,19 @@
}
}
+/**
+ * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
+ * @crtc_state: the DRM CRTC state
+ * @stream_state: the DC stream state.
+ *
+ * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
+ * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
+ */
+static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
+ struct dc_stream_state *stream_state)
+{
+ stream_state->mode_changed = crtc_state->mode_changed;
+}
static int amdgpu_dm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state,
@@ -4081,11 +4122,8 @@
struct amdgpu_display_manager *dm = &adev->dm;
struct dm_atomic_state *dm_state;
uint32_t i, j;
- uint32_t new_crtcs_count = 0;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
- struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
- struct dc_stream_state *new_stream = NULL;
unsigned long flags;
bool wait_for_vblank = true;
struct drm_connector *connector;
@@ -4115,6 +4153,12 @@
new_crtc_state->active_changed,
new_crtc_state->connectors_changed);
+ /* Copy all transient state flags into dc state */
+ if (dm_new_crtc_state->stream) {
+ amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
+ dm_new_crtc_state->stream);
+ }
+
/* handles headless hotplug case, updating new_state and
* aconnector as needed
*/
@@ -4144,25 +4188,9 @@
continue;
}
-
if (dm_old_crtc_state->stream)
remove_stream(adev, acrtc, dm_old_crtc_state->stream);
-
- /*
- * this loop saves set mode crtcs
- * we needed to enable vblanks once all
- * resources acquired in dc after dc_commit_streams
- */
-
- /*TODO move all this into dm_crtc_state, get rid of
- * new_crtcs array and use old and new atomic states
- * instead
- */
- new_crtcs[new_crtcs_count] = acrtc;
- new_crtcs_count++;
-
- new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
acrtc->enabled = true;
acrtc->hw_mode = new_crtc_state->mode;
crtc->hwmode = new_crtc_state->mode;
@@ -4180,31 +4208,61 @@
* are removed from freesync module
*/
if (adev->dm.freesync_module) {
- for (i = 0; i < new_crtcs_count; i++) {
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
struct amdgpu_dm_connector *aconnector = NULL;
+ struct dm_connector_state *dm_new_con_state = NULL;
+ struct amdgpu_crtc *acrtc = NULL;
+ bool modeset_needed;
- new_crtc_state = drm_atomic_get_new_crtc_state(state,
- &new_crtcs[i]->base);
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+ modeset_needed = modeset_required(
+ new_crtc_state,
+ dm_new_crtc_state->stream,
+ dm_old_crtc_state->stream);
+ /* We add stream to freesync if:
+ * 1. Said stream is not null, and
+ * 2. A modeset is requested. This means that the
+ * stream was removed previously, and needs to be
+ * replaced.
+ */
+ if (dm_new_crtc_state->stream == NULL ||
+ !modeset_needed)
+ continue;
- new_stream = dm_new_crtc_state->stream;
- aconnector = amdgpu_dm_find_first_crtc_matching_connector(
- state,
- &new_crtcs[i]->base);
+ acrtc = to_amdgpu_crtc(crtc);
+
+ aconnector =
+ amdgpu_dm_find_first_crtc_matching_connector(
+ state, crtc);
if (!aconnector) {
- DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
- "skipping freesync init\n",
- new_crtcs[i]->crtc_id);
+ DRM_DEBUG_DRIVER("Atomic commit: Failed to "
+ "find connector for acrtc "
+ "id:%d skipping freesync "
+ "init\n",
+ acrtc->crtc_id);
continue;
}
mod_freesync_add_stream(adev->dm.freesync_module,
- new_stream, &aconnector->caps);
+ dm_new_crtc_state->stream,
+ &aconnector->caps);
+ new_con_state = drm_atomic_get_new_connector_state(
+ state, &aconnector->base);
+ dm_new_con_state = to_dm_connector_state(new_con_state);
+
+ mod_freesync_set_user_enable(adev->dm.freesync_module,
+ &dm_new_crtc_state->stream,
+ 1,
+ &dm_new_con_state->user_enable);
}
}
- if (dm_state->context)
+ if (dm_state->context) {
+ dm_enable_per_frame_crtc_master_sync(dm_state->context);
WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
+ }
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
@@ -4262,18 +4320,28 @@
dm_error("%s: Failed to update stream scaling!\n", __func__);
}
- for (i = 0; i < new_crtcs_count; i++) {
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
/*
* loop to enable interrupts on newly arrived crtc
*/
- struct amdgpu_crtc *acrtc = new_crtcs[i];
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ bool modeset_needed;
- new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+ modeset_needed = modeset_required(
+ new_crtc_state,
+ dm_new_crtc_state->stream,
+ dm_old_crtc_state->stream);
+
+ if (dm_new_crtc_state->stream == NULL || !modeset_needed)
+ continue;
if (adev->dm.freesync_module)
mod_freesync_notify_mode_change(
- adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
+ adev->dm.freesync_module,
+ &dm_new_crtc_state->stream, 1);
manage_dm_interrupts(adev, acrtc, true);
}
@@ -4507,18 +4575,15 @@
__func__, acrtc->base.base.id);
break;
}
+
+ if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
+ dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
+ new_crtc_state->mode_changed = false;
+ DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
+ new_crtc_state->mode_changed);
+ }
}
- if (enable && dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
- dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
-
- new_crtc_state->mode_changed = false;
-
- DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
- new_crtc_state->mode_changed);
- }
-
-
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
goto next_crtc;
@@ -4575,6 +4640,7 @@
WARN_ON(dm_new_crtc_state->stream);
dm_new_crtc_state->stream = new_stream;
+
dc_stream_retain(new_stream);
DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
@@ -4671,6 +4737,7 @@
*lock_and_validation_needed = true;
} else { /* Add new planes */
+ struct dc_plane_state *dc_new_plane_state;
if (drm_atomic_plane_disabling(plane->state, new_plane_state))
continue;
@@ -4690,36 +4757,50 @@
WARN_ON(dm_new_plane_state->dc_state);
- dm_new_plane_state->dc_state = dc_create_plane_state(dc);
+ dc_new_plane_state = dc_create_plane_state(dc);
+ if (!dc_new_plane_state) {
+ ret = -EINVAL;
+ return ret;
+ }
DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
plane->base.id, new_plane_crtc->base.id);
- if (!dm_new_plane_state->dc_state) {
- ret = -EINVAL;
+ ret = fill_plane_attributes(
+ new_plane_crtc->dev->dev_private,
+ dc_new_plane_state,
+ new_plane_state,
+ new_crtc_state);
+ if (ret) {
+ dc_plane_state_release(dc_new_plane_state);
return ret;
}
- ret = fill_plane_attributes(
- new_plane_crtc->dev->dev_private,
- dm_new_plane_state->dc_state,
- new_plane_state,
- new_crtc_state,
- false);
- if (ret)
- return ret;
-
-
+ /*
+ * Any atomic check errors that occur after this will
+ * not need a release. The plane state will be attached
+ * to the stream, and therefore part of the atomic
+ * state. It'll be released when the atomic state is
+ * cleaned.
+ */
if (!dc_add_plane_to_context(
dc,
dm_new_crtc_state->stream,
- dm_new_plane_state->dc_state,
+ dc_new_plane_state,
dm_state->context)) {
+ dc_plane_state_release(dc_new_plane_state);
ret = -EINVAL;
return ret;
}
+ dm_new_plane_state->dc_state = dc_new_plane_state;
+
+ /* Tell DC to do a full surface update every time there
+ * is a plane change. Inefficient, but works for now.
+ */
+ dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
+
*lock_and_validation_needed = true;
}
}
@@ -4744,6 +4825,9 @@
return -EDEADLK;
crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
if (crtc->primary == plane && crtc_state->active) {
if (!plane_state->fb)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 0610acd23..f153eeb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -245,6 +245,18 @@
#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
+struct dm_connector_state {
+ struct drm_connector_state base;
+
+ enum amdgpu_rmx_type scaling;
+ uint8_t underscan_vborder;
+ uint8_t underscan_hborder;
+ bool underscan_enable;
+ struct mod_freesync_user_enable user_enable;
+};
+
+#define to_dm_connector_state(x)\
+ container_of((x), struct dm_connector_state, base)
void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
struct drm_connector_state *
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 9bd142f..e1acc10 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -109,7 +109,7 @@
struct cea_sad *sad = &sads[i];
edid_caps->audio_modes[i].format_code = sad->format;
- edid_caps->audio_modes[i].channel_count = sad->channels;
+ edid_caps->audio_modes[i].channel_count = sad->channels + 1;
edid_caps->audio_modes[i].sample_rate = sad->freq;
edid_caps->audio_modes[i].sample_size = sad->byte2;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index ca5d0d15..4220550 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -683,13 +683,14 @@
void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+
+ adev->crtc_irq.num_types = adev->mode_info.num_crtc;
adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
- adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+ adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
- adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+ adev->hpd_irq.num_types = adev->mode_info.num_hpd;
adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 1c197a6..79a2373 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -201,6 +201,12 @@
.link = aconnector->dc_link,
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
+ /*
+ * TODO: Need to further figure out why ddc.algo is NULL while MST port exists
+ */
+ if (!aconnector->port || !aconnector->port->aux.ddc.algo)
+ return;
+
edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
if (!edid) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5df8fd5..56e5492 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -41,6 +41,10 @@
return 0;
}
+void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
+{
+}
+
bool dm_write_persistent_data(struct dc_context *ctx,
const struct dc_sink *sink,
const char *module_name,
@@ -131,11 +135,12 @@
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
/* TODO: complete implementation of
- * amd_powerplay_display_configuration_change().
+ * pp_display_configuration_change().
* Follow example of:
* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
- amd_powerplay_display_configuration_change(
+ if (adev->powerplay.pp_funcs->display_configuration_change)
+ adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
@@ -264,22 +269,26 @@
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
- if (amd_powerplay_get_clock_by_type(pp_handle,
+ if (adev->powerplay.pp_funcs->get_clock_by_type) {
+ if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), &pp_clks)) {
/* Error in pplib. Provide default values. */
- get_default_clock_levels(clk_type, dc_clks);
- return true;
+ get_default_clock_levels(clk_type, dc_clks);
+ return true;
+ }
}
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
- if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
- &validation_clks)) {
- /* Error in pplib. Provide default values. */
- DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
- validation_clks.engine_max_clock = 72000;
- validation_clks.memory_max_clock = 80000;
- validation_clks.level = 0;
+ if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
+ if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
+ pp_handle, &validation_clks)) {
+ /* Error in pplib. Provide default values. */
+ DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
+ validation_clks.engine_max_clock = 72000;
+ validation_clks.memory_max_clock = 80000;
+ validation_clks.level = 0;
+ }
}
DRM_INFO("DM_PPLIB: Validation clocks:\n");
diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile
index 6af8c8a..bca33bd 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile
@@ -24,7 +24,7 @@
# It provides the general basic services required by other DAL
# subcomponents.
-BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \
+BASICS = conversion.o fixpt31_32.o fixpt32_32.o \
logger.o log_helpers.o vector.o
AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
index 23c9a0e..3109649 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
@@ -46,7 +46,7 @@
arg));
if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
- numerator = (uint16_t)dal_fixed31_32_floor(
+ numerator = (uint16_t)dal_fixed31_32_round(
dal_fixed31_32_mul_int(
arg,
divisor));
diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 2693689..011a97f 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -554,6 +554,22 @@
return result | fractional_part;
}
+static inline uint32_t clamp_ux_dy(
+ int64_t value,
+ uint32_t integer_bits,
+ uint32_t fractional_bits,
+ uint32_t min_clamp)
+{
+ uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits);
+
+ if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))
+ return (1 << (integer_bits + fractional_bits)) - 1;
+ else if (truncated_val > min_clamp)
+ return truncated_val;
+ else
+ return min_clamp;
+}
+
uint32_t dal_fixed31_32_u2d19(
struct fixed31_32 arg)
{
@@ -565,3 +581,15 @@
{
return ux_dy(arg.value, 0, 19);
}
+
+uint32_t dal_fixed31_32_clamp_u0d14(
+ struct fixed31_32 arg)
+{
+ return clamp_ux_dy(arg.value, 0, 14, 1);
+}
+
+uint32_t dal_fixed31_32_clamp_u0d10(
+ struct fixed31_32 arg)
+{
+ return clamp_ux_dy(arg.value, 0, 10, 1);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c b/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c
deleted file mode 100644
index 1478225..0000000
--- a/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/grph_object_id.h"
-
-static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
-{
- bool rc = true;
-
- switch (id.type) {
- case OBJECT_TYPE_UNKNOWN:
- rc = false;
- break;
- case OBJECT_TYPE_GPU:
- case OBJECT_TYPE_ENGINE:
- /* do NOT check for id.id == 0 */
- if (id.enum_id == ENUM_ID_UNKNOWN)
- rc = false;
- break;
- default:
- if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
- rc = false;
- break;
- }
-
- return rc;
-}
-
-bool dal_graphics_object_id_is_equal(
- struct graphics_object_id id1,
- struct graphics_object_id id2)
-{
- if (false == dal_graphics_object_id_is_valid(id1)) {
- dm_output_to_console(
- "%s: Warning: comparing invalid object 'id1'!\n", __func__);
- return false;
- }
-
- if (false == dal_graphics_object_id_is_valid(id2)) {
- dm_output_to_console(
- "%s: Warning: comparing invalid object 'id2'!\n", __func__);
- return false;
- }
-
- if (id1.id == id2.id && id1.enum_id == id2.enum_id
- && id1.type == id2.type)
- return true;
-
- return false;
-}
-
-
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 6e43168..854678a 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -83,15 +83,11 @@
link->link_index);
va_start(args, msg);
- entry.buf_offset += dm_log_to_buffer(
- &entry.buf[entry.buf_offset],
- LOG_MAX_LINE_SIZE - entry.buf_offset,
- msg, args);
+ dm_logger_append_va(&entry, msg, args);
- if (entry.buf[strlen(entry.buf) - 1] == '\n') {
- entry.buf[strlen(entry.buf) - 1] = '\0';
+ if (entry.buf_offset > 0 &&
+ entry.buf[entry.buf_offset - 1] == '\n')
entry.buf_offset--;
- }
if (hex_data)
for (i = 0; i < hex_data_count; i++)
diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index e04e8ec..180a9d6 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -70,9 +70,8 @@
{
/* malloc buffer and init offsets */
logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
- logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char),
- GFP_KERNEL);
-
+ logger->log_buffer = kcalloc(logger->log_buffer_size, sizeof(char),
+ GFP_KERNEL);
if (!logger->log_buffer)
return false;
@@ -313,6 +312,18 @@
const char *msg,
...)
{
+ va_list args;
+
+ va_start(args, msg);
+ dm_logger_append_va(entry, msg, args);
+ va_end(args);
+}
+
+void dm_logger_append_va(
+ struct log_entry *entry,
+ const char *msg,
+ va_list args)
+{
struct dal_logger *logger;
if (!entry) {
@@ -326,11 +337,8 @@
dal_logger_should_log(logger, entry->type)) {
uint32_t size;
- va_list args;
char buffer[LOG_MAX_LINE_SIZE];
- va_start(args, msg);
-
size = dm_log_to_buffer(
buffer, LOG_MAX_LINE_SIZE, msg, args);
@@ -339,8 +347,6 @@
} else {
append_entry(entry, "LOG_ERROR, line too long\n", 27);
}
-
- va_end(args);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 86e6438..c00e405 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -190,6 +190,7 @@
struct bios_parser *bp = BP_FROM_DCB(dcb);
struct graphics_object_id object_id = dal_graphics_object_id_init(
0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
+ uint16_t id;
uint32_t connector_table_offset = bp->object_info_tbl_offset
+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
@@ -197,12 +198,19 @@
ATOM_OBJECT_TABLE *tbl =
GET_IMAGE(ATOM_OBJECT_TABLE, connector_table_offset);
- if (tbl && tbl->ucNumberOfObjects > i) {
- const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-
- object_id = object_id_from_bios_object_id(id);
+ if (!tbl) {
+ dm_error("Can't get connector table from atom bios.\n");
+ return object_id;
}
+ if (tbl->ucNumberOfObjects <= i) {
+ dm_error("Can't find connector id %d in connector table of size %d.\n",
+ i, tbl->ucNumberOfObjects);
+ return object_id;
+ }
+
+ id = le16_to_cpu(tbl->asObjects[i].usObjectID);
+ object_id = object_id_from_bios_object_id(id);
return object_id;
}
@@ -2254,6 +2262,52 @@
return BP_RESULT_OK;
}
+static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
+{
+ bool rc = true;
+
+ switch (id.type) {
+ case OBJECT_TYPE_UNKNOWN:
+ rc = false;
+ break;
+ case OBJECT_TYPE_GPU:
+ case OBJECT_TYPE_ENGINE:
+ /* do NOT check for id.id == 0 */
+ if (id.enum_id == ENUM_ID_UNKNOWN)
+ rc = false;
+ break;
+ default:
+ if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
+ rc = false;
+ break;
+ }
+
+ return rc;
+}
+
+static bool dal_graphics_object_id_is_equal(
+ struct graphics_object_id id1,
+ struct graphics_object_id id2)
+{
+ if (false == dal_graphics_object_id_is_valid(id1)) {
+ dm_output_to_console(
+ "%s: Warning: comparing invalid object 'id1'!\n", __func__);
+ return false;
+ }
+
+ if (false == dal_graphics_object_id_is_valid(id2)) {
+ dm_output_to_console(
+ "%s: Warning: comparing invalid object 'id2'!\n", __func__);
+ return false;
+ }
+
+ if (id1.id == id2.id && id1.enum_id == id2.enum_id
+ && id1.type == id2.type)
+ return true;
+
+ return false;
+}
+
static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
struct graphics_object_id id)
{
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 3f7b2da..4b5fdd5 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -387,6 +387,7 @@
bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
break;
default:
+ dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
bp->cmd_tbl.transmitter_control = NULL;
break;
}
@@ -910,6 +911,8 @@
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
break;
default:
+ dm_output_to_console("Don't have set_pixel_clock for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock));
bp->cmd_tbl.set_pixel_clock = NULL;
break;
}
@@ -1227,6 +1230,8 @@
enable_spread_spectrum_on_ppll_v3;
break;
default:
+ dm_output_to_console("Don't have enable_spread_spectrum_on_ppll for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL));
bp->cmd_tbl.enable_spread_spectrum_on_ppll = NULL;
break;
}
@@ -1422,6 +1427,8 @@
bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v3;
break;
default:
+ dm_output_to_console("Don't have adjust_display_pll for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll));
bp->cmd_tbl.adjust_display_pll = NULL;
break;
}
@@ -1695,6 +1702,8 @@
set_crtc_using_dtd_timing_v3;
break;
default:
+ dm_output_to_console("Don't have set_crtc_timing for dtd v%d\n",
+ dtd_version);
bp->cmd_tbl.set_crtc_timing = NULL;
break;
}
@@ -1704,6 +1713,8 @@
bp->cmd_tbl.set_crtc_timing = set_crtc_timing_v1;
break;
default:
+ dm_output_to_console("Don't have set_crtc_timing for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_Timing));
bp->cmd_tbl.set_crtc_timing = NULL;
break;
}
@@ -1890,6 +1901,8 @@
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
break;
default:
+ dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source));
bp->cmd_tbl.select_crtc_source = NULL;
break;
}
@@ -1997,6 +2010,8 @@
bp->cmd_tbl.enable_crtc = enable_crtc_v1;
break;
default:
+ dm_output_to_console("Don't have enable_crtc for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(EnableCRTC));
bp->cmd_tbl.enable_crtc = NULL;
break;
}
@@ -2103,6 +2118,8 @@
bp->cmd_tbl.program_clock = program_clock_v6;
break;
default:
+ dm_output_to_console("Don't have program_clock for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock));
bp->cmd_tbl.program_clock = NULL;
break;
}
@@ -2324,6 +2341,8 @@
enable_disp_power_gating_v2_1;
break;
default:
+ dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating));
bp->cmd_tbl.enable_disp_power_gating = NULL;
break;
}
@@ -2371,6 +2390,8 @@
bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
break;
default:
+ dm_output_to_console("Don't have set_dce_clock for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(SetDCEClock));
bp->cmd_tbl.set_dce_clock = NULL;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index ba68693..fea5e83 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -118,6 +118,7 @@
bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;
break;
default:
+ dm_output_to_console("Don't have dig_encoder_control for v%d\n", version);
bp->cmd_tbl.dig_encoder_control = NULL;
break;
}
@@ -205,6 +206,7 @@
bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
break;
default:
+ dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
bp->cmd_tbl.transmitter_control = NULL;
break;
}
@@ -268,6 +270,8 @@
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
break;
default:
+ dm_output_to_console("Don't have set_pixel_clock for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));
bp->cmd_tbl.set_pixel_clock = NULL;
break;
}
@@ -379,6 +383,7 @@
set_crtc_using_dtd_timing_v3;
break;
default:
+ dm_output_to_console("Don't have set_crtc_timing for v%d\n", dtd_version);
bp->cmd_tbl.set_crtc_timing = NULL;
break;
}
@@ -498,6 +503,8 @@
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
break;
default:
+ dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source));
bp->cmd_tbl.select_crtc_source = NULL;
break;
}
@@ -565,6 +572,8 @@
bp->cmd_tbl.enable_crtc = enable_crtc_v1;
break;
default:
+ dm_output_to_console("Don't have enable_crtc for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(enablecrtc));
bp->cmd_tbl.enable_crtc = NULL;
break;
}
@@ -661,6 +670,8 @@
enable_disp_power_gating_v2_1;
break;
default:
+ dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating));
bp->cmd_tbl.enable_disp_power_gating = NULL;
break;
}
@@ -710,6 +721,8 @@
bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
break;
default:
+ dm_output_to_console("Don't have set_dce_clock for v%d\n",
+ BIOS_CMD_TABLE_PARA_REVISION(setdceclock));
bp->cmd_tbl.set_dce_clock = NULL;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 320aaacc..bb03a9c 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -29,6 +29,15 @@
#include "core_types.h"
#include "dal_asic_id.h"
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
/*******************************************************************************
* Private Functions
******************************************************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index 626f9cf..5e2ea12 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -27,6 +27,15 @@
#include "dcn_calc_auto.h"
#include "dcn_calc_math.h"
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
/*REVISION#250*/
void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
{
@@ -773,11 +782,11 @@
v->dst_y_after_scaler = 0.0;
}
v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep;
- v->v_update_offset[k] =dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
+ v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0 / (v->required_dispclk[i][j] / (j + 1)) + 3.0 / v->required_dispclk[i][j]);
- v->v_update_width[k] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k];
- v->v_ready_offset[k] =dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k];
- v->time_setup = (v->v_update_offset[k] + v->v_update_width[k] + v->v_ready_offset[k]) / v->pixel_clock[k];
+ v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k];
+ v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k];
+ v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k];
v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i];
if (v->pte_enable == dcn_bw_yes) {
v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0 / v->return_bw_per_state[i];
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
index ae38cdb..7600a4a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -27,6 +27,15 @@
#define isNaN(number) ((number) != (number))
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
float dcn_bw_mod(const float arg1, const float arg2)
{
if (isNaN(arg1))
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index b142629..331891c 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -33,6 +33,15 @@
#include "dcn10/dcn10_resource.h"
#include "dcn_calc_math.h"
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
/* Defaults from spreadsheet rev#247 */
const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
@@ -432,25 +441,13 @@
input.clks_cfg.dcfclk_mhz = v->dcfclk;
input.clks_cfg.dispclk_mhz = v->dispclk;
input.clks_cfg.dppclk_mhz = v->dppclk;
- input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000;
+ input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
input.clks_cfg.socclk_mhz = v->socclk;
input.clks_cfg.voltage = v->voltage_level;
// dc->dml.logger = pool->base.logger;
input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
//input[in_idx].dout.output_standard;
- switch (v->output_deep_color[in_idx]) {
- case dcn_bw_encoder_12bpc:
- input.dout.output_bpc = dm_out_12;
- break;
- case dcn_bw_encoder_10bpc:
- input.dout.output_bpc = dm_out_10;
- break;
- case dcn_bw_encoder_8bpc:
- default:
- input.dout.output_bpc = dm_out_8;
- break;
- }
/*todo: soc->sr_enter_plus_exit_time??*/
dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
@@ -890,6 +887,17 @@
+ pipe->bottom_pipe->plane_res.scl_data.recout.width;
}
+ if (pipe->plane_state->rotation % 2 == 0) {
+ ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+ || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
+ ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+ || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
+ } else {
+ ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+ || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
+ ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+ || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
+ }
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
pipe->plane_state->format);
@@ -1006,9 +1014,9 @@
if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
continue;
- pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
- pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
- pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
+ pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
+ pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
+ pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
@@ -1034,6 +1042,8 @@
if (pipe->plane_state) {
struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
+ pipe->plane_state->update_flags.bits.full_update = 1;
+
if (v->dpp_per_plane[input_idx] == 2 ||
((pipe->stream->view_format ==
VIEW_3D_FORMAT_SIDE_BY_SIDE ||
@@ -1045,9 +1055,9 @@
TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* update previously split pipe */
- hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
- hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
- hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
+ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
+ hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
+ hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
@@ -1073,6 +1083,9 @@
hsplit_pipe->stream = NULL;
hsplit_pipe->top_pipe = NULL;
hsplit_pipe->bottom_pipe = NULL;
+ /* Clear plane_res and stream_res */
+ memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
+ memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
resource_build_scaling_params(pipe);
}
/* for now important to do this after pipe split for building e2e params */
@@ -1240,40 +1253,62 @@
return dcf_clk;
}
+static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
+{
+ int i;
+
+ if (clks->num_levels == 0)
+ return false;
+
+ for (i = 0; i < clks->num_levels; i++)
+ /* Ensure that the result is sane */
+ if (clks->data[i].clocks_in_khz == 0)
+ return false;
+
+ return true;
+}
+
void dcn_bw_update_from_pplib(struct dc *dc)
{
struct dc_context *ctx = dc->ctx;
- struct dm_pp_clock_levels_with_voltage clks = {0};
+ struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
+ bool res;
kernel_fpu_begin();
/* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
+ res = dm_pp_get_clock_levels_by_type_with_voltage(
+ ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
- if (dm_pp_get_clock_levels_by_type_with_voltage(
- ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) &&
- clks.num_levels != 0) {
- ASSERT(clks.num_levels >= 3);
- dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0;
- if (clks.num_levels > 2) {
- dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
- (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
- } else {
- dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
- (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
- }
+ if (res)
+ res = verify_clock_values(&fclks);
+
+ if (res) {
+ ASSERT(fclks.num_levels >= 3);
+ dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
+ dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
+ (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
+ * ddr4_dram_factor_single_Channel / 1000.0;
dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
- (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
+ * ddr4_dram_factor_single_Channel / 1000.0;
dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
- (clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
+ * ddr4_dram_factor_single_Channel / 1000.0;
} else
BREAK_TO_DEBUGGER();
- if (dm_pp_get_clock_levels_by_type_with_voltage(
- ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) &&
- clks.num_levels >= 3) {
- dc->dcn_soc->dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0;
- dc->dcn_soc->dcfclkv_mid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0;
- dc->dcn_soc->dcfclkv_nom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0;
- dc->dcn_soc->dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
+
+ res = dm_pp_get_clock_levels_by_type_with_voltage(
+ ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
+
+ if (res)
+ res = verify_clock_values(&dcfclks);
+
+ if (res && dcfclks.num_levels >= 3) {
+ dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
+ dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
+ dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
+ dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
} else
BREAK_TO_DEBUGGER();
@@ -1550,35 +1585,6 @@
dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
dc->dcn_ip->dcfclk_cstate_latency);
- dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc->socclk;
- dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc->socclk;
- dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc->socclk;
- dc->dml.soc.vmax.socclk_mhz = dc->dcn_soc->socclk;
-
- dc->dml.soc.vmin.dcfclk_mhz = dc->dcn_soc->dcfclkv_min0p65;
- dc->dml.soc.vmid.dcfclk_mhz = dc->dcn_soc->dcfclkv_mid0p72;
- dc->dml.soc.vnom.dcfclk_mhz = dc->dcn_soc->dcfclkv_nom0p8;
- dc->dml.soc.vmax.dcfclk_mhz = dc->dcn_soc->dcfclkv_max0p9;
-
- dc->dml.soc.vmin.dispclk_mhz = dc->dcn_soc->max_dispclk_vmin0p65;
- dc->dml.soc.vmid.dispclk_mhz = dc->dcn_soc->max_dispclk_vmid0p72;
- dc->dml.soc.vnom.dispclk_mhz = dc->dcn_soc->max_dispclk_vnom0p8;
- dc->dml.soc.vmax.dispclk_mhz = dc->dcn_soc->max_dispclk_vmax0p9;
-
- dc->dml.soc.vmin.dppclk_mhz = dc->dcn_soc->max_dppclk_vmin0p65;
- dc->dml.soc.vmid.dppclk_mhz = dc->dcn_soc->max_dppclk_vmid0p72;
- dc->dml.soc.vnom.dppclk_mhz = dc->dcn_soc->max_dppclk_vnom0p8;
- dc->dml.soc.vmax.dppclk_mhz = dc->dcn_soc->max_dppclk_vmax0p9;
-
- dc->dml.soc.vmin.phyclk_mhz = dc->dcn_soc->phyclkv_min0p65;
- dc->dml.soc.vmid.phyclk_mhz = dc->dcn_soc->phyclkv_mid0p72;
- dc->dml.soc.vnom.phyclk_mhz = dc->dcn_soc->phyclkv_nom0p8;
- dc->dml.soc.vmax.phyclk_mhz = dc->dcn_soc->phyclkv_max0p9;
-
- dc->dml.soc.vmin.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
- dc->dml.soc.vmid.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
- dc->dml.soc.vnom.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
- dc->dml.soc.vmax.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3b5b79b..65980b0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -29,6 +29,7 @@
#include "core_status.h"
#include "core_types.h"
#include "hw_sequencer.h"
+#include "dce/dce_hwseq.h"
#include "resource.h"
@@ -54,6 +55,13 @@
/*******************************************************************************
* Private functions
******************************************************************************/
+
+static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
+{
+ if (new > *original)
+ *original = new;
+}
+
static void destroy_links(struct dc *dc)
{
uint32_t i;
@@ -157,7 +165,7 @@
return false;
}
-static bool stream_adjust_vmin_vmax(struct dc *dc,
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state **streams, int num_streams,
int vmin, int vmax)
{
@@ -182,7 +190,7 @@
return ret;
}
-static bool stream_get_crtc_position(struct dc *dc,
+bool dc_stream_get_crtc_position(struct dc *dc,
struct dc_stream_state **streams, int num_streams,
unsigned int *v_pos, unsigned int *nom_v_pos)
{
@@ -207,45 +215,7 @@
return ret;
}
-static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
-{
- int i = 0;
- bool ret = false;
- struct pipe_ctx *pipes;
-
- for (i = 0; i < MAX_PIPES; i++) {
- if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
- pipes = &dc->current_state->res_ctx.pipe_ctx[i];
- dc->hwss.program_gamut_remap(pipes);
- ret = true;
- }
- }
-
- return ret;
-}
-
-static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
-{
- int i = 0;
- bool ret = false;
- struct pipe_ctx *pipes;
-
- for (i = 0; i < MAX_PIPES; i++) {
- if (dc->current_state->res_ctx.pipe_ctx[i].stream
- == stream) {
-
- pipes = &dc->current_state->res_ctx.pipe_ctx[i];
- dc->hwss.program_csc_matrix(pipes,
- stream->output_color_space,
- stream->csc_color_matrix.matrix);
- ret = true;
- }
- }
-
- return ret;
-}
-
-static void set_static_screen_events(struct dc *dc,
+void dc_stream_set_static_screen_events(struct dc *dc,
struct dc_stream_state **streams,
int num_streams,
const struct dc_static_screen_events *events)
@@ -270,177 +240,6 @@
dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
}
-static void set_drive_settings(struct dc *dc,
- struct link_training_settings *lt_settings,
- const struct dc_link *link)
-{
-
- int i;
-
- for (i = 0; i < dc->link_count; i++) {
- if (dc->links[i] == link)
- break;
- }
-
- if (i >= dc->link_count)
- ASSERT_CRITICAL(false);
-
- dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
-}
-
-static void perform_link_training(struct dc *dc,
- struct dc_link_settings *link_setting,
- bool skip_video_pattern)
-{
- int i;
-
- for (i = 0; i < dc->link_count; i++)
- dc_link_dp_perform_link_training(
- dc->links[i],
- link_setting,
- skip_video_pattern);
-}
-
-static void set_preferred_link_settings(struct dc *dc,
- struct dc_link_settings *link_setting,
- struct dc_link *link)
-{
- link->preferred_link_setting = *link_setting;
- dp_retrain_link_dp_test(link, link_setting, false);
-}
-
-static void enable_hpd(const struct dc_link *link)
-{
- dc_link_dp_enable_hpd(link);
-}
-
-static void disable_hpd(const struct dc_link *link)
-{
- dc_link_dp_disable_hpd(link);
-}
-
-
-static void set_test_pattern(
- struct dc_link *link,
- enum dp_test_pattern test_pattern,
- const struct link_training_settings *p_link_settings,
- const unsigned char *p_custom_pattern,
- unsigned int cust_pattern_size)
-{
- if (link != NULL)
- dc_link_dp_set_test_pattern(
- link,
- test_pattern,
- p_link_settings,
- p_custom_pattern,
- cust_pattern_size);
-}
-
-static void set_dither_option(struct dc_stream_state *stream,
- enum dc_dither_option option)
-{
- struct bit_depth_reduction_params params;
- struct dc_link *link = stream->status.link;
- struct pipe_ctx *pipes = NULL;
- int i;
-
- for (i = 0; i < MAX_PIPES; i++) {
- if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
- stream) {
- pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
- break;
- }
- }
-
- memset(¶ms, 0, sizeof(params));
- if (!pipes)
- return;
- if (option > DITHER_OPTION_MAX)
- return;
-
- stream->dither_option = option;
-
- resource_build_bit_depth_reduction_params(stream,
- ¶ms);
- stream->bit_depth_params = params;
- pipes->stream_res.opp->funcs->
- opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms);
-}
-
-void set_dpms(
- struct dc *dc,
- struct dc_stream_state *stream,
- bool dpms_off)
-{
- struct pipe_ctx *pipe_ctx = NULL;
- int i;
-
- for (i = 0; i < MAX_PIPES; i++) {
- if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
- pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
- break;
- }
- }
-
- if (!pipe_ctx) {
- ASSERT(0);
- return;
- }
-
- if (stream->dpms_off != dpms_off) {
- stream->dpms_off = dpms_off;
- if (dpms_off)
- core_link_disable_stream(pipe_ctx,
- KEEP_ACQUIRED_RESOURCE);
- else
- core_link_enable_stream(dc->current_state, pipe_ctx);
- }
-}
-
-static void allocate_dc_stream_funcs(struct dc *dc)
-{
- if (dc->hwss.set_drr != NULL) {
- dc->stream_funcs.adjust_vmin_vmax =
- stream_adjust_vmin_vmax;
- }
-
- dc->stream_funcs.set_static_screen_events =
- set_static_screen_events;
-
- dc->stream_funcs.get_crtc_position =
- stream_get_crtc_position;
-
- dc->stream_funcs.set_gamut_remap =
- set_gamut_remap;
-
- dc->stream_funcs.program_csc_matrix =
- program_csc_matrix;
-
- dc->stream_funcs.set_dither_option =
- set_dither_option;
-
- dc->stream_funcs.set_dpms =
- set_dpms;
-
- dc->link_funcs.set_drive_settings =
- set_drive_settings;
-
- dc->link_funcs.perform_link_training =
- perform_link_training;
-
- dc->link_funcs.set_preferred_link_settings =
- set_preferred_link_settings;
-
- dc->link_funcs.enable_hpd =
- enable_hpd;
-
- dc->link_funcs.disable_hpd =
- disable_hpd;
-
- dc->link_funcs.set_test_pattern =
- set_test_pattern;
-}
-
static void destruct(struct dc *dc)
{
dc_release_state(dc->current_state);
@@ -485,19 +284,17 @@
const struct dc_init_data *init_params)
{
struct dal_logger *logger;
- struct dc_context *dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
- struct bw_calcs_dceip *dc_dceip = kzalloc(sizeof(*dc_dceip),
- GFP_KERNEL);
- struct bw_calcs_vbios *dc_vbios = kzalloc(sizeof(*dc_vbios),
- GFP_KERNEL);
+ struct dc_context *dc_ctx;
+ struct bw_calcs_dceip *dc_dceip;
+ struct bw_calcs_vbios *dc_vbios;
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
- struct dcn_soc_bounding_box *dcn_soc = kzalloc(sizeof(*dcn_soc),
- GFP_KERNEL);
- struct dcn_ip_params *dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
+ struct dcn_soc_bounding_box *dcn_soc;
+ struct dcn_ip_params *dcn_ip;
#endif
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+ dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
if (!dc_dceip) {
dm_error("%s: failed to create dceip\n", __func__);
goto fail;
@@ -505,6 +302,7 @@
dc->bw_dceip = dc_dceip;
+ dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
if (!dc_vbios) {
dm_error("%s: failed to create vbios\n", __func__);
goto fail;
@@ -512,6 +310,7 @@
dc->bw_vbios = dc_vbios;
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
if (!dcn_soc) {
dm_error("%s: failed to create dcn_soc\n", __func__);
goto fail;
@@ -519,6 +318,7 @@
dc->dcn_soc = dcn_soc;
+ dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
if (!dcn_ip) {
dm_error("%s: failed to create dcn_ip\n", __func__);
goto fail;
@@ -527,22 +327,24 @@
dc->dcn_ip = dcn_ip;
#endif
+ dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
if (!dc_ctx) {
dm_error("%s: failed to create ctx\n", __func__);
goto fail;
}
- dc->current_state = dc_create_state();
-
- if (!dc->current_state) {
- dm_error("%s: failed to create validate ctx\n", __func__);
- goto fail;
- }
-
dc_ctx->cgs_device = init_params->cgs_device;
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = dc;
dc_ctx->asic_id = init_params->asic_id;
+ dc->ctx = dc_ctx;
+
+ dc->current_state = dc_create_state();
+
+ if (!dc->current_state) {
+ dm_error("%s: failed to create validate ctx\n", __func__);
+ goto fail;
+ }
/* Create logger */
logger = dal_logger_create(dc_ctx, init_params->log_mask);
@@ -553,11 +355,11 @@
goto fail;
}
dc_ctx->logger = logger;
- dc->ctx = dc_ctx;
- dc->ctx->dce_environment = init_params->dce_environment;
+ dc_ctx->dce_environment = init_params->dce_environment;
dc_version = resource_parse_asic_id(init_params->asic_id);
- dc->ctx->dce_version = dc_version;
+ dc_ctx->dce_version = dc_version;
+
#if defined(CONFIG_DRM_AMD_DC_FBC)
dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr;
#endif
@@ -616,8 +418,6 @@
if (!create_links(dc, init_params->num_virtual_links))
goto fail;
- allocate_dc_stream_funcs(dc);
-
return true;
fail:
@@ -686,6 +486,7 @@
dc->caps.max_links = dc->link_count;
dc->caps.max_audios = dc->res_pool->audio_count;
+ dc->caps.linear_pitch_alignment = 64;
dc->config = init_params->flags;
@@ -712,6 +513,28 @@
*dc = NULL;
}
+static void enable_timing_multisync(
+ struct dc *dc,
+ struct dc_state *ctx)
+{
+ int i = 0, multisync_count = 0;
+ int pipe_count = dc->res_pool->pipe_count;
+ struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
+
+ for (i = 0; i < pipe_count; i++) {
+ if (!ctx->res_ctx.pipe_ctx[i].stream ||
+ !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
+ continue;
+ multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
+ multisync_count++;
+ }
+
+ if (multisync_count > 1) {
+ dc->hwss.enable_per_frame_crtc_position_reset(
+ dc, multisync_count, multisync_pipes);
+ }
+}
+
static void program_timing_sync(
struct dc *dc,
struct dc_state *ctx)
@@ -758,7 +581,7 @@
for (j = 0; j < group_size; j++) {
struct pipe_ctx *temp;
- if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
+ if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
if (j == 0)
break;
@@ -771,7 +594,7 @@
/* remove any other unblanked pipes as they have already been synced */
for (j = j + 1; j < group_size; j++) {
- if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
+ if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
group_size--;
pipe_set[j] = pipe_set[group_size];
j--;
@@ -838,7 +661,7 @@
struct dc_bios *dcb = dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
struct pipe_ctx *pipe;
- int i, j, k, l;
+ int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
disable_dangling_plane(dc, context);
@@ -849,9 +672,44 @@
if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.enable_accelerated_mode(dc);
+ /* re-program planes for existing stream, in case we need to
+ * free up plane resource for later use
+ */
+ for (i = 0; i < context->stream_count; i++) {
+ if (context->streams[i]->mode_changed)
+ continue;
+
+ dc->hwss.apply_ctx_for_surface(
+ dc, context->streams[i],
+ context->stream_status[i].plane_count,
+ context); /* use new pipe config in new context */
+ }
+
+ /* Program hardware */
+ dc->hwss.ready_shared_resources(dc, context);
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ pipe = &context->res_ctx.pipe_ctx[i];
+ dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
+ }
+
+ result = dc->hwss.apply_ctx_to_hw(dc, context);
+
+ if (result != DC_OK)
+ return result;
+
+ if (context->stream_count > 1) {
+ enable_timing_multisync(dc, context);
+ program_timing_sync(dc, context);
+ }
+
+ /* Program all planes within new context*/
for (i = 0; i < context->stream_count; i++) {
const struct dc_sink *sink = context->streams[i]->sink;
+ if (!context->streams[i]->mode_changed)
+ continue;
+
dc->hwss.apply_ctx_for_surface(
dc, context->streams[i],
context->stream_status[i].plane_count,
@@ -880,27 +738,8 @@
context->streams[i]->timing.pix_clk_khz);
}
- dc->hwss.ready_shared_resources(dc, context);
-
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- pipe = &context->res_ctx.pipe_ctx[i];
- dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
- }
- result = dc->hwss.apply_ctx_to_hw(dc, context);
-
- program_timing_sync(dc, context);
-
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
- for (i = 0; i < context->stream_count; i++) {
- for (j = 0; j < MAX_PIPES; j++) {
- pipe = &context->res_ctx.pipe_ctx[j];
-
- if (!pipe->top_pipe && pipe->stream == context->streams[i])
- dc->hwss.pipe_control_lock(dc, pipe, false);
- }
- }
-
dc_release_state(dc->current_state);
dc->current_state = context;
@@ -936,7 +775,6 @@
return (result == DC_OK);
}
-
bool dc_post_update_surfaces_to_stream(struct dc *dc)
{
int i;
@@ -945,9 +783,13 @@
post_surface_trace(dc);
for (i = 0; i < dc->res_pool->pipe_count; i++)
- if (context->res_ctx.pipe_ctx[i].stream == NULL
- || context->res_ctx.pipe_ctx[i].plane_state == NULL)
- dc->hwss.power_down_front_end(dc, i);
+ if (context->res_ctx.pipe_ctx[i].stream == NULL ||
+ context->res_ctx.pipe_ctx[i].plane_state == NULL) {
+ context->res_ctx.pipe_ctx[i].pipe_idx = i;
+ dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
+ }
+
+ dc->optimized_required = false;
/* 3rd param should be true, temp w/a for RV*/
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -1014,6 +856,7 @@
flip_addr[i].address = plane_states[i]->address;
flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
plane_info[i].color_space = plane_states[i]->color_space;
+ plane_info[i].input_tf = plane_states[i]->input_tf;
plane_info[i].format = plane_states[i]->format;
plane_info[i].plane_size = plane_states[i]->plane_size;
plane_info[i].rotation = plane_states[i]->rotation;
@@ -1118,79 +961,100 @@
}
}
-static enum surface_update_type get_plane_info_update_type(
- const struct dc_surface_update *u,
- int surface_index)
+static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
{
- struct dc_plane_info temp_plane_info;
- memset(&temp_plane_info, 0, sizeof(temp_plane_info));
+ union surface_update_flags *update_flags = &u->surface->update_flags;
if (!u->plane_info)
return UPDATE_TYPE_FAST;
- temp_plane_info = *u->plane_info;
+ if (u->plane_info->color_space != u->surface->color_space)
+ update_flags->bits.color_space_change = 1;
- /* Copy all parameters that will cause a full update
- * from current surface, the rest of the parameters
- * from provided plane configuration.
- * Perform memory compare and special validation
- * for those that can cause fast/medium updates
- */
+ if (u->plane_info->input_tf != u->surface->input_tf)
+ update_flags->bits.input_tf_change = 1;
- /* Full update parameters */
- temp_plane_info.color_space = u->surface->color_space;
- temp_plane_info.dcc = u->surface->dcc;
- temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
- temp_plane_info.plane_size = u->surface->plane_size;
- temp_plane_info.rotation = u->surface->rotation;
- temp_plane_info.stereo_format = u->surface->stereo_format;
+ if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
+ update_flags->bits.horizontal_mirror_change = 1;
- if (surface_index == 0)
- temp_plane_info.visible = u->plane_info->visible;
- else
- temp_plane_info.visible = u->surface->visible;
+ if (u->plane_info->rotation != u->surface->rotation)
+ update_flags->bits.rotation_change = 1;
- if (memcmp(u->plane_info, &temp_plane_info,
- sizeof(struct dc_plane_info)) != 0)
- return UPDATE_TYPE_FULL;
+ if (u->plane_info->stereo_format != u->surface->stereo_format)
+ update_flags->bits.stereo_format_change = 1;
+
+ if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
+ update_flags->bits.per_pixel_alpha_change = 1;
+
+ if (u->plane_info->dcc.enable != u->surface->dcc.enable
+ || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
+ || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
+ update_flags->bits.dcc_change = 1;
if (pixel_format_to_bpp(u->plane_info->format) !=
- pixel_format_to_bpp(u->surface->format)) {
+ pixel_format_to_bpp(u->surface->format))
/* different bytes per element will require full bandwidth
* and DML calculation
*/
- return UPDATE_TYPE_FULL;
- }
+ update_flags->bits.bpp_change = 1;
+
+ if (u->gamma && dce_use_lut(u->plane_info->format))
+ update_flags->bits.gamma_change = 1;
if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
sizeof(union dc_tiling_info)) != 0) {
+ update_flags->bits.swizzle_change = 1;
/* todo: below are HW dependent, we should add a hook to
* DCE/N resource and validated there.
*/
- if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
+ if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
/* swizzled mode requires RQ to be setup properly,
* thus need to run DML to calculate RQ settings
*/
- return UPDATE_TYPE_FULL;
- }
+ update_flags->bits.bandwidth_change = 1;
}
+ if (update_flags->bits.rotation_change
+ || update_flags->bits.stereo_format_change
+ || update_flags->bits.gamma_change
+ || update_flags->bits.bpp_change
+ || update_flags->bits.bandwidth_change)
+ return UPDATE_TYPE_FULL;
+
return UPDATE_TYPE_MED;
}
-static enum surface_update_type get_scaling_info_update_type(
+static enum surface_update_type get_scaling_info_update_type(
const struct dc_surface_update *u)
{
+ union surface_update_flags *update_flags = &u->surface->update_flags;
+
if (!u->scaling_info)
return UPDATE_TYPE_FAST;
- if (u->scaling_info->src_rect.width != u->surface->src_rect.width
- || u->scaling_info->src_rect.height != u->surface->src_rect.height
- || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
+ if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
|| u->scaling_info->clip_rect.height != u->surface->clip_rect.height
|| u->scaling_info->dst_rect.width != u->surface->dst_rect.width
- || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
- return UPDATE_TYPE_FULL;
+ || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
+ update_flags->bits.scaling_change = 1;
+
+ if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
+ || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
+ && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
+ || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
+ /* Making dst rect smaller requires a bandwidth change */
+ update_flags->bits.bandwidth_change = 1;
+ }
+
+ if (u->scaling_info->src_rect.width != u->surface->src_rect.width
+ || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
+
+ update_flags->bits.scaling_change = 1;
+ if (u->scaling_info->src_rect.width > u->surface->src_rect.width
+ && u->scaling_info->src_rect.height > u->surface->src_rect.height)
+ /* Making src rect bigger requires a bandwidth change */
+ update_flags->bits.clock_change = 1;
+ }
if (u->scaling_info->src_rect.x != u->surface->src_rect.x
|| u->scaling_info->src_rect.y != u->surface->src_rect.y
@@ -1198,41 +1062,56 @@
|| u->scaling_info->clip_rect.y != u->surface->clip_rect.y
|| u->scaling_info->dst_rect.x != u->surface->dst_rect.x
|| u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
+ update_flags->bits.position_change = 1;
+
+ if (update_flags->bits.clock_change
+ || update_flags->bits.bandwidth_change)
+ return UPDATE_TYPE_FULL;
+
+ if (update_flags->bits.scaling_change
+ || update_flags->bits.position_change)
return UPDATE_TYPE_MED;
return UPDATE_TYPE_FAST;
}
-static enum surface_update_type det_surface_update(
- const struct dc *dc,
- const struct dc_surface_update *u,
- int surface_index)
+static enum surface_update_type det_surface_update(const struct dc *dc,
+ const struct dc_surface_update *u)
{
const struct dc_state *context = dc->current_state;
- enum surface_update_type type = UPDATE_TYPE_FAST;
+ enum surface_update_type type;
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
+ union surface_update_flags *update_flags = &u->surface->update_flags;
- if (!is_surface_in_context(context, u->surface))
+ update_flags->raw = 0; // Reset all flags
+
+ if (!is_surface_in_context(context, u->surface)) {
+ update_flags->bits.new_plane = 1;
return UPDATE_TYPE_FULL;
+ }
- type = get_plane_info_update_type(u, surface_index);
- if (overall_type < type)
- overall_type = type;
+ type = get_plane_info_update_type(u);
+ elevate_update_type(&overall_type, type);
type = get_scaling_info_update_type(u);
- if (overall_type < type)
- overall_type = type;
+ elevate_update_type(&overall_type, type);
- if (u->in_transfer_func ||
- u->hdr_static_metadata) {
- if (overall_type < UPDATE_TYPE_MED)
- overall_type = UPDATE_TYPE_MED;
+ if (u->in_transfer_func)
+ update_flags->bits.in_transfer_func_change = 1;
+
+ if (u->input_csc_color_matrix)
+ update_flags->bits.input_csc_change = 1;
+
+ if (update_flags->bits.in_transfer_func_change
+ || update_flags->bits.input_csc_change) {
+ type = UPDATE_TYPE_MED;
+ elevate_update_type(&overall_type, type);
}
return overall_type;
}
-enum surface_update_type dc_check_update_surfaces_for_stream(
+static enum surface_update_type check_update_surfaces_for_stream(
struct dc *dc,
struct dc_surface_update *updates,
int surface_count,
@@ -1250,18 +1129,38 @@
for (i = 0 ; i < surface_count; i++) {
enum surface_update_type type =
- det_surface_update(dc, &updates[i], i);
+ det_surface_update(dc, &updates[i]);
if (type == UPDATE_TYPE_FULL)
return type;
- if (overall_type < type)
- overall_type = type;
+ elevate_update_type(&overall_type, type);
}
return overall_type;
}
+enum surface_update_type dc_check_update_surfaces_for_stream(
+ struct dc *dc,
+ struct dc_surface_update *updates,
+ int surface_count,
+ struct dc_stream_update *stream_update,
+ const struct dc_stream_status *stream_status)
+{
+ int i;
+ enum surface_update_type type;
+
+ for (i = 0; i < surface_count; i++)
+ updates[i].surface->update_flags.raw = 0;
+
+ type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
+ if (type == UPDATE_TYPE_FULL)
+ for (i = 0; i < surface_count; i++)
+ updates[i].surface->update_flags.bits.full_update = 1;
+
+ return type;
+}
+
static struct dc_stream_status *stream_get_status(
struct dc_state *ctx,
struct dc_stream_state *stream)
@@ -1295,14 +1194,6 @@
context_clock_trace(dc, context);
}
- if (update_type > UPDATE_TYPE_FAST) {
- for (j = 0; j < dc->res_pool->pipe_count; j++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-
- dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
- }
- }
-
if (surface_count == 0) {
/*
* In case of turning off screen, no need to program front end a second time.
@@ -1312,103 +1203,58 @@
return;
}
- /* Lock pipes for provided surfaces, or all active if full update*/
- for (i = 0; i < surface_count; i++) {
- struct dc_plane_state *plane_state = srf_updates[i].surface;
-
- for (j = 0; j < dc->res_pool->pipe_count; j++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-
- if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state)
- continue;
- if (!pipe_ctx->plane_state || pipe_ctx->top_pipe)
- continue;
-
- dc->hwss.pipe_control_lock(
- dc,
- pipe_ctx,
- true);
- }
- if (update_type == UPDATE_TYPE_FULL)
- break;
- }
-
/* Full fe update*/
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
- if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state)
+ if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state)
continue;
- if (!pipe_ctx->top_pipe && pipe_ctx->stream) {
- struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream);
+ if (!pipe_ctx->top_pipe &&
+ pipe_ctx->stream &&
+ pipe_ctx->stream == stream) {
+ struct dc_stream_status *stream_status =
+ stream_get_status(context, pipe_ctx->stream);
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, stream_status->plane_count, context);
}
}
- if (update_type > UPDATE_TYPE_FAST)
+ if (update_type == UPDATE_TYPE_FULL)
context_timing_trace(dc, &context->res_ctx);
/* Perform requested Updates */
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
- if (update_type == UPDATE_TYPE_MED)
- dc->hwss.apply_ctx_for_surface(
- dc, stream, surface_count, context);
-
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+ if (pipe_ctx->stream != stream)
+ continue;
+
if (pipe_ctx->plane_state != plane_state)
continue;
- if (srf_updates[i].flip_addr)
- dc->hwss.update_plane_addr(dc, pipe_ctx);
+ if (update_type == UPDATE_TYPE_FAST && srf_updates[i].flip_addr)
+ dc->hwss.update_plane_addr(dc, pipe_ctx);
+ }
+ }
- if (update_type == UPDATE_TYPE_FAST)
+ if (stream && stream_update && update_type > UPDATE_TYPE_FAST)
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ struct pipe_ctx *pipe_ctx =
+ &context->res_ctx.pipe_ctx[j];
+
+ if (pipe_ctx->stream != stream)
continue;
- /* work around to program degamma regs for split pipe after set mode. */
- if (srf_updates[i].in_transfer_func || (pipe_ctx->top_pipe &&
- pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state))
- dc->hwss.set_input_transfer_func(
- pipe_ctx, pipe_ctx->plane_state);
-
- if (stream_update != NULL &&
- stream_update->out_transfer_func != NULL) {
- dc->hwss.set_output_transfer_func(
- pipe_ctx, pipe_ctx->stream);
- }
-
- if (srf_updates[i].hdr_static_metadata) {
+ if (stream_update->hdr_static_metadata) {
resource_build_info_frame(pipe_ctx);
dc->hwss.update_info_frame(pipe_ctx);
}
}
- }
-
- /* Unlock pipes */
- for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
- for (j = 0; j < surface_count; j++) {
- if (update_type != UPDATE_TYPE_FULL &&
- srf_updates[j].surface != pipe_ctx->plane_state)
- continue;
- if (!pipe_ctx->plane_state || pipe_ctx->top_pipe)
- continue;
-
- dc->hwss.pipe_control_lock(
- dc,
- pipe_ctx,
- false);
-
- break;
- }
- }
}
void dc_commit_updates_for_stream(struct dc *dc,
@@ -1517,13 +1363,13 @@
return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
}
-void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
+bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
{
if (dc == NULL)
- return;
+ return false;
- dal_irq_service_set(dc->res_pool->irqs, src, enable);
+ return dal_irq_service_set(dc->res_pool->irqs, src, enable);
}
void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 43c7a7f..1babac0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -159,6 +159,7 @@
"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
"plane_state->tiling_info.gfx8.array_mode = %d;\n"
"plane_state->color_space = %d;\n"
+ "plane_state->input_tf = %d;\n"
"plane_state->dcc.enable = %d;\n"
"plane_state->format = %d;\n"
"plane_state->rotation = %d;\n"
@@ -166,6 +167,7 @@
plane_state->tiling_info.gfx8.pipe_config,
plane_state->tiling_info.gfx8.array_mode,
plane_state->color_space,
+ plane_state->input_tf,
plane_state->dcc.enable,
plane_state->format,
plane_state->rotation,
@@ -206,6 +208,7 @@
if (update->plane_info) {
SURFACE_TRACE(
"plane_info->color_space = %d;\n"
+ "plane_info->input_tf = %d;\n"
"plane_info->format = %d;\n"
"plane_info->plane_size.grph.surface_pitch = %d;\n"
"plane_info->plane_size.grph.surface_size.height = %d;\n"
@@ -214,6 +217,7 @@
"plane_info->plane_size.grph.surface_size.y = %d;\n"
"plane_info->rotation = %d;\n",
update->plane_info->color_space,
+ update->plane_info->input_tf,
update->plane_info->format,
update->plane_info->plane_size.grph.surface_pitch,
update->plane_info->plane_size.grph.surface_size.height,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 94c1fe8..481f6928 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -28,6 +28,8 @@
#include "timing_generator.h"
#include "hw_sequencer.h"
+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
/* used as index in array of black_color_format */
enum black_color_format {
BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
@@ -38,6 +40,15 @@
BLACK_COLOR_FORMAT_DEBUG,
};
+enum dc_color_space_type {
+ COLOR_SPACE_RGB_TYPE,
+ COLOR_SPACE_RGB_LIMITED_TYPE,
+ COLOR_SPACE_YCBCR601_TYPE,
+ COLOR_SPACE_YCBCR709_TYPE,
+ COLOR_SPACE_YCBCR601_LIMITED_TYPE,
+ COLOR_SPACE_YCBCR709_LIMITED_TYPE
+};
+
static const struct tg_color black_color_format[] = {
/* BlackColorFormat_RGB_FullRange */
{0, 0, 0},
@@ -53,6 +64,140 @@
{0xff, 0xff, 0},
};
+struct out_csc_color_matrix_type {
+ enum dc_color_space_type color_space_type;
+ uint16_t regval[12];
+};
+
+static const struct out_csc_color_matrix_type output_csc_matrix[] = {
+ { COLOR_SPACE_RGB_TYPE,
+ { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+ { COLOR_SPACE_RGB_LIMITED_TYPE,
+ { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} },
+ { COLOR_SPACE_YCBCR601_TYPE,
+ { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 0xFB45,
+ 0xF6B7, 0xE04, 0x1004} },
+ { COLOR_SPACE_YCBCR709_TYPE,
+ { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA,
+ 0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} },
+
+ /* TODO: correct values below */
+ { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
+ { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
+ 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
+ { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
+ { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
+ 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
+};
+
+static bool is_rgb_type(
+ enum dc_color_space color_space)
+{
+ bool ret = false;
+
+ if (color_space == COLOR_SPACE_SRGB ||
+ color_space == COLOR_SPACE_XR_RGB ||
+ color_space == COLOR_SPACE_MSREF_SCRGB ||
+ color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
+ color_space == COLOR_SPACE_ADOBERGB ||
+ color_space == COLOR_SPACE_DCIP3 ||
+ color_space == COLOR_SPACE_DOLBYVISION)
+ ret = true;
+ return ret;
+}
+
+static bool is_rgb_limited_type(
+ enum dc_color_space color_space)
+{
+ bool ret = false;
+
+ if (color_space == COLOR_SPACE_SRGB_LIMITED ||
+ color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
+ ret = true;
+ return ret;
+}
+
+static bool is_ycbcr601_type(
+ enum dc_color_space color_space)
+{
+ bool ret = false;
+
+ if (color_space == COLOR_SPACE_YCBCR601 ||
+ color_space == COLOR_SPACE_XV_YCC_601)
+ ret = true;
+ return ret;
+}
+
+static bool is_ycbcr601_limited_type(
+ enum dc_color_space color_space)
+{
+ bool ret = false;
+
+ if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
+ ret = true;
+ return ret;
+}
+
+static bool is_ycbcr709_type(
+ enum dc_color_space color_space)
+{
+ bool ret = false;
+
+ if (color_space == COLOR_SPACE_YCBCR709 ||
+ color_space == COLOR_SPACE_XV_YCC_709)
+ ret = true;
+ return ret;
+}
+
+static bool is_ycbcr709_limited_type(
+ enum dc_color_space color_space)
+{
+ bool ret = false;
+
+ if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
+ ret = true;
+ return ret;
+}
+enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
+{
+ enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
+
+ if (is_rgb_type(color_space))
+ type = COLOR_SPACE_RGB_TYPE;
+ else if (is_rgb_limited_type(color_space))
+ type = COLOR_SPACE_RGB_LIMITED_TYPE;
+ else if (is_ycbcr601_type(color_space))
+ type = COLOR_SPACE_YCBCR601_TYPE;
+ else if (is_ycbcr709_type(color_space))
+ type = COLOR_SPACE_YCBCR709_TYPE;
+ else if (is_ycbcr601_limited_type(color_space))
+ type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
+ else if (is_ycbcr709_limited_type(color_space))
+ type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
+
+ return type;
+}
+
+const uint16_t *find_color_matrix(enum dc_color_space color_space,
+ uint32_t *array_size)
+{
+ int i;
+ enum dc_color_space_type type;
+ const uint16_t *val = NULL;
+ int arr_size = NUM_ELEMENTS(output_csc_matrix);
+
+ type = get_color_space_type(color_space);
+ for (i = 0; i < arr_size; i++)
+ if (output_csc_matrix[i].color_space_type == type) {
+ val = output_csc_matrix[i].regval;
+ *array_size = 12;
+ break;
+ }
+
+ return val;
+}
+
+
void color_space_to_black_color(
const struct dc *dc,
enum dc_color_space colorspace,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 92559d7..dbc8b52 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -677,8 +677,6 @@
case EDID_NO_RESPONSE:
dm_logger_write(link->ctx->logger, LOG_ERROR,
"No EDID read.\n");
- return false;
-
default:
break;
}
@@ -938,8 +936,9 @@
link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
- dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d!\n",
- __func__, init_params->connector_index);
+ dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
+ __func__, init_params->connector_index,
+ link->link_id.type, OBJECT_TYPE_CONNECTOR);
goto create_fail;
}
@@ -1271,6 +1270,24 @@
return status;
}
+static enum dc_status enable_link_edp(
+ struct dc_state *state,
+ struct pipe_ctx *pipe_ctx)
+{
+ enum dc_status status;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dc_link *link = stream->sink->link;
+
+ link->dc->hwss.edp_power_control(link, true);
+ link->dc->hwss.edp_wait_for_hpd_ready(link, true);
+
+ status = enable_link_dp(state, pipe_ctx);
+
+ link->dc->hwss.edp_backlight_control(link, true);
+
+ return status;
+}
+
static enum dc_status enable_link_dp_mst(
struct dc_state *state,
struct pipe_ctx *pipe_ctx)
@@ -1730,8 +1747,7 @@
link->link_enc,
pipe_ctx->clock_source->id,
display_color_depth,
- pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
- pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
+ pipe_ctx->stream->signal,
stream->phy_pix_clk);
if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
@@ -1746,9 +1762,11 @@
enum dc_status status = DC_ERROR_UNEXPECTED;
switch (pipe_ctx->stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
- case SIGNAL_TYPE_EDP:
status = enable_link_dp(state, pipe_ctx);
break;
+ case SIGNAL_TYPE_EDP:
+ status = enable_link_edp(state, pipe_ctx);
+ break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
status = enable_link_dp_mst(state, pipe_ctx);
msleep(200);
@@ -1798,7 +1816,7 @@
else
dp_disable_link_phy_mst(link, signal);
} else
- link->link_enc->funcs->disable_output(link->link_enc, signal, link);
+ link->link_enc->funcs->disable_output(link->link_enc, signal);
}
static bool dp_active_dongle_validate_timing(
@@ -1871,7 +1889,7 @@
const struct dc_crtc_timing *timing)
{
uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
- struct dc_dongle_caps *dongle_caps = &link->link_status.dpcd_caps->dongle_caps;
+ struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
/* A hack to avoid failing any modes for EDID override feature on
* topology change such as lower quality cable for DP or different dongle
@@ -1909,12 +1927,18 @@
{
struct dc *core_dc = link->ctx->dc;
struct abm *abm = core_dc->res_pool->abm;
+ struct dmcu *dmcu = core_dc->res_pool->dmcu;
unsigned int controller_id = 0;
+ bool use_smooth_brightness = true;
int i;
- if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
+ if ((dmcu == NULL) ||
+ (abm == NULL) ||
+ (abm->funcs->set_backlight_level == NULL))
return false;
+ use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
+
dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,
"New Backlight level: %d (0x%X)\n", level, level);
@@ -1937,7 +1961,8 @@
abm,
level,
frame_ramp,
- controller_id);
+ controller_id,
+ use_smooth_brightness);
}
return true;
@@ -2282,6 +2307,9 @@
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
deallocate_mst_payload(pipe_ctx);
+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+ core_dc->hwss.edp_backlight_control(pipe_ctx->stream->sink->link, false);
+
core_dc->hwss.disable_stream(pipe_ctx, option);
disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 08100de..2961c7ed 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -220,8 +220,7 @@
size_in_bytes);
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
- "%s:\n %x VS set = %x PE set = %x \
- max VS Reached = %x max PE Reached = %x\n",
+ "%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
__func__,
DP_TRAINING_LANE0_SET,
dpcd_lane[0].bits.VOLTAGE_SWING_SET,
@@ -558,8 +557,7 @@
*/
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
- "%s\n %x VS set = %x PE set = %x \
- max VS Reached = %x max PE Reached = %x\n",
+ "%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
__func__,
DP_TRAINING_LANE0_SET,
dpcd_lane[0].bits.VOLTAGE_SWING_SET,
@@ -872,9 +870,8 @@
if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
ASSERT(0);
dm_logger_write(link->ctx->logger, LOG_ERROR,
- "%s: Link Training Error, could not \
- get CR after %d tries. \
- Possibly voltage swing issue", __func__,
+ "%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
+ __func__,
LINK_TRAINING_MAX_CR_RETRY);
}
@@ -1468,7 +1465,13 @@
/* MST doesn't perform link training for now
* TODO: add MST specific link training routine
*/
- if (is_mst_supported(link)) {
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ *link_setting = link->verified_link_cap;
+ return;
+ }
+
+ /* EDP use the link cap setting */
+ if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
*link_setting = link->verified_link_cap;
return;
}
@@ -2127,7 +2130,7 @@
union dwnstream_port_caps_byte3_hdmi
hdmi_caps = {.raw = det_caps[3] };
- union dwnstream_port_caps_byte1
+ union dwnstream_port_caps_byte2
hdmi_color_caps = {.raw = det_caps[2] };
link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
det_caps[1] * 25000;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 9a33b47..2096f2a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -88,15 +88,7 @@
}
if (dc_is_dp_sst_signal(signal)) {
- if (signal == SIGNAL_TYPE_EDP) {
- link->dc->hwss.edp_power_control(link->link_enc, true);
- link_enc->funcs->enable_dp_output(
- link_enc,
- link_settings,
- clock_source);
- link->dc->hwss.edp_backlight_control(link, true);
- } else
- link_enc->funcs->enable_dp_output(
+ link_enc->funcs->enable_dp_output(
link_enc,
link_settings,
clock_source);
@@ -138,12 +130,11 @@
dp_receiver_power_ctrl(link, false);
if (signal == SIGNAL_TYPE_EDP) {
- link->dc->hwss.edp_backlight_control(link, false);
edp_receiver_ready_T9(link);
- link->link_enc->funcs->disable_output(link->link_enc, signal, link);
- link->dc->hwss.edp_power_control(link->link_enc, false);
+ link->link_enc->funcs->disable_output(link->link_enc, signal);
+ link->dc->hwss.edp_power_control(link, false);
} else
- link->link_enc->funcs->disable_output(link->link_enc, signal, link);
+ link->link_enc->funcs->disable_output(link->link_enc, signal);
/* Clear current link setting.*/
memset(&link->cur_link_settings, 0,
@@ -286,8 +277,7 @@
link->link_enc->funcs->disable_output(
link->link_enc,
- SIGNAL_TYPE_DISPLAY_PORT,
- link);
+ SIGNAL_TYPE_DISPLAY_PORT);
/* Clear current link setting. */
memset(&link->cur_link_settings, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9288958..4d07ffe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -426,15 +426,8 @@
static void rect_swap_helper(struct rect *rect)
{
- uint32_t temp = 0;
-
- temp = rect->height;
- rect->height = rect->width;
- rect->width = temp;
-
- temp = rect->x;
- rect->x = rect->y;
- rect->y = temp;
+ swap(rect->height, rect->width);
+ swap(rect->x, rect->y);
}
static void calculate_viewport(struct pipe_ctx *pipe_ctx)
@@ -505,26 +498,15 @@
data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
/* Handle hsplit */
- if (pri_split || sec_split) {
- /* HMirror XOR Secondary_pipe XOR Rotation_180 */
- bool right_view = (sec_split != plane_state->horizontal_mirror) !=
- (plane_state->rotation == ROTATION_ANGLE_180);
-
- if (plane_state->rotation == ROTATION_ANGLE_90
- || plane_state->rotation == ROTATION_ANGLE_270)
- /* Secondary_pipe XOR Rotation_270 */
- right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
-
- if (right_view) {
- data->viewport.x += data->viewport.width / 2;
- data->viewport_c.x += data->viewport_c.width / 2;
- /* Ceil offset pipe */
- data->viewport.width = (data->viewport.width + 1) / 2;
- data->viewport_c.width = (data->viewport_c.width + 1) / 2;
- } else {
- data->viewport.width /= 2;
- data->viewport_c.width /= 2;
- }
+ if (sec_split) {
+ data->viewport.x += data->viewport.width / 2;
+ data->viewport_c.x += data->viewport_c.width / 2;
+ /* Ceil offset pipe */
+ data->viewport.width = (data->viewport.width + 1) / 2;
+ data->viewport_c.width = (data->viewport_c.width + 1) / 2;
+ } else if (pri_split) {
+ data->viewport.width /= 2;
+ data->viewport_c.width /= 2;
}
if (plane_state->rotation == ROTATION_ANGLE_90 ||
@@ -541,6 +523,11 @@
struct rect surf_src = plane_state->src_rect;
struct rect surf_clip = plane_state->clip_rect;
int recout_full_x, recout_full_y;
+ bool pri_split = pipe_ctx->bottom_pipe &&
+ pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
+ bool sec_split = pipe_ctx->top_pipe &&
+ pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
+ bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
@@ -575,33 +562,43 @@
- pipe_ctx->plane_res.scl_data.recout.y;
/* Handle h & vsplit */
- if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
- pipe_ctx->plane_state) {
- if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
- pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2;
- /* Floor primary pipe, ceil 2ndary pipe */
- pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
- } else {
- pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2;
- pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
- }
- } else if (pipe_ctx->bottom_pipe &&
- pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
- if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
- pipe_ctx->plane_res.scl_data.recout.height /= 2;
- else
- pipe_ctx->plane_res.scl_data.recout.width /= 2;
- }
+ if (sec_split && top_bottom_split) {
+ pipe_ctx->plane_res.scl_data.recout.y +=
+ pipe_ctx->plane_res.scl_data.recout.height / 2;
+ /* Floor primary pipe, ceil 2ndary pipe */
+ pipe_ctx->plane_res.scl_data.recout.height =
+ (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
+ } else if (pri_split && top_bottom_split)
+ pipe_ctx->plane_res.scl_data.recout.height /= 2;
+ else if (pri_split || sec_split) {
+ /* HMirror XOR Secondary_pipe XOR Rotation_180 */
+ bool right_view = (sec_split != plane_state->horizontal_mirror) !=
+ (plane_state->rotation == ROTATION_ANGLE_180);
+ if (plane_state->rotation == ROTATION_ANGLE_90
+ || plane_state->rotation == ROTATION_ANGLE_270)
+ /* Secondary_pipe XOR Rotation_270 */
+ right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
+
+ if (right_view) {
+ pipe_ctx->plane_res.scl_data.recout.x +=
+ pipe_ctx->plane_res.scl_data.recout.width / 2;
+ /* Ceil offset pipe */
+ pipe_ctx->plane_res.scl_data.recout.width =
+ (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
+ } else {
+ pipe_ctx->plane_res.scl_data.recout.width /= 2;
+ }
+ }
/* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
* * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
* ratio)
*/
- recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
+ recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
* stream->dst.width / stream->src.width -
surf_src.x * plane_state->dst_rect.width / surf_src.width
* stream->dst.width / stream->src.width;
- recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
+ recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
* stream->dst.height / stream->src.height -
surf_src.y * plane_state->dst_rect.height / surf_src.height
* stream->dst.height / stream->src.height;
@@ -657,7 +654,20 @@
struct rect src = pipe_ctx->plane_state->src_rect;
int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
+ bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
+ /*
+ * Need to calculate the scan direction for viewport to make adjustments
+ */
+ if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
+ flip_vert_scan_dir = true;
+ flip_horz_scan_dir = true;
+ } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
+ flip_vert_scan_dir = true;
+ else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
+ flip_horz_scan_dir = true;
+ if (pipe_ctx->plane_state->horizontal_mirror)
+ flip_horz_scan_dir = !flip_horz_scan_dir;
if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
@@ -722,7 +732,7 @@
}
/* Adjust for non-0 viewport offset */
- if (data->viewport.x) {
+ if (data->viewport.x && !flip_horz_scan_dir) {
int int_part;
data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
@@ -743,7 +753,7 @@
data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
}
- if (data->viewport_c.x) {
+ if (data->viewport_c.x && !flip_horz_scan_dir) {
int int_part;
data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
@@ -764,7 +774,7 @@
data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
}
- if (data->viewport.y) {
+ if (data->viewport.y && !flip_vert_scan_dir) {
int int_part;
data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
@@ -785,7 +795,7 @@
data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
}
- if (data->viewport_c.y) {
+ if (data->viewport_c.y && !flip_vert_scan_dir) {
int int_part;
data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
@@ -1350,9 +1360,6 @@
return true;
}
-/* Maximum TMDS single link pixel clock 165MHz */
-#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
-
static void update_stream_engine_usage(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -2319,20 +2326,13 @@
static void set_hdr_static_info_packet(
struct encoder_info_packet *info_packet,
- struct dc_plane_state *plane_state,
struct dc_stream_state *stream)
{
uint16_t i = 0;
enum signal_type signal = stream->signal;
- struct dc_hdr_static_metadata hdr_metadata;
uint32_t data;
- if (!plane_state)
- return;
-
- hdr_metadata = plane_state->hdr_static_ctx;
-
- if (!hdr_metadata.hdr_supported)
+ if (!stream->hdr_static_metadata.hdr_supported)
return;
if (dc_is_hdmi_signal(signal)) {
@@ -2352,55 +2352,55 @@
i = 2;
}
- data = hdr_metadata.is_hdr;
+ data = stream->hdr_static_metadata.is_hdr;
info_packet->sb[i++] = data ? 0x02 : 0x00;
info_packet->sb[i++] = 0x00;
- data = hdr_metadata.chromaticity_green_x / 2;
+ data = stream->hdr_static_metadata.chromaticity_green_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_green_y / 2;
+ data = stream->hdr_static_metadata.chromaticity_green_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_blue_x / 2;
+ data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_blue_y / 2;
+ data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_red_x / 2;
+ data = stream->hdr_static_metadata.chromaticity_red_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_red_y / 2;
+ data = stream->hdr_static_metadata.chromaticity_red_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_white_point_x / 2;
+ data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.chromaticity_white_point_y / 2;
+ data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.max_luminance;
+ data = stream->hdr_static_metadata.max_luminance;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.min_luminance;
+ data = stream->hdr_static_metadata.min_luminance;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.maximum_content_light_level;
+ data = stream->hdr_static_metadata.maximum_content_light_level;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
- data = hdr_metadata.maximum_frame_average_light_level;
+ data = stream->hdr_static_metadata.maximum_frame_average_light_level;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
@@ -2551,16 +2551,14 @@
set_spd_info_packet(&info->spd, pipe_ctx->stream);
- set_hdr_static_info_packet(&info->hdrsmd,
- pipe_ctx->plane_state, pipe_ctx->stream);
+ set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
} else if (dc_is_dp_signal(signal)) {
set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
set_spd_info_packet(&info->spd, pipe_ctx->stream);
- set_hdr_static_info_packet(&info->hdrsmd,
- pipe_ctx->plane_state, pipe_ctx->stream);
+ set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
}
patch_gamut_packet_checksum(&info->gamut);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index e230cc4..cd58197 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -33,23 +33,20 @@
/*******************************************************************************
* Private functions
******************************************************************************/
-#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
-static void update_stream_signal(struct dc_stream_state *stream)
+void update_stream_signal(struct dc_stream_state *stream)
{
- if (stream->output_signal == SIGNAL_TYPE_NONE) {
- struct dc_sink *dc_sink = stream->sink;
- if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
- stream->signal = stream->sink->link->connector_signal;
- else
- stream->signal = dc_sink->sink_signal;
- } else {
- stream->signal = stream->output_signal;
- }
+ struct dc_sink *dc_sink = stream->sink;
+
+ if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
+ stream->signal = stream->sink->link->connector_signal;
+ else
+ stream->signal = dc_sink->sink_signal;
if (dc_is_dvi_signal(stream->signal)) {
- if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
- stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
+ if (stream->ctx->dc->caps.dual_link_dvi &&
+ stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
+ stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
else
stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
@@ -196,44 +193,20 @@
core_dc = stream->ctx->dc;
res_ctx = &core_dc->current_state->res_ctx;
+ stream->cursor_attributes = *attributes;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
- if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
+ if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm &&
+ !pipe_ctx->plane_res.dpp) || !pipe_ctx->plane_res.ipp)
continue;
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
continue;
- if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL)
- pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
- pipe_ctx->plane_res.ipp, attributes);
-
- if (pipe_ctx->plane_res.hubp != NULL &&
- pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL)
- pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
- pipe_ctx->plane_res.hubp, attributes);
-
- if (pipe_ctx->plane_res.mi != NULL &&
- pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)
- pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
- pipe_ctx->plane_res.mi, attributes);
-
-
- if (pipe_ctx->plane_res.xfm != NULL &&
- pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)
- pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
- pipe_ctx->plane_res.xfm, attributes);
-
- if (pipe_ctx->plane_res.dpp != NULL &&
- pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
- pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
- pipe_ctx->plane_res.dpp, attributes);
+ core_dc->hwss.set_cursor_attribute(pipe_ctx);
}
-
- stream->cursor_attributes = *attributes;
-
return true;
}
@@ -257,51 +230,19 @@
core_dc = stream->ctx->dc;
res_ctx = &core_dc->current_state->res_ctx;
+ stream->cursor_position = *position;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
- struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
- struct mem_input *mi = pipe_ctx->plane_res.mi;
- struct hubp *hubp = pipe_ctx->plane_res.hubp;
- struct dpp *dpp = pipe_ctx->plane_res.dpp;
- struct dc_cursor_position pos_cpy = *position;
- struct dc_cursor_mi_param param = {
- .pixel_clk_khz = stream->timing.pix_clk_khz,
- .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
- .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
- .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
- .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
- };
if (pipe_ctx->stream != stream ||
(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
!pipe_ctx->plane_state ||
- (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
+ (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
+ !pipe_ctx->plane_res.ipp)
continue;
- if (pipe_ctx->plane_state->address.type
- == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
- pos_cpy.enable = false;
-
- if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
- pos_cpy.enable = false;
-
-
- if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
- ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
-
- if (mi != NULL && mi->funcs->set_cursor_position != NULL)
- mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
-
- if (!hubp)
- continue;
-
- if (hubp->funcs->set_cursor_position != NULL)
- hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
-
- if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
- dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width);
-
+ core_dc->hwss.set_cursor_position(pipe_ctx);
}
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9d8f4a5..3f2da2b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
#include "inc/compressor.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.1.07"
+#define DC_VER "3.1.27"
#define MAX_SURFACES 3
#define MAX_STREAMS 6
@@ -58,8 +58,11 @@
uint32_t i2c_speed_in_khz;
unsigned int max_cursor_size;
unsigned int max_video_width;
+ int linear_pitch_alignment;
bool dcc_const_color;
bool dynamic_audio;
+ bool is_apu;
+ bool dual_link_dvi;
};
struct dc_dcc_surface_param {
@@ -97,69 +100,53 @@
bool overlay_update;
};
+
+/* Surface update type is used by dc_update_surfaces_and_stream
+ * The update type is determined at the very beginning of the function based
+ * on parameters passed in and decides how much programming (or updating) is
+ * going to be done during the call.
+ *
+ * UPDATE_TYPE_FAST is used for really fast updates that do not require much
+ * logical calculations or hardware register programming. This update MUST be
+ * ISR safe on windows. Currently fast update will only be used to flip surface
+ * address.
+ *
+ * UPDATE_TYPE_MED is used for slower updates which require significant hw
+ * re-programming however do not affect bandwidth consumption or clock
+ * requirements. At present, this is the level at which front end updates
+ * that do not require us to run bw_calcs happen. These are in/out transfer func
+ * updates, viewport offset changes, recout size changes and pixel depth changes.
+ * This update can be done at ISR, but we want to minimize how often this happens.
+ *
+ * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
+ * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
+ * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
+ * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
+ * a full update. This cannot be done at ISR level and should be a rare event.
+ * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
+ * underscan we don't expect to see this call at all.
+ */
+
+enum surface_update_type {
+ UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
+ UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
+ UPDATE_TYPE_FULL, /* may need to shuffle resources */
+};
+
/* Forward declaration*/
struct dc;
struct dc_plane_state;
struct dc_state;
+
struct dc_cap_funcs {
bool (*get_dcc_compression_cap)(const struct dc *dc,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output);
};
-struct dc_stream_state_funcs {
- bool (*adjust_vmin_vmax)(struct dc *dc,
- struct dc_stream_state **stream,
- int num_streams,
- int vmin,
- int vmax);
- bool (*get_crtc_position)(struct dc *dc,
- struct dc_stream_state **stream,
- int num_streams,
- unsigned int *v_pos,
- unsigned int *nom_v_pos);
-
- bool (*set_gamut_remap)(struct dc *dc,
- const struct dc_stream_state *stream);
-
- bool (*program_csc_matrix)(struct dc *dc,
- struct dc_stream_state *stream);
-
- void (*set_static_screen_events)(struct dc *dc,
- struct dc_stream_state **stream,
- int num_streams,
- const struct dc_static_screen_events *events);
-
- void (*set_dither_option)(struct dc_stream_state *stream,
- enum dc_dither_option option);
-
- void (*set_dpms)(struct dc *dc,
- struct dc_stream_state *stream,
- bool dpms_off);
-};
-
struct link_training_settings;
-struct dc_link_funcs {
- void (*set_drive_settings)(struct dc *dc,
- struct link_training_settings *lt_settings,
- const struct dc_link *link);
- void (*perform_link_training)(struct dc *dc,
- struct dc_link_settings *link_setting,
- bool skip_video_pattern);
- void (*set_preferred_link_settings)(struct dc *dc,
- struct dc_link_settings *link_setting,
- struct dc_link *link);
- void (*enable_hpd)(const struct dc_link *link);
- void (*disable_hpd)(const struct dc_link *link);
- void (*set_test_pattern)(
- struct dc_link *link,
- enum dp_test_pattern test_pattern,
- const struct link_training_settings *p_link_settings,
- const unsigned char *p_custom_pattern,
- unsigned int cust_pattern_size);
-};
/* Structure to hold configuration flags set by dm at dc creation. */
struct dc_config {
@@ -232,8 +219,6 @@
struct dc {
struct dc_caps caps;
struct dc_cap_funcs cap_funcs;
- struct dc_stream_state_funcs stream_funcs;
- struct dc_link_funcs link_funcs;
struct dc_config config;
struct dc_debug debug;
@@ -266,6 +251,8 @@
*/
struct dm_pp_display_configuration prev_display_config;
+ bool optimized_required;
+
/* FBC compressor */
#if defined(CONFIG_DRM_AMD_DC_FBC)
struct compressor *fbc_compressor;
@@ -333,24 +320,6 @@
transfer_func_gamma_26
};
-enum color_color_space {
- color_space_unsupported,
- color_space_srgb,
- color_space_bt601,
- color_space_bt709,
- color_space_xv_ycc_bt601,
- color_space_xv_ycc_bt709,
- color_space_xr_rgb,
- color_space_bt2020,
- color_space_adobe,
- color_space_dci_p3,
- color_space_sc_rgb_ms_ref,
- color_space_display_native,
- color_space_app_ctrl,
- color_space_dolby_vision,
- color_space_custom_coordinates
-};
-
struct dc_hdr_static_metadata {
/* display chromaticities and white point in units of 0.00001 */
unsigned int chromaticity_green_x;
@@ -374,7 +343,7 @@
enum dc_transfer_func_type {
TF_TYPE_PREDEFINED,
TF_TYPE_DISTRIBUTED_POINTS,
- TF_TYPE_BYPASS
+ TF_TYPE_BYPASS,
};
struct dc_transfer_func_distributed_points {
@@ -393,6 +362,7 @@
TRANSFER_FUNCTION_BT709,
TRANSFER_FUNCTION_PQ,
TRANSFER_FUNCTION_LINEAR,
+ TRANSFER_FUNCTION_UNITY,
};
struct dc_transfer_func {
@@ -415,6 +385,35 @@
bool is_right_eye;
};
+union surface_update_flags {
+
+ struct {
+ /* Medium updates */
+ uint32_t dcc_change:1;
+ uint32_t color_space_change:1;
+ uint32_t input_tf_change:1;
+ uint32_t horizontal_mirror_change:1;
+ uint32_t per_pixel_alpha_change:1;
+ uint32_t rotation_change:1;
+ uint32_t swizzle_change:1;
+ uint32_t scaling_change:1;
+ uint32_t position_change:1;
+ uint32_t in_transfer_func_change:1;
+ uint32_t input_csc_change:1;
+
+ /* Full updates */
+ uint32_t new_plane:1;
+ uint32_t bpp_change:1;
+ uint32_t gamma_change:1;
+ uint32_t bandwidth_change:1;
+ uint32_t clock_change:1;
+ uint32_t stereo_format_change:1;
+ uint32_t full_update:1;
+ } bits;
+
+ uint32_t raw;
+};
+
struct dc_plane_state {
struct dc_plane_address address;
struct scaling_taps scaling_quality;
@@ -426,27 +425,30 @@
union dc_tiling_info tiling_info;
struct dc_plane_dcc_param dcc;
- struct dc_hdr_static_metadata hdr_static_ctx;
struct dc_gamma *gamma_correction;
struct dc_transfer_func *in_transfer_func;
+ struct dc_bias_and_scale *bias_and_scale;
+ struct csc_transform input_csc_color_matrix;
+ struct fixed31_32 coeff_reduction_factor;
- // sourceContentAttribute cache
- bool is_source_input_valid;
- struct dc_hdr_static_metadata source_input_mastering_info;
- enum color_color_space source_input_color_space;
- enum color_transfer_func source_input_tf;
+ // TODO: No longer used, remove
+ struct dc_hdr_static_metadata hdr_static_ctx;
enum dc_color_space color_space;
+ enum color_transfer_func input_tf;
+
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
enum plane_stereo_format stereo_format;
+ bool is_tiling_rotated;
bool per_pixel_alpha;
bool visible;
bool flip_immediate;
bool horizontal_mirror;
+ union surface_update_flags update_flags;
/* private to DC core */
struct dc_plane_status status;
struct dc_context *ctx;
@@ -463,10 +465,12 @@
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
enum plane_stereo_format stereo_format;
- enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
+ enum dc_color_space color_space;
+ enum color_transfer_func input_tf;
bool horizontal_mirror;
bool visible;
bool per_pixel_alpha;
+ bool input_csc_enabled;
};
struct dc_scaling_info {
@@ -483,13 +487,18 @@
struct dc_flip_addrs *flip_addr;
struct dc_plane_info *plane_info;
struct dc_scaling_info *scaling_info;
+
/* following updates require alloc/sleep/spin that is not isr safe,
* null means no updates
*/
/* gamma TO BE REMOVED */
struct dc_gamma *gamma;
+ enum color_transfer_func color_input_tf;
+ enum color_transfer_func color_output_tf;
struct dc_transfer_func *in_transfer_func;
- struct dc_hdr_static_metadata *hdr_static_metadata;
+
+ struct csc_transform *input_csc_color_matrix;
+ struct fixed31_32 *coeff_reduction_factor;
};
/*
@@ -524,197 +533,7 @@
bool dc_post_update_surfaces_to_stream(
struct dc *dc);
-/* Surface update type is used by dc_update_surfaces_and_stream
- * The update type is determined at the very beginning of the function based
- * on parameters passed in and decides how much programming (or updating) is
- * going to be done during the call.
- *
- * UPDATE_TYPE_FAST is used for really fast updates that do not require much
- * logical calculations or hardware register programming. This update MUST be
- * ISR safe on windows. Currently fast update will only be used to flip surface
- * address.
- *
- * UPDATE_TYPE_MED is used for slower updates which require significant hw
- * re-programming however do not affect bandwidth consumption or clock
- * requirements. At present, this is the level at which front end updates
- * that do not require us to run bw_calcs happen. These are in/out transfer func
- * updates, viewport offset changes, recout size changes and pixel depth changes.
- * This update can be done at ISR, but we want to minimize how often this happens.
- *
- * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
- * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
- * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
- * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
- * a full update. This cannot be done at ISR level and should be a rare event.
- * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
- * underscan we don't expect to see this call at all.
- */
-
-enum surface_update_type {
- UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
- UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
- UPDATE_TYPE_FULL, /* may need to shuffle resources */
-};
-
-/*******************************************************************************
- * Stream Interfaces
- ******************************************************************************/
-
-struct dc_stream_status {
- int primary_otg_inst;
- int stream_enc_inst;
- int plane_count;
- struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
-
- /*
- * link this stream passes through
- */
- struct dc_link *link;
-};
-
-struct dc_stream_state {
- struct dc_sink *sink;
- struct dc_crtc_timing timing;
-
- struct rect src; /* composition area */
- struct rect dst; /* stream addressable area */
-
- struct audio_info audio_info;
-
- struct freesync_context freesync_ctx;
-
- struct dc_transfer_func *out_transfer_func;
- struct colorspace_transform gamut_remap_matrix;
- struct csc_transform csc_color_matrix;
-
- enum signal_type output_signal;
-
- enum dc_color_space output_color_space;
- enum dc_dither_option dither_option;
-
- enum view_3d_format view_format;
-
- bool ignore_msa_timing_param;
- /* TODO: custom INFO packets */
- /* TODO: ABM info (DMCU) */
- /* TODO: PSR info */
- /* TODO: CEA VIC */
-
- /* from core_stream struct */
- struct dc_context *ctx;
-
- /* used by DCP and FMT */
- struct bit_depth_reduction_params bit_depth_params;
- struct clamping_and_pixel_encoding_params clamping;
-
- int phy_pix_clk;
- enum signal_type signal;
- bool dpms_off;
-
- struct dc_stream_status status;
-
- struct dc_cursor_attributes cursor_attributes;
-
- /* from stream struct */
- struct kref refcount;
-};
-
-struct dc_stream_update {
- struct rect src;
- struct rect dst;
- struct dc_transfer_func *out_transfer_func;
-};
-
-bool dc_is_stream_unchanged(
- struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-bool dc_is_stream_scaling_unchanged(
- struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-
-/*
- * Set up surface attributes and associate to a stream
- * The surfaces parameter is an absolute set of all surface active for the stream.
- * If no surfaces are provided, the stream will be blanked; no memory read.
- * Any flip related attribute changes must be done through this interface.
- *
- * After this call:
- * Surfaces attributes are programmed and configured to be composed into stream.
- * This does not trigger a flip. No surface address is programmed.
- */
-
-bool dc_commit_planes_to_stream(
- struct dc *dc,
- struct dc_plane_state **plane_states,
- uint8_t new_plane_count,
- struct dc_stream_state *dc_stream,
- struct dc_state *state);
-
-void dc_commit_updates_for_stream(struct dc *dc,
- struct dc_surface_update *srf_updates,
- int surface_count,
- struct dc_stream_state *stream,
- struct dc_stream_update *stream_update,
- struct dc_plane_state **plane_states,
- struct dc_state *state);
-/*
- * Log the current stream state.
- */
-void dc_stream_log(
- const struct dc_stream_state *stream,
- struct dal_logger *dc_logger,
- enum dc_log_type log_type);
-
-uint8_t dc_get_current_stream_count(struct dc *dc);
-struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
-
-/*
- * Return the current frame counter.
- */
-uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
-
-/* TODO: Return parsed values rather than direct register read
- * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
- * being refactored properly to be dce-specific
- */
-bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
- uint32_t *v_blank_start,
- uint32_t *v_blank_end,
- uint32_t *h_position,
- uint32_t *v_position);
-
-enum dc_status dc_add_stream_to_ctx(
- struct dc *dc,
- struct dc_state *new_ctx,
- struct dc_stream_state *stream);
-
-enum dc_status dc_remove_stream_from_ctx(
- struct dc *dc,
- struct dc_state *new_ctx,
- struct dc_stream_state *stream);
-
-
-bool dc_add_plane_to_context(
- const struct dc *dc,
- struct dc_stream_state *stream,
- struct dc_plane_state *plane_state,
- struct dc_state *context);
-
-bool dc_remove_plane_from_context(
- const struct dc *dc,
- struct dc_stream_state *stream,
- struct dc_plane_state *plane_state,
- struct dc_state *context);
-
-bool dc_rem_all_planes_for_stream(
- const struct dc *dc,
- struct dc_stream_state *stream,
- struct dc_state *context);
-
-bool dc_add_all_planes_for_stream(
- const struct dc *dc,
- struct dc_stream_state *stream,
- struct dc_plane_state * const *plane_states,
- int plane_count,
- struct dc_state *context);
+#include "dc_stream.h"
/*
* Structure to store surface/stream associations for validation
@@ -725,22 +544,12 @@
uint8_t plane_count;
};
-enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
-
enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
enum dc_status dc_validate_global_state(
struct dc *dc,
struct dc_state *new_ctx);
-/*
- * This function takes a stream and checks if it is guaranteed to be supported.
- * Guaranteed means that MAX_COFUNC similar streams are supported.
- *
- * After this call:
- * No hardware is programmed for call. Only validation is done.
- */
-
void dc_resource_state_construct(
const struct dc *dc,
@@ -767,42 +576,6 @@
*/
bool dc_commit_state(struct dc *dc, struct dc_state *context);
-/*
- * Set up streams and links associated to drive sinks
- * The streams parameter is an absolute set of all active streams.
- *
- * After this call:
- * Phy, Encoder, Timing Generator are programmed and enabled.
- * New streams are enabled with blank stream; no memory read.
- */
-/*
- * Enable stereo when commit_streams is not required,
- * for example, frame alternate.
- */
-bool dc_enable_stereo(
- struct dc *dc,
- struct dc_state *context,
- struct dc_stream_state *streams[],
- uint8_t stream_count);
-
-/**
- * Create a new default stream for the requested sink
- */
-struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
-
-void dc_stream_retain(struct dc_stream_state *dc_stream);
-void dc_stream_release(struct dc_stream_state *dc_stream);
-
-struct dc_stream_status *dc_stream_get_status(
- struct dc_stream_state *dc_stream);
-
-enum surface_update_type dc_check_update_surfaces_for_stream(
- struct dc *dc,
- struct dc_surface_update *updates,
- int surface_count,
- struct dc_stream_update *stream_update,
- const struct dc_stream_status *stream_status);
-
struct dc_state *dc_create_state(void);
void dc_retain_state(struct dc_state *context);
@@ -835,171 +608,7 @@
bool dpcd_display_control_capable;
};
-struct dc_link_status {
- struct dpcd_caps *dpcd_caps;
-};
-
-/* DP MST stream allocation (payload bandwidth number) */
-struct link_mst_stream_allocation {
- /* DIG front */
- const struct stream_encoder *stream_enc;
- /* associate DRM payload table with DC stream encoder */
- uint8_t vcp_id;
- /* number of slots required for the DP stream in transport packet */
- uint8_t slot_count;
-};
-
-/* DP MST stream allocation table */
-struct link_mst_stream_allocation_table {
- /* number of DP video streams */
- int stream_count;
- /* array of stream allocations */
- struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
-};
-
-/*
- * A link contains one or more sinks and their connected status.
- * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
- */
-struct dc_link {
- struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
- unsigned int sink_count;
- struct dc_sink *local_sink;
- unsigned int link_index;
- enum dc_connection_type type;
- enum signal_type connector_signal;
- enum dc_irq_source irq_source_hpd;
- enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
- /* caps is the same as reported_link_cap. link_traing use
- * reported_link_cap. Will clean up. TODO
- */
- struct dc_link_settings reported_link_cap;
- struct dc_link_settings verified_link_cap;
- struct dc_link_settings cur_link_settings;
- struct dc_lane_settings cur_lane_setting;
- struct dc_link_settings preferred_link_setting;
-
- uint8_t ddc_hw_inst;
-
- uint8_t hpd_src;
-
- uint8_t link_enc_hw_inst;
-
- bool test_pattern_enabled;
- union compliance_test_state compliance_test_state;
-
- void *priv;
-
- struct ddc_service *ddc;
-
- bool aux_mode;
-
- /* Private to DC core */
-
- const struct dc *dc;
-
- struct dc_context *ctx;
-
- struct link_encoder *link_enc;
- struct graphics_object_id link_id;
- union ddi_channel_mapping ddi_channel_mapping;
- struct connector_device_tag_info device_tag;
- struct dpcd_caps dpcd_caps;
- unsigned short chip_caps;
- unsigned int dpcd_sink_count;
- enum edp_revision edp_revision;
- bool psr_enabled;
-
- /* MST record stream using this link */
- struct link_flags {
- bool dp_keep_receiver_powered;
- } wa_flags;
- struct link_mst_stream_allocation_table mst_stream_alloc_table;
-
- struct dc_link_status link_status;
-
-};
-
-const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
-
-/*
- * Return an enumerated dc_link. dc_link order is constant and determined at
- * boot time. They cannot be created or destroyed.
- * Use dc_get_caps() to get number of links.
- */
-static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
-{
- return dc->links[link_index];
-}
-
-/* Set backlight level of an embedded panel (eDP, LVDS). */
-bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
- uint32_t frame_ramp, const struct dc_stream_state *stream);
-
-bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
-
-bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
-
-bool dc_link_setup_psr(struct dc_link *dc_link,
- const struct dc_stream_state *stream, struct psr_config *psr_config,
- struct psr_context *psr_context);
-
-/* Request DC to detect if there is a Panel connected.
- * boot - If this call is during initial boot.
- * Return false for any type of detection failure or MST detection
- * true otherwise. True meaning further action is required (status update
- * and OS notification).
- */
-enum dc_detect_reason {
- DETECT_REASON_BOOT,
- DETECT_REASON_HPD,
- DETECT_REASON_HPDRX,
-};
-
-bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
-
-/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
- * Return:
- * true - Downstream port status changed. DM should call DC to do the
- * detection.
- * false - no change in Downstream port status. No further action required
- * from DM. */
-bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
- union hpd_irq_data *hpd_irq_dpcd_data);
-
-struct dc_sink_init_data;
-
-struct dc_sink *dc_link_add_remote_sink(
- struct dc_link *dc_link,
- const uint8_t *edid,
- int len,
- struct dc_sink_init_data *init_data);
-
-void dc_link_remove_remote_sink(
- struct dc_link *link,
- struct dc_sink *sink);
-
-/* Used by diagnostics for virtual link at the moment */
-
-void dc_link_dp_set_drive_settings(
- struct dc_link *link,
- struct link_training_settings *lt_settings);
-
-enum link_training_result dc_link_dp_perform_link_training(
- struct dc_link *link,
- const struct dc_link_settings *link_setting,
- bool skip_video_pattern);
-
-void dc_link_dp_enable_hpd(const struct dc_link *link);
-
-void dc_link_dp_disable_hpd(const struct dc_link *link);
-
-bool dc_link_dp_set_test_pattern(
- struct dc_link *link,
- enum dp_test_pattern test_pattern,
- const struct link_training_settings *p_link_settings,
- const unsigned char *p_custom_pattern,
- unsigned int cust_pattern_size);
+#include "dc_link.h"
/*******************************************************************************
* Sink Interfaces - A sink corresponds to a display output device
@@ -1037,6 +646,7 @@
/* private to dc_sink.c */
struct kref refcount;
+
};
void dc_sink_retain(struct dc_sink *sink);
@@ -1051,18 +661,6 @@
struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
-/*******************************************************************************
- * Cursor interfaces - To manages the cursor within a stream
- ******************************************************************************/
-/* TODO: Deprecated once we switch to dc_set_cursor_position */
-bool dc_stream_set_cursor_attributes(
- struct dc_stream_state *stream,
- const struct dc_cursor_attributes *attributes);
-
-bool dc_stream_set_cursor_position(
- struct dc_stream_state *stream,
- const struct dc_cursor_position *position);
-
/* Newer interfaces */
struct dc_cursor {
struct dc_plane_address address;
@@ -1076,7 +674,7 @@
struct dc *dc,
uint32_t src_id,
uint32_t ext_id);
-void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
+bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
enum dc_irq_source dc_get_hpd_irq_source_at_index(
struct dc *dc, uint32_t link_index);
@@ -1090,14 +688,4 @@
enum dc_acpi_cm_power_state power_state);
void dc_resume(struct dc *dc);
-/*
- * DPCD access interfaces
- */
-
-bool dc_submit_i2c(
- struct dc *dc,
- uint32_t link_index,
- struct i2c_command *cmd);
-
-
#endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 77e2de6..2726b02 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -255,7 +255,7 @@
DOWN_STREAM_DETAILED_DP_PLUS_PLUS
};
-union dwnstream_port_caps_byte1 {
+union dwnstream_port_caps_byte2 {
struct {
uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
uint8_t RESERVED:6;
@@ -298,6 +298,32 @@
/*4-byte structure for detailed capabilities of a down-stream port
(DP-to-TMDS converter).*/
+union dwnstream_portxcaps {
+ struct {
+ union dwnstream_port_caps_byte0 byte0;
+ unsigned char max_TMDS_clock; //byte1
+ union dwnstream_port_caps_byte2 byte2;
+
+ union {
+ union dwnstream_port_caps_byte3_dvi byteDVI;
+ union dwnstream_port_caps_byte3_hdmi byteHDMI;
+ } byte3;
+ } bytes;
+
+ unsigned char raw[4];
+};
+
+union downstream_port {
+ struct {
+ unsigned char present:1;
+ unsigned char type:2;
+ unsigned char format_conv:1;
+ unsigned char detailed_caps:1;
+ unsigned char reserved:3;
+ } bits;
+ unsigned char raw;
+};
+
union sink_status {
struct {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 90e81f7..48e1fcf5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -178,8 +178,13 @@
field_value = get_reg_field_value_ex(reg_val, mask, shift);
- if (field_value == condition_value)
+ if (field_value == condition_value) {
+ if (i * delay_between_poll_us > 1000)
+ dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n",
+ delay_between_poll_us * i / 1000,
+ func_name, line);
return reg_val;
+ }
}
dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 1a9f57f..03029f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -492,15 +492,24 @@
enum dc_color_space {
COLOR_SPACE_UNKNOWN,
COLOR_SPACE_SRGB,
+ COLOR_SPACE_XR_RGB,
COLOR_SPACE_SRGB_LIMITED,
+ COLOR_SPACE_MSREF_SCRGB,
COLOR_SPACE_YCBCR601,
COLOR_SPACE_YCBCR709,
+ COLOR_SPACE_XV_YCC_709,
+ COLOR_SPACE_XV_YCC_601,
COLOR_SPACE_YCBCR601_LIMITED,
COLOR_SPACE_YCBCR709_LIMITED,
COLOR_SPACE_2020_RGB_FULLRANGE,
COLOR_SPACE_2020_RGB_LIMITEDRANGE,
COLOR_SPACE_2020_YCBCR,
COLOR_SPACE_ADOBERGB,
+ COLOR_SPACE_DCIP3,
+ COLOR_SPACE_DISPLAYNATIVE,
+ COLOR_SPACE_DOLBYVISION,
+ COLOR_SPACE_APPCTRL,
+ COLOR_SPACE_CUSTOMPOINTS,
};
enum dc_dither_option {
@@ -570,8 +579,6 @@
TIMING_STANDARD_MAX
};
-
-
enum dc_color_depth {
COLOR_DEPTH_UNDEFINED,
COLOR_DEPTH_666,
@@ -664,6 +671,22 @@
TIMING_3D_FORMAT_MAX,
};
+enum trigger_delay {
+ TRIGGER_DELAY_NEXT_PIXEL = 0,
+ TRIGGER_DELAY_NEXT_LINE,
+};
+
+enum crtc_event {
+ CRTC_EVENT_VSYNC_RISING = 0,
+ CRTC_EVENT_VSYNC_FALLING
+};
+
+struct crtc_trigger_info {
+ bool enabled;
+ struct dc_stream_state *event_source;
+ enum crtc_event event;
+ enum trigger_delay delay;
+};
struct dc_crtc_timing {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
new file mode 100644
index 0000000..f11a734
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2012-14 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DC_LINK_H_
+#define DC_LINK_H_
+
+#include "dc_types.h"
+#include "grph_object_defs.h"
+
+struct dc_link_status {
+ struct dpcd_caps *dpcd_caps;
+};
+
+/* DP MST stream allocation (payload bandwidth number) */
+struct link_mst_stream_allocation {
+ /* DIG front */
+ const struct stream_encoder *stream_enc;
+ /* associate DRM payload table with DC stream encoder */
+ uint8_t vcp_id;
+ /* number of slots required for the DP stream in transport packet */
+ uint8_t slot_count;
+};
+
+/* DP MST stream allocation table */
+struct link_mst_stream_allocation_table {
+ /* number of DP video streams */
+ int stream_count;
+ /* array of stream allocations */
+ struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
+};
+
+/*
+ * A link contains one or more sinks and their connected status.
+ * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
+ */
+struct dc_link {
+ struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
+ unsigned int sink_count;
+ struct dc_sink *local_sink;
+ unsigned int link_index;
+ enum dc_connection_type type;
+ enum signal_type connector_signal;
+ enum dc_irq_source irq_source_hpd;
+ enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
+ /* caps is the same as reported_link_cap. link_traing use
+ * reported_link_cap. Will clean up. TODO
+ */
+ struct dc_link_settings reported_link_cap;
+ struct dc_link_settings verified_link_cap;
+ struct dc_link_settings cur_link_settings;
+ struct dc_lane_settings cur_lane_setting;
+ struct dc_link_settings preferred_link_setting;
+
+ uint8_t ddc_hw_inst;
+
+ uint8_t hpd_src;
+
+ uint8_t link_enc_hw_inst;
+
+ bool test_pattern_enabled;
+ union compliance_test_state compliance_test_state;
+
+ void *priv;
+
+ struct ddc_service *ddc;
+
+ bool aux_mode;
+
+ /* Private to DC core */
+
+ const struct dc *dc;
+
+ struct dc_context *ctx;
+
+ struct link_encoder *link_enc;
+ struct graphics_object_id link_id;
+ union ddi_channel_mapping ddi_channel_mapping;
+ struct connector_device_tag_info device_tag;
+ struct dpcd_caps dpcd_caps;
+ unsigned short chip_caps;
+ unsigned int dpcd_sink_count;
+ enum edp_revision edp_revision;
+ bool psr_enabled;
+
+ /* MST record stream using this link */
+ struct link_flags {
+ bool dp_keep_receiver_powered;
+ } wa_flags;
+ struct link_mst_stream_allocation_table mst_stream_alloc_table;
+
+ struct dc_link_status link_status;
+
+};
+
+const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
+
+/*
+ * Return an enumerated dc_link. dc_link order is constant and determined at
+ * boot time. They cannot be created or destroyed.
+ * Use dc_get_caps() to get number of links.
+ */
+static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
+{
+ return dc->links[link_index];
+}
+
+/* Set backlight level of an embedded panel (eDP, LVDS). */
+bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
+ uint32_t frame_ramp, const struct dc_stream_state *stream);
+
+bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
+
+bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
+
+bool dc_link_setup_psr(struct dc_link *dc_link,
+ const struct dc_stream_state *stream, struct psr_config *psr_config,
+ struct psr_context *psr_context);
+
+/* Request DC to detect if there is a Panel connected.
+ * boot - If this call is during initial boot.
+ * Return false for any type of detection failure or MST detection
+ * true otherwise. True meaning further action is required (status update
+ * and OS notification).
+ */
+enum dc_detect_reason {
+ DETECT_REASON_BOOT,
+ DETECT_REASON_HPD,
+ DETECT_REASON_HPDRX,
+};
+
+bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
+
+/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
+ * Return:
+ * true - Downstream port status changed. DM should call DC to do the
+ * detection.
+ * false - no change in Downstream port status. No further action required
+ * from DM. */
+bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
+ union hpd_irq_data *hpd_irq_dpcd_data);
+
+struct dc_sink_init_data;
+
+struct dc_sink *dc_link_add_remote_sink(
+ struct dc_link *dc_link,
+ const uint8_t *edid,
+ int len,
+ struct dc_sink_init_data *init_data);
+
+void dc_link_remove_remote_sink(
+ struct dc_link *link,
+ struct dc_sink *sink);
+
+/* Used by diagnostics for virtual link at the moment */
+
+void dc_link_dp_set_drive_settings(
+ struct dc_link *link,
+ struct link_training_settings *lt_settings);
+
+enum link_training_result dc_link_dp_perform_link_training(
+ struct dc_link *link,
+ const struct dc_link_settings *link_setting,
+ bool skip_video_pattern);
+
+void dc_link_dp_enable_hpd(const struct dc_link *link);
+
+void dc_link_dp_disable_hpd(const struct dc_link *link);
+
+bool dc_link_dp_set_test_pattern(
+ struct dc_link *link,
+ enum dp_test_pattern test_pattern,
+ const struct link_training_settings *p_link_settings,
+ const unsigned char *p_custom_pattern,
+ unsigned int cust_pattern_size);
+
+/*
+ * DPCD access interfaces
+ */
+
+bool dc_submit_i2c(
+ struct dc *dc,
+ uint32_t link_index,
+ struct i2c_command *cmd);
+
+#endif /* DC_LINK_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
new file mode 100644
index 0000000..456e4d2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright 2012-14 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DC_STREAM_H_
+#define DC_STREAM_H_
+
+#include "dc_types.h"
+#include "grph_object_defs.h"
+
+/*******************************************************************************
+ * Stream Interfaces
+ ******************************************************************************/
+
+struct dc_stream_status {
+ int primary_otg_inst;
+ int stream_enc_inst;
+ int plane_count;
+ struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
+
+ /*
+ * link this stream passes through
+ */
+ struct dc_link *link;
+};
+
+struct dc_stream_state {
+ struct dc_sink *sink;
+ struct dc_crtc_timing timing;
+
+ struct rect src; /* composition area */
+ struct rect dst; /* stream addressable area */
+
+ struct audio_info audio_info;
+
+ struct freesync_context freesync_ctx;
+
+ struct dc_hdr_static_metadata hdr_static_metadata;
+ struct dc_transfer_func *out_transfer_func;
+ struct colorspace_transform gamut_remap_matrix;
+ struct csc_transform csc_color_matrix;
+
+ enum dc_color_space output_color_space;
+ enum dc_dither_option dither_option;
+
+ enum view_3d_format view_format;
+
+ bool ignore_msa_timing_param;
+ /* TODO: custom INFO packets */
+ /* TODO: ABM info (DMCU) */
+ /* TODO: PSR info */
+ /* TODO: CEA VIC */
+
+ /* from core_stream struct */
+ struct dc_context *ctx;
+
+ /* used by DCP and FMT */
+ struct bit_depth_reduction_params bit_depth_params;
+ struct clamping_and_pixel_encoding_params clamping;
+
+ int phy_pix_clk;
+ enum signal_type signal;
+ bool dpms_off;
+
+ struct dc_stream_status status;
+
+ struct dc_cursor_attributes cursor_attributes;
+ struct dc_cursor_position cursor_position;
+
+ /* from stream struct */
+ struct kref refcount;
+
+ struct crtc_trigger_info triggered_crtc_reset;
+
+ /* Computed state bits */
+ bool mode_changed : 1;
+
+};
+
+struct dc_stream_update {
+ struct rect src;
+ struct rect dst;
+ struct dc_transfer_func *out_transfer_func;
+ struct dc_hdr_static_metadata *hdr_static_metadata;
+};
+
+bool dc_is_stream_unchanged(
+ struct dc_stream_state *old_stream, struct dc_stream_state *stream);
+bool dc_is_stream_scaling_unchanged(
+ struct dc_stream_state *old_stream, struct dc_stream_state *stream);
+
+/*
+ * Set up surface attributes and associate to a stream
+ * The surfaces parameter is an absolute set of all surface active for the stream.
+ * If no surfaces are provided, the stream will be blanked; no memory read.
+ * Any flip related attribute changes must be done through this interface.
+ *
+ * After this call:
+ * Surfaces attributes are programmed and configured to be composed into stream.
+ * This does not trigger a flip. No surface address is programmed.
+ */
+
+bool dc_commit_planes_to_stream(
+ struct dc *dc,
+ struct dc_plane_state **plane_states,
+ uint8_t new_plane_count,
+ struct dc_stream_state *dc_stream,
+ struct dc_state *state);
+
+void dc_commit_updates_for_stream(struct dc *dc,
+ struct dc_surface_update *srf_updates,
+ int surface_count,
+ struct dc_stream_state *stream,
+ struct dc_stream_update *stream_update,
+ struct dc_plane_state **plane_states,
+ struct dc_state *state);
+/*
+ * Log the current stream state.
+ */
+void dc_stream_log(
+ const struct dc_stream_state *stream,
+ struct dal_logger *dc_logger,
+ enum dc_log_type log_type);
+
+uint8_t dc_get_current_stream_count(struct dc *dc);
+struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
+
+/*
+ * Return the current frame counter.
+ */
+uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
+
+/* TODO: Return parsed values rather than direct register read
+ * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
+ * being refactored properly to be dce-specific
+ */
+bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position);
+
+enum dc_status dc_add_stream_to_ctx(
+ struct dc *dc,
+ struct dc_state *new_ctx,
+ struct dc_stream_state *stream);
+
+enum dc_status dc_remove_stream_from_ctx(
+ struct dc *dc,
+ struct dc_state *new_ctx,
+ struct dc_stream_state *stream);
+
+
+bool dc_add_plane_to_context(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_plane_state *plane_state,
+ struct dc_state *context);
+
+bool dc_remove_plane_from_context(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_plane_state *plane_state,
+ struct dc_state *context);
+
+bool dc_rem_all_planes_for_stream(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_state *context);
+
+bool dc_add_all_planes_for_stream(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_plane_state * const *plane_states,
+ int plane_count,
+ struct dc_state *context);
+
+enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
+
+/*
+ * This function takes a stream and checks if it is guaranteed to be supported.
+ * Guaranteed means that MAX_COFUNC similar streams are supported.
+ *
+ * After this call:
+ * No hardware is programmed for call. Only validation is done.
+ */
+
+/*
+ * Set up streams and links associated to drive sinks
+ * The streams parameter is an absolute set of all active streams.
+ *
+ * After this call:
+ * Phy, Encoder, Timing Generator are programmed and enabled.
+ * New streams are enabled with blank stream; no memory read.
+ */
+/*
+ * Enable stereo when commit_streams is not required,
+ * for example, frame alternate.
+ */
+bool dc_enable_stereo(
+ struct dc *dc,
+ struct dc_state *context,
+ struct dc_stream_state *streams[],
+ uint8_t stream_count);
+
+
+enum surface_update_type dc_check_update_surfaces_for_stream(
+ struct dc *dc,
+ struct dc_surface_update *updates,
+ int surface_count,
+ struct dc_stream_update *stream_update,
+ const struct dc_stream_status *stream_status);
+
+/**
+ * Create a new default stream for the requested sink
+ */
+struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
+
+void update_stream_signal(struct dc_stream_state *stream);
+
+void dc_stream_retain(struct dc_stream_state *dc_stream);
+void dc_stream_release(struct dc_stream_state *dc_stream);
+
+struct dc_stream_status *dc_stream_get_status(
+ struct dc_stream_state *dc_stream);
+
+/*******************************************************************************
+ * Cursor interfaces - To manages the cursor within a stream
+ ******************************************************************************/
+/* TODO: Deprecated once we switch to dc_set_cursor_position */
+bool dc_stream_set_cursor_attributes(
+ struct dc_stream_state *stream,
+ const struct dc_cursor_attributes *attributes);
+
+bool dc_stream_set_cursor_position(
+ struct dc_stream_state *stream,
+ const struct dc_cursor_position *position);
+
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
+ struct dc_stream_state **stream,
+ int num_streams,
+ int vmin,
+ int vmax);
+
+bool dc_stream_get_crtc_position(struct dc *dc,
+ struct dc_stream_state **stream,
+ int num_streams,
+ unsigned int *v_pos,
+ unsigned int *nom_v_pos);
+
+void dc_stream_set_static_screen_events(struct dc *dc,
+ struct dc_stream_state **stream,
+ int num_streams,
+ const struct dc_static_screen_events *events);
+
+
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
+ struct dc_stream_state **stream,
+ int num_streams,
+ int vmin,
+ int vmax);
+
+bool dc_stream_get_crtc_position(struct dc *dc,
+ struct dc_stream_state **stream,
+ int num_streams,
+ unsigned int *v_pos,
+ unsigned int *nom_v_pos);
+
+void dc_stream_set_static_screen_events(struct dc *dc,
+ struct dc_stream_state **stream,
+ int num_streams,
+ const struct dc_static_screen_events *events);
+
+#endif /* DC_STREAM_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index a8698e39..9faddfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -218,6 +218,7 @@
bool lte_340mcsc_scramble;
bool edid_hdmi;
+ bool hdr_supported;
};
struct view {
@@ -638,11 +639,6 @@
bool enable_remap;
};
-struct csc_transform {
- uint16_t matrix[12];
- bool enable_adjustment;
-};
-
enum i2c_mot_mode {
I2C_MOT_UNDEF,
I2C_MOT_TRUE,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index 7de2aa1..7a57a63 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -51,16 +51,6 @@
#define MCP_DISABLE_ABM_IMMEDIATELY 255
-struct abm_backlight_registers {
- unsigned int BL_PWM_CNTL;
- unsigned int BL_PWM_CNTL2;
- unsigned int BL_PWM_PERIOD_CNTL;
- unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
-};
-
-/* registers setting needs to be save and restored used at InitBacklight */
-static struct abm_backlight_registers stored_backlight_registers = {0};
-
static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
{
@@ -348,16 +338,16 @@
*/
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
if (value == 0 || value == 1) {
- if (stored_backlight_registers.BL_PWM_CNTL != 0) {
+ if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
REG_WRITE(BL_PWM_CNTL,
- stored_backlight_registers.BL_PWM_CNTL);
+ abm->stored_backlight_registers.BL_PWM_CNTL);
REG_WRITE(BL_PWM_CNTL2,
- stored_backlight_registers.BL_PWM_CNTL2);
+ abm->stored_backlight_registers.BL_PWM_CNTL2);
REG_WRITE(BL_PWM_PERIOD_CNTL,
- stored_backlight_registers.BL_PWM_PERIOD_CNTL);
+ abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
BL_PWM_REF_DIV,
- stored_backlight_registers.
+ abm->stored_backlight_registers.
LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
} else {
/* TODO: Note: This should not really happen since VBIOS
@@ -367,15 +357,15 @@
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
}
} else {
- stored_backlight_registers.BL_PWM_CNTL =
+ abm->stored_backlight_registers.BL_PWM_CNTL =
REG_READ(BL_PWM_CNTL);
- stored_backlight_registers.BL_PWM_CNTL2 =
+ abm->stored_backlight_registers.BL_PWM_CNTL2 =
REG_READ(BL_PWM_CNTL2);
- stored_backlight_registers.BL_PWM_PERIOD_CNTL =
+ abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
REG_READ(BL_PWM_PERIOD_CNTL);
REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
- &stored_backlight_registers.
+ &abm->stored_backlight_registers.
LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
}
@@ -396,21 +386,12 @@
return true;
}
-static bool is_dmcu_initialized(struct abm *abm)
-{
- struct dce_abm *abm_dce = TO_DCE_ABM(abm);
- unsigned int dmcu_uc_reset;
-
- REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
-
- return !dmcu_uc_reset;
-}
-
static bool dce_abm_set_backlight_level(
struct abm *abm,
unsigned int backlight_level,
unsigned int frame_ramp,
- unsigned int controller_id)
+ unsigned int controller_id,
+ bool use_smooth_brightness)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
@@ -419,7 +400,7 @@
backlight_level, backlight_level);
/* If DMCU is in reset state, DMCU is uninitialized */
- if (is_dmcu_initialized(abm))
+ if (use_smooth_brightness)
dmcu_set_backlight_level(abm_dce,
backlight_level,
frame_ramp,
@@ -436,8 +417,7 @@
.init_backlight = dce_abm_init_backlight,
.set_backlight_level = dce_abm_set_backlight_level,
.get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
- .set_abm_immediate_disable = dce_abm_immediate_disable,
- .is_dmcu_initialized = is_dmcu_initialized
+ .set_abm_immediate_disable = dce_abm_immediate_disable
};
static void dce_abm_construct(
@@ -451,6 +431,10 @@
base->ctx = ctx;
base->funcs = &dce_funcs;
+ base->stored_backlight_registers.BL_PWM_CNTL = 0;
+ base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
+ base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
+ base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
abm_dce->regs = regs;
abm_dce->abm_shift = abm_shift;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index 59e909e..ff94369 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -37,8 +37,7 @@
SR(LVTMA_PWRSEQ_REF_DIV), \
SR(MASTER_COMM_CNTL_REG), \
SR(MASTER_COMM_CMD_REG), \
- SR(MASTER_COMM_DATA_REG1), \
- SR(DMCU_STATUS)
+ SR(MASTER_COMM_DATA_REG1)
#define ABM_DCE110_COMMON_REG_LIST() \
ABM_COMMON_REG_LIST_DCE_BASE(), \
@@ -84,8 +83,7 @@
ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
- ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \
- ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh)
+ ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
@@ -174,7 +172,6 @@
type MASTER_COMM_CMD_REG_BYTE2; \
type BL_PWM_REF_DIV; \
type BL_PWM_EN; \
- type UC_IN_RESET; \
type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
type BL_PWM_GRP1_REG_LOCK; \
type BL_PWM_GRP1_REG_UPDATE_PENDING
@@ -206,7 +203,6 @@
uint32_t MASTER_COMM_CMD_REG;
uint32_t MASTER_COMM_DATA_REG1;
uint32_t BIOS_SCRATCH_2;
- uint32_t DMCU_STATUS;
uint32_t BL_PWM_GRP1_REG_LOCK;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 0f34a9ed..856599c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -29,7 +29,6 @@
#include "fixed32_32.h"
#include "bios_parser_interface.h"
#include "dc.h"
-#include "dce_abm.h"
#include "dmcu.h"
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn_calcs.h"
@@ -384,7 +383,6 @@
struct bp_set_dce_clock_parameters dce_clk_params;
struct dc_bios *bp = clk->ctx->dc_bios;
struct dc *core_dc = clk->ctx->dc;
- struct abm *abm = core_dc->res_pool->abm;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
int actual_clock = requested_clk_khz;
/* Prepare to program display clock*/
@@ -417,7 +415,7 @@
bp->funcs->set_dce_clock(bp, &dce_clk_params);
- if (abm->funcs->is_dmcu_initialized(abm) && clk_dce->dfs_bypass_disp_clk != actual_clock)
+ if (clk_dce->dfs_bypass_disp_clk != actual_clock)
dmcu->funcs->set_psr_wait_loop(dmcu,
actual_clock / 1000 / 7);
clk_dce->dfs_bypass_disp_clk = actual_clock;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index fd77df5..f663adb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -49,8 +49,16 @@
#define PSR_EXIT 0x21
#define PSR_SET 0x23
#define PSR_SET_WAITLOOP 0x31
+#define MCP_INIT_DMCU 0x88
+#define MCP_INIT_IRAM 0x89
+#define MCP_DMCU_VERSION 0x90
#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
-unsigned int cached_wait_loop_number = 0;
+
+static bool dce_dmcu_init(struct dmcu *dmcu)
+{
+ // Do nothing
+ return true;
+}
bool dce_dmcu_load_iram(struct dmcu *dmcu,
unsigned int start_offset,
@@ -84,7 +92,7 @@
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
- uint32_t psrStateOffset = 0xf0;
+ uint32_t psr_state_offset = 0xf0;
/* Enable write access to IRAM */
REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
@@ -92,7 +100,7 @@
REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
- REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
+ REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
@@ -255,13 +263,33 @@
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
}
+static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+ unsigned int dmcu_uc_reset;
+
+ /* microcontroller is not running */
+ REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
+
+ /* DMCU is not running */
+ if (dmcu_uc_reset)
+ return false;
+
+ return true;
+}
+
static void dce_psr_wait_loop(
struct dmcu *dmcu,
unsigned int wait_loop_number)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
- if (cached_wait_loop_number == wait_loop_number)
+
+ if (dmcu->cached_wait_loop_number == wait_loop_number)
+ return;
+
+ /* DMCU is not running */
+ if (!dce_is_dmcu_initialized(dmcu))
return;
/* waitDMCUReadyForCmd */
@@ -269,7 +297,7 @@
masterCmdData1.u32 = 0;
masterCmdData1.bits.wait_loop = wait_loop_number;
- cached_wait_loop_number = wait_loop_number;
+ dmcu->cached_wait_loop_number = wait_loop_number;
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
/* setDMCUParam_Cmd */
@@ -279,14 +307,136 @@
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
}
-static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
+static void dce_get_psr_wait_loop(
+ struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
{
- *psr_wait_loop_number = cached_wait_loop_number;
+ *psr_wait_loop_number = dmcu->cached_wait_loop_number;
return;
}
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
+static void dcn10_get_dmcu_state(struct dmcu *dmcu)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+ uint32_t dmcu_state_offset = 0xf6;
+
+ /* Enable write access to IRAM */
+ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
+ IRAM_HOST_ACCESS_EN, 1,
+ IRAM_RD_ADDR_AUTO_INC, 1);
+
+ REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
+
+ /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
+ REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset);
+
+ /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
+ dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA);
+
+ /* Disable write access to IRAM to allow dynamic sleep state */
+ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
+ IRAM_HOST_ACCESS_EN, 0,
+ IRAM_RD_ADDR_AUTO_INC, 0);
+}
+
+static void dcn10_get_dmcu_version(struct dmcu *dmcu)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+ uint32_t dmcu_version_offset = 0xf1;
+
+ /* Clear scratch */
+ REG_WRITE(DC_DMCU_SCRATCH, 0);
+
+ /* Enable write access to IRAM */
+ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
+ IRAM_HOST_ACCESS_EN, 1,
+ IRAM_RD_ADDR_AUTO_INC, 1);
+
+ REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
+
+ /* Write address to IRAM_RD_ADDR and read from DATA register */
+ REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
+ dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
+ dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
+ REG_READ(DMCU_IRAM_RD_DATA));
+ dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);
+ dmcu->dmcu_version.day = REG_READ(DMCU_IRAM_RD_DATA);
+
+ /* Disable write access to IRAM to allow dynamic sleep state */
+ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
+ IRAM_HOST_ACCESS_EN, 0,
+ IRAM_RD_ADDR_AUTO_INC, 0);
+
+ /* Send MCP command message to DMCU to get version reply from FW.
+ * We expect this version should match the one in IRAM, otherwise
+ * something is wrong with DMCU and we should fail and disable UC.
+ */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+
+ /* Set command to get DMCU version from microcontroller */
+ REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+ MCP_DMCU_VERSION);
+
+ /* Notify microcontroller of new command */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+ /* Ensure command has been executed before continuing */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+
+ /* Somehow version does not match, so fail and return version 0 */
+ if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH))
+ dmcu->dmcu_version.interface_version = 0;
+}
+
+static bool dcn10_dmcu_init(struct dmcu *dmcu)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+
+ /* DMCU FW should populate the scratch register if running */
+ if (REG_READ(DC_DMCU_SCRATCH) == 0)
+ return false;
+
+ /* Check state is uninitialized */
+ dcn10_get_dmcu_state(dmcu);
+
+ /* If microcontroller is already initialized, do nothing */
+ if (dmcu->dmcu_state == DMCU_RUNNING)
+ return true;
+
+ /* Retrieve and cache the DMCU firmware version. */
+ dcn10_get_dmcu_version(dmcu);
+
+ /* Check interface version to confirm firmware is loaded and running */
+ if (dmcu->dmcu_version.interface_version == 0)
+ return false;
+
+ /* Wait until microcontroller is ready to process interrupt */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+
+ /* Set initialized ramping boundary value */
+ REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
+
+ /* Set command to initialize microcontroller */
+ REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+ MCP_INIT_DMCU);
+
+ /* Notify microcontroller of new command */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+ /* Ensure command has been executed before continuing */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+
+ // Check state is initialized
+ dcn10_get_dmcu_state(dmcu);
+
+ // If microcontroller is not in running state, fail
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return false;
+
+ return true;
+}
+
+static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
unsigned int start_offset,
const char *src,
unsigned int bytes)
@@ -294,7 +444,9 @@
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
unsigned int count = 0;
- REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1);
+ /* If microcontroller is not running, do nothing */
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return false;
/* Enable write access to IRAM */
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
@@ -313,6 +465,19 @@
IRAM_HOST_ACCESS_EN, 0,
IRAM_WR_ADDR_AUTO_INC, 0);
+ /* Wait until microcontroller is ready to process interrupt */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+
+ /* Set command to signal IRAM is loaded and to initialize IRAM */
+ REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+ MCP_INIT_IRAM);
+
+ /* Notify microcontroller of new command */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+ /* Ensure command has been executed before continuing */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+
return true;
}
@@ -320,7 +485,11 @@
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
- uint32_t psrStateOffset = 0xf0;
+ uint32_t psr_state_offset = 0xf0;
+
+ /* If microcontroller is not running, do nothing */
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return;
/* Enable write access to IRAM */
REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
@@ -328,7 +497,7 @@
REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
- REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
+ REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
@@ -348,6 +517,10 @@
unsigned int retryCount;
uint32_t psr_state = 0;
+ /* If microcontroller is not running, do nothing */
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return;
+
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
dmcu_wait_reg_ready_interval,
@@ -399,6 +572,10 @@
union dce_dmcu_psr_config_data_reg2 masterCmdData2;
union dce_dmcu_psr_config_data_reg3 masterCmdData3;
+ /* If microcontroller is not running, do nothing */
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return;
+
link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
psr_context->psrExitLinkTrainingRequired);
@@ -505,13 +682,18 @@
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
+
+ /* If microcontroller is not running, do nothing */
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return;
+
if (wait_loop_number != 0) {
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
masterCmdData1.u32 = 0;
masterCmdData1.bits.wait_loop = wait_loop_number;
- cached_wait_loop_number = wait_loop_number;
+ dmcu->cached_wait_loop_number = wait_loop_number;
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
/* setDMCUParam_Cmd */
@@ -522,31 +704,44 @@
}
}
-static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
+static void dcn10_get_psr_wait_loop(
+ struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
{
- *psr_wait_loop_number = cached_wait_loop_number;
+ *psr_wait_loop_number = dmcu->cached_wait_loop_number;
return;
}
+static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
+{
+ /* microcontroller is not running */
+ if (dmcu->dmcu_state != DMCU_RUNNING)
+ return false;
+ return true;
+}
+
#endif
static const struct dmcu_funcs dce_funcs = {
+ .dmcu_init = dce_dmcu_init,
.load_iram = dce_dmcu_load_iram,
.set_psr_enable = dce_dmcu_set_psr_enable,
.setup_psr = dce_dmcu_setup_psr,
.get_psr_state = dce_get_dmcu_psr_state,
.set_psr_wait_loop = dce_psr_wait_loop,
- .get_psr_wait_loop = dce_get_psr_wait_loop
+ .get_psr_wait_loop = dce_get_psr_wait_loop,
+ .is_dmcu_initialized = dce_is_dmcu_initialized
};
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
static const struct dmcu_funcs dcn10_funcs = {
+ .dmcu_init = dcn10_dmcu_init,
.load_iram = dcn10_dmcu_load_iram,
.set_psr_enable = dcn10_dmcu_set_psr_enable,
.setup_psr = dcn10_dmcu_setup_psr,
.get_psr_state = dcn10_get_dmcu_psr_state,
.set_psr_wait_loop = dcn10_psr_wait_loop,
- .get_psr_wait_loop = dcn10_get_psr_wait_loop
+ .get_psr_wait_loop = dcn10_get_psr_wait_loop,
+ .is_dmcu_initialized = dcn10_is_dmcu_initialized
};
#endif
@@ -561,6 +756,7 @@
base->ctx = ctx;
base->funcs = &dce_funcs;
+ base->cached_wait_loop_number = 0;
dmcu_dce->regs = regs;
dmcu_dce->dmcu_shift = dmcu_shift;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index b85f53c..1d4546f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -31,6 +31,7 @@
#define DMCU_COMMON_REG_LIST_DCE_BASE() \
SR(DMCU_CTRL), \
+ SR(DMCU_STATUS), \
SR(DMCU_RAM_ACCESS_CTRL), \
SR(DMCU_IRAM_WR_CTRL), \
SR(DMCU_IRAM_WR_DATA), \
@@ -42,7 +43,8 @@
SR(DMCU_IRAM_RD_CTRL), \
SR(DMCU_IRAM_RD_DATA), \
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
- SR(SMU_INTERRUPT_CONTROL)
+ SR(SMU_INTERRUPT_CONTROL), \
+ SR(DC_DMCU_SCRATCH)
#define DMCU_DCE110_COMMON_REG_LIST() \
DMCU_COMMON_REG_LIST_DCE_BASE(), \
@@ -58,10 +60,16 @@
#define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
DMCU_SF(DMCU_CTRL, \
DMCU_ENABLE, mask_sh), \
+ DMCU_SF(DMCU_STATUS, \
+ UC_IN_STOP_MODE, mask_sh), \
+ DMCU_SF(DMCU_STATUS, \
+ UC_IN_RESET, mask_sh), \
DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
IRAM_HOST_ACCESS_EN, mask_sh), \
DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
IRAM_WR_ADDR_AUTO_INC, mask_sh), \
+ DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+ IRAM_RD_ADDR_AUTO_INC, mask_sh), \
DMCU_SF(MASTER_COMM_CMD_REG, \
MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
@@ -89,7 +97,10 @@
type DMCU_IRAM_MEM_PWR_STATE; \
type IRAM_HOST_ACCESS_EN; \
type IRAM_WR_ADDR_AUTO_INC; \
+ type IRAM_RD_ADDR_AUTO_INC; \
type DMCU_ENABLE; \
+ type UC_IN_STOP_MODE; \
+ type UC_IN_RESET; \
type MASTER_COMM_CMD_REG_BYTE0; \
type MASTER_COMM_INTERRUPT; \
type DPHY_RX_FAST_TRAINING_CAPABLE; \
@@ -112,6 +123,7 @@
struct dce_dmcu_registers {
uint32_t DMCU_CTRL;
+ uint32_t DMCU_STATUS;
uint32_t DMCU_RAM_ACCESS_CTRL;
uint32_t DCI_MEM_PWR_STATUS;
uint32_t DMU_MEM_PWR_CNTL;
@@ -127,6 +139,7 @@
uint32_t DMCU_IRAM_RD_DATA;
uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
uint32_t SMU_INTERRUPT_CONTROL;
+ uint32_t DC_DMCU_SCRATCH;
};
struct dce_dmcu {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index c3c6b0d..dba6958 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -198,9 +198,9 @@
}
/* Only use LUT for 8 bit formats */
-bool dce_use_lut(const struct dc_plane_state *plane_state)
+bool dce_use_lut(enum surface_pixel_format format)
{
- switch (plane_state->format) {
+ switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 5250615..b003984 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -140,10 +140,6 @@
BL_REG_LIST()
#define HWSEQ_DCN_REG_LIST()\
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
SRII(DCHUBP_CNTL, HUBP, 0), \
SRII(DCHUBP_CNTL, HUBP, 1), \
SRII(DCHUBP_CNTL, HUBP, 2), \
@@ -240,6 +236,7 @@
SR(D2VGA_CONTROL), \
SR(D3VGA_CONTROL), \
SR(D4VGA_CONTROL), \
+ SR(VGA_TEST_CONTROL), \
SR(DC_IP_REQUEST_CNTL), \
BL_REG_LIST()
@@ -264,7 +261,6 @@
uint32_t DCHUB_AGP_BOT;
uint32_t DCHUB_AGP_TOP;
- uint32_t OTG_GLOBAL_SYNC_STATUS[4];
uint32_t DCHUBP_CNTL[4];
uint32_t HUBP_CLK_CNTL[4];
uint32_t DPP_CONTROL[4];
@@ -342,6 +338,7 @@
uint32_t D2VGA_CONTROL;
uint32_t D3VGA_CONTROL;
uint32_t D4VGA_CONTROL;
+ uint32_t VGA_TEST_CONTROL;
/* MMHUB registers. read only. temporary hack */
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -438,8 +435,6 @@
#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
- HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
- HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
@@ -500,6 +495,12 @@
HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+ HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
@@ -536,8 +537,6 @@
type LVTMA_PWRSEQ_TARGET_STATE_R;
#define HWSEQ_DCN_REG_FIELD_LIST(type) \
- type VUPDATE_NO_LOCK_EVENT_CLEAR; \
- type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
type HUBP_VTG_SEL; \
type HUBP_CLOCK_ENABLE; \
type DPP_CLOCK_ENABLE; \
@@ -591,7 +590,14 @@
type DOMAIN7_PGFSM_PWR_STATUS; \
type DCFCLK_GATE_DIS; \
type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
- type DENTIST_DPPCLK_WDIVIDER;
+ type DENTIST_DPPCLK_WDIVIDER; \
+ type DENTIST_DISPCLK_WDIVIDER; \
+ type VGA_TEST_ENABLE; \
+ type VGA_TEST_RENDER_START; \
+ type D1VGA_MODE_ENABLE; \
+ type D2VGA_MODE_ENABLE; \
+ type D3VGA_MODE_ENABLE; \
+ type D4VGA_MODE_ENABLE;
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
@@ -627,5 +633,5 @@
struct clock_source *clk_src,
unsigned int tg_inst);
-bool dce_use_lut(const struct dc_plane_state *plane_state);
+bool dce_use_lut(enum surface_pixel_format format);
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
index d618fdd..d737e91 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
@@ -135,36 +135,34 @@
}
-static void dce_ipp_program_prescale(
- struct input_pixel_processor *ipp,
- struct ipp_prescale_params *params)
+static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
+ struct ipp_prescale_params *params)
{
struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
/* set to bypass mode first before change */
REG_UPDATE(PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_BYPASS,
- 1);
+ GRPH_PRESCALE_BYPASS, 1);
REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
- GRPH_PRESCALE_SCALE_R, params->scale,
- GRPH_PRESCALE_BIAS_R, params->bias);
+ GRPH_PRESCALE_SCALE_R, params->scale,
+ GRPH_PRESCALE_BIAS_R, params->bias);
REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
- GRPH_PRESCALE_SCALE_G, params->scale,
- GRPH_PRESCALE_BIAS_G, params->bias);
+ GRPH_PRESCALE_SCALE_G, params->scale,
+ GRPH_PRESCALE_BIAS_G, params->bias);
REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
- GRPH_PRESCALE_SCALE_B, params->scale,
- GRPH_PRESCALE_BIAS_B, params->bias);
+ GRPH_PRESCALE_SCALE_B, params->scale,
+ GRPH_PRESCALE_BIAS_B, params->bias);
if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
REG_UPDATE(PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_BYPASS, 0);
+ GRPH_PRESCALE_BYPASS, 0);
/* If prescale is in use, then legacy lut should be bypassed */
REG_UPDATE(INPUT_GAMMA_CONTROL,
- GRPH_INPUT_GAMMA_MODE, 1);
+ GRPH_INPUT_GAMMA_MODE, 1);
}
}
@@ -223,13 +221,12 @@
struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
- ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||
- mode == IPP_DEGAMMA_MODE_HW_sRGB);
+ ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
REG_SET_3(DEGAMMA_CONTROL, 0,
- GRPH_DEGAMMA_MODE, degamma_type,
- CURSOR_DEGAMMA_MODE, degamma_type,
- CURSOR2_DEGAMMA_MODE, degamma_type);
+ GRPH_DEGAMMA_MODE, degamma_type,
+ CURSOR_DEGAMMA_MODE, degamma_type,
+ CURSOR2_DEGAMMA_MODE, degamma_type);
}
static const struct ipp_funcs dce_ipp_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index fe88852..e4741f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -82,13 +82,6 @@
#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
-/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-#define TMDS_MIN_PIXEL_CLOCK 25000
-/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-#define TMDS_MAX_PIXEL_CLOCK 165000
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLOCK 600000
-
enum {
DP_MST_UPDATE_MAX_RETRY = 50
};
@@ -683,6 +676,7 @@
{
struct bp_encoder_cap_info bp_cap_info = {0};
const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+ enum bp_result result = BP_RESULT_OK;
enc110->base.funcs = &dce110_lnk_enc_funcs;
enc110->base.ctx = init_data->ctx;
@@ -757,15 +751,24 @@
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
}
+ /* default to one to mirror Windows behavior */
+ enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+ result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
+ enc110->base.id, &bp_cap_info);
+
/* Override features with DCE-specific values */
- if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
- enc110->base.ctx->dc_bios, enc110->base.id,
- &bp_cap_info)) {
+ if (BP_RESULT_OK == result) {
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
bp_cap_info.DP_HBR2_EN;
enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
bp_cap_info.DP_HBR3_EN;
enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+ } else {
+ dm_logger_write(enc110->base.ctx->logger, LOG_WARNING,
+ "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+ __func__,
+ result);
}
}
@@ -845,8 +848,6 @@
ASSERT(result == BP_RESULT_OK);
- } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- ctx->dc->hwss.edp_power_control(enc, true);
}
aux_initialize(enc110);
@@ -906,8 +907,7 @@
struct link_encoder *enc,
enum clock_source_id clock_source,
enum dc_color_depth color_depth,
- bool hdmi,
- bool dual_link,
+ enum signal_type signal,
uint32_t pixel_clock)
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
@@ -921,16 +921,12 @@
cntl.engine_id = enc->preferred_engine;
cntl.transmitter = enc110->base.transmitter;
cntl.pll_id = clock_source;
- if (hdmi) {
- cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- cntl.lanes_number = 4;
- } else if (dual_link) {
- cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
+ cntl.signal = signal;
+ if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
cntl.lanes_number = 8;
- } else {
- cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
+ else
cntl.lanes_number = 4;
- }
+
cntl.hpd_sel = enc110->base.hpd_source;
cntl.pixel_clock = pixel_clock;
@@ -1033,8 +1029,7 @@
*/
void dce110_link_encoder_disable_output(
struct link_encoder *enc,
- enum signal_type signal,
- struct dc_link *link)
+ enum signal_type signal)
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
struct dc_context *ctx = enc110->base.ctx;
@@ -1045,8 +1040,6 @@
/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
return;
}
- if (enc110->base.connector.id == CONNECTOR_ID_EDP)
- ctx->dc->hwss.edp_backlight_control(link, false);
/* Power-down RX and disable GPU PHY should be paired.
* Disabling PHY without powering down RX may cause
* symbol lock loss, on which we will get DP Sink interrupt. */
@@ -1077,20 +1070,6 @@
/* disable encoder */
if (dc_is_dp_signal(signal))
link_encoder_disable(enc110);
-
- if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- /* power down eDP panel */
- /* TODO: Power control cause regression, we should implement
- * it properly, for now just comment it.
- *
- * link_encoder_edp_wait_for_hpd_ready(
- link_enc,
- link_enc->connector,
- false);
-
- * link_encoder_edp_power_control(
- link_enc, false); */
- }
}
void dce110_link_encoder_dp_set_lane_settings(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 494067d..0ec3433 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -210,8 +210,7 @@
struct link_encoder *enc,
enum clock_source_id clock_source,
enum dc_color_depth color_depth,
- bool hdmi,
- bool dual_link,
+ enum signal_type signal,
uint32_t pixel_clock);
/* enables DP PHY output */
@@ -228,9 +227,8 @@
/* disable PHY output */
void dce110_link_encoder_disable_output(
- struct link_encoder *link_enc,
- enum signal_type signal,
- struct dc_link *link);
+ struct link_encoder *enc,
+ enum signal_type signal);
/* set DP lane settings */
void dce110_link_encoder_dp_set_lane_settings(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 3931412..8709389 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -128,23 +128,22 @@
return;
}
/* on other format-to do */
- if (params->flags.TRUNCATE_ENABLED == 0 ||
- params->flags.TRUNCATE_DEPTH == 2)
+ if (params->flags.TRUNCATE_ENABLED == 0)
return;
/*Set truncation depth and Enable truncation*/
REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
FMT_TRUNCATE_EN, 1,
FMT_TRUNCATE_DEPTH,
- params->flags.TRUNCATE_MODE,
+ params->flags.TRUNCATE_DEPTH,
FMT_TRUNCATE_MODE,
- params->flags.TRUNCATE_DEPTH);
+ params->flags.TRUNCATE_MODE);
}
/**
* set_spatial_dither
* 1) set spatial dithering mode: pattern of seed
- * 2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
+ * 2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
* 3) set random seed
* 4) set random mode
* lfsr is reset every frame or not reset
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index e42b6eb..83bae20 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -300,6 +300,8 @@
uint32_t h_back_porch;
uint8_t synchronous_clock = 0; /* asynchronous mode */
uint8_t colorimetry_bpc;
+ uint8_t dynamic_range_rgb = 0; /*full range*/
+ uint8_t dynamic_range_ycbcr = 1; /*bt709*/
#endif
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
@@ -380,11 +382,7 @@
}
/* set dynamic range and YCbCr range */
- if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
- REG_UPDATE_2(
- DP_PIXEL_FORMAT,
- DP_DYN_RANGE, 0,
- DP_YCBCR_RANGE, 0);
+
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
switch (crtc_timing->display_color_depth) {
@@ -413,37 +411,57 @@
case COLOR_SPACE_SRGB:
misc0 = misc0 | 0x0;
misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_rgb = 0; /*full range*/
break;
case COLOR_SPACE_SRGB_LIMITED:
misc0 = misc0 | 0x8; /* bit3=1 */
misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_rgb = 1; /*limited range*/
break;
case COLOR_SPACE_YCBCR601:
+ case COLOR_SPACE_YCBCR601_LIMITED:
misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_ycbcr = 0; /*bt601*/
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
break;
case COLOR_SPACE_YCBCR709:
+ case COLOR_SPACE_YCBCR709_LIMITED:
misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_ycbcr = 1; /*bt709*/
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
break;
- case COLOR_SPACE_2020_RGB_FULLRANGE:
case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+ dynamic_range_rgb = 1; /*limited range*/
+ break;
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
case COLOR_SPACE_2020_YCBCR:
+ case COLOR_SPACE_XR_RGB:
+ case COLOR_SPACE_MSREF_SCRGB:
case COLOR_SPACE_ADOBERGB:
+ case COLOR_SPACE_DCIP3:
+ case COLOR_SPACE_XV_YCC_709:
+ case COLOR_SPACE_XV_YCC_601:
+ case COLOR_SPACE_DISPLAYNATIVE:
+ case COLOR_SPACE_DOLBYVISION:
+ case COLOR_SPACE_APPCTRL:
+ case COLOR_SPACE_CUSTOMPOINTS:
case COLOR_SPACE_UNKNOWN:
- case COLOR_SPACE_YCBCR601_LIMITED:
- case COLOR_SPACE_YCBCR709_LIMITED:
/* do nothing */
break;
}
+ if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
+ REG_UPDATE_2(
+ DP_PIXEL_FORMAT,
+ DP_DYN_RANGE, dynamic_range_rgb,
+ DP_YCBCR_RANGE, dynamic_range_ycbcr);
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (REG(DP_MSA_COLORIMETRY))
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index df8f82b..ac28113 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1177,207 +1177,160 @@
default_adjust->out_color_space);
}
-static void program_pwl(
- struct dce_transform *xfm_dce,
- const struct pwl_params *params)
+static void program_pwl(struct dce_transform *xfm_dce,
+ const struct pwl_params *params)
{
- uint32_t value;
int retval;
+ uint8_t max_tries = 10;
+ uint8_t counter = 0;
+ uint32_t i = 0;
+ const struct pwl_result_data *rgb = params->rgb_resulted;
- {
- uint8_t max_tries = 10;
- uint8_t counter = 0;
+ /* Power on LUT memory */
+ if (REG(DCFE_MEM_PWR_CTRL))
+ REG_UPDATE(DCFE_MEM_PWR_CTRL,
+ DCP_REGAMMA_MEM_PWR_DIS, 1);
+ else
+ REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
+ REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
- /* Power on LUT memory */
- if (REG(DCFE_MEM_PWR_CTRL))
- REG_UPDATE(DCFE_MEM_PWR_CTRL,
- DCP_REGAMMA_MEM_PWR_DIS, 1);
- else
- REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
+ while (counter < max_tries) {
+ if (REG(DCFE_MEM_PWR_STATUS)) {
+ REG_GET(DCFE_MEM_PWR_STATUS,
+ DCP_REGAMMA_MEM_PWR_STATE,
+ &retval);
- while (counter < max_tries) {
- if (REG(DCFE_MEM_PWR_STATUS)) {
- value = REG_READ(DCFE_MEM_PWR_STATUS);
- REG_GET(DCFE_MEM_PWR_STATUS,
- DCP_REGAMMA_MEM_PWR_STATE,
- &retval);
+ if (retval == 0)
+ break;
+ ++counter;
+ } else {
+ REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
+ REGAMMA_LUT_MEM_PWR_STATE,
+ &retval);
- if (retval == 0)
- break;
- ++counter;
- } else {
- value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
- REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_MEM_PWR_STATE,
- &retval);
-
- if (retval == 0)
- break;
- ++counter;
- }
+ if (retval == 0)
+ break;
+ ++counter;
}
+ }
- if (counter == max_tries) {
- dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
+ if (counter == max_tries) {
+ dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
"%s: regamma lut was not powered on "
"in a timely manner,"
" programming still proceeds\n",
__func__);
- }
}
REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
- REGAMMA_LUT_WRITE_EN_MASK, 7);
+ REGAMMA_LUT_WRITE_EN_MASK, 7);
REG_WRITE(REGAMMA_LUT_INDEX, 0);
/* Program REGAMMA_LUT_DATA */
- {
- uint32_t i = 0;
- const struct pwl_result_data *rgb = params->rgb_resulted;
+ while (i != params->hw_points_num) {
- while (i != params->hw_points_num) {
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
-
- ++rgb;
- ++i;
- }
+ ++rgb;
+ ++i;
}
/* we are done with DCP LUT memory; re-enable low power mode */
if (REG(DCFE_MEM_PWR_CTRL))
REG_UPDATE(DCFE_MEM_PWR_CTRL,
- DCP_REGAMMA_MEM_PWR_DIS, 0);
+ DCP_REGAMMA_MEM_PWR_DIS, 0);
else
REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
+ REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
}
-static void regamma_config_regions_and_segments(
- struct dce_transform *xfm_dce,
- const struct pwl_params *params)
+static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
+ const struct pwl_params *params)
{
const struct gamma_curve *curve;
- {
- REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
- REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
- REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
- }
- {
- REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
- REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
+ REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
+ REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
+ REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
- }
- {
- REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
- REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
- }
- {
- REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
- REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
- REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope);
- }
+ REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
+ REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
+
+ REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
+ REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
+ REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
+ REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope);
curve = params->arr_curve_points;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
- }
-
+ REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
curve += 2;
- {
- REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
- }
+ REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
}
-void dce110_opp_program_regamma_pwl(
- struct transform *xfm,
- const struct pwl_params *params)
+void dce110_opp_program_regamma_pwl(struct transform *xfm,
+ const struct pwl_params *params)
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
@@ -1388,47 +1341,42 @@
program_pwl(xfm_dce, params);
}
-void dce110_opp_power_on_regamma_lut(
- struct transform *xfm,
- bool power_on)
+void dce110_opp_power_on_regamma_lut(struct transform *xfm,
+ bool power_on)
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
if (REG(DCFE_MEM_PWR_CTRL))
REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
- DCP_REGAMMA_MEM_PWR_DIS, power_on,
- DCP_LUT_MEM_PWR_DIS, power_on);
+ DCP_REGAMMA_MEM_PWR_DIS, power_on,
+ DCP_LUT_MEM_PWR_DIS, power_on);
else
REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
- DCP_LUT_LIGHT_SLEEP_DIS, power_on);
+ REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
+ DCP_LUT_LIGHT_SLEEP_DIS, power_on);
}
void dce110_opp_set_regamma_mode(struct transform *xfm,
- enum opp_regamma mode)
+ enum opp_regamma mode)
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
REG_SET(REGAMMA_CONTROL, 0,
- GRPH_REGAMMA_MODE, mode);
+ GRPH_REGAMMA_MODE, mode);
}
static const struct transform_funcs dce_transform_funcs = {
.transform_reset = dce_transform_reset,
- .transform_set_scaler =
- dce_transform_set_scaler,
- .transform_set_gamut_remap =
- dce_transform_set_gamut_remap,
+ .transform_set_scaler = dce_transform_set_scaler,
+ .transform_set_gamut_remap = dce_transform_set_gamut_remap,
.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
.opp_set_csc_default = dce110_opp_set_csc_default,
.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
- .transform_set_pixel_storage_depth =
- dce_transform_set_pixel_storage_depth,
- .transform_get_optimal_number_of_taps =
- dce_transform_get_optimal_number_of_taps
+ .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth,
+ .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps
};
/*****************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index e7a6948..469af05 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -148,5 +148,7 @@
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc->hwss.set_bandwidth = dce100_set_bandwidth;
+ dc->hwss.pplib_apply_display_requirements =
+ dce100_pplib_apply_display_requirements;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3ea43e2..442dd2d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -852,6 +852,7 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b3b183a..e2f4963 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -257,9 +257,9 @@
}
}
-static bool dce110_set_input_transfer_func(
- struct pipe_ctx *pipe_ctx,
- const struct dc_plane_state *plane_state)
+static bool
+dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ const struct dc_plane_state *plane_state)
{
struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
const struct dc_transfer_func *tf = NULL;
@@ -275,30 +275,24 @@
build_prescale_params(&prescale_params, plane_state);
ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
- if (plane_state->gamma_correction && dce_use_lut(plane_state))
+ if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
if (tf == NULL) {
/* Default case if no input transfer function specified */
- ipp->funcs->ipp_set_degamma(ipp,
- IPP_DEGAMMA_MODE_HW_sRGB);
+ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
} else if (tf->type == TF_TYPE_PREDEFINED) {
switch (tf->tf) {
case TRANSFER_FUNCTION_SRGB:
- ipp->funcs->ipp_set_degamma(ipp,
- IPP_DEGAMMA_MODE_HW_sRGB);
+ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
break;
case TRANSFER_FUNCTION_BT709:
- ipp->funcs->ipp_set_degamma(ipp,
- IPP_DEGAMMA_MODE_HW_xvYCC);
+ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
break;
case TRANSFER_FUNCTION_LINEAR:
- ipp->funcs->ipp_set_degamma(ipp,
- IPP_DEGAMMA_MODE_BYPASS);
+ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
break;
case TRANSFER_FUNCTION_PQ:
- result = false;
- break;
default:
result = false;
break;
@@ -313,10 +307,9 @@
return result;
}
-static bool convert_to_custom_float(
- struct pwl_result_data *rgb_resulted,
- struct curve_points *arr_points,
- uint32_t hw_points_num)
+static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
+ struct curve_points *arr_points,
+ uint32_t hw_points_num)
{
struct custom_float_format fmt;
@@ -328,26 +321,20 @@
fmt.mantissa_bits = 12;
fmt.sign = true;
- if (!convert_to_custom_float_format(
- arr_points[0].x,
- &fmt,
- &arr_points[0].custom_float_x)) {
+ if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
+ &arr_points[0].custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- arr_points[0].offset,
- &fmt,
- &arr_points[0].custom_float_offset)) {
+ if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
+ &arr_points[0].custom_float_offset)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- arr_points[0].slope,
- &fmt,
- &arr_points[0].custom_float_slope)) {
+ if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
+ &arr_points[0].custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
@@ -355,26 +342,20 @@
fmt.mantissa_bits = 10;
fmt.sign = false;
- if (!convert_to_custom_float_format(
- arr_points[1].x,
- &fmt,
- &arr_points[1].custom_float_x)) {
+ if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
+ &arr_points[1].custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- arr_points[1].y,
- &fmt,
- &arr_points[1].custom_float_y)) {
+ if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
+ &arr_points[1].custom_float_y)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- arr_points[2].slope,
- &fmt,
- &arr_points[2].custom_float_slope)) {
+ if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
+ &arr_points[1].custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
@@ -383,50 +364,38 @@
fmt.sign = true;
while (i != hw_points_num) {
- if (!convert_to_custom_float_format(
- rgb->red,
- &fmt,
- &rgb->red_reg)) {
+ if (!convert_to_custom_float_format(rgb->red, &fmt,
+ &rgb->red_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- rgb->green,
- &fmt,
- &rgb->green_reg)) {
+ if (!convert_to_custom_float_format(rgb->green, &fmt,
+ &rgb->green_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- rgb->blue,
- &fmt,
- &rgb->blue_reg)) {
+ if (!convert_to_custom_float_format(rgb->blue, &fmt,
+ &rgb->blue_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- rgb->delta_red,
- &fmt,
- &rgb->delta_red_reg)) {
+ if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
+ &rgb->delta_red_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- rgb->delta_green,
- &fmt,
- &rgb->delta_green_reg)) {
+ if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
+ &rgb->delta_green_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
- if (!convert_to_custom_float_format(
- rgb->delta_blue,
- &fmt,
- &rgb->delta_blue_reg)) {
+ if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
+ &rgb->delta_blue_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
@@ -438,8 +407,9 @@
return true;
}
-static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
- *output_tf, struct pwl_params *regamma_params)
+static bool
+dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
+ struct pwl_params *regamma_params)
{
struct curve_points *arr_points;
struct pwl_result_data *rgb_resulted;
@@ -454,8 +424,7 @@
int32_t segment_start, segment_end;
uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
- if (output_tf == NULL || regamma_params == NULL ||
- output_tf->type == TF_TYPE_BYPASS)
+ if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
return false;
arr_points = regamma_params->arr_points;
@@ -534,19 +503,14 @@
/* last point */
start_index = (segment_end + 25) * 32;
- rgb_resulted[hw_points - 1].red =
- output_tf->tf_pts.red[start_index];
- rgb_resulted[hw_points - 1].green =
- output_tf->tf_pts.green[start_index];
- rgb_resulted[hw_points - 1].blue =
- output_tf->tf_pts.blue[start_index];
+ rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
+ rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_start));
+ dal_fixed31_32_from_int(segment_start));
arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_end));
- arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_end));
+ dal_fixed31_32_from_int(segment_end));
y_r = rgb_resulted[0].red;
y_g = rgb_resulted[0].green;
@@ -555,9 +519,8 @@
y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
arr_points[0].y = y1_min;
- arr_points[0].slope = dal_fixed31_32_div(
- arr_points[0].y,
- arr_points[0].x);
+ arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y,
+ arr_points[0].x);
y_r = rgb_resulted[hw_points - 1].red;
y_g = rgb_resulted[hw_points - 1].green;
@@ -569,24 +532,18 @@
y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
arr_points[1].y = y3_max;
- arr_points[2].y = y3_max;
arr_points[1].slope = dal_fixed31_32_zero;
- arr_points[2].slope = dal_fixed31_32_zero;
if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
/* for PQ, we want to have a straight line from last HW X point,
* and the slope to be such that we hit 1.0 at 10000 nits.
*/
- const struct fixed31_32 end_value =
- dal_fixed31_32_from_int(125);
+ const struct fixed31_32 end_value = dal_fixed31_32_from_int(125);
arr_points[1].slope = dal_fixed31_32_div(
- dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
- dal_fixed31_32_sub(end_value, arr_points[1].x));
- arr_points[2].slope = dal_fixed31_32_div(
- dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
- dal_fixed31_32_sub(end_value, arr_points[1].x));
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
}
regamma_params->hw_points_num = hw_points;
@@ -594,18 +551,15 @@
i = 1;
for (k = 0; k < 16 && i < 16; k++) {
if (seg_distr[k] != -1) {
- regamma_params->arr_curve_points[k].segments_num =
- seg_distr[k];
+ regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
regamma_params->arr_curve_points[i].offset =
- regamma_params->arr_curve_points[k].
- offset + (1 << seg_distr[k]);
+ regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
i++;
}
if (seg_distr[k] != -1)
- regamma_params->arr_curve_points[k].segments_num =
- seg_distr[k];
+ regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
rgb = rgb_resulted;
rgb_plus_1 = rgb_resulted + 1;
@@ -620,15 +574,9 @@
if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
rgb_plus_1->blue = rgb->blue;
- rgb->delta_red = dal_fixed31_32_sub(
- rgb_plus_1->red,
- rgb->red);
- rgb->delta_green = dal_fixed31_32_sub(
- rgb_plus_1->green,
- rgb->green);
- rgb->delta_blue = dal_fixed31_32_sub(
- rgb_plus_1->blue,
- rgb->blue);
+ rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
+ rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
+ rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
++rgb_plus_1;
++rgb;
@@ -640,9 +588,9 @@
return true;
}
-static bool dce110_set_output_transfer_func(
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+static bool
+dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ const struct dc_stream_state *stream)
{
struct transform *xfm = pipe_ctx->plane_res.xfm;
@@ -650,13 +598,11 @@
xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
if (stream->out_transfer_func &&
- stream->out_transfer_func->type ==
- TF_TYPE_PREDEFINED &&
- stream->out_transfer_func->tf ==
- TRANSFER_FUNCTION_SRGB) {
+ stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
+ stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
- } else if (dce110_translate_regamma_to_hw_format(
- stream->out_transfer_func, &xfm->regamma_params)) {
+ } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
+ &xfm->regamma_params)) {
xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
} else {
@@ -742,15 +688,22 @@
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
struct dc_link *link = pipe_ctx->stream->sink->link;
- /* 1. update AVI info frame (HDMI, DP)
- * we always need to update info frame
- */
+
uint32_t active_total_with_borders;
uint32_t early_control = 0;
struct timing_generator *tg = pipe_ctx->stream_res.tg;
- /* TODOFPGA may change to hwss.update_info_frame */
+ /* For MST, there are multiply stream go to only one link.
+ * connect DIG back_end to front_end while enable_stream and
+ * disconnect them during disable_stream
+ * BY this, it is logic clean to separate stream and link */
+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+ pipe_ctx->stream_res.stream_enc->id, true);
+
+ /* update AVI info frame (HDMI, DP)*/
+ /* TODO: FPGA may change to hwss.update_info_frame */
dce110_update_info_frame(pipe_ctx);
+
/* enable early control to avoid corruption on DP monitor*/
active_total_with_borders =
timing->h_addressable
@@ -771,12 +724,8 @@
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
}
- /* For MST, there are multiply stream go to only one link.
- * connect DIG back_end to front_end while enable_stream and
- * disconnect them during disable_stream
- * BY this, it is logic clean to separate stream and link */
- link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
- pipe_ctx->stream_res.stream_enc->id, true);
+
+
}
@@ -814,11 +763,11 @@
* eDP only.
*/
void hwss_edp_wait_for_hpd_ready(
- struct link_encoder *enc,
- bool power_up)
+ struct dc_link *link,
+ bool power_up)
{
- struct dc_context *ctx = enc->ctx;
- struct graphics_object_id connector = enc->connector;
+ struct dc_context *ctx = link->ctx;
+ struct graphics_object_id connector = link->link_enc->connector;
struct gpio *hpd;
bool edp_hpd_high = false;
uint32_t time_elapsed = 0;
@@ -882,16 +831,16 @@
}
void hwss_edp_power_control(
- struct link_encoder *enc,
- bool power_up)
+ struct dc_link *link,
+ bool power_up)
{
- struct dc_context *ctx = enc->ctx;
+ struct dc_context *ctx = link->ctx;
struct dce_hwseq *hwseq = ctx->dc->hwseq;
struct bp_transmitter_control cntl = { 0 };
enum bp_result bp_result;
- if (dal_graphics_object_id_get_connector_id(enc->connector)
+ if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
!= CONNECTOR_ID_EDP) {
BREAK_TO_DEBUGGER();
return;
@@ -907,11 +856,11 @@
cntl.action = power_up ?
TRANSMITTER_CONTROL_POWER_ON :
TRANSMITTER_CONTROL_POWER_OFF;
- cntl.transmitter = enc->transmitter;
- cntl.connector_obj_id = enc->connector;
+ cntl.transmitter = link->link_enc->transmitter;
+ cntl.connector_obj_id = link->link_enc->connector;
cntl.coherent = false;
cntl.lanes_number = LANE_COUNT_FOUR;
- cntl.hpd_sel = enc->hpd_source;
+ cntl.hpd_sel = link->link_enc->hpd_source;
bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
@@ -924,8 +873,6 @@
"%s: Skipping Panel Power action: %s\n",
__func__, (power_up ? "On":"Off"));
}
-
- hwss_edp_wait_for_hpd_ready(enc, true);
}
/*todo: cloned in stream enc, fix*/
@@ -934,14 +881,14 @@
* eDP only. Control the backlight of the eDP panel
*/
void hwss_edp_backlight_control(
- struct dc_link *link,
- bool enable)
+ struct dc_link *link,
+ bool enable)
{
- struct dce_hwseq *hws = link->dc->hwseq;
- struct dc_context *ctx = link->dc->ctx;
+ struct dc_context *ctx = link->ctx;
+ struct dce_hwseq *hws = ctx->dc->hwseq;
struct bp_transmitter_control cntl = { 0 };
- if (dal_graphics_object_id_get_connector_id(link->link_id)
+ if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
!= CONNECTOR_ID_EDP) {
BREAK_TO_DEBUGGER();
return;
@@ -982,7 +929,7 @@
* Enable it in the future if necessary.
*/
/* dc_service_sleep_in_milliseconds(50); */
- link_transmitter_control(link->dc->ctx->dc_bios, &cntl);
+ link_transmitter_control(ctx->dc_bios, &cntl);
}
void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
@@ -1026,11 +973,9 @@
}
/* blank at encoder level */
- if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
- if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP)
- hwss_edp_backlight_control(link, false);
+ if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
- }
+
link->link_enc->funcs->connect_dig_be_to_fe(
link->link_enc,
pipe_ctx->stream_res.stream_enc->id,
@@ -1042,15 +987,12 @@
struct dc_link_settings *link_settings)
{
struct encoder_unblank_param params = { { 0 } };
- struct dc_link *link = pipe_ctx->stream->sink->link;
/* only 3 items below are used by unblank */
params.pixel_clk_khz =
pipe_ctx->stream->timing.pix_clk_khz;
params.link_settings.link_rate = link_settings->link_rate;
pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
- if (link->connector_signal == SIGNAL_TYPE_EDP)
- hwss_edp_backlight_control(link, true);
}
@@ -1401,7 +1343,7 @@
}
dc->links[i]->link_enc->funcs->disable_output(
- dc->links[i]->link_enc, signal, dc->links[i]);
+ dc->links[i]->link_enc, signal);
}
}
@@ -1462,7 +1404,9 @@
enable_display_pipe_clock_gating(ctx,
true);
- dc->hwss.power_down_front_end(dc, i);
+ dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
+ dc->hwss.disable_plane(dc,
+ &dc->current_state->res_ctx.pipe_ctx[i]);
}
}
@@ -1896,7 +1840,7 @@
if (old_clk)
old_clk->funcs->cs_power_down(old_clk);
- dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
+ dc->hwss.disable_plane(dc, pipe_ctx_old);
pipe_ctx_old->stream = NULL;
}
@@ -2084,8 +2028,7 @@
if (pipe_ctx->stream == pipe_ctx_old->stream)
continue;
- if (pipe_ctx->stream && pipe_ctx_old->stream
- && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
+ if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
continue;
if (pipe_ctx->top_pipe)
@@ -2121,9 +2064,6 @@
context,
dc);
- if (dc->hwss.power_on_front_end)
- dc->hwss.power_on_front_end(dc, pipe_ctx, context);
-
if (DC_OK != status)
return status;
}
@@ -2153,16 +2093,8 @@
struct default_adjustment default_adjust = { 0 };
default_adjust.force_hw_default = false;
- if (pipe_ctx->plane_state == NULL)
- default_adjust.in_color_space = COLOR_SPACE_SRGB;
- else
- default_adjust.in_color_space =
- pipe_ctx->plane_state->color_space;
- if (pipe_ctx->stream == NULL)
- default_adjust.out_color_space = COLOR_SPACE_SRGB;
- else
- default_adjust.out_color_space =
- pipe_ctx->stream->output_color_space;
+ default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
+ default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
@@ -2287,8 +2219,7 @@
dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
set_default_colors(pipe_ctx);
- if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
- == true) {
+ if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
tbl_entry.color_space =
pipe_ctx->stream->output_color_space;
@@ -2466,20 +2397,16 @@
for (i = 1 /* skip the master */; i < group_size; i++)
grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
- grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
-
-
+ grouped_pipes[i]->stream_res.tg,
+ gsl_params.gsl_group);
for (i = 1 /* skip the master */; i < group_size; i++) {
DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
- /* Regardless of success of the wait above, remove the reset or
- * the driver will start timing out on Display requests. */
- DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
- grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
+ grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
+ grouped_pipes[i]->stream_res.tg);
}
-
/* GSL Vblank synchronization is a one time sync mechanism, assumption
* is that the sync'ed displays will not drift out of sync over time*/
DC_SYNC_INFO("GSL: Restoring register states.\n");
@@ -2489,6 +2416,39 @@
DC_SYNC_INFO("GSL: Set-up complete.\n");
}
+static void dce110_enable_per_frame_crtc_position_reset(
+ struct dc *dc,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[])
+{
+ struct dc_context *dc_ctx = dc->ctx;
+ struct dcp_gsl_params gsl_params = { 0 };
+ int i;
+
+ gsl_params.gsl_group = 0;
+ gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
+
+ for (i = 0; i < group_size; i++)
+ grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
+ grouped_pipes[i]->stream_res.tg, &gsl_params);
+
+ DC_SYNC_INFO("GSL: enabling trigger-reset\n");
+
+ for (i = 1; i < group_size; i++)
+ grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
+ grouped_pipes[i]->stream_res.tg,
+ gsl_params.gsl_master,
+ &grouped_pipes[i]->stream->triggered_crtc_reset);
+
+ DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
+ for (i = 1; i < group_size; i++)
+ wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
+
+ for (i = 0; i < group_size; i++)
+ grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
+
+}
+
static void init_hw(struct dc *dc)
{
int i;
@@ -2521,6 +2481,10 @@
* required signal (which may be different from the
* default signal on connector). */
struct dc_link *link = dc->links[i];
+
+ if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
+ dc->hwss.edp_power_control(link, true);
+
link->link_enc->funcs->hw_init(link->link_enc);
}
@@ -2575,6 +2539,10 @@
ASSERT(pipe_ctx != NULL);
+ /* only notify active stream */
+ if (stream->dpms_off)
+ continue;
+
num_cfgs++;
cfg->signal = pipe_ctx->stream->signal;
cfg->pipe_idx = pipe_ctx->pipe_idx;
@@ -2730,8 +2698,6 @@
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
- struct pipe_ctx *cur_pipe_ctx =
- &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
unsigned int i;
#if defined(CONFIG_DRM_AMD_DC_FBC)
unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
@@ -2827,12 +2793,13 @@
plane_state->rotation);
/* Moved programming gamma from dc to hwss */
- if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
- dc->hwss.set_input_transfer_func(
- pipe_ctx, pipe_ctx->plane_state);
- dc->hwss.set_output_transfer_func(
- pipe_ctx, pipe_ctx->stream);
- }
+ if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+ dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
+
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
dm_logger_write(dc->ctx->logger, LOG_SURFACE,
"Pipe:%d 0x%x: addr hi:0x%x, "
@@ -2901,13 +2868,12 @@
continue;
/* Need to allocate mem before program front end for Fiji */
- if (pipe_ctx->plane_res.mi != NULL)
- pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
- pipe_ctx->plane_res.mi,
- pipe_ctx->stream->timing.h_total,
- pipe_ctx->stream->timing.v_total,
- pipe_ctx->stream->timing.pix_clk_khz,
- context->stream_count);
+ pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
+ pipe_ctx->plane_res.mi,
+ pipe_ctx->stream->timing.h_total,
+ pipe_ctx->stream->timing.v_total,
+ pipe_ctx->stream->timing.pix_clk_khz,
+ context->stream_count);
dce110_program_front_end_for_pipe(dc, pipe_ctx);
@@ -2928,8 +2894,10 @@
}
}
-static void dce110_power_down_fe(struct dc *dc, int fe_idx)
+static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
+ int fe_idx = pipe_ctx->pipe_idx;
+
/* Do not power down fe when stream is active on dce*/
if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
return;
@@ -2971,6 +2939,49 @@
}
}
+void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
+{
+ struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
+ struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
+ struct mem_input *mi = pipe_ctx->plane_res.mi;
+ struct dc_cursor_mi_param param = {
+ .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
+ .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
+ .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
+ .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
+ .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
+ };
+
+ if (pipe_ctx->plane_state->address.type
+ == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+ pos_cpy.enable = false;
+
+ if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
+ pos_cpy.enable = false;
+
+ if (ipp->funcs->ipp_cursor_set_position)
+ ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
+ if (mi->funcs->set_cursor_position)
+ mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
+}
+
+void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+{
+ struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+
+ if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
+ pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
+ pipe_ctx->plane_res.ipp, attributes);
+
+ if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
+ pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
+ pipe_ctx->plane_res.mi, attributes);
+
+ if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
+ pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
+ pipe_ctx->plane_res.xfm, attributes);
+}
+
static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
static void optimize_shared_resources(struct dc *dc) {}
@@ -2989,13 +3000,14 @@
.power_down = dce110_power_down,
.enable_accelerated_mode = dce110_enable_accelerated_mode,
.enable_timing_synchronization = dce110_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
.update_info_frame = dce110_update_info_frame,
.enable_stream = dce110_enable_stream,
.disable_stream = dce110_disable_stream,
.unblank_stream = dce110_unblank_stream,
.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
.enable_display_power_gating = dce110_enable_display_power_gating,
- .power_down_front_end = dce110_power_down_fe,
+ .disable_plane = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
.set_bandwidth = dce110_set_bandwidth,
.set_drr = set_drr,
@@ -3008,8 +3020,12 @@
.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
.ready_shared_resources = ready_shared_resources,
.optimize_shared_resources = optimize_shared_resources,
+ .pplib_apply_display_requirements = pplib_apply_display_requirements,
.edp_backlight_control = hwss_edp_backlight_control,
.edp_power_control = hwss_edp_power_control,
+ .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
+ .set_cursor_position = dce110_set_cursor_position,
+ .set_cursor_attribute = dce110_set_cursor_attribute
};
void dce110_hw_sequencer_construct(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index 4d72bb9..fc63764 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -70,12 +70,16 @@
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
void hwss_edp_power_control(
- struct link_encoder *enc,
- bool power_up);
+ struct dc_link *link,
+ bool power_up);
void hwss_edp_backlight_control(
struct dc_link *link,
bool enable);
+void hwss_edp_wait_for_hpd_ready(
+ struct dc_link *link,
+ bool power_up);
+
#endif /* __DC_HWSS_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index a06c602..7bab8c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -237,26 +237,14 @@
if (rotation == ROTATION_ANGLE_90 ||
rotation == ROTATION_ANGLE_270) {
- uint32_t swap;
- swap = local_size.video.luma_size.x;
- local_size.video.luma_size.x =
- local_size.video.luma_size.y;
- local_size.video.luma_size.y = swap;
-
- swap = local_size.video.luma_size.width;
- local_size.video.luma_size.width =
- local_size.video.luma_size.height;
- local_size.video.luma_size.height = swap;
-
- swap = local_size.video.chroma_size.x;
- local_size.video.chroma_size.x =
- local_size.video.chroma_size.y;
- local_size.video.chroma_size.y = swap;
-
- swap = local_size.video.chroma_size.width;
- local_size.video.chroma_size.width =
- local_size.video.chroma_size.height;
- local_size.video.chroma_size.height = swap;
+ swap(local_size.video.luma_size.x,
+ local_size.video.luma_size.y);
+ swap(local_size.video.luma_size.width,
+ local_size.video.luma_size.height);
+ swap(local_size.video.chroma_size.x,
+ local_size.video.chroma_size.y);
+ swap(local_size.video.chroma_size.width,
+ local_size.video.chroma_size.height);
}
value = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
index e98ed30..9b65b77e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
@@ -175,7 +175,7 @@
value = 0;
set_reg_field_value(
value,
- params->arr_points[2].custom_float_slope,
+ params->arr_points[1].custom_float_slope,
GAMMA_CORR_CNTLA_END_CNTL2,
GAMMA_CORR_CNTLA_EXP_REGION_END_BASE);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 0488853..00f18c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1174,6 +1174,7 @@
dc->caps.max_downscale_ratio = 150;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 128;
+ dc->caps.is_apu = true;
/*************************************************
* Create resources *
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 4befce6..25ca721 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1224,26 +1224,46 @@
/* This pipe will belong to GSL Group zero. */
set_reg_field_value(value,
- 1,
- DCP_GSL_CONTROL,
- DCP_GSL0_EN);
+ 1,
+ DCP_GSL_CONTROL,
+ DCP_GSL0_EN);
set_reg_field_value(value,
- gsl_params->gsl_master == tg->inst,
- DCP_GSL_CONTROL,
- DCP_GSL_MASTER_EN);
+ gsl_params->gsl_master == tg->inst,
+ DCP_GSL_CONTROL,
+ DCP_GSL_MASTER_EN);
set_reg_field_value(value,
- HFLIP_READY_DELAY,
- DCP_GSL_CONTROL,
- DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
+ HFLIP_READY_DELAY,
+ DCP_GSL_CONTROL,
+ DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
/* Keep signal low (pending high) during 6 lines.
* Also defines minimum interval before re-checking signal. */
set_reg_field_value(value,
- HFLIP_CHECK_DELAY,
- DCP_GSL_CONTROL,
- DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
+ HFLIP_CHECK_DELAY,
+ DCP_GSL_CONTROL,
+ DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value);
+ value = 0;
+
+ set_reg_field_value(value,
+ gsl_params->gsl_master,
+ DCIO_GSL0_CNTL,
+ DCIO_GSL0_VSYNC_SEL);
+
+ set_reg_field_value(value,
+ 0,
+ DCIO_GSL0_CNTL,
+ DCIO_GSL0_TIMING_SYNC_SEL);
+
+ set_reg_field_value(value,
+ 0,
+ DCIO_GSL0_CNTL,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value);
{
@@ -1253,38 +1273,38 @@
CRTC_REG(mmCRTC_V_TOTAL));
set_reg_field_value(value,
- 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */
- DCP_GSL_CONTROL,
- DCP_GSL_SYNC_SOURCE);
+ 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */
+ DCP_GSL_CONTROL,
+ DCP_GSL_SYNC_SOURCE);
/* Checkpoint relative to end of frame */
check_point = get_reg_field_value(value_crtc_vtotal,
- CRTC_V_TOTAL,
- CRTC_V_TOTAL);
+ CRTC_V_TOTAL,
+ CRTC_V_TOTAL);
dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0);
}
set_reg_field_value(value,
- 1,
- DCP_GSL_CONTROL,
- DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
+ 1,
+ DCP_GSL_CONTROL,
+ DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
dm_write_reg(tg->ctx, address, value);
/********************************************************************/
address = CRTC_REG(mmCRTC_GSL_CONTROL);
- value = 0;
+ value = dm_read_reg(tg->ctx, address);
set_reg_field_value(value,
- check_point - FLIP_READY_BACK_LOOKUP,
- CRTC_GSL_CONTROL,
- CRTC_GSL_CHECK_LINE_NUM);
+ check_point - FLIP_READY_BACK_LOOKUP,
+ CRTC_GSL_CONTROL,
+ CRTC_GSL_CHECK_LINE_NUM);
set_reg_field_value(value,
- VFLIP_READY_DELAY,
- CRTC_GSL_CONTROL,
- CRTC_GSL_FORCE_DELAY);
+ VFLIP_READY_DELAY,
+ CRTC_GSL_CONTROL,
+ CRTC_GSL_FORCE_DELAY);
dm_write_reg(tg->ctx, address, value);
}
@@ -1555,6 +1575,138 @@
dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
}
+void dce110_timing_generator_enable_crtc_reset(
+ struct timing_generator *tg,
+ int source_tg_inst,
+ struct crtc_trigger_info *crtc_tp)
+{
+ uint32_t value = 0;
+ uint32_t rising_edge = 0;
+ uint32_t falling_edge = 0;
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
+ /* Setup trigger edge */
+ switch (crtc_tp->event) {
+ case CRTC_EVENT_VSYNC_RISING:
+ rising_edge = 1;
+ break;
+
+ case CRTC_EVENT_VSYNC_FALLING:
+ falling_edge = 1;
+ break;
+ }
+
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
+
+ set_reg_field_value(value,
+ source_tg_inst,
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_SOURCE_SELECT);
+
+ set_reg_field_value(value,
+ TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_POLARITY_SELECT);
+
+ set_reg_field_value(value,
+ rising_edge,
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_RISING_EDGE_DETECT_CNTL);
+
+ set_reg_field_value(value,
+ falling_edge,
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL);
+
+ set_reg_field_value(value,
+ 1, /* clear trigger status */
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_CLEAR);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
+
+ /**************************************************************/
+
+ switch (crtc_tp->delay) {
+ case TRIGGER_DELAY_NEXT_LINE:
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
+
+ set_reg_field_value(value,
+ 0, /* force H count to H_TOTAL and V count to V_TOTAL */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_MODE);
+
+ set_reg_field_value(value,
+ 0, /* TriggerB - we never use TriggerA */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_TRIG_SEL);
+
+ set_reg_field_value(value,
+ 1, /* clear trigger status */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_CLEAR);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
+
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+
+ set_reg_field_value(value,
+ 1,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
+
+ set_reg_field_value(value,
+ 2,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_AUTO_FORCE_VSYNC_MODE);
+
+ break;
+
+ case TRIGGER_DELAY_NEXT_PIXEL:
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+
+ set_reg_field_value(value,
+ 1,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
+
+ set_reg_field_value(value,
+ 0,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_AUTO_FORCE_VSYNC_MODE);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value);
+
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
+
+ set_reg_field_value(value,
+ 2, /* force H count to H_TOTAL and V count to V_TOTAL */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_MODE);
+
+ set_reg_field_value(value,
+ 1, /* TriggerB - we never use TriggerA */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_TRIG_SEL);
+
+ set_reg_field_value(value,
+ 1, /* clear trigger status */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_CLEAR);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
+ break;
+ }
+
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
+
+ set_reg_field_value(value,
+ 2,
+ CRTC_MASTER_UPDATE_MODE,
+ MASTER_UPDATE_MODE);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
+}
void dce110_timing_generator_disable_reset_trigger(
struct timing_generator *tg)
{
@@ -1564,34 +1716,48 @@
value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
set_reg_field_value(value,
- 0, /* force counter now mode is disabled */
- CRTC_FORCE_COUNT_NOW_CNTL,
- CRTC_FORCE_COUNT_NOW_MODE);
+ 0, /* force counter now mode is disabled */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_MODE);
set_reg_field_value(value,
- 1, /* clear trigger status */
- CRTC_FORCE_COUNT_NOW_CNTL,
- CRTC_FORCE_COUNT_NOW_CLEAR);
+ 1, /* clear trigger status */
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_CLEAR);
dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
+ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+
+ set_reg_field_value(value,
+ 1,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
+
+ set_reg_field_value(value,
+ 0,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_AUTO_FORCE_VSYNC_MODE);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value);
+
/********************************************************************/
value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
set_reg_field_value(value,
- TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
- CRTC_TRIGB_CNTL,
- CRTC_TRIGB_SOURCE_SELECT);
+ TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_SOURCE_SELECT);
set_reg_field_value(value,
- TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
- CRTC_TRIGB_CNTL,
- CRTC_TRIGB_POLARITY_SELECT);
+ TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_POLARITY_SELECT);
set_reg_field_value(value,
- 1, /* clear trigger status */
- CRTC_TRIGB_CNTL,
- CRTC_TRIGB_CLEAR);
+ 1, /* clear trigger status */
+ CRTC_TRIGB_CNTL,
+ CRTC_TRIGB_CLEAR);
dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
}
@@ -1611,10 +1777,16 @@
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t value = dm_read_reg(tg->ctx,
CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
+ uint32_t value1 = dm_read_reg(tg->ctx,
+ CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+ bool force = get_reg_field_value(value,
+ CRTC_FORCE_COUNT_NOW_CNTL,
+ CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
+ bool vert_sync = get_reg_field_value(value1,
+ CRTC_VERT_SYNC_CONTROL,
+ CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED) != 0;
- return get_reg_field_value(value,
- CRTC_FORCE_COUNT_NOW_CNTL,
- CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
+ return (force || vert_sync);
}
/**
@@ -1928,6 +2100,7 @@
.setup_global_swap_lock =
dce110_timing_generator_setup_global_swap_lock,
.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
+ .enable_crtc_reset = dce110_timing_generator_enable_crtc_reset,
.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
.tear_down_global_swap_lock =
dce110_timing_generator_tear_down_global_swap_lock,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index 82737dea..232747c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -174,6 +174,12 @@
void dce110_timing_generator_tear_down_global_swap_lock(
struct timing_generator *tg);
+/* Reset crtc position on master VSync */
+void dce110_timing_generator_enable_crtc_reset(
+ struct timing_generator *tg,
+ int source,
+ struct crtc_trigger_info *crtc_tp);
+
/* Reset slave controllers on master VSync */
void dce110_timing_generator_enable_reset_trigger(
struct timing_generator *tg,
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 663e0a0..98d9cd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1103,6 +1103,8 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+
/*************************************************
* Create resources *
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
index 1a0b54d..75d02974 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
@@ -31,9 +31,9 @@
#include "dce110/dce110_hw_sequencer.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
#include "reg_helper.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 5c48c22..5aab01d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -54,10 +54,10 @@
#include "dce/dce_abm.h"
#include "dce/dce_dmcu.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
-#include "vega10/NBIO/nbio_6_1_offset.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
+#include "nbio/nbio_6_1_offset.h"
#include "reg_helper.h"
#include "dce100/dce100_resource.h"
@@ -835,6 +835,8 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+
dc->debug = debug_defaults;
/*************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 2502182..0aa60e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -25,9 +25,9 @@
#include "dm_services.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
#include "dc_types.h"
#include "dc_bios_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 9c18efd..25d7eb1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -793,6 +793,7 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
/*************************************************
* Create resources *
@@ -957,6 +958,7 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.max_cursor_size = 128;
+ dc->caps.is_apu = true;
/*************************************************
* Create resources *
@@ -1121,6 +1123,7 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.max_cursor_size = 128;
+ dc->caps.is_apu = true;
/*************************************************
* Create resources *
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index f565a60..5469bdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -23,9 +23,10 @@
# Makefile for DCN.
DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
- dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
+ dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
dcn10_hubp.o dcn10_mpc.o \
- dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o
+ dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
+ dcn10_hubbub.o
AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 7f579cb..53ba360 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -22,11 +22,12 @@
* Authors: AMD
*
*/
-
+#include "dc.h"
#include "reg_helper.h"
#include "dcn10_dpp.h"
#include "dcn10_cm_common.h"
+#include "custom_float.h"
#define REG(reg) reg
@@ -121,3 +122,294 @@
}
}
+
+
+
+bool cm_helper_convert_to_custom_float(
+ struct pwl_result_data *rgb_resulted,
+ struct curve_points *arr_points,
+ uint32_t hw_points_num,
+ bool fixpoint)
+{
+ struct custom_float_format fmt;
+
+ struct pwl_result_data *rgb = rgb_resulted;
+
+ uint32_t i = 0;
+
+ fmt.exponenta_bits = 6;
+ fmt.mantissa_bits = 12;
+ fmt.sign = false;
+
+ if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
+ &arr_points[0].custom_float_x)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
+ &arr_points[0].custom_float_offset)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
+ &arr_points[0].custom_float_slope)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ fmt.mantissa_bits = 10;
+ fmt.sign = false;
+
+ if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
+ &arr_points[1].custom_float_x)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (fixpoint == true)
+ arr_points[1].custom_float_y = dal_fixed31_32_clamp_u0d14(arr_points[1].y);
+ else if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
+ &arr_points[1].custom_float_y)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
+ &arr_points[1].custom_float_slope)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (hw_points_num == 0 || rgb_resulted == NULL || fixpoint == true)
+ return true;
+
+ fmt.mantissa_bits = 12;
+ fmt.sign = true;
+
+ while (i != hw_points_num) {
+ if (!convert_to_custom_float_format(rgb->red, &fmt,
+ &rgb->red_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(rgb->green, &fmt,
+ &rgb->green_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(rgb->blue, &fmt,
+ &rgb->blue_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
+ &rgb->delta_red_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
+ &rgb->delta_green_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
+ &rgb->delta_blue_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ ++rgb;
+ ++i;
+ }
+
+ return true;
+}
+
+
+#define MAX_REGIONS_NUMBER 34
+#define MAX_LOW_POINT 25
+#define NUMBER_SEGMENTS 32
+
+bool cm_helper_translate_curve_to_hw_format(
+ const struct dc_transfer_func *output_tf,
+ struct pwl_params *lut_params, bool fixpoint)
+{
+ struct curve_points *arr_points;
+ struct pwl_result_data *rgb_resulted;
+ struct pwl_result_data *rgb;
+ struct pwl_result_data *rgb_plus_1;
+ struct fixed31_32 y_r;
+ struct fixed31_32 y_g;
+ struct fixed31_32 y_b;
+ struct fixed31_32 y1_min;
+ struct fixed31_32 y3_max;
+
+ int32_t segment_start, segment_end;
+ int32_t i;
+ uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
+
+ if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS)
+ return false;
+
+ PERF_TRACE();
+
+ arr_points = lut_params->arr_points;
+ rgb_resulted = lut_params->rgb_resulted;
+ hw_points = 0;
+
+ memset(lut_params, 0, sizeof(struct pwl_params));
+ memset(seg_distr, 0, sizeof(seg_distr));
+
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ /* 32 segments
+ * segments are from 2^-25 to 2^7
+ */
+ for (i = 0; i < 32 ; i++)
+ seg_distr[i] = 3;
+
+ segment_start = -25;
+ segment_end = 7;
+ } else {
+ /* 10 segments
+ * segment is from 2^-10 to 2^0
+ * There are less than 256 points, for optimization
+ */
+ seg_distr[0] = 3;
+ seg_distr[1] = 4;
+ seg_distr[2] = 4;
+ seg_distr[3] = 4;
+ seg_distr[4] = 4;
+ seg_distr[5] = 4;
+ seg_distr[6] = 4;
+ seg_distr[7] = 4;
+ seg_distr[8] = 5;
+ seg_distr[9] = 5;
+
+ segment_start = -10;
+ segment_end = 0;
+ }
+
+ for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
+ seg_distr[i] = -1;
+
+ for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
+ if (seg_distr[k] != -1)
+ hw_points += (1 << seg_distr[k]);
+ }
+
+ j = 0;
+ for (k = 0; k < (segment_end - segment_start); k++) {
+ increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
+ start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
+ for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
+ if (j == hw_points - 1)
+ break;
+ rgb_resulted[j].red = output_tf->tf_pts.red[i];
+ rgb_resulted[j].green = output_tf->tf_pts.green[i];
+ rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
+ j++;
+ }
+ }
+
+ /* last point */
+ start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
+ rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
+ rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+
+ arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_start));
+ arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_end));
+
+ y_r = rgb_resulted[0].red;
+ y_g = rgb_resulted[0].green;
+ y_b = rgb_resulted[0].blue;
+
+ y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
+
+ arr_points[0].y = y1_min;
+ arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x);
+ y_r = rgb_resulted[hw_points - 1].red;
+ y_g = rgb_resulted[hw_points - 1].green;
+ y_b = rgb_resulted[hw_points - 1].blue;
+
+ /* see comment above, m_arrPoints[1].y should be the Y value for the
+ * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
+ */
+ y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
+
+ arr_points[1].y = y3_max;
+
+ arr_points[1].slope = dal_fixed31_32_zero;
+
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ /* for PQ, we want to have a straight line from last HW X point,
+ * and the slope to be such that we hit 1.0 at 10000 nits.
+ */
+ const struct fixed31_32 end_value =
+ dal_fixed31_32_from_int(125);
+
+ arr_points[1].slope = dal_fixed31_32_div(
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
+ }
+
+ lut_params->hw_points_num = hw_points;
+
+ i = 1;
+ for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
+ if (seg_distr[k] != -1) {
+ lut_params->arr_curve_points[k].segments_num =
+ seg_distr[k];
+ lut_params->arr_curve_points[i].offset =
+ lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
+ }
+ i++;
+ }
+
+ if (seg_distr[k] != -1)
+ lut_params->arr_curve_points[k].segments_num = seg_distr[k];
+
+ rgb = rgb_resulted;
+ rgb_plus_1 = rgb_resulted + 1;
+
+ i = 1;
+ while (i != hw_points + 1) {
+ if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
+ rgb_plus_1->red = rgb->red;
+ if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
+ rgb_plus_1->green = rgb->green;
+ if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
+ rgb_plus_1->blue = rgb->blue;
+
+ rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
+ rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
+ rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
+
+ if (fixpoint == true) {
+ rgb->delta_red_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_red);
+ rgb->delta_green_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_green);
+ rgb->delta_blue_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_blue);
+ rgb->red_reg = dal_fixed31_32_clamp_u0d14(rgb->red);
+ rgb->green_reg = dal_fixed31_32_clamp_u0d14(rgb->green);
+ rgb->blue_reg = dal_fixed31_32_clamp_u0d14(rgb->blue);
+ }
+
+ ++rgb_plus_1;
+ ++rgb;
+ ++i;
+ }
+ cm_helper_convert_to_custom_float(rgb_resulted,
+ lut_params->arr_points,
+ hw_points, fixpoint);
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h
index 64836dc..64e476b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h
@@ -96,4 +96,14 @@
const struct pwl_params *params,
const struct xfer_func_reg *reg);
+bool cm_helper_convert_to_custom_float(
+ struct pwl_result_data *rgb_resulted,
+ struct curve_points *arr_points,
+ uint32_t hw_points_num,
+ bool fixpoint);
+
+bool cm_helper_translate_curve_to_hw_format(
+ const struct dc_transfer_func *output_tf,
+ struct pwl_params *lut_params, bool fixpoint);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index a9d55d0..f2a08b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -177,37 +177,17 @@
dpp->filter_h = NULL;
dpp->filter_v = NULL;
- /* set boundary mode to 0 */
- REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
+ memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
+ memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
}
static void dpp1_cm_set_regamma_pwl(
- struct dpp *dpp_base, const struct pwl_params *params)
-{
- struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-
- dpp1_cm_power_on_regamma_lut(dpp_base, true);
- dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
-
- if (dpp->is_write_to_ram_a_safe)
- dpp1_cm_program_regamma_luta_settings(dpp_base, params);
- else
- dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
-
- dpp1_cm_program_regamma_lut(
- dpp_base, params->rgb_resulted, params->hw_points_num);
-}
-
-static void dpp1_cm_set_regamma_mode(
- struct dpp *dpp_base,
- enum opp_regamma mode)
+ struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint32_t re_mode = 0;
- uint32_t obuf_bypass = 0; /* need for pipe split */
- uint32_t obuf_hupscale = 0;
switch (mode) {
case OPP_REGAMMA_BYPASS:
@@ -220,17 +200,29 @@
re_mode = 2;
break;
case OPP_REGAMMA_USER:
+ re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
+ if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
+ break;
+
+ dpp1_cm_power_on_regamma_lut(dpp_base, true);
+ dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
+
+ if (dpp->is_write_to_ram_a_safe)
+ dpp1_cm_program_regamma_luta_settings(dpp_base, params);
+ else
+ dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
+
+ dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
+ params->hw_points_num);
+ dpp->pwl_data = *params;
+
re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
break;
default:
break;
}
-
REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
- REG_UPDATE_2(OBUF_CONTROL,
- OBUF_BYPASS, obuf_bypass,
- OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
}
static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
@@ -263,8 +255,10 @@
void dpp1_cnv_setup (
struct dpp *dpp_base,
- enum surface_pixel_format input_format,
- enum expansion_mode mode)
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct csc_transform input_csc_color_matrix,
+ enum dc_color_space input_color_space)
{
uint32_t pixel_format;
uint32_t alpha_en;
@@ -274,8 +268,10 @@
bool is_float;
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
bool force_disable_cursor = false;
+ struct out_csc_color_matrix tbl_entry;
+ int i = 0;
- dpp1_setup_format_flags(input_format, &fmt);
+ dpp1_setup_format_flags(format, &fmt);
alpha_en = 1;
pixel_format = 0;
color_space = COLOR_SPACE_SRGB;
@@ -305,7 +301,7 @@
dpp1_set_degamma_format_float(dpp_base, is_float);
- switch (input_format) {
+ switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
pixel_format = 1;
break;
@@ -361,7 +357,23 @@
CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
- dpp1_program_input_csc(dpp_base, color_space, select);
+ // if input adjustments exist, program icsc with those values
+
+ if (input_csc_color_matrix.enable_adjustment
+ == true) {
+ for (i = 0; i < 12; i++)
+ tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
+
+ tbl_entry.color_space = input_color_space;
+
+ if (color_space >= COLOR_SPACE_YCBCR601)
+ select = INPUT_CSC_SELECT_ICSC;
+ else
+ select = INPUT_CSC_SELECT_BYPASS;
+
+ dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
+ } else
+ dpp1_program_input_csc(dpp_base, color_space, select, NULL);
if (force_disable_cursor) {
REG_UPDATE(CURSOR_CONTROL,
@@ -373,10 +385,9 @@
void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
- const struct dc_cursor_attributes *attr)
+ enum dc_cursor_color_format color_format)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
- enum dc_cursor_color_format color_format = attr->color_format;
REG_UPDATE_2(CURSOR0_CONTROL,
CUR0_MODE, color_format,
@@ -389,13 +400,6 @@
REG_UPDATE(CURSOR0_COLOR1,
CUR0_COLOR1, 0xFFFFFFFF);
}
-
- /* TODO: Fixed vs float */
-
- REG_UPDATE_3(FORMAT_CONTROL,
- CNVC_BYPASS, 0,
- FORMAT_CONTROL__ALPHA_EN, 1,
- FORMAT_EXPANSION_MODE, 0);
}
@@ -425,20 +429,20 @@
.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
- .opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
- .opp_set_csc_default = dpp1_cm_set_output_csc_default,
- .opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
- .opp_program_regamma_lut = dpp1_cm_program_regamma_lut,
- .opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
- .opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
- .opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
- .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
- .opp_set_regamma_mode = dpp1_cm_set_regamma_mode,
- .ipp_set_degamma = dpp1_set_degamma,
- .ipp_program_input_lut = dpp1_program_input_lut,
- .ipp_program_degamma_pwl = dpp1_set_degamma_pwl,
- .ipp_setup = dpp1_cnv_setup,
- .ipp_full_bypass = dpp1_full_bypass,
+ .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
+ .dpp_set_csc_default = dpp1_cm_set_output_csc_default,
+ .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
+ .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
+ .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
+ .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
+ .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
+ .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
+ .dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
+ .dpp_set_degamma = dpp1_set_degamma,
+ .dpp_program_input_lut = dpp1_program_input_lut,
+ .dpp_program_degamma_pwl = dpp1_set_degamma_pwl,
+ .dpp_setup = dpp1_cnv_setup,
+ .dpp_full_bypass = dpp1_full_bypass,
.set_cursor_attributes = dpp1_set_cursor_attributes,
.set_cursor_position = dpp1_set_cursor_position,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 34daf895..f56ee4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -54,7 +54,6 @@
SRI(LB_MEMORY_CTRL, DSCL, id), \
SRI(DSCL_AUTOCAL, DSCL, id), \
SRI(SCL_BLACK_OFFSET, DSCL, id), \
- SRI(DSCL_CONTROL, DSCL, id), \
SRI(SCL_TAP_CONTROL, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
@@ -72,7 +71,6 @@
SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
SRI(RECOUT_START, DSCL, id), \
SRI(RECOUT_SIZE, DSCL, id), \
- SRI(OBUF_CONTROL, DSCL, id), \
SRI(CM_ICSC_CONTROL, CM, id), \
SRI(CM_ICSC_C11_C12, CM, id), \
SRI(CM_ICSC_C33_C34, CM, id), \
@@ -127,6 +125,9 @@
SRI(CM_OCSC_CONTROL, CM, id), \
SRI(CM_OCSC_C11_C12, CM, id), \
SRI(CM_OCSC_C33_C34, CM, id), \
+ SRI(CM_BNS_VALUES_R, CM, id), \
+ SRI(CM_BNS_VALUES_G, CM, id), \
+ SRI(CM_BNS_VALUES_B, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_RGAM_LUT_DATA, CM, id), \
SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
@@ -191,7 +192,6 @@
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
- TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
@@ -235,7 +235,6 @@
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
- TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
@@ -329,6 +328,12 @@
TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
+ TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
+ TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
+ TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
+ TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
+ TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
+ TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
@@ -387,7 +392,6 @@
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
- TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
@@ -431,7 +435,6 @@
type AUTOCAL_PIPE_ID; \
type SCL_BLACK_OFFSET_RGB_Y; \
type SCL_BLACK_OFFSET_CBCR; \
- type SCL_BOUNDARY_MODE; \
type SCL_V_NUM_TAPS; \
type SCL_H_NUM_TAPS; \
type SCL_V_NUM_TAPS_C; \
@@ -552,8 +555,6 @@
type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
type CM_RGAM_LUT_MODE; \
type CM_CMOUT_ROUND_TRUNC_MODE; \
- type OBUF_BYPASS; \
- type OBUF_H_2X_UPSCALE_EN; \
type CM_BLNDGAM_LUT_MODE; \
type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
@@ -729,8 +730,9 @@
type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
type CM_BLNDGAM_LUT_WRITE_SEL; \
+ type CM_BLNDGAM_CONFIG_STATUS; \
type CM_BLNDGAM_LUT_INDEX; \
- type CM_BLNDGAM_LUT_DATA; \
+ type BLNDGAM_MEM_PWR_FORCE; \
type CM_3DLUT_MODE; \
type CM_3DLUT_SIZE; \
type CM_3DLUT_INDEX; \
@@ -904,6 +906,7 @@
type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \
type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \
type CM_SHAPER_LUT_WRITE_EN_MASK; \
+ type CM_SHAPER_CONFIG_STATUS; \
type CM_SHAPER_LUT_WRITE_SEL; \
type CM_SHAPER_LUT_INDEX; \
type CM_SHAPER_LUT_DATA; \
@@ -913,6 +916,12 @@
type CM_ICSC_C12; \
type CM_ICSC_C33; \
type CM_ICSC_C34; \
+ type CM_BNS_BIAS_R; \
+ type CM_BNS_BIAS_G; \
+ type CM_BNS_BIAS_B; \
+ type CM_BNS_SCALE_R; \
+ type CM_BNS_SCALE_G; \
+ type CM_BNS_SCALE_B; \
type CM_DGAM_RAMB_EXP_REGION_START_B; \
type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
type CM_DGAM_RAMB_EXP_REGION_START_G; \
@@ -998,257 +1007,255 @@
type CM_BYPASS; \
type FORMAT_CONTROL__ALPHA_EN; \
type CUR0_COLOR0; \
- type CUR0_COLOR1
-
-
+ type CUR0_COLOR1;
struct dcn_dpp_shift {
- TF_REG_FIELD_LIST(uint8_t);
+ TF_REG_FIELD_LIST(uint8_t)
};
struct dcn_dpp_mask {
- TF_REG_FIELD_LIST(uint32_t);
+ TF_REG_FIELD_LIST(uint32_t)
};
-
-
+#define DPP_COMMON_REG_VARIABLE_LIST \
+ uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \
+ uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \
+ uint32_t OTG_H_BLANK; \
+ uint32_t OTG_V_BLANK; \
+ uint32_t SCL_MODE; \
+ uint32_t LB_DATA_FORMAT; \
+ uint32_t LB_MEMORY_CTRL; \
+ uint32_t DSCL_AUTOCAL; \
+ uint32_t SCL_BLACK_OFFSET; \
+ uint32_t SCL_TAP_CONTROL; \
+ uint32_t SCL_COEF_RAM_TAP_SELECT; \
+ uint32_t SCL_COEF_RAM_TAP_DATA; \
+ uint32_t DSCL_2TAP_CONTROL; \
+ uint32_t MPC_SIZE; \
+ uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \
+ uint32_t SCL_VERT_FILTER_SCALE_RATIO; \
+ uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \
+ uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \
+ uint32_t SCL_HORZ_FILTER_INIT; \
+ uint32_t SCL_HORZ_FILTER_INIT_C; \
+ uint32_t SCL_VERT_FILTER_INIT; \
+ uint32_t SCL_VERT_FILTER_INIT_BOT; \
+ uint32_t SCL_VERT_FILTER_INIT_C; \
+ uint32_t SCL_VERT_FILTER_INIT_BOT_C; \
+ uint32_t RECOUT_START; \
+ uint32_t RECOUT_SIZE; \
+ uint32_t CM_GAMUT_REMAP_CONTROL; \
+ uint32_t CM_GAMUT_REMAP_C11_C12; \
+ uint32_t CM_GAMUT_REMAP_C33_C34; \
+ uint32_t CM_COMA_C11_C12; \
+ uint32_t CM_COMA_C33_C34; \
+ uint32_t CM_COMB_C11_C12; \
+ uint32_t CM_COMB_C33_C34; \
+ uint32_t CM_OCSC_CONTROL; \
+ uint32_t CM_OCSC_C11_C12; \
+ uint32_t CM_OCSC_C33_C34; \
+ uint32_t CM_MEM_PWR_CTRL; \
+ uint32_t CM_RGAM_LUT_DATA; \
+ uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \
+ uint32_t CM_RGAM_LUT_INDEX; \
+ uint32_t CM_RGAM_RAMB_START_CNTL_B; \
+ uint32_t CM_RGAM_RAMB_START_CNTL_G; \
+ uint32_t CM_RGAM_RAMB_START_CNTL_R; \
+ uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \
+ uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \
+ uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \
+ uint32_t CM_RGAM_RAMB_END_CNTL1_B; \
+ uint32_t CM_RGAM_RAMB_END_CNTL2_B; \
+ uint32_t CM_RGAM_RAMB_END_CNTL1_G; \
+ uint32_t CM_RGAM_RAMB_END_CNTL2_G; \
+ uint32_t CM_RGAM_RAMB_END_CNTL1_R; \
+ uint32_t CM_RGAM_RAMB_END_CNTL2_R; \
+ uint32_t CM_RGAM_RAMB_REGION_0_1; \
+ uint32_t CM_RGAM_RAMB_REGION_32_33; \
+ uint32_t CM_RGAM_RAMA_START_CNTL_B; \
+ uint32_t CM_RGAM_RAMA_START_CNTL_G; \
+ uint32_t CM_RGAM_RAMA_START_CNTL_R; \
+ uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \
+ uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \
+ uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \
+ uint32_t CM_RGAM_RAMA_END_CNTL1_B; \
+ uint32_t CM_RGAM_RAMA_END_CNTL2_B; \
+ uint32_t CM_RGAM_RAMA_END_CNTL1_G; \
+ uint32_t CM_RGAM_RAMA_END_CNTL2_G; \
+ uint32_t CM_RGAM_RAMA_END_CNTL1_R; \
+ uint32_t CM_RGAM_RAMA_END_CNTL2_R; \
+ uint32_t CM_RGAM_RAMA_REGION_0_1; \
+ uint32_t CM_RGAM_RAMA_REGION_32_33; \
+ uint32_t CM_RGAM_CONTROL; \
+ uint32_t CM_CMOUT_CONTROL; \
+ uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
+ uint32_t CM_BLNDGAM_CONTROL; \
+ uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \
+ uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \
+ uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \
+ uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \
+ uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \
+ uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \
+ uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \
+ uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \
+ uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \
+ uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \
+ uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \
+ uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \
+ uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \
+ uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \
+ uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \
+ uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \
+ uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \
+ uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \
+ uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \
+ uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \
+ uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \
+ uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \
+ uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \
+ uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \
+ uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \
+ uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \
+ uint32_t CM_BLNDGAM_LUT_INDEX; \
+ uint32_t CM_3DLUT_MODE; \
+ uint32_t CM_3DLUT_INDEX; \
+ uint32_t CM_3DLUT_DATA; \
+ uint32_t CM_3DLUT_DATA_30BIT; \
+ uint32_t CM_3DLUT_READ_WRITE_CONTROL; \
+ uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \
+ uint32_t CM_SHAPER_CONTROL; \
+ uint32_t CM_SHAPER_RAMB_START_CNTL_B; \
+ uint32_t CM_SHAPER_RAMB_START_CNTL_G; \
+ uint32_t CM_SHAPER_RAMB_START_CNTL_R; \
+ uint32_t CM_SHAPER_RAMB_END_CNTL_B; \
+ uint32_t CM_SHAPER_RAMB_END_CNTL_G; \
+ uint32_t CM_SHAPER_RAMB_END_CNTL_R; \
+ uint32_t CM_SHAPER_RAMB_REGION_0_1; \
+ uint32_t CM_SHAPER_RAMB_REGION_2_3; \
+ uint32_t CM_SHAPER_RAMB_REGION_4_5; \
+ uint32_t CM_SHAPER_RAMB_REGION_6_7; \
+ uint32_t CM_SHAPER_RAMB_REGION_8_9; \
+ uint32_t CM_SHAPER_RAMB_REGION_10_11; \
+ uint32_t CM_SHAPER_RAMB_REGION_12_13; \
+ uint32_t CM_SHAPER_RAMB_REGION_14_15; \
+ uint32_t CM_SHAPER_RAMB_REGION_16_17; \
+ uint32_t CM_SHAPER_RAMB_REGION_18_19; \
+ uint32_t CM_SHAPER_RAMB_REGION_20_21; \
+ uint32_t CM_SHAPER_RAMB_REGION_22_23; \
+ uint32_t CM_SHAPER_RAMB_REGION_24_25; \
+ uint32_t CM_SHAPER_RAMB_REGION_26_27; \
+ uint32_t CM_SHAPER_RAMB_REGION_28_29; \
+ uint32_t CM_SHAPER_RAMB_REGION_30_31; \
+ uint32_t CM_SHAPER_RAMB_REGION_32_33; \
+ uint32_t CM_SHAPER_RAMA_START_CNTL_B; \
+ uint32_t CM_SHAPER_RAMA_START_CNTL_G; \
+ uint32_t CM_SHAPER_RAMA_START_CNTL_R; \
+ uint32_t CM_SHAPER_RAMA_END_CNTL_B; \
+ uint32_t CM_SHAPER_RAMA_END_CNTL_G; \
+ uint32_t CM_SHAPER_RAMA_END_CNTL_R; \
+ uint32_t CM_SHAPER_RAMA_REGION_0_1; \
+ uint32_t CM_SHAPER_RAMA_REGION_2_3; \
+ uint32_t CM_SHAPER_RAMA_REGION_4_5; \
+ uint32_t CM_SHAPER_RAMA_REGION_6_7; \
+ uint32_t CM_SHAPER_RAMA_REGION_8_9; \
+ uint32_t CM_SHAPER_RAMA_REGION_10_11; \
+ uint32_t CM_SHAPER_RAMA_REGION_12_13; \
+ uint32_t CM_SHAPER_RAMA_REGION_14_15; \
+ uint32_t CM_SHAPER_RAMA_REGION_16_17; \
+ uint32_t CM_SHAPER_RAMA_REGION_18_19; \
+ uint32_t CM_SHAPER_RAMA_REGION_20_21; \
+ uint32_t CM_SHAPER_RAMA_REGION_22_23; \
+ uint32_t CM_SHAPER_RAMA_REGION_24_25; \
+ uint32_t CM_SHAPER_RAMA_REGION_26_27; \
+ uint32_t CM_SHAPER_RAMA_REGION_28_29; \
+ uint32_t CM_SHAPER_RAMA_REGION_30_31; \
+ uint32_t CM_SHAPER_RAMA_REGION_32_33; \
+ uint32_t CM_SHAPER_LUT_INDEX; \
+ uint32_t CM_SHAPER_LUT_DATA; \
+ uint32_t CM_ICSC_CONTROL; \
+ uint32_t CM_ICSC_C11_C12; \
+ uint32_t CM_ICSC_C33_C34; \
+ uint32_t CM_BNS_VALUES_R; \
+ uint32_t CM_BNS_VALUES_G; \
+ uint32_t CM_BNS_VALUES_B; \
+ uint32_t CM_DGAM_RAMB_START_CNTL_B; \
+ uint32_t CM_DGAM_RAMB_START_CNTL_G; \
+ uint32_t CM_DGAM_RAMB_START_CNTL_R; \
+ uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \
+ uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \
+ uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \
+ uint32_t CM_DGAM_RAMB_END_CNTL1_B; \
+ uint32_t CM_DGAM_RAMB_END_CNTL2_B; \
+ uint32_t CM_DGAM_RAMB_END_CNTL1_G; \
+ uint32_t CM_DGAM_RAMB_END_CNTL2_G; \
+ uint32_t CM_DGAM_RAMB_END_CNTL1_R; \
+ uint32_t CM_DGAM_RAMB_END_CNTL2_R; \
+ uint32_t CM_DGAM_RAMB_REGION_0_1; \
+ uint32_t CM_DGAM_RAMB_REGION_14_15; \
+ uint32_t CM_DGAM_RAMA_START_CNTL_B; \
+ uint32_t CM_DGAM_RAMA_START_CNTL_G; \
+ uint32_t CM_DGAM_RAMA_START_CNTL_R; \
+ uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \
+ uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \
+ uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \
+ uint32_t CM_DGAM_RAMA_END_CNTL1_B; \
+ uint32_t CM_DGAM_RAMA_END_CNTL2_B; \
+ uint32_t CM_DGAM_RAMA_END_CNTL1_G; \
+ uint32_t CM_DGAM_RAMA_END_CNTL2_G; \
+ uint32_t CM_DGAM_RAMA_END_CNTL1_R; \
+ uint32_t CM_DGAM_RAMA_END_CNTL2_R; \
+ uint32_t CM_DGAM_RAMA_REGION_0_1; \
+ uint32_t CM_DGAM_RAMA_REGION_14_15; \
+ uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \
+ uint32_t CM_DGAM_LUT_INDEX; \
+ uint32_t CM_DGAM_LUT_DATA; \
+ uint32_t CM_CONTROL; \
+ uint32_t CM_DGAM_CONTROL; \
+ uint32_t CM_IGAM_CONTROL; \
+ uint32_t CM_IGAM_LUT_RW_CONTROL; \
+ uint32_t CM_IGAM_LUT_RW_INDEX; \
+ uint32_t CM_IGAM_LUT_SEQ_COLOR; \
+ uint32_t FORMAT_CONTROL; \
+ uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
+ uint32_t CURSOR_CONTROL; \
+ uint32_t CURSOR0_CONTROL; \
+ uint32_t CURSOR0_COLOR0; \
+ uint32_t CURSOR0_COLOR1;
struct dcn_dpp_registers {
- uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
- uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
- uint32_t OTG_H_BLANK;
- uint32_t OTG_V_BLANK;
- uint32_t SCL_MODE;
- uint32_t LB_DATA_FORMAT;
- uint32_t LB_MEMORY_CTRL;
- uint32_t DSCL_AUTOCAL;
- uint32_t SCL_BLACK_OFFSET;
- uint32_t DSCL_CONTROL;
- uint32_t SCL_TAP_CONTROL;
- uint32_t SCL_COEF_RAM_TAP_SELECT;
- uint32_t SCL_COEF_RAM_TAP_DATA;
- uint32_t DSCL_2TAP_CONTROL;
- uint32_t MPC_SIZE;
- uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
- uint32_t SCL_VERT_FILTER_SCALE_RATIO;
- uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C;
- uint32_t SCL_VERT_FILTER_SCALE_RATIO_C;
- uint32_t SCL_HORZ_FILTER_INIT;
- uint32_t SCL_HORZ_FILTER_INIT_C;
- uint32_t SCL_VERT_FILTER_INIT;
- uint32_t SCL_VERT_FILTER_INIT_BOT;
- uint32_t SCL_VERT_FILTER_INIT_C;
- uint32_t SCL_VERT_FILTER_INIT_BOT_C;
- uint32_t RECOUT_START;
- uint32_t RECOUT_SIZE;
- uint32_t CM_GAMUT_REMAP_CONTROL;
- uint32_t CM_GAMUT_REMAP_C11_C12;
- uint32_t CM_GAMUT_REMAP_C33_C34;
- uint32_t CM_COMA_C11_C12;
- uint32_t CM_COMA_C33_C34;
- uint32_t CM_COMB_C11_C12;
- uint32_t CM_COMB_C33_C34;
- uint32_t CM_OCSC_CONTROL;
- uint32_t CM_OCSC_C11_C12;
- uint32_t CM_OCSC_C33_C34;
- uint32_t CM_MEM_PWR_CTRL;
- uint32_t CM_RGAM_LUT_DATA;
- uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
- uint32_t CM_RGAM_LUT_INDEX;
- uint32_t CM_RGAM_RAMB_START_CNTL_B;
- uint32_t CM_RGAM_RAMB_START_CNTL_G;
- uint32_t CM_RGAM_RAMB_START_CNTL_R;
- uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
- uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
- uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
- uint32_t CM_RGAM_RAMB_END_CNTL1_B;
- uint32_t CM_RGAM_RAMB_END_CNTL2_B;
- uint32_t CM_RGAM_RAMB_END_CNTL1_G;
- uint32_t CM_RGAM_RAMB_END_CNTL2_G;
- uint32_t CM_RGAM_RAMB_END_CNTL1_R;
- uint32_t CM_RGAM_RAMB_END_CNTL2_R;
- uint32_t CM_RGAM_RAMB_REGION_0_1;
- uint32_t CM_RGAM_RAMB_REGION_32_33;
- uint32_t CM_RGAM_RAMA_START_CNTL_B;
- uint32_t CM_RGAM_RAMA_START_CNTL_G;
- uint32_t CM_RGAM_RAMA_START_CNTL_R;
- uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
- uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
- uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
- uint32_t CM_RGAM_RAMA_END_CNTL1_B;
- uint32_t CM_RGAM_RAMA_END_CNTL2_B;
- uint32_t CM_RGAM_RAMA_END_CNTL1_G;
- uint32_t CM_RGAM_RAMA_END_CNTL2_G;
- uint32_t CM_RGAM_RAMA_END_CNTL1_R;
- uint32_t CM_RGAM_RAMA_END_CNTL2_R;
- uint32_t CM_RGAM_RAMA_REGION_0_1;
- uint32_t CM_RGAM_RAMA_REGION_32_33;
- uint32_t CM_RGAM_CONTROL;
- uint32_t CM_CMOUT_CONTROL;
- uint32_t OBUF_CONTROL;
- uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK;
- uint32_t CM_BLNDGAM_CONTROL;
- uint32_t CM_BLNDGAM_RAMB_START_CNTL_B;
- uint32_t CM_BLNDGAM_RAMB_START_CNTL_G;
- uint32_t CM_BLNDGAM_RAMB_START_CNTL_R;
- uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B;
- uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G;
- uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R;
- uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B;
- uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B;
- uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G;
- uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G;
- uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R;
- uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R;
- uint32_t CM_BLNDGAM_RAMB_REGION_0_1;
- uint32_t CM_BLNDGAM_RAMB_REGION_2_3;
- uint32_t CM_BLNDGAM_RAMB_REGION_4_5;
- uint32_t CM_BLNDGAM_RAMB_REGION_6_7;
- uint32_t CM_BLNDGAM_RAMB_REGION_8_9;
- uint32_t CM_BLNDGAM_RAMB_REGION_10_11;
- uint32_t CM_BLNDGAM_RAMB_REGION_12_13;
- uint32_t CM_BLNDGAM_RAMB_REGION_14_15;
- uint32_t CM_BLNDGAM_RAMB_REGION_16_17;
- uint32_t CM_BLNDGAM_RAMB_REGION_18_19;
- uint32_t CM_BLNDGAM_RAMB_REGION_20_21;
- uint32_t CM_BLNDGAM_RAMB_REGION_22_23;
- uint32_t CM_BLNDGAM_RAMB_REGION_24_25;
- uint32_t CM_BLNDGAM_RAMB_REGION_26_27;
- uint32_t CM_BLNDGAM_RAMB_REGION_28_29;
- uint32_t CM_BLNDGAM_RAMB_REGION_30_31;
- uint32_t CM_BLNDGAM_RAMB_REGION_32_33;
- uint32_t CM_BLNDGAM_RAMA_START_CNTL_B;
- uint32_t CM_BLNDGAM_RAMA_START_CNTL_G;
- uint32_t CM_BLNDGAM_RAMA_START_CNTL_R;
- uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B;
- uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G;
- uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R;
- uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B;
- uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B;
- uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G;
- uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G;
- uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R;
- uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R;
- uint32_t CM_BLNDGAM_RAMA_REGION_0_1;
- uint32_t CM_BLNDGAM_RAMA_REGION_2_3;
- uint32_t CM_BLNDGAM_RAMA_REGION_4_5;
- uint32_t CM_BLNDGAM_RAMA_REGION_6_7;
- uint32_t CM_BLNDGAM_RAMA_REGION_8_9;
- uint32_t CM_BLNDGAM_RAMA_REGION_10_11;
- uint32_t CM_BLNDGAM_RAMA_REGION_12_13;
- uint32_t CM_BLNDGAM_RAMA_REGION_14_15;
- uint32_t CM_BLNDGAM_RAMA_REGION_16_17;
- uint32_t CM_BLNDGAM_RAMA_REGION_18_19;
- uint32_t CM_BLNDGAM_RAMA_REGION_20_21;
- uint32_t CM_BLNDGAM_RAMA_REGION_22_23;
- uint32_t CM_BLNDGAM_RAMA_REGION_24_25;
- uint32_t CM_BLNDGAM_RAMA_REGION_26_27;
- uint32_t CM_BLNDGAM_RAMA_REGION_28_29;
- uint32_t CM_BLNDGAM_RAMA_REGION_30_31;
- uint32_t CM_BLNDGAM_RAMA_REGION_32_33;
- uint32_t CM_BLNDGAM_LUT_INDEX;
- uint32_t CM_BLNDGAM_LUT_DATA;
- uint32_t CM_3DLUT_MODE;
- uint32_t CM_3DLUT_INDEX;
- uint32_t CM_3DLUT_DATA;
- uint32_t CM_3DLUT_DATA_30BIT;
- uint32_t CM_3DLUT_READ_WRITE_CONTROL;
- uint32_t CM_SHAPER_LUT_WRITE_EN_MASK;
- uint32_t CM_SHAPER_CONTROL;
- uint32_t CM_SHAPER_RAMB_START_CNTL_B;
- uint32_t CM_SHAPER_RAMB_START_CNTL_G;
- uint32_t CM_SHAPER_RAMB_START_CNTL_R;
- uint32_t CM_SHAPER_RAMB_END_CNTL_B;
- uint32_t CM_SHAPER_RAMB_END_CNTL_G;
- uint32_t CM_SHAPER_RAMB_END_CNTL_R;
- uint32_t CM_SHAPER_RAMB_REGION_0_1;
- uint32_t CM_SHAPER_RAMB_REGION_2_3;
- uint32_t CM_SHAPER_RAMB_REGION_4_5;
- uint32_t CM_SHAPER_RAMB_REGION_6_7;
- uint32_t CM_SHAPER_RAMB_REGION_8_9;
- uint32_t CM_SHAPER_RAMB_REGION_10_11;
- uint32_t CM_SHAPER_RAMB_REGION_12_13;
- uint32_t CM_SHAPER_RAMB_REGION_14_15;
- uint32_t CM_SHAPER_RAMB_REGION_16_17;
- uint32_t CM_SHAPER_RAMB_REGION_18_19;
- uint32_t CM_SHAPER_RAMB_REGION_20_21;
- uint32_t CM_SHAPER_RAMB_REGION_22_23;
- uint32_t CM_SHAPER_RAMB_REGION_24_25;
- uint32_t CM_SHAPER_RAMB_REGION_26_27;
- uint32_t CM_SHAPER_RAMB_REGION_28_29;
- uint32_t CM_SHAPER_RAMB_REGION_30_31;
- uint32_t CM_SHAPER_RAMB_REGION_32_33;
- uint32_t CM_SHAPER_RAMA_START_CNTL_B;
- uint32_t CM_SHAPER_RAMA_START_CNTL_G;
- uint32_t CM_SHAPER_RAMA_START_CNTL_R;
- uint32_t CM_SHAPER_RAMA_END_CNTL_B;
- uint32_t CM_SHAPER_RAMA_END_CNTL_G;
- uint32_t CM_SHAPER_RAMA_END_CNTL_R;
- uint32_t CM_SHAPER_RAMA_REGION_0_1;
- uint32_t CM_SHAPER_RAMA_REGION_2_3;
- uint32_t CM_SHAPER_RAMA_REGION_4_5;
- uint32_t CM_SHAPER_RAMA_REGION_6_7;
- uint32_t CM_SHAPER_RAMA_REGION_8_9;
- uint32_t CM_SHAPER_RAMA_REGION_10_11;
- uint32_t CM_SHAPER_RAMA_REGION_12_13;
- uint32_t CM_SHAPER_RAMA_REGION_14_15;
- uint32_t CM_SHAPER_RAMA_REGION_16_17;
- uint32_t CM_SHAPER_RAMA_REGION_18_19;
- uint32_t CM_SHAPER_RAMA_REGION_20_21;
- uint32_t CM_SHAPER_RAMA_REGION_22_23;
- uint32_t CM_SHAPER_RAMA_REGION_24_25;
- uint32_t CM_SHAPER_RAMA_REGION_26_27;
- uint32_t CM_SHAPER_RAMA_REGION_28_29;
- uint32_t CM_SHAPER_RAMA_REGION_30_31;
- uint32_t CM_SHAPER_RAMA_REGION_32_33;
- uint32_t CM_SHAPER_LUT_INDEX;
- uint32_t CM_SHAPER_LUT_DATA;
- uint32_t CM_ICSC_CONTROL;
- uint32_t CM_ICSC_C11_C12;
- uint32_t CM_ICSC_C33_C34;
- uint32_t CM_DGAM_RAMB_START_CNTL_B;
- uint32_t CM_DGAM_RAMB_START_CNTL_G;
- uint32_t CM_DGAM_RAMB_START_CNTL_R;
- uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B;
- uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G;
- uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R;
- uint32_t CM_DGAM_RAMB_END_CNTL1_B;
- uint32_t CM_DGAM_RAMB_END_CNTL2_B;
- uint32_t CM_DGAM_RAMB_END_CNTL1_G;
- uint32_t CM_DGAM_RAMB_END_CNTL2_G;
- uint32_t CM_DGAM_RAMB_END_CNTL1_R;
- uint32_t CM_DGAM_RAMB_END_CNTL2_R;
- uint32_t CM_DGAM_RAMB_REGION_0_1;
- uint32_t CM_DGAM_RAMB_REGION_14_15;
- uint32_t CM_DGAM_RAMA_START_CNTL_B;
- uint32_t CM_DGAM_RAMA_START_CNTL_G;
- uint32_t CM_DGAM_RAMA_START_CNTL_R;
- uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B;
- uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G;
- uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R;
- uint32_t CM_DGAM_RAMA_END_CNTL1_B;
- uint32_t CM_DGAM_RAMA_END_CNTL2_B;
- uint32_t CM_DGAM_RAMA_END_CNTL1_G;
- uint32_t CM_DGAM_RAMA_END_CNTL2_G;
- uint32_t CM_DGAM_RAMA_END_CNTL1_R;
- uint32_t CM_DGAM_RAMA_END_CNTL2_R;
- uint32_t CM_DGAM_RAMA_REGION_0_1;
- uint32_t CM_DGAM_RAMA_REGION_14_15;
- uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
- uint32_t CM_DGAM_LUT_INDEX;
- uint32_t CM_DGAM_LUT_DATA;
- uint32_t CM_CONTROL;
- uint32_t CM_DGAM_CONTROL;
- uint32_t CM_IGAM_CONTROL;
- uint32_t CM_IGAM_LUT_RW_CONTROL;
- uint32_t CM_IGAM_LUT_RW_INDEX;
- uint32_t CM_IGAM_LUT_SEQ_COLOR;
- uint32_t FORMAT_CONTROL;
- uint32_t CNVC_SURFACE_PIXEL_FORMAT;
- uint32_t CURSOR_CONTROL;
- uint32_t CURSOR0_CONTROL;
- uint32_t CURSOR0_COLOR0;
- uint32_t CURSOR0_COLOR1;
+ DPP_COMMON_REG_VARIABLE_LIST
};
struct dcn10_dpp {
@@ -1266,6 +1273,8 @@
int lb_memory_size;
int lb_bits_per_entry;
bool is_write_to_ram_a_safe;
+ struct scaler_data scl_data;
+ struct pwl_params pwl_data;
};
enum dcn10_input_csc_select {
@@ -1274,6 +1283,10 @@
INPUT_CSC_SELECT_COMA
};
+void dpp1_set_cursor_attributes(
+ struct dpp *dpp_base,
+ enum dc_cursor_color_format color_format);
+
bool dpp1_dscl_is_lb_conf_valid(
int ceil_vratio,
int num_partitions,
@@ -1310,7 +1323,12 @@
void dpp1_program_input_csc(
struct dpp *dpp_base,
enum dc_color_space color_space,
- enum dcn10_input_csc_select select);
+ enum dcn10_input_csc_select select,
+ const struct out_csc_color_matrix *tbl_entry);
+
+void dpp1_program_bias_and_scale(
+ struct dpp *dpp_base,
+ struct dc_bias_and_scale *params);
void dpp1_program_input_lut(
struct dpp *dpp_base,
@@ -1356,7 +1374,7 @@
const struct pwl_params *params);
void dpp1_cm_set_output_csc_adjustment(
struct dpp *dpp_base,
- const struct out_csc_color_matrix *tbl_entry);
+ const uint16_t *regval);
void dpp1_cm_set_output_csc_default(
struct dpp *dpp_base,
@@ -1372,8 +1390,10 @@
void dpp1_cnv_setup (
struct dpp *dpp_base,
- enum surface_pixel_format input_format,
- enum expansion_mode mode);
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct csc_transform input_csc_color_matrix,
+ enum dc_color_space input_color_space);
void dpp1_full_bypass(struct dpp *dpp_base);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index ed1216b..a5b0990 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -49,6 +49,8 @@
#define FN(reg_name, field_name) \
dpp->tf_shift->field_name, dpp->tf_mask->field_name
+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
struct dcn10_input_csc_matrix {
enum dc_color_space color_space;
uint16_t regval[12];
@@ -117,8 +119,6 @@
0x2568, 0x43ee, 0xdbb2} }
};
-
-
static void program_gamut_remap(
struct dcn10_dpp *dpp,
const uint16_t *regval,
@@ -223,39 +223,63 @@
}
}
+static void dpp1_cm_program_color_matrix(
+ struct dcn10_dpp *dpp,
+ const uint16_t *regval)
+{
+ uint32_t mode;
+ struct color_matrices_reg gam_regs;
+
+ REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
+
+ if (regval == NULL) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+ mode = 4;
+ gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
+ gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
+ gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
+ gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
+
+ if (mode == 4) {
+
+ gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
+ gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
+
+ cm_helper_program_color_matrices(
+ dpp->base.ctx,
+ regval,
+ &gam_regs);
+
+ } else {
+
+ gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
+ gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
+
+ cm_helper_program_color_matrices(
+ dpp->base.ctx,
+ regval,
+ &gam_regs);
+ }
+}
+
void dpp1_cm_set_output_csc_default(
struct dpp *dpp_base,
enum dc_color_space colorspace)
{
-
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
- uint32_t ocsc_mode = 0;
+ const uint16_t *regval = NULL;
+ int arr_size;
+ uint32_t ocsc_mode = 4;
- switch (colorspace) {
- case COLOR_SPACE_SRGB:
- case COLOR_SPACE_2020_RGB_FULLRANGE:
- ocsc_mode = 0;
- break;
- case COLOR_SPACE_SRGB_LIMITED:
- case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
- ocsc_mode = 1;
- break;
- case COLOR_SPACE_YCBCR601:
- case COLOR_SPACE_YCBCR601_LIMITED:
- ocsc_mode = 2;
- break;
- case COLOR_SPACE_YCBCR709:
- case COLOR_SPACE_YCBCR709_LIMITED:
- case COLOR_SPACE_2020_YCBCR:
- ocsc_mode = 3;
- break;
- case COLOR_SPACE_UNKNOWN:
- default:
- break;
+ regval = find_color_matrix(colorspace, &arr_size);
+ if (regval == NULL) {
+ BREAK_TO_DEBUGGER();
+ return;
}
-
+ dpp1_cm_program_color_matrix(dpp, regval);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
-
}
static void dpp1_cm_get_reg_field(
@@ -285,114 +309,41 @@
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
}
-static void dpp1_cm_program_color_matrix(
- struct dcn10_dpp *dpp,
- const struct out_csc_color_matrix *tbl_entry)
-{
- uint32_t mode;
- struct color_matrices_reg gam_regs;
-
- REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
-
- if (tbl_entry == NULL) {
- BREAK_TO_DEBUGGER();
- return;
- }
-
- gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
- gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
- gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
- gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
-
- if (mode == 4) {
-
- gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
- gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
-
- cm_helper_program_color_matrices(
- dpp->base.ctx,
- tbl_entry->regval,
- &gam_regs);
-
- } else {
-
- gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
- gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
-
- cm_helper_program_color_matrices(
- dpp->base.ctx,
- tbl_entry->regval,
- &gam_regs);
- }
-}
-
void dpp1_cm_set_output_csc_adjustment(
struct dpp *dpp_base,
- const struct out_csc_color_matrix *tbl_entry)
+ const uint16_t *regval)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
- //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
uint32_t ocsc_mode = 4;
-
- /**
- *if (tbl_entry != NULL) {
- * switch (tbl_entry->color_space) {
- * case COLOR_SPACE_SRGB:
- * case COLOR_SPACE_2020_RGB_FULLRANGE:
- * ocsc_mode = 0;
- * break;
- * case COLOR_SPACE_SRGB_LIMITED:
- * case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
- * ocsc_mode = 1;
- * break;
- * case COLOR_SPACE_YCBCR601:
- * case COLOR_SPACE_YCBCR601_LIMITED:
- * ocsc_mode = 2;
- * break;
- * case COLOR_SPACE_YCBCR709:
- * case COLOR_SPACE_YCBCR709_LIMITED:
- * case COLOR_SPACE_2020_YCBCR:
- * ocsc_mode = 3;
- * break;
- * case COLOR_SPACE_UNKNOWN:
- * default:
- * break;
- * }
- *}
- */
-
+ dpp1_cm_program_color_matrix(dpp, regval);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
- dpp1_cm_program_color_matrix(dpp, tbl_entry);
}
-void dpp1_cm_power_on_regamma_lut(
- struct dpp *dpp_base,
- bool power_on)
+void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
+ bool power_on)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
REG_SET(CM_MEM_PWR_CTRL, 0,
- RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+ RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
}
-void dpp1_cm_program_regamma_lut(
- struct dpp *dpp_base,
- const struct pwl_result_data *rgb,
- uint32_t num)
+void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
+ const struct pwl_result_data *rgb,
+ uint32_t num)
{
uint32_t i;
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
for (i = 0 ; i < num; i++) {
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
- REG_SET(CM_RGAM_LUT_DATA, 0,
- CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
- REG_SET(CM_RGAM_LUT_DATA, 0,
- CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
- REG_SET(CM_RGAM_LUT_DATA, 0,
- CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
}
@@ -471,7 +422,8 @@
void dpp1_program_input_csc(
struct dpp *dpp_base,
enum dc_color_space color_space,
- enum dcn10_input_csc_select select)
+ enum dcn10_input_csc_select select,
+ const struct out_csc_color_matrix *tbl_entry)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
int i;
@@ -485,15 +437,19 @@
return;
}
- for (i = 0; i < arr_size; i++)
- if (dcn10_input_csc_matrix[i].color_space == color_space) {
- regval = dcn10_input_csc_matrix[i].regval;
- break;
- }
+ if (tbl_entry == NULL) {
+ for (i = 0; i < arr_size; i++)
+ if (dcn10_input_csc_matrix[i].color_space == color_space) {
+ regval = dcn10_input_csc_matrix[i].regval;
+ break;
+ }
- if (regval == NULL) {
- BREAK_TO_DEBUGGER();
- return;
+ if (regval == NULL) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+ } else {
+ regval = tbl_entry->regval;
}
if (select == INPUT_CSC_SELECT_COMA)
@@ -528,6 +484,27 @@
}
}
+//keep here for now, decide multi dce support later
+void dpp1_program_bias_and_scale(
+ struct dpp *dpp_base,
+ struct dc_bias_and_scale *params)
+{
+ struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
+ REG_SET_2(CM_BNS_VALUES_R, 0,
+ CM_BNS_SCALE_R, params->scale_red,
+ CM_BNS_BIAS_R, params->bias_red);
+
+ REG_SET_2(CM_BNS_VALUES_G, 0,
+ CM_BNS_SCALE_G, params->scale_green,
+ CM_BNS_BIAS_G, params->bias_green);
+
+ REG_SET_2(CM_BNS_VALUES_B, 0,
+ CM_BNS_SCALE_B, params->scale_blue,
+ CM_BNS_BIAS_B, params->bias_blue);
+
+}
+
/*program de gamma RAM B*/
void dpp1_program_degamma_lutb_settings(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index cbad3641..3eb824d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -648,6 +648,13 @@
bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
+ if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
+ return;
+
+ PERF_TRACE();
+
+ dpp->scl_data = *scl_data;
+
/* Recout */
dpp1_dscl_set_recout(dpp, &scl_data->recout);
@@ -699,4 +706,5 @@
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
+ PERF_TRACE();
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
new file mode 100644
index 0000000..eb83171
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -0,0 +1,516 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dcn10_hubp.h"
+#include "dcn10_hubbub.h"
+#include "reg_helper.h"
+
+#define CTX \
+ hubbub->ctx
+#define REG(reg)\
+ hubbub->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+ hubbub->shifts->field_name, hubbub->masks->field_name
+
+void hubbub1_wm_read_state(struct hubbub *hubbub,
+ struct dcn_hubbub_wm *wm)
+{
+ struct dcn_hubbub_wm_set *s;
+
+ memset(wm, 0, sizeof(struct dcn_hubbub_wm));
+
+ s = &wm->sets[0];
+ s->wm_set = 0;
+ s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
+ s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
+ s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
+ s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+ }
+ s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
+
+ s = &wm->sets[1];
+ s->wm_set = 1;
+ s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
+ s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
+ s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
+ s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
+ }
+ s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
+
+ s = &wm->sets[2];
+ s->wm_set = 2;
+ s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
+ s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
+ s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
+ s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
+ }
+ s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
+
+ s = &wm->sets[3];
+ s->wm_set = 3;
+ s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
+ s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
+ s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
+ s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
+ }
+ s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
+}
+
+bool hubbub1_verify_allow_pstate_change_high(
+ struct hubbub *hubbub)
+{
+ /* pstate latency is ~20us so if we wait over 40us and pstate allow
+ * still not asserted, we are probably stuck and going to hang
+ *
+ * TODO: Figure out why it takes ~100us on linux
+ * pstate takes around ~100us on linux. Unknown currently as to
+ * why it takes that long on linux
+ */
+ static unsigned int pstate_wait_timeout_us = 200;
+ static unsigned int pstate_wait_expected_timeout_us = 40;
+ static unsigned int max_sampled_pstate_wait_us; /* data collection */
+ static bool forced_pstate_allow; /* help with revert wa */
+
+ unsigned int debug_index = 0x7;
+ unsigned int debug_data;
+ unsigned int i;
+
+ if (forced_pstate_allow) {
+ /* we hacked to force pstate allow to prevent hang last time
+ * we verify_allow_pstate_change_high. so disable force
+ * here so we can check status
+ */
+ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+ DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
+ DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
+ forced_pstate_allow = false;
+ }
+
+ /* description "3-0: Pipe0 cursor0 QOS
+ * 7-4: Pipe1 cursor0 QOS
+ * 11-8: Pipe2 cursor0 QOS
+ * 15-12: Pipe3 cursor0 QOS
+ * 16: Pipe0 Plane0 Allow Pstate Change
+ * 17: Pipe1 Plane0 Allow Pstate Change
+ * 18: Pipe2 Plane0 Allow Pstate Change
+ * 19: Pipe3 Plane0 Allow Pstate Change
+ * 20: Pipe0 Plane1 Allow Pstate Change
+ * 21: Pipe1 Plane1 Allow Pstate Change
+ * 22: Pipe2 Plane1 Allow Pstate Change
+ * 23: Pipe3 Plane1 Allow Pstate Change
+ * 24: Pipe0 cursor0 Allow Pstate Change
+ * 25: Pipe1 cursor0 Allow Pstate Change
+ * 26: Pipe2 cursor0 Allow Pstate Change
+ * 27: Pipe3 cursor0 Allow Pstate Change
+ * 28: WB0 Allow Pstate Change
+ * 29: WB1 Allow Pstate Change
+ * 30: Arbiter's allow_pstate_change
+ * 31: SOC pstate change request
+ */
+
+ REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
+
+ for (i = 0; i < pstate_wait_timeout_us; i++) {
+ debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
+
+ if (debug_data & (1 << 30)) {
+
+ if (i > pstate_wait_expected_timeout_us)
+ dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
+ "pstate took longer than expected ~%dus\n",
+ i);
+
+ return true;
+ }
+ if (max_sampled_pstate_wait_us < i)
+ max_sampled_pstate_wait_us = i;
+
+ udelay(1);
+ }
+
+ /* force pstate allow to prevent system hang
+ * and break to debugger to investigate
+ */
+ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+ DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
+ DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
+ forced_pstate_allow = true;
+
+ dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
+ "pstate TEST_DEBUG_DATA: 0x%X\n",
+ debug_data);
+
+ return false;
+}
+
+static uint32_t convert_and_clamp(
+ uint32_t wm_ns,
+ uint32_t refclk_mhz,
+ uint32_t clamp_value)
+{
+ uint32_t ret_val = 0;
+ ret_val = wm_ns * refclk_mhz;
+ ret_val /= 1000;
+
+ if (ret_val > clamp_value)
+ ret_val = clamp_value;
+
+ return ret_val;
+}
+
+
+void hubbub1_program_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz)
+{
+ uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;
+ /*
+ * Need to clamp to max of the register values (i.e. no wrap)
+ * for dcn1, all wm registers are 21-bit wide
+ */
+ uint32_t prog_wm_value;
+
+ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
+
+ /* Repeat for water mark set A, B, C and D. */
+ /* clock state A */
+ prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "URGENCY_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.urgent_ns, prog_wm_value);
+
+ prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.pte_meta_urgent_ns, prog_wm_value);
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
+ prog_wm_value = convert_and_clamp(
+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->a.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_EXIT_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+ }
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->a.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n\n",
+ watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+
+ /* clock state B */
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "URGENCY_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.pte_meta_urgent_ns, prog_wm_value);
+
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_ENTER_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_EXIT_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+ }
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+ /* clock state C */
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "URGENCY_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.pte_meta_urgent_ns, prog_wm_value);
+
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_ENTER_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_EXIT_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+ }
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+ /* clock state D */
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "URGENCY_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.urgent_ns, prog_wm_value);
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.pte_meta_urgent_ns, prog_wm_value);
+
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_ENTER_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "SR_EXIT_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+ }
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
+ dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n\n",
+ watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
+
+ REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
+ DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+ REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
+
+ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
+ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
+
+#if 0
+ REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
+#endif
+}
+
+void hubbub1_update_dchub(
+ struct hubbub *hubbub,
+ struct dchub_init_data *dh_data)
+{
+ /* TODO: port code from dal2 */
+ switch (dh_data->fb_mode) {
+ case FRAME_BUFFER_MODE_ZFB_ONLY:
+ /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+ REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
+ SDPIF_FB_TOP, 0);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
+ SDPIF_FB_BASE, 0x0FFFF);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+ SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+ SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+ SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1) >> 22);
+ break;
+ case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+ SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+ SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+ SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1) >> 22);
+ break;
+ case FRAME_BUFFER_MODE_LOCAL_ONLY:
+ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+ SDPIF_AGP_BASE, 0);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+ SDPIF_AGP_BOT, 0X03FFFF);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+ SDPIF_AGP_TOP, 0);
+ break;
+ default:
+ break;
+ }
+
+ dh_data->dchub_initialzied = true;
+ dh_data->dchub_info_valid = false;
+}
+
+void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
+{
+ uint32_t watermark_change_req;
+
+ REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
+
+ if (watermark_change_req)
+ watermark_change_req = 0;
+ else
+ watermark_change_req = 1;
+
+ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
+}
+
+static const struct hubbub_funcs hubbub1_funcs = {
+ .update_dchub = hubbub1_update_dchub
+};
+
+void hubbub1_construct(struct hubbub *hubbub,
+ struct dc_context *ctx,
+ const struct dcn_hubbub_registers *hubbub_regs,
+ const struct dcn_hubbub_shift *hubbub_shift,
+ const struct dcn_hubbub_mask *hubbub_mask)
+{
+ hubbub->ctx = ctx;
+
+ hubbub->funcs = &hubbub1_funcs;
+
+ hubbub->regs = hubbub_regs;
+ hubbub->shifts = hubbub_shift;
+ hubbub->masks = hubbub_mask;
+
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
new file mode 100644
index 0000000..d5c9784
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBBUB_DCN10_H__
+#define __DC_HUBBUB_DCN10_H__
+
+#include "core_types.h"
+
+#define HUBHUB_REG_LIST_DCN()\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+ SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
+ SR(DCHUBBUB_ARB_SAT_LEVEL),\
+ SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
+ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+ SR(DCHUBBUB_TEST_DEBUG_INDEX), \
+ SR(DCHUBBUB_TEST_DEBUG_DATA)
+
+#define HUBBUB_SR_WATERMARK_REG_LIST()\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
+
+#define HUBBUB_REG_LIST_DCN10(id)\
+ HUBHUB_REG_LIST_DCN(), \
+ HUBBUB_SR_WATERMARK_REG_LIST(), \
+ SR(DCHUBBUB_SDPIF_FB_TOP),\
+ SR(DCHUBBUB_SDPIF_FB_BASE),\
+ SR(DCHUBBUB_SDPIF_FB_OFFSET),\
+ SR(DCHUBBUB_SDPIF_AGP_BASE),\
+ SR(DCHUBBUB_SDPIF_AGP_BOT),\
+ SR(DCHUBBUB_SDPIF_AGP_TOP)
+
+struct dcn_hubbub_registers {
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
+ uint32_t DCHUBBUB_ARB_SAT_LEVEL;
+ uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
+ uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
+ uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
+ uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
+ uint32_t DCHUBBUB_TEST_DEBUG_DATA;
+ uint32_t DCHUBBUB_SDPIF_FB_TOP;
+ uint32_t DCHUBBUB_SDPIF_FB_BASE;
+ uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
+ uint32_t DCHUBBUB_SDPIF_AGP_BASE;
+ uint32_t DCHUBBUB_SDPIF_AGP_BOT;
+ uint32_t DCHUBBUB_SDPIF_AGP_TOP;
+ uint32_t DCHUBBUB_CRC_CTRL;
+};
+
+/* set field name */
+#define HUBBUB_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\
+ HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh)
+
+#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\
+ HUBBUB_MASK_SH_LIST_DCN(mask_sh), \
+ HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
+ HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh)
+
+#define DCN_HUBBUB_REG_FIELD_LIST(type) \
+ type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
+ type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
+ type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
+ type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
+ type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
+ type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
+ type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
+ type DCHUBBUB_ARB_SAT_LEVEL;\
+ type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
+ type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
+ type SDPIF_FB_TOP;\
+ type SDPIF_FB_BASE;\
+ type SDPIF_FB_OFFSET;\
+ type SDPIF_AGP_BASE;\
+ type SDPIF_AGP_BOT;\
+ type SDPIF_AGP_TOP
+
+
+struct dcn_hubbub_shift {
+ DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn_hubbub_mask {
+ DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
+};
+
+struct dc;
+
+struct dcn_hubbub_wm_set {
+ uint32_t wm_set;
+ uint32_t data_urgent;
+ uint32_t pte_meta_urgent;
+ uint32_t sr_enter;
+ uint32_t sr_exit;
+ uint32_t dram_clk_chanage;
+};
+
+struct dcn_hubbub_wm {
+ struct dcn_hubbub_wm_set sets[4];
+};
+
+struct hubbub_funcs {
+ void (*update_dchub)(
+ struct hubbub *hubbub,
+ struct dchub_init_data *dh_data);
+};
+
+struct hubbub {
+ const struct hubbub_funcs *funcs;
+ struct dc_context *ctx;
+ const struct dcn_hubbub_registers *regs;
+ const struct dcn_hubbub_shift *shifts;
+ const struct dcn_hubbub_mask *masks;
+};
+
+void hubbub1_update_dchub(
+ struct hubbub *hubbub,
+ struct dchub_init_data *dh_data);
+
+bool hubbub1_verify_allow_pstate_change_high(
+ struct hubbub *hubbub);
+
+void hubbub1_program_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz);
+
+void hubbub1_toggle_watermark_change_req(
+ struct hubbub *hubbub);
+
+void hubbub1_wm_read_state(struct hubbub *hubbub,
+ struct dcn_hubbub_wm *wm);
+
+void hubbub1_construct(struct hubbub *hubbub,
+ struct dc_context *ctx,
+ const struct dcn_hubbub_registers *hubbub_regs,
+ const struct dcn_hubbub_shift *hubbub_shift,
+ const struct dcn_hubbub_mask *hubbub_mask);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index b13dee6..585b333 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -29,14 +29,14 @@
#include "dcn10_hubp.h"
#define REG(reg)\
- hubp1->mi_regs->reg
+ hubp1->hubp_regs->reg
#define CTX \
hubp1->base.ctx
#undef FN
#define FN(reg_name, field_name) \
- hubp1->mi_shift->field_name, hubp1->mi_mask->field_name
+ hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
void hubp1_set_blank(struct hubp *hubp, bool blank)
{
@@ -48,14 +48,33 @@
HUBP_TTU_DISABLE, blank_en);
if (blank) {
- REG_WAIT(DCHUBP_CNTL,
- HUBP_NO_OUTSTANDING_REQ, 1,
- 1, 200);
+ uint32_t reg_val = REG_READ(DCHUBP_CNTL);
+
+ if (reg_val) {
+ /* init sequence workaround: in case HUBP is
+ * power gated, this wait would timeout.
+ *
+ * we just wrote reg_val to non-0, if it stay 0
+ * it means HUBP is gated
+ */
+ REG_WAIT(DCHUBP_CNTL,
+ HUBP_NO_OUTSTANDING_REQ, 1,
+ 1, 200);
+ }
+
hubp->mpcc_id = 0xf;
hubp->opp_id = 0xf;
}
}
+static void hubp1_disconnect(struct hubp *hubp)
+{
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+ REG_UPDATE(DCHUBP_CNTL,
+ HUBP_TTU_DISABLE, 1);
+}
+
static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@@ -88,10 +107,12 @@
}
void hubp1_program_tiling(
- struct dcn10_hubp *hubp1,
+ struct hubp *hubp,
const union dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
REG_UPDATE_6(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
NUM_BANKS, log_2(info->gfx9.num_banks),
@@ -108,13 +129,14 @@
}
void hubp1_program_size_and_rotation(
- struct dcn10_hubp *hubp1,
+ struct hubp *hubp,
enum dc_rotation_angle rotation,
enum surface_pixel_format format,
const union plane_size *plane_size,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)
{
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror;
/* Program data and meta surface pitch (calculation from addrlib)
@@ -170,9 +192,10 @@
}
void hubp1_program_pixel_format(
- struct dcn10_hubp *hubp1,
+ struct hubp *hubp,
enum surface_pixel_format format)
{
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t red_bar = 3;
uint32_t blue_bar = 2;
@@ -416,13 +439,11 @@
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)
{
- struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-
hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
- hubp1_program_tiling(hubp1, tiling_info, format);
+ hubp1_program_tiling(hubp, tiling_info, format);
hubp1_program_size_and_rotation(
- hubp1, rotation, format, plane_size, dcc, horizontal_mirror);
- hubp1_program_pixel_format(hubp1, format);
+ hubp, rotation, format, plane_size, dcc, horizontal_mirror);
+ hubp1_program_pixel_format(hubp, format);
}
void hubp1_program_requestor(
@@ -757,42 +778,7 @@
QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
}
-enum cursor_pitch {
- CURSOR_PITCH_64_PIXELS = 0,
- CURSOR_PITCH_128_PIXELS,
- CURSOR_PITCH_256_PIXELS
-};
-
-enum cursor_lines_per_chunk {
- CURSOR_LINE_PER_CHUNK_2 = 1,
- CURSOR_LINE_PER_CHUNK_4,
- CURSOR_LINE_PER_CHUNK_8,
- CURSOR_LINE_PER_CHUNK_16
-};
-
-static bool ippn10_cursor_program_control(
- struct dcn10_hubp *hubp1,
- bool pixel_data_invert,
- enum dc_cursor_color_format color_format)
-{
- if (REG(CURSOR_SETTINS))
- REG_SET_2(CURSOR_SETTINS, 0,
- /* no shift of the cursor HDL schedule */
- CURSOR0_DST_Y_OFFSET, 0,
- /* used to shift the cursor chunk request deadline */
- CURSOR0_CHUNK_HDL_ADJUST, 3);
- else
- REG_SET_2(CURSOR_SETTINGS, 0,
- /* no shift of the cursor HDL schedule */
- CURSOR0_DST_Y_OFFSET, 0,
- /* used to shift the cursor chunk request deadline */
- CURSOR0_CHUNK_HDL_ADJUST, 3);
-
- return true;
-}
-
-static enum cursor_pitch ippn10_get_cursor_pitch(
- unsigned int pitch)
+enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
{
enum cursor_pitch hw_pitch;
@@ -815,7 +801,7 @@
return hw_pitch;
}
-static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk(
+static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
unsigned int cur_width,
enum dc_cursor_color_format format)
{
@@ -841,8 +827,8 @@
const struct dc_cursor_attributes *attr)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
- enum cursor_pitch hw_pitch = ippn10_get_cursor_pitch(attr->pitch);
- enum cursor_lines_per_chunk lpc = ippn10_get_lines_per_chunk(
+ enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
+ enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
attr->width, attr->color_format);
hubp->curs_attr = *attr;
@@ -855,13 +841,17 @@
REG_UPDATE_2(CURSOR_SIZE,
CURSOR_WIDTH, attr->width,
CURSOR_HEIGHT, attr->height);
+
REG_UPDATE_3(CURSOR_CONTROL,
CURSOR_MODE, attr->color_format,
CURSOR_PITCH, hw_pitch,
CURSOR_LINES_PER_CHUNK, lpc);
- ippn10_cursor_program_control(hubp1,
- attr->attribute_flags.bits.INVERT_PIXEL_DATA,
- attr->color_format);
+
+ REG_SET_2(CURSOR_SETTINS, 0,
+ /* no shift of the cursor HDL schedule */
+ CURSOR0_DST_Y_OFFSET, 0,
+ /* used to shift the cursor chunk request deadline */
+ CURSOR0_CHUNK_HDL_ADJUST, 3);
}
void hubp1_cursor_set_position(
@@ -901,7 +891,8 @@
cur_en = 0; /* not visible beyond left edge*/
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
- hubp1_cursor_set_attributes(hubp, &hubp->curs_attr);
+ hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
+
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, cur_en);
@@ -933,6 +924,7 @@
.set_hubp_blank_en = hubp1_set_hubp_blank_en,
.set_cursor_attributes = hubp1_cursor_set_attributes,
.set_cursor_position = hubp1_cursor_set_position,
+ .hubp_disconnect = hubp1_disconnect,
};
/*****************************************/
@@ -943,15 +935,15 @@
struct dcn10_hubp *hubp1,
struct dc_context *ctx,
uint32_t inst,
- const struct dcn_mi_registers *mi_regs,
- const struct dcn_mi_shift *mi_shift,
- const struct dcn_mi_mask *mi_mask)
+ const struct dcn_mi_registers *hubp_regs,
+ const struct dcn_mi_shift *hubp_shift,
+ const struct dcn_mi_mask *hubp_mask)
{
hubp1->base.funcs = &dcn10_hubp_funcs;
hubp1->base.ctx = ctx;
- hubp1->mi_regs = mi_regs;
- hubp1->mi_shift = mi_shift;
- hubp1->mi_mask = mi_mask;
+ hubp1->hubp_regs = hubp_regs;
+ hubp1->hubp_shift = hubp_shift;
+ hubp1->hubp_mask = hubp_mask;
hubp1->base.inst = inst;
hubp1->base.opp_id = 0xf;
hubp1->base.mpcc_id = 0xf;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 66db453..33e91d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -30,7 +30,7 @@
#define TO_DCN10_HUBP(hubp)\
container_of(hubp, struct dcn10_hubp, base)
-#define MI_REG_LIST_DCN(id)\
+#define HUBP_REG_LIST_DCN(id)\
SRI(DCHUBP_CNTL, HUBP, id),\
SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
@@ -98,8 +98,8 @@
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
-#define MI_REG_LIST_DCN10(id)\
- MI_REG_LIST_DCN(id),\
+#define HUBP_REG_LIST_DCN10(id)\
+ HUBP_REG_LIST_DCN(id),\
SRI(PREFETCH_SETTINS, HUBPREQ, id),\
SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -127,277 +127,274 @@
SRI(CURSOR_HOT_SPOT, CURSOR, id), \
SRI(CURSOR_DST_OFFSET, CURSOR, id)
+#define HUBP_COMMON_REG_VARIABLE_LIST \
+ uint32_t DCHUBP_CNTL; \
+ uint32_t HUBPREQ_DEBUG_DB; \
+ uint32_t DCSURF_ADDR_CONFIG; \
+ uint32_t DCSURF_TILING_CONFIG; \
+ uint32_t DCSURF_SURFACE_PITCH; \
+ uint32_t DCSURF_SURFACE_PITCH_C; \
+ uint32_t DCSURF_SURFACE_CONFIG; \
+ uint32_t DCSURF_FLIP_CONTROL; \
+ uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \
+ uint32_t DCSURF_PRI_VIEWPORT_START; \
+ uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \
+ uint32_t DCSURF_SEC_VIEWPORT_START; \
+ uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
+ uint32_t DCSURF_PRI_VIEWPORT_START_C; \
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
+ uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
+ uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \
+ uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \
+ uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
+ uint32_t DCSURF_SURFACE_INUSE; \
+ uint32_t DCSURF_SURFACE_INUSE_HIGH; \
+ uint32_t DCSURF_SURFACE_INUSE_C; \
+ uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \
+ uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \
+ uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \
+ uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
+ uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
+ uint32_t DCSURF_SURFACE_CONTROL; \
+ uint32_t HUBPRET_CONTROL; \
+ uint32_t DCN_EXPANSION_MODE; \
+ uint32_t DCHUBP_REQ_SIZE_CONFIG; \
+ uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \
+ uint32_t BLANK_OFFSET_0; \
+ uint32_t BLANK_OFFSET_1; \
+ uint32_t DST_DIMENSIONS; \
+ uint32_t DST_AFTER_SCALER; \
+ uint32_t PREFETCH_SETTINS; \
+ uint32_t PREFETCH_SETTINGS; \
+ uint32_t VBLANK_PARAMETERS_0; \
+ uint32_t REF_FREQ_TO_PIX_FREQ; \
+ uint32_t VBLANK_PARAMETERS_1; \
+ uint32_t VBLANK_PARAMETERS_3; \
+ uint32_t NOM_PARAMETERS_0; \
+ uint32_t NOM_PARAMETERS_1; \
+ uint32_t NOM_PARAMETERS_4; \
+ uint32_t NOM_PARAMETERS_5; \
+ uint32_t PER_LINE_DELIVERY_PRE; \
+ uint32_t PER_LINE_DELIVERY; \
+ uint32_t PREFETCH_SETTINS_C; \
+ uint32_t PREFETCH_SETTINGS_C; \
+ uint32_t VBLANK_PARAMETERS_2; \
+ uint32_t VBLANK_PARAMETERS_4; \
+ uint32_t NOM_PARAMETERS_2; \
+ uint32_t NOM_PARAMETERS_3; \
+ uint32_t NOM_PARAMETERS_6; \
+ uint32_t NOM_PARAMETERS_7; \
+ uint32_t DCN_TTU_QOS_WM; \
+ uint32_t DCN_GLOBAL_TTU_CNTL; \
+ uint32_t DCN_SURF0_TTU_CNTL0; \
+ uint32_t DCN_SURF0_TTU_CNTL1; \
+ uint32_t DCN_SURF1_TTU_CNTL0; \
+ uint32_t DCN_SURF1_TTU_CNTL1; \
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \
+ uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \
+ uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \
+ uint32_t DCN_VM_MX_L1_TLB_CNTL; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
+ uint32_t DCHUBBUB_SDPIF_FB_BASE; \
+ uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \
+ uint32_t DCN_VM_FB_LOCATION_TOP; \
+ uint32_t DCN_VM_FB_LOCATION_BASE; \
+ uint32_t DCN_VM_FB_OFFSET; \
+ uint32_t DCN_VM_AGP_BASE; \
+ uint32_t DCN_VM_AGP_BOT; \
+ uint32_t DCN_VM_AGP_TOP; \
+ uint32_t CURSOR_SETTINS; \
+ uint32_t CURSOR_SETTINGS; \
+ uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
+ uint32_t CURSOR_SURFACE_ADDRESS; \
+ uint32_t CURSOR_SIZE; \
+ uint32_t CURSOR_CONTROL; \
+ uint32_t CURSOR_POSITION; \
+ uint32_t CURSOR_HOT_SPOT; \
+ uint32_t CURSOR_DST_OFFSET
-
-struct dcn_mi_registers {
- uint32_t DCHUBP_CNTL;
- uint32_t HUBPREQ_DEBUG_DB;
- uint32_t DCSURF_ADDR_CONFIG;
- uint32_t DCSURF_TILING_CONFIG;
- uint32_t DCSURF_SURFACE_PITCH;
- uint32_t DCSURF_SURFACE_PITCH_C;
- uint32_t DCSURF_SURFACE_CONFIG;
- uint32_t DCSURF_FLIP_CONTROL;
- uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
- uint32_t DCSURF_PRI_VIEWPORT_START;
- uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
- uint32_t DCSURF_SEC_VIEWPORT_START;
- uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
- uint32_t DCSURF_PRI_VIEWPORT_START_C;
- uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
- uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
- uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
- uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
- uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
- uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
- uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
- uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
- uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
- uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
- uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
- uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
- uint32_t DCSURF_SURFACE_INUSE;
- uint32_t DCSURF_SURFACE_INUSE_HIGH;
- uint32_t DCSURF_SURFACE_INUSE_C;
- uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
- uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
- uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
- uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
- uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
- uint32_t DCSURF_SURFACE_CONTROL;
- uint32_t HUBPRET_CONTROL;
- uint32_t DCN_EXPANSION_MODE;
- uint32_t DCHUBP_REQ_SIZE_CONFIG;
- uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
- uint32_t BLANK_OFFSET_0;
- uint32_t BLANK_OFFSET_1;
- uint32_t DST_DIMENSIONS;
- uint32_t DST_AFTER_SCALER;
- uint32_t PREFETCH_SETTINS;
- uint32_t PREFETCH_SETTINGS;
- uint32_t VBLANK_PARAMETERS_0;
- uint32_t REF_FREQ_TO_PIX_FREQ;
- uint32_t VBLANK_PARAMETERS_1;
- uint32_t VBLANK_PARAMETERS_3;
- uint32_t NOM_PARAMETERS_0;
- uint32_t NOM_PARAMETERS_1;
- uint32_t NOM_PARAMETERS_4;
- uint32_t NOM_PARAMETERS_5;
- uint32_t PER_LINE_DELIVERY_PRE;
- uint32_t PER_LINE_DELIVERY;
- uint32_t PREFETCH_SETTINS_C;
- uint32_t PREFETCH_SETTINGS_C;
- uint32_t VBLANK_PARAMETERS_2;
- uint32_t VBLANK_PARAMETERS_4;
- uint32_t NOM_PARAMETERS_2;
- uint32_t NOM_PARAMETERS_3;
- uint32_t NOM_PARAMETERS_6;
- uint32_t NOM_PARAMETERS_7;
- uint32_t DCN_TTU_QOS_WM;
- uint32_t DCN_GLOBAL_TTU_CNTL;
- uint32_t DCN_SURF0_TTU_CNTL0;
- uint32_t DCN_SURF0_TTU_CNTL1;
- uint32_t DCN_SURF1_TTU_CNTL0;
- uint32_t DCN_SURF1_TTU_CNTL1;
- uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
- uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
- uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
- uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
- uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
- uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
- uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
- uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
- uint32_t DCN_VM_MX_L1_TLB_CNTL;
- uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
- uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
- uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
- uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
- uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
- uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
- uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR;
- uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR;
- uint32_t DCHUBBUB_SDPIF_FB_BASE;
- uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
- uint32_t DCN_VM_FB_LOCATION_TOP;
- uint32_t DCN_VM_FB_LOCATION_BASE;
- uint32_t DCN_VM_FB_OFFSET;
- uint32_t DCN_VM_AGP_BASE;
- uint32_t DCN_VM_AGP_BOT;
- uint32_t DCN_VM_AGP_TOP;
- uint32_t CURSOR_SETTINS;
- uint32_t CURSOR_SETTINGS;
- uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
- uint32_t CURSOR_SURFACE_ADDRESS;
- uint32_t CURSOR_SIZE;
- uint32_t CURSOR_CONTROL;
- uint32_t CURSOR_POSITION;
- uint32_t CURSOR_HOT_SPOT;
- uint32_t CURSOR_DST_OFFSET;
-};
-
-#define MI_SF(reg_name, field_name, post_fix)\
+#define HUBP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
-#define MI_MASK_SH_LIST_DCN(mask_sh)\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
- MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
- MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
- MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
- MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
- MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
- MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
- MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
- MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
- MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
- MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
- MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
- MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
- MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
- MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
- MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
- MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
- MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
- MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
- MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
- MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
- MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
- MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
- MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
- MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
- MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
- MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
- MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
- MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
- MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
- MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
- MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
- MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
- MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
- MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
- MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
- MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
- MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
- MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
- MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
- MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
- MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
- MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
- MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
- MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
- MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
- MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
+#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
+ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
+ HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
+ HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
+ HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
+ HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
+ HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
+ HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
+ HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
+ HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
+ HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
+ HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
+ HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
-#define MI_MASK_SH_LIST_DCN10(mask_sh)\
- MI_MASK_SH_LIST_DCN(mask_sh),\
- MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
- MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
- MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
- MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
- MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
- MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
- MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
- MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
- MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
- MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
- MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
- MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
- MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
- MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
- MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
- MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
- MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
- MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
- MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
- MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
- MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
- MI_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
+#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
+ HUBP_MASK_SH_LIST_DCN(mask_sh),\
+ HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
+ HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
+ HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
+ HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
+ HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
+ HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+ HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
-#define DCN_MI_REG_FIELD_LIST(type) \
+#define DCN_HUBP_REG_FIELD_LIST(type) \
type HUBP_BLANK_EN;\
type HUBP_TTU_DISABLE;\
type HUBP_NO_OUTSTANDING_REQ;\
@@ -576,19 +573,23 @@
type CURSOR_DST_X_OFFSET; \
type OUTPUT_FP
+struct dcn_mi_registers {
+ HUBP_COMMON_REG_VARIABLE_LIST;
+};
+
struct dcn_mi_shift {
- DCN_MI_REG_FIELD_LIST(uint8_t);
+ DCN_HUBP_REG_FIELD_LIST(uint8_t);
};
struct dcn_mi_mask {
- DCN_MI_REG_FIELD_LIST(uint32_t);
+ DCN_HUBP_REG_FIELD_LIST(uint32_t);
};
struct dcn10_hubp {
struct hubp base;
- const struct dcn_mi_registers *mi_regs;
- const struct dcn_mi_shift *mi_shift;
- const struct dcn_mi_mask *mi_mask;
+ const struct dcn_mi_registers *hubp_regs;
+ const struct dcn_mi_shift *hubp_shift;
+ const struct dcn_mi_mask *hubp_mask;
};
void hubp1_program_surface_config(
@@ -610,11 +611,11 @@
struct _vcs_dpi_display_rq_regs_st *rq_regs);
void hubp1_program_pixel_format(
- struct dcn10_hubp *hubp,
+ struct hubp *hubp,
enum surface_pixel_format format);
void hubp1_program_size_and_rotation(
- struct dcn10_hubp *hubp,
+ struct hubp *hubp,
enum dc_rotation_angle rotation,
enum surface_pixel_format format,
const union plane_size *plane_size,
@@ -622,7 +623,7 @@
bool horizontal_mirror);
void hubp1_program_tiling(
- struct dcn10_hubp *hubp,
+ struct hubp *hubp,
const union dc_tiling_info *info,
const enum surface_pixel_format pixel_format);
@@ -656,9 +657,9 @@
struct dcn10_hubp *hubp1,
struct dc_context *ctx,
uint32_t inst,
- const struct dcn_mi_registers *mi_regs,
- const struct dcn_mi_shift *mi_shift,
- const struct dcn_mi_mask *mi_mask);
+ const struct dcn_mi_registers *hubp_regs,
+ const struct dcn_mi_shift *hubp_shift,
+ const struct dcn_mi_mask *hubp_mask);
struct dcn_hubp_state {
@@ -680,4 +681,6 @@
void hubp1_read_state(struct dcn10_hubp *hubp1,
struct dcn_hubp_state *s);
+enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 05dc01e..bbe8d91 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -31,7 +31,8 @@
#include "dce110/dce110_hw_sequencer.h"
#include "dce/dce_hwseq.h"
#include "abm.h"
-#include "dcn10/dcn10_timing_generator.h"
+#include "dmcu.h"
+#include "dcn10_optc.h"
#include "dcn10/dcn10_dpp.h"
#include "dcn10/dcn10_mpc.h"
#include "timing_generator.h"
@@ -41,6 +42,8 @@
#include "reg_helper.h"
#include "custom_float.h"
#include "dcn10_hubp.h"
+#include "dcn10_hubbub.h"
+#include "dcn10_cm_common.h"
#define CTX \
hws->ctx
@@ -51,6 +54,21 @@
#define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
+#define DTN_INFO_MICRO_SEC(ref_cycle) \
+ print_microsec(dc_ctx, ref_cycle)
+
+void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
+{
+ static const uint32_t ref_clk_mhz = 48;
+ static const unsigned int frac = 10;
+ uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
+
+ DTN_INFO("%d.%d \t ",
+ us_x10 / frac,
+ us_x10 % frac);
+}
+
+
static void log_mpc_crc(struct dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
@@ -64,78 +82,13 @@
REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
}
-void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
-{
- static const uint32_t ref_clk_mhz = 48;
- static const unsigned int frac = 10;
- uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
-
- DTN_INFO("%d.%d \t ",
- us_x10 / frac,
- us_x10 % frac);
-}
-
-#define DTN_INFO_MICRO_SEC(ref_cycle) \
- print_microsec(dc_ctx, ref_cycle)
-
-struct dcn_hubbub_wm_set {
- uint32_t wm_set;
- uint32_t data_urgent;
- uint32_t pte_meta_urgent;
- uint32_t sr_enter;
- uint32_t sr_exit;
- uint32_t dram_clk_chanage;
-};
-
-struct dcn_hubbub_wm {
- struct dcn_hubbub_wm_set sets[4];
-};
-
-static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,
- struct dcn_hubbub_wm *wm)
-{
- struct dcn_hubbub_wm_set *s;
-
- s = &wm->sets[0];
- s->wm_set = 0;
- s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
- s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
- s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
- s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
- s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
-
- s = &wm->sets[1];
- s->wm_set = 1;
- s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
- s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
- s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
- s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
- s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
-
- s = &wm->sets[2];
- s->wm_set = 2;
- s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
- s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
- s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
- s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
- s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
-
- s = &wm->sets[3];
- s->wm_set = 3;
- s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
- s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
- s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
- s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
- s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
-}
-
-static void dcn10_log_hubbub_state(struct dc *dc)
+void dcn10_log_hubbub_state(struct dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
struct dcn_hubbub_wm wm;
int i;
- dcn10_hubbub_wm_read_state(dc->hwseq, &wm);
+ hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
"sr_enter \t sr_exit \t dram_clk_change \n");
@@ -156,7 +109,7 @@
DTN_INFO("\n");
}
-static void dcn10_log_hw_state(struct dc *dc)
+void dcn10_log_hw_state(struct dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
@@ -206,7 +159,7 @@
struct timing_generator *tg = pool->timing_generators[i];
struct dcn_otg_state s = {0};
- tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+ optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
//only print if OTG master is enabled
if ((s.otg_enabled & 1) == 0)
@@ -240,97 +193,6 @@
DTN_INFO_END();
}
-static void verify_allow_pstate_change_high(
- struct dce_hwseq *hws)
-{
- /* pstate latency is ~20us so if we wait over 40us and pstate allow
- * still not asserted, we are probably stuck and going to hang
- *
- * TODO: Figure out why it takes ~100us on linux
- * pstate takes around ~100us on linux. Unknown currently as to
- * why it takes that long on linux
- */
- static unsigned int pstate_wait_timeout_us = 200;
- static unsigned int pstate_wait_expected_timeout_us = 40;
- static unsigned int max_sampled_pstate_wait_us; /* data collection */
- static bool forced_pstate_allow; /* help with revert wa */
- static bool should_log_hw_state; /* prevent hw state log by default */
-
- unsigned int debug_index = 0x7;
- unsigned int debug_data;
- unsigned int i;
-
- if (forced_pstate_allow) {
- /* we hacked to force pstate allow to prevent hang last time
- * we verify_allow_pstate_change_high. so disable force
- * here so we can check status
- */
- REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
- DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
- DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
- forced_pstate_allow = false;
- }
-
- /* description "3-0: Pipe0 cursor0 QOS
- * 7-4: Pipe1 cursor0 QOS
- * 11-8: Pipe2 cursor0 QOS
- * 15-12: Pipe3 cursor0 QOS
- * 16: Pipe0 Plane0 Allow Pstate Change
- * 17: Pipe1 Plane0 Allow Pstate Change
- * 18: Pipe2 Plane0 Allow Pstate Change
- * 19: Pipe3 Plane0 Allow Pstate Change
- * 20: Pipe0 Plane1 Allow Pstate Change
- * 21: Pipe1 Plane1 Allow Pstate Change
- * 22: Pipe2 Plane1 Allow Pstate Change
- * 23: Pipe3 Plane1 Allow Pstate Change
- * 24: Pipe0 cursor0 Allow Pstate Change
- * 25: Pipe1 cursor0 Allow Pstate Change
- * 26: Pipe2 cursor0 Allow Pstate Change
- * 27: Pipe3 cursor0 Allow Pstate Change
- * 28: WB0 Allow Pstate Change
- * 29: WB1 Allow Pstate Change
- * 30: Arbiter's allow_pstate_change
- * 31: SOC pstate change request
- */
-
- REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
-
- for (i = 0; i < pstate_wait_timeout_us; i++) {
- debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
-
- if (debug_data & (1 << 30)) {
-
- if (i > pstate_wait_expected_timeout_us)
- dm_logger_write(hws->ctx->logger, LOG_WARNING,
- "pstate took longer than expected ~%dus\n",
- i);
-
- return;
- }
- if (max_sampled_pstate_wait_us < i)
- max_sampled_pstate_wait_us = i;
-
- udelay(1);
- }
-
- /* force pstate allow to prevent system hang
- * and break to debugger to investigate
- */
- REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
- DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
- DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
- forced_pstate_allow = true;
-
- if (should_log_hw_state) {
- dcn10_log_hw_state(hws->ctx->dc);
- }
-
- dm_logger_write(hws->ctx->logger, LOG_WARNING,
- "pstate TEST_DEBUG_DATA: 0x%X\n",
- debug_data);
- BREAK_TO_DEBUGGER();
-}
-
static void enable_dppclk(
struct dce_hwseq *hws,
uint8_t plane_id,
@@ -376,10 +238,34 @@
static void disable_vga(
struct dce_hwseq *hws)
{
+ unsigned int in_vga1_mode = 0;
+ unsigned int in_vga2_mode = 0;
+ unsigned int in_vga3_mode = 0;
+ unsigned int in_vga4_mode = 0;
+
+ REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
+ REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
+ REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
+ REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
+
+ if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
+ in_vga3_mode == 0 && in_vga4_mode == 0)
+ return;
+
REG_WRITE(D1VGA_CONTROL, 0);
REG_WRITE(D2VGA_CONTROL, 0);
REG_WRITE(D3VGA_CONTROL, 0);
REG_WRITE(D4VGA_CONTROL, 0);
+
+ /* HW Engineer's Notes:
+ * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
+ * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
+ *
+ * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
+ * VGA_TEST_ENABLE, to leave it in the same state as before.
+ */
+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
}
static void dpp_pg_control(
@@ -432,312 +318,6 @@
}
}
-static uint32_t convert_and_clamp(
- uint32_t wm_ns,
- uint32_t refclk_mhz,
- uint32_t clamp_value)
-{
- uint32_t ret_val = 0;
- ret_val = wm_ns * refclk_mhz;
- ret_val /= 1000;
-
- if (ret_val > clamp_value)
- ret_val = clamp_value;
-
- return ret_val;
-}
-
-static void program_watermarks(
- struct dce_hwseq *hws,
- struct dcn_watermark_set *watermarks,
- unsigned int refclk_mhz)
-{
- uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
- /*
- * Need to clamp to max of the register values (i.e. no wrap)
- * for dcn1, all wm registers are 21-bit wide
- */
- uint32_t prog_wm_value;
-
- REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
-
- /* Repeat for water mark set A, B, C and D. */
- /* clock state A */
- prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
-
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "URGENCY_WATERMARK_A calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->a.urgent_ns, prog_wm_value);
-
- prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->a.pte_meta_urgent_ns, prog_wm_value);
-
- if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
- prog_wm_value = convert_and_clamp(
- watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->a.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_EXIT_WATERMARK_A calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
- }
-
- prog_wm_value = convert_and_clamp(
- watermarks->a.cstate_pstate.pstate_change_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
- "HW register value = 0x%x\n\n",
- watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
-
-
- /* clock state B */
- prog_wm_value = convert_and_clamp(
- watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "URGENCY_WATERMARK_B calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->b.urgent_ns, prog_wm_value);
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->b.pte_meta_urgent_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->b.pte_meta_urgent_ns, prog_wm_value);
-
-
- if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
- prog_wm_value = convert_and_clamp(
- watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_ENTER_WATERMARK_B calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->b.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_EXIT_WATERMARK_B calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
- }
-
- prog_wm_value = convert_and_clamp(
- watermarks->b.cstate_pstate.pstate_change_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
- "HW register value = 0x%x\n",
- watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
-
- /* clock state C */
- prog_wm_value = convert_and_clamp(
- watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "URGENCY_WATERMARK_C calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->c.urgent_ns, prog_wm_value);
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->c.pte_meta_urgent_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->c.pte_meta_urgent_ns, prog_wm_value);
-
-
- if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
- prog_wm_value = convert_and_clamp(
- watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_ENTER_WATERMARK_C calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->c.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_EXIT_WATERMARK_C calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
- }
-
- prog_wm_value = convert_and_clamp(
- watermarks->c.cstate_pstate.pstate_change_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
- "HW register value = 0x%x\n",
- watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
-
- /* clock state D */
- prog_wm_value = convert_and_clamp(
- watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "URGENCY_WATERMARK_D calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->d.urgent_ns, prog_wm_value);
-
- prog_wm_value = convert_and_clamp(
- watermarks->d.pte_meta_urgent_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->d.pte_meta_urgent_ns, prog_wm_value);
-
-
- if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
- prog_wm_value = convert_and_clamp(
- watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_ENTER_WATERMARK_D calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->d.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "SR_EXIT_WATERMARK_D calculated =%d\n"
- "HW register value = 0x%x\n",
- watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
- }
-
-
- prog_wm_value = convert_and_clamp(
- watermarks->d.cstate_pstate.pstate_change_ns,
- refclk_mhz, 0x1fffff);
- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
- dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
- "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
- "HW register value = 0x%x\n\n",
- watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
-
- REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
-
- REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
- DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
- REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
- DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
-
- REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
-
-#if 0
- REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
- DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
-#endif
-}
-
-
-static void dcn10_update_dchub(
- struct dce_hwseq *hws,
- struct dchub_init_data *dh_data)
-{
- /* TODO: port code from dal2 */
- switch (dh_data->fb_mode) {
- case FRAME_BUFFER_MODE_ZFB_ONLY:
- /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
- REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
- SDPIF_FB_TOP, 0);
-
- REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
- SDPIF_FB_BASE, 0x0FFFF);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
- dh_data->zfb_size_in_byte - 1) >> 22);
- break;
- case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
- dh_data->zfb_size_in_byte - 1) >> 22);
- break;
- case FRAME_BUFFER_MODE_LOCAL_ONLY:
- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
- SDPIF_AGP_BASE, 0);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
- SDPIF_AGP_BOT, 0X03FFFF);
-
- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
- SDPIF_AGP_TOP, 0);
- break;
- default:
- break;
- }
-
- dh_data->dchub_initialzied = true;
- dh_data->dchub_info_valid = false;
-}
-
static void hubp_pg_control(
struct dce_hwseq *hws,
unsigned int hubp_inst,
@@ -808,11 +388,8 @@
{
struct dce_hwseq *hws = dc->hwseq;
struct hubp *hubp = dc->res_pool->hubps[0];
- int pwr_status = 0;
- REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status);
- /* Don't need to blank if hubp is power gated*/
- if (pwr_status == 2)
+ if (!hws->wa_state.DEGVIDCN10_253_applied)
return;
hubp->funcs->set_blank(hubp, true);
@@ -823,16 +400,29 @@
hubp_pg_control(hws, 0, false);
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 0);
+
+ hws->wa_state.DEGVIDCN10_253_applied = false;
}
static void apply_DEGVIDCN10_253_wa(struct dc *dc)
{
struct dce_hwseq *hws = dc->hwseq;
struct hubp *hubp = dc->res_pool->hubps[0];
+ int i;
if (dc->debug.disable_stutter)
return;
+ if (!hws->wa.DEGVIDCN10_253)
+ return;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ if (!dc->res_pool->hubps[i]->power_gated)
+ return;
+ }
+
+ /* all pipe power gated, apply work around to enable stutter. */
+
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 1);
@@ -841,6 +431,7 @@
IP_REQUEST_EN, 0);
hubp->funcs->set_hubp_blank_en(hubp, false);
+ hws->wa_state.DEGVIDCN10_253_applied = true;
}
static void bios_golden_init(struct dc *dc)
@@ -859,85 +450,32 @@
}
}
-static void dcn10_init_hw(struct dc *dc)
+static void false_optc_underflow_wa(
+ struct dc *dc,
+ const struct dc_stream_state *stream,
+ struct timing_generator *tg)
{
int i;
- struct abm *abm = dc->res_pool->abm;
- struct dce_hwseq *hws = dc->hwseq;
+ bool underflow;
- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
- REG_WRITE(REFCLK_CNTL, 0);
- REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
- REG_WRITE(DIO_MEM_PWR_CTRL, 0);
-
- if (!dc->debug.disable_clock_gate) {
- /* enable all DCN clock gating */
- REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
- REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
-
- REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
- }
-
- enable_power_gating_plane(dc->hwseq, true);
+ if (!dc->hwseq->wa.false_optc_underflow)
return;
- }
- /* end of FPGA. Below if real ASIC */
- bios_golden_init(dc);
-
- disable_vga(dc->hwseq);
-
- for (i = 0; i < dc->link_count; i++) {
- /* Power up AND update implementation according to the
- * required signal (which may be different from the
- * default signal on connector).
- */
- struct dc_link *link = dc->links[i];
-
- link->link_enc->funcs->hw_init(link->link_enc);
- }
+ underflow = tg->funcs->is_optc_underflow_occurred(tg);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct dpp *dpp = dc->res_pool->dpps[i];
- struct timing_generator *tg = dc->res_pool->timing_generators[i];
+ struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
- dpp->funcs->dpp_reset(dpp);
- dc->res_pool->mpc->funcs->remove(
- dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree),
- dc->res_pool->opps[i]->inst, i);
+ if (old_pipe_ctx->stream != stream)
+ continue;
- /* Blank controller using driver code instead of
- * command table.
- */
- tg->funcs->set_blank(tg, true);
- hwss_wait_for_blank_complete(tg);
+ dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
}
- for (i = 0; i < dc->res_pool->audio_count; i++) {
- struct audio *audio = dc->res_pool->audios[i];
+ tg->funcs->set_blank_data_double_buffer(tg, true);
- audio->funcs->hw_init(audio);
- }
-
- if (abm != NULL) {
- abm->funcs->init_backlight(abm);
- abm->funcs->abm_init(abm);
- }
-
- /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
- REG_WRITE(DIO_MEM_PWR_CTRL, 0);
-
- if (!dc->debug.disable_clock_gate) {
- /* enable all DCN clock gating */
- REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
- REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
-
- REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
- }
-
- enable_power_gating_plane(dc->hwseq, true);
+ if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
+ tg->funcs->clear_optc_underflow(tg);
}
static enum dc_status dcn10_prog_pixclk_crtc_otg(
@@ -948,10 +486,6 @@
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_color_space color_space;
struct tg_color black_color = {0};
- bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
- false:true;
- bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
-
/* by upper caller loop, pipe0 is parent pipe and be called first.
* back end is set up by for pipe0. Other children pipe share back end
@@ -986,11 +520,6 @@
&stream->timing,
true);
- pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
- pipe_ctx->stream_res.opp,
- enableStereo,
- rightEyePolarity);
-
#if 0 /* move to after enable_crtc */
/* TODO: OPP FMT, ABM. etc. should be done here. */
/* or FPGA now. instance 0 only. TODO: move to opp.c */
@@ -1005,12 +534,18 @@
/* program otg blank color */
color_space = stream->output_color_space;
color_space_to_black_color(dc, color_space, &black_color);
- pipe_ctx->stream_res.tg->funcs->set_blank_color(
- pipe_ctx->stream_res.tg,
- &black_color);
- pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
- hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
+ if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
+ pipe_ctx->stream_res.tg->funcs->set_blank_color(
+ pipe_ctx->stream_res.tg,
+ &black_color);
+
+ if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
+ !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
+ pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
+ hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
+ false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
+ }
/* VTG is within DCHUB command block. DCFCLK is always on */
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
@@ -1070,83 +605,55 @@
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
}
-/* trigger HW to start disconnect plane from stream on the next vsync */
-static void plane_atomic_disconnect(struct dc *dc,
- int fe_idx)
+static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
{
+ static bool should_log_hw_state; /* prevent hw state log by default */
+
+ if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
+ if (should_log_hw_state) {
+ dcn10_log_hw_state(dc);
+ }
+
+ BREAK_TO_DEBUGGER();
+ }
+}
+
+/* trigger HW to start disconnect plane from stream on the next vsync */
+static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ int fe_idx = pipe_ctx->pipe_idx;
struct hubp *hubp = dc->res_pool->hubps[fe_idx];
struct mpc *mpc = dc->res_pool->mpc;
- int opp_id, z_idx;
- int mpcc_id = -1;
+ int opp_id;
+ struct mpc_tree *mpc_tree_params;
+ struct mpcc *mpcc_to_remove = NULL;
/* look at tree rather than mi here to know if we already reset */
for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
- for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) {
- if (opp->mpc_tree.dpp[z_idx] == fe_idx) {
- mpcc_id = opp->mpc_tree.mpcc[z_idx];
- break;
- }
- }
- if (mpcc_id != -1)
+ mpc_tree_params = &(opp->mpc_tree_params);
+ mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, fe_idx);
+ if (mpcc_to_remove != NULL)
break;
}
+
/*Already reset*/
if (opp_id == dc->res_pool->pipe_count)
return;
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
- hubp->funcs->dcc_control(hubp, false, false);
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
+ mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
+ dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true;
- mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
- dc->res_pool->opps[opp_id]->inst, fe_idx);
+ dc->optimized_required = true;
+
+ if (hubp->funcs->hubp_disconnect)
+ hubp->funcs->hubp_disconnect(hubp);
+
+ if (dc->debug.sanity_checks)
+ dcn10_verify_allow_pstate_change_high(dc);
}
-/* disable HW used by plane.
- * note: cannot disable until disconnect is complete */
-static void plane_atomic_disable(struct dc *dc,
- int fe_idx)
-{
- struct dce_hwseq *hws = dc->hwseq;
- struct hubp *hubp = dc->res_pool->hubps[fe_idx];
- struct mpc *mpc = dc->res_pool->mpc;
- int opp_id = hubp->opp_id;
-
- if (opp_id == 0xf)
- return;
-
- mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
- dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
- /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
- "[debug_mpo: atomic disable finished on mpcc %d]\n",
- fe_idx);*/
-
- hubp->funcs->set_blank(hubp, true);
-
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
-
- REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
- HUBP_CLOCK_ENABLE, 0);
- REG_UPDATE(DPP_CONTROL[fe_idx],
- DPP_CLOCK_ENABLE, 0);
-
- if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
- REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
- OPP_PIPE_CLOCK_EN, 0);
-
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
-}
-
-/*
- * kill power to plane hw
- * note: cannot power down until plane is disable
- */
static void plane_atomic_power_down(struct dc *dc, int fe_idx)
{
struct dce_hwseq *hws = dc->hwseq;
@@ -1162,67 +669,192 @@
IP_REQUEST_EN, 0);
dm_logger_write(dc->ctx->logger, LOG_DEBUG,
"Power gated front end %d\n", fe_idx);
-
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
}
}
-
-static void reset_front_end(
- struct dc *dc,
- int fe_idx)
+/* disable HW used by plane.
+ * note: cannot disable until disconnect is complete
+ */
+static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
+ int fe_idx = pipe_ctx->pipe_idx;
struct dce_hwseq *hws = dc->hwseq;
- struct timing_generator *tg;
- int opp_id = dc->res_pool->hubps[fe_idx]->opp_id;
+ struct hubp *hubp = dc->res_pool->hubps[fe_idx];
+ int opp_id = hubp->opp_id;
- /*Already reset*/
- if (opp_id == 0xf)
- return;
+ dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
- tg = dc->res_pool->timing_generators[opp_id];
- tg->funcs->lock(tg);
+ REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
+ HUBP_CLOCK_ENABLE, 0);
+ REG_UPDATE(DPP_CONTROL[fe_idx],
+ DPP_CLOCK_ENABLE, 0);
- plane_atomic_disconnect(dc, fe_idx);
+ if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL)
+ REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
+ OPP_PIPE_CLOCK_EN, 0);
- REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
- tg->funcs->unlock(tg);
+ hubp->power_gated = true;
+ dc->optimized_required = false; /* We're powering off, no need to optimize */
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(hws);
+ plane_atomic_power_down(dc, fe_idx);
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
- VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
- 1, 100000);
-
- plane_atomic_disable(dc, fe_idx);
-
- dm_logger_write(dc->ctx->logger, LOG_DC,
- "Reset front end %d\n",
- fe_idx);
+ pipe_ctx->stream = NULL;
+ memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
+ memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
+ pipe_ctx->top_pipe = NULL;
+ pipe_ctx->bottom_pipe = NULL;
+ pipe_ctx->plane_state = NULL;
}
-static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
+static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
+ if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
+ return;
+
+ plane_atomic_disable(dc, pipe_ctx);
+
+ apply_DEGVIDCN10_253_wa(dc);
+
+ dm_logger_write(dc->ctx->logger, LOG_DC,
+ "Power down front end %d\n",
+ pipe_ctx->pipe_idx);
+}
+
+static void dcn10_init_hw(struct dc *dc)
+{
+ int i;
+ struct abm *abm = dc->res_pool->abm;
+ struct dmcu *dmcu = dc->res_pool->dmcu;
struct dce_hwseq *hws = dc->hwseq;
- struct dpp *dpp = dc->res_pool->dpps[fe_idx];
+ struct dc_bios *dcb = dc->ctx->dc_bios;
+ struct dc_state *context = dc->current_state;
- reset_front_end(dc, fe_idx);
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ REG_WRITE(REFCLK_CNTL, 0);
+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+ REG_WRITE(DIO_MEM_PWR_CTRL, 0);
- REG_SET(DC_IP_REQUEST_CNTL, 0,
- IP_REQUEST_EN, 1);
- dpp_pg_control(hws, fe_idx, false);
- hubp_pg_control(hws, fe_idx, false);
- dpp->funcs->dpp_reset(dpp);
- REG_SET(DC_IP_REQUEST_CNTL, 0,
- IP_REQUEST_EN, 0);
- dm_logger_write(dc->ctx->logger, LOG_DEBUG,
- "Power gated front end %d\n", fe_idx);
+ if (!dc->debug.disable_clock_gate) {
+ /* enable all DCN clock gating */
+ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
+ REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+ REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ }
+
+ enable_power_gating_plane(dc->hwseq, true);
+ return;
+ }
+ /* end of FPGA. Below if real ASIC */
+
+ if (!dcb->funcs->is_accelerated_mode(dcb)) {
+ bios_golden_init(dc);
+ disable_vga(dc->hwseq);
+ }
+
+ for (i = 0; i < dc->link_count; i++) {
+ /* Power up AND update implementation according to the
+ * required signal (which may be different from the
+ * default signal on connector).
+ */
+ struct dc_link *link = dc->links[i];
+
+ if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
+ dc->hwss.edp_power_control(link, true);
+
+ link->link_enc->funcs->hw_init(link->link_enc);
+ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg = dc->res_pool->timing_generators[i];
+
+ if (tg->funcs->is_tg_enabled(tg))
+ tg->funcs->lock(tg);
+ }
+
+ /* Blank controller using driver code instead of
+ * command table.
+ */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg = dc->res_pool->timing_generators[i];
+
+ if (tg->funcs->is_tg_enabled(tg)) {
+ tg->funcs->set_blank(tg, true);
+ hwss_wait_for_blank_complete(tg);
+ }
+ }
+
+ /* Reset all MPCC muxes */
+ dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg = dc->res_pool->timing_generators[i];
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ struct hubp *hubp = dc->res_pool->hubps[i];
+
+ pipe_ctx->stream_res.tg = tg;
+ pipe_ctx->pipe_idx = i;
+
+ pipe_ctx->plane_res.hubp = hubp;
+ hubp->mpcc_id = i;
+ hubp->opp_id = 0xf;
+ hubp->power_gated = false;
+
+ dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
+ dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+ dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true;
+ pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+
+ plane_atomic_disconnect(dc, pipe_ctx);
+ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg = dc->res_pool->timing_generators[i];
+
+ if (tg->funcs->is_tg_enabled(tg))
+ tg->funcs->unlock(tg);
+ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg = dc->res_pool->timing_generators[i];
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ dcn10_disable_plane(dc, pipe_ctx);
+
+ pipe_ctx->stream_res.tg = NULL;
+ pipe_ctx->plane_res.hubp = NULL;
+
+ tg->funcs->tg_init(tg);
+ }
+
+ for (i = 0; i < dc->res_pool->audio_count; i++) {
+ struct audio *audio = dc->res_pool->audios[i];
+
+ audio->funcs->hw_init(audio);
+ }
+
+ if (abm != NULL) {
+ abm->funcs->init_backlight(abm);
+ abm->funcs->abm_init(abm);
+ }
+
+ if (dmcu != NULL)
+ dmcu->funcs->dmcu_init(dmcu);
+
+ /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+ REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+ if (!dc->debug.disable_clock_gate) {
+ /* enable all DCN clock gating */
+ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+ REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+ REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ }
+
+ enable_power_gating_plane(dc->hwseq, true);
}
static void reset_hw_ctx_wrap(
@@ -1231,56 +863,6 @@
{
int i;
- /* Reset Front End*/
- /* Lock*/
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
- struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
-
- if (cur_pipe_ctx->stream)
- tg->funcs->lock(tg);
- }
- /* Disconnect*/
- for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
- struct pipe_ctx *pipe_ctx_old =
- &dc->current_state->res_ctx.pipe_ctx[i];
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
- if (!pipe_ctx->stream ||
- !pipe_ctx->plane_state ||
- pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
-
- plane_atomic_disconnect(dc, i);
- }
- }
- /* Unlock*/
- for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
- struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
- struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
-
- if (cur_pipe_ctx->stream)
- tg->funcs->unlock(tg);
- }
-
- /* Disable and Powerdown*/
- for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
- struct pipe_ctx *pipe_ctx_old =
- &dc->current_state->res_ctx.pipe_ctx[i];
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
- /*if (!pipe_ctx_old->stream)
- continue;*/
-
- if (pipe_ctx->stream && pipe_ctx->plane_state
- && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
- continue;
-
- plane_atomic_disable(dc, i);
-
- if (!pipe_ctx->stream || !pipe_ctx->plane_state)
- plane_atomic_power_down(dc, i);
- }
-
/* Reset Back End*/
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
struct pipe_ctx *pipe_ctx_old =
@@ -1298,7 +880,6 @@
struct clock_source *old_clk = pipe_ctx_old->clock_source;
reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
-
if (old_clk)
old_clk->funcs->cs_power_down(old_clk);
}
@@ -1332,21 +913,7 @@
return false;
}
-static void toggle_watermark_change_req(struct dce_hwseq *hws)
-{
- uint32_t watermark_change_req;
- REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
-
- if (watermark_change_req)
- watermark_change_req = 0;
- else
- watermark_change_req = 1;
-
- REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
-}
static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
{
@@ -1366,8 +933,8 @@
pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
}
-static bool dcn10_set_input_transfer_func(
- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
+static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ const struct dc_plane_state *plane_state)
{
struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
const struct dc_transfer_func *tf = NULL;
@@ -1379,35 +946,29 @@
if (plane_state->in_transfer_func)
tf = plane_state->in_transfer_func;
- if (plane_state->gamma_correction && dce_use_lut(plane_state))
- dpp_base->funcs->ipp_program_input_lut(dpp_base,
- plane_state->gamma_correction);
+ if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
+ dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
if (tf == NULL)
- dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
+ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
else if (tf->type == TF_TYPE_PREDEFINED) {
switch (tf->tf) {
case TRANSFER_FUNCTION_SRGB:
- dpp_base->funcs->ipp_set_degamma(dpp_base,
- IPP_DEGAMMA_MODE_HW_sRGB);
+ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
break;
case TRANSFER_FUNCTION_BT709:
- dpp_base->funcs->ipp_set_degamma(dpp_base,
- IPP_DEGAMMA_MODE_HW_xvYCC);
+ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
break;
case TRANSFER_FUNCTION_LINEAR:
- dpp_base->funcs->ipp_set_degamma(dpp_base,
- IPP_DEGAMMA_MODE_BYPASS);
+ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
break;
case TRANSFER_FUNCTION_PQ:
- result = false;
- break;
default:
result = false;
break;
}
} else if (tf->type == TF_TYPE_BYPASS) {
- dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
+ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
} else {
/*TF_TYPE_DISTRIBUTED_POINTS*/
result = false;
@@ -1415,324 +976,14 @@
return result;
}
-/*modify the method to handle rgb for arr_points*/
-static bool convert_to_custom_float(
- struct pwl_result_data *rgb_resulted,
- struct curve_points *arr_points,
- uint32_t hw_points_num)
-{
- struct custom_float_format fmt;
- struct pwl_result_data *rgb = rgb_resulted;
- uint32_t i = 0;
- fmt.exponenta_bits = 6;
- fmt.mantissa_bits = 12;
- fmt.sign = false;
- if (!convert_to_custom_float_format(
- arr_points[0].x,
- &fmt,
- &arr_points[0].custom_float_x)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
- if (!convert_to_custom_float_format(
- arr_points[0].offset,
- &fmt,
- &arr_points[0].custom_float_offset)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[0].slope,
- &fmt,
- &arr_points[0].custom_float_slope)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- fmt.mantissa_bits = 10;
- fmt.sign = false;
-
- if (!convert_to_custom_float_format(
- arr_points[1].x,
- &fmt,
- &arr_points[1].custom_float_x)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[1].y,
- &fmt,
- &arr_points[1].custom_float_y)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[1].slope,
- &fmt,
- &arr_points[1].custom_float_slope)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- fmt.mantissa_bits = 12;
- fmt.sign = true;
-
- while (i != hw_points_num) {
- if (!convert_to_custom_float_format(
- rgb->red,
- &fmt,
- &rgb->red_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->green,
- &fmt,
- &rgb->green_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->blue,
- &fmt,
- &rgb->blue_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->delta_red,
- &fmt,
- &rgb->delta_red_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->delta_green,
- &fmt,
- &rgb->delta_green_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->delta_blue,
- &fmt,
- &rgb->delta_blue_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- ++rgb;
- ++i;
- }
-
- return true;
-}
-#define MAX_REGIONS_NUMBER 34
-#define MAX_LOW_POINT 25
-#define NUMBER_SEGMENTS 32
-
-static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
- *output_tf, struct pwl_params *regamma_params)
-{
- struct curve_points *arr_points;
- struct pwl_result_data *rgb_resulted;
- struct pwl_result_data *rgb;
- struct pwl_result_data *rgb_plus_1;
- struct fixed31_32 y_r;
- struct fixed31_32 y_g;
- struct fixed31_32 y_b;
- struct fixed31_32 y1_min;
- struct fixed31_32 y3_max;
-
- int32_t segment_start, segment_end;
- int32_t i;
- uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
-
- if (output_tf == NULL || regamma_params == NULL ||
- output_tf->type == TF_TYPE_BYPASS)
- return false;
-
- arr_points = regamma_params->arr_points;
- rgb_resulted = regamma_params->rgb_resulted;
- hw_points = 0;
-
- memset(regamma_params, 0, sizeof(struct pwl_params));
- memset(seg_distr, 0, sizeof(seg_distr));
-
- if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
- /* 32 segments
- * segments are from 2^-25 to 2^7
- */
- for (i = 0; i < 32 ; i++)
- seg_distr[i] = 3;
-
- segment_start = -25;
- segment_end = 7;
- } else {
- /* 10 segments
- * segment is from 2^-10 to 2^0
- * There are less than 256 points, for optimization
- */
- seg_distr[0] = 3;
- seg_distr[1] = 4;
- seg_distr[2] = 4;
- seg_distr[3] = 4;
- seg_distr[4] = 4;
- seg_distr[5] = 4;
- seg_distr[6] = 4;
- seg_distr[7] = 4;
- seg_distr[8] = 5;
- seg_distr[9] = 5;
-
- segment_start = -10;
- segment_end = 0;
- }
-
- for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
- seg_distr[i] = -1;
-
- for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
- if (seg_distr[k] != -1)
- hw_points += (1 << seg_distr[k]);
- }
-
- j = 0;
- for (k = 0; k < (segment_end - segment_start); k++) {
- increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
- start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
- for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
- if (j == hw_points - 1)
- break;
- rgb_resulted[j].red = output_tf->tf_pts.red[i];
- rgb_resulted[j].green = output_tf->tf_pts.green[i];
- rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
- j++;
- }
- }
-
- /* last point */
- start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
- rgb_resulted[hw_points - 1].red =
- output_tf->tf_pts.red[start_index];
- rgb_resulted[hw_points - 1].green =
- output_tf->tf_pts.green[start_index];
- rgb_resulted[hw_points - 1].blue =
- output_tf->tf_pts.blue[start_index];
-
- arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_start));
- arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_end));
- arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_end));
-
- y_r = rgb_resulted[0].red;
- y_g = rgb_resulted[0].green;
- y_b = rgb_resulted[0].blue;
-
- y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
-
- arr_points[0].y = y1_min;
- arr_points[0].slope = dal_fixed31_32_div(
- arr_points[0].y,
- arr_points[0].x);
- y_r = rgb_resulted[hw_points - 1].red;
- y_g = rgb_resulted[hw_points - 1].green;
- y_b = rgb_resulted[hw_points - 1].blue;
-
- /* see comment above, m_arrPoints[1].y should be the Y value for the
- * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
- */
- y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-
- arr_points[1].y = y3_max;
- arr_points[2].y = y3_max;
-
- arr_points[1].slope = dal_fixed31_32_zero;
- arr_points[2].slope = dal_fixed31_32_zero;
-
- if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
- /* for PQ, we want to have a straight line from last HW X point,
- * and the slope to be such that we hit 1.0 at 10000 nits.
- */
- const struct fixed31_32 end_value =
- dal_fixed31_32_from_int(125);
-
- arr_points[1].slope = dal_fixed31_32_div(
- dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
- dal_fixed31_32_sub(end_value, arr_points[1].x));
- arr_points[2].slope = dal_fixed31_32_div(
- dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
- dal_fixed31_32_sub(end_value, arr_points[1].x));
- }
-
- regamma_params->hw_points_num = hw_points;
-
- i = 1;
- for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
- if (seg_distr[k] != -1) {
- regamma_params->arr_curve_points[k].segments_num =
- seg_distr[k];
- regamma_params->arr_curve_points[i].offset =
- regamma_params->arr_curve_points[k].
- offset + (1 << seg_distr[k]);
- }
- i++;
- }
-
- if (seg_distr[k] != -1)
- regamma_params->arr_curve_points[k].segments_num =
- seg_distr[k];
-
- rgb = rgb_resulted;
- rgb_plus_1 = rgb_resulted + 1;
-
- i = 1;
-
- while (i != hw_points + 1) {
- if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
- rgb_plus_1->red = rgb->red;
- if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
- rgb_plus_1->green = rgb->green;
- if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
- rgb_plus_1->blue = rgb->blue;
-
- rgb->delta_red = dal_fixed31_32_sub(
- rgb_plus_1->red,
- rgb->red);
- rgb->delta_green = dal_fixed31_32_sub(
- rgb_plus_1->green,
- rgb->green);
- rgb->delta_blue = dal_fixed31_32_sub(
- rgb_plus_1->blue,
- rgb->blue);
-
- ++rgb_plus_1;
- ++rgb;
- ++i;
- }
-
- convert_to_custom_float(rgb_resulted, arr_points, hw_points);
-
- return true;
-}
-
-static bool dcn10_set_output_transfer_func(
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+static bool
+dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ const struct dc_stream_state *stream)
{
struct dpp *dpp = pipe_ctx->plane_res.dpp;
@@ -1742,18 +993,21 @@
dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
if (stream->out_transfer_func &&
- stream->out_transfer_func->type ==
- TF_TYPE_PREDEFINED &&
- stream->out_transfer_func->tf ==
- TRANSFER_FUNCTION_SRGB) {
- dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_SRGB);
- } else if (dcn10_translate_regamma_to_hw_format(
- stream->out_transfer_func, &dpp->regamma_params)) {
- dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params);
- dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_USER);
- } else {
- dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_BYPASS);
- }
+ stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
+ stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
+ dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
+
+ /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
+ * update.
+ */
+ else if (cm_helper_translate_curve_to_hw_format(
+ stream->out_transfer_func,
+ &dpp->regamma_params, false)) {
+ dpp->funcs->dpp_program_regamma_pwl(
+ dpp,
+ &dpp->regamma_params, OPP_REGAMMA_USER);
+ } else
+ dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
return true;
}
@@ -1772,7 +1026,7 @@
return;
if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
if (lock)
pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
@@ -1780,7 +1034,7 @@
pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
static bool wait_for_reset_trigger_to_occur(
@@ -1833,14 +1087,15 @@
for (i = 1; i < group_size; i++)
grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
- grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst);
-
+ grouped_pipes[i]->stream_res.tg,
+ grouped_pipes[0]->stream_res.tg->inst);
DC_SYNC_INFO("Waiting for trigger\n");
/* Need to get only check 1 pipe for having reset as all the others are
* synchronized. Look at last pipe programmed to reset.
*/
+
wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
for (i = 1; i < group_size; i++)
grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
@@ -1849,7 +1104,30 @@
DC_SYNC_INFO("Sync complete\n");
}
-static void print_rq_dlg_ttu(
+static void dcn10_enable_per_frame_crtc_position_reset(
+ struct dc *dc,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[])
+{
+ struct dc_context *dc_ctx = dc->ctx;
+ int i;
+
+ DC_SYNC_INFO("Setting up\n");
+ for (i = 0; i < group_size; i++)
+ grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
+ grouped_pipes[i]->stream_res.tg,
+ grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
+ &grouped_pipes[i]->stream->triggered_crtc_reset);
+
+ DC_SYNC_INFO("Waiting for trigger\n");
+
+ for (i = 1; i < group_size; i++)
+ wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
+
+ DC_SYNC_INFO("Multi-display sync is complete\n");
+}
+
+/*static void print_rq_dlg_ttu(
struct dc *core_dc,
struct pipe_ctx *pipe_ctx)
{
@@ -1970,19 +1248,104 @@
pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
);
}
+*/
-static void dcn10_power_on_fe(
+static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
+ struct vm_system_aperture_param *apt,
+ struct dce_hwseq *hws)
+{
+ PHYSICAL_ADDRESS_LOC physical_page_number;
+ uint32_t logical_addr_low;
+ uint32_t logical_addr_high;
+
+ REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+ PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
+ REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+ PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
+
+ REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ LOGICAL_ADDR, &logical_addr_low);
+
+ REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ LOGICAL_ADDR, &logical_addr_high);
+
+ apt->sys_default.quad_part = physical_page_number.quad_part << 12;
+ apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
+ apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
+}
+
+/* Temporary read settings, future will get values from kmd directly */
+static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
+ struct vm_context0_param *vm0,
+ struct dce_hwseq *hws)
+{
+ PHYSICAL_ADDRESS_LOC fb_base;
+ PHYSICAL_ADDRESS_LOC fb_offset;
+ uint32_t fb_base_value;
+ uint32_t fb_offset_value;
+
+ REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
+ REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
+
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
+
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
+
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
+
+ REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+ PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
+ REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+ PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
+
+ /*
+ * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
+ * Therefore we need to do
+ * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
+ */
+ fb_base.quad_part = (uint64_t)fb_base_value << 24;
+ fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
+ vm0->pte_base.quad_part += fb_base.quad_part;
+ vm0->pte_base.quad_part -= fb_offset.quad_part;
+}
+
+
+static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
+{
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+ struct vm_system_aperture_param apt = { {{ 0 } } };
+ struct vm_context0_param vm0 = { { { 0 } } };
+
+ mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
+ mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
+
+ hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
+ hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
+}
+
+static void dcn10_enable_plane(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
- struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct dce_hwseq *hws = dc->hwseq;
if (dc->debug.sanity_checks) {
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
+ undo_DEGVIDCN10_253_wa(dc);
+
power_on_plane(dc->hwseq,
pipe_ctx->pipe_idx);
@@ -1993,8 +1356,8 @@
/* make sure OPP_PIPE_CLOCK_EN = 1 */
REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
OPP_PIPE_CLOCK_EN, 1);
- /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
+/* TODO: enable/disable in dm as per update type.
if (plane_state) {
dm_logger_write(dc->ctx->logger, LOG_DC,
"Pipe:%d 0x%x: addr hi:0x%x, "
@@ -2030,9 +1393,12 @@
pipe_ctx->plane_res.scl_data.recout.y);
print_rq_dlg_ttu(dc, pipe_ctx);
}
+*/
+ if (dc->config.gpu_vm_support)
+ dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
if (dc->debug.sanity_checks) {
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
}
@@ -2082,25 +1448,27 @@
enum dc_color_space colorspace,
uint16_t *matrix)
{
- int i;
- struct out_csc_color_matrix tbl_entry;
-
- if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
- == true) {
- enum dc_color_space color_space =
- pipe_ctx->stream->output_color_space;
-
- //uint16_t matrix[12];
- for (i = 0; i < 12; i++)
- tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
-
- tbl_entry.color_space = color_space;
- //tbl_entry.regval = matrix;
- pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
+ if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
+ if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
+ pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
} else {
- pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
+ if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
+ pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
}
}
+
+static void program_output_csc(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ enum dc_color_space colorspace,
+ uint16_t *matrix,
+ int opp_id)
+{
+ if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
+ program_csc_matrix(pipe_ctx,
+ colorspace,
+ matrix);
+}
+
static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->plane_state->visible)
@@ -2188,91 +1556,169 @@
}
}
-static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
- struct vm_system_aperture_param *apt,
- struct dce_hwseq *hws)
+static uint16_t fixed_point_to_int_frac(
+ struct fixed31_32 arg,
+ uint8_t integer_bits,
+ uint8_t fractional_bits)
{
- PHYSICAL_ADDRESS_LOC physical_page_number;
- uint32_t logical_addr_low;
- uint32_t logical_addr_high;
+ int32_t numerator;
+ int32_t divisor = 1 << fractional_bits;
- REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
- PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
- REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
- PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
+ uint16_t result;
- REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
- LOGICAL_ADDR, &logical_addr_low);
+ uint16_t d = (uint16_t)dal_fixed31_32_floor(
+ dal_fixed31_32_abs(
+ arg));
- REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
- LOGICAL_ADDR, &logical_addr_high);
+ if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
+ numerator = (uint16_t)dal_fixed31_32_floor(
+ dal_fixed31_32_mul_int(
+ arg,
+ divisor));
+ else {
+ numerator = dal_fixed31_32_floor(
+ dal_fixed31_32_sub(
+ dal_fixed31_32_from_int(
+ 1LL << integer_bits),
+ dal_fixed31_32_recip(
+ dal_fixed31_32_from_int(
+ divisor))));
+ }
- apt->sys_default.quad_part = physical_page_number.quad_part << 12;
- apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
- apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
+ if (numerator >= 0)
+ result = (uint16_t)numerator;
+ else
+ result = (uint16_t)(
+ (1 << (integer_bits + fractional_bits + 1)) + numerator);
+
+ if ((result != 0) && dal_fixed31_32_lt(
+ arg, dal_fixed31_32_zero))
+ result |= 1 << (integer_bits + fractional_bits);
+
+ return result;
}
-/* Temporary read settings, future will get values from kmd directly */
-static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
- struct vm_context0_param *vm0,
- struct dce_hwseq *hws)
+void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
+ const struct dc_plane_state *plane_state)
{
- PHYSICAL_ADDRESS_LOC fb_base;
- PHYSICAL_ADDRESS_LOC fb_offset;
- uint32_t fb_base_value;
- uint32_t fb_offset_value;
+ if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
+ && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
+ && plane_state->input_csc_color_matrix.enable_adjustment
+ && plane_state->coeff_reduction_factor.value != 0) {
+ bias_and_scale->scale_blue = fixed_point_to_int_frac(
+ dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
+ dal_fixed31_32_from_fraction(256, 255)),
+ 2,
+ 13);
+ bias_and_scale->scale_red = bias_and_scale->scale_blue;
+ bias_and_scale->scale_green = bias_and_scale->scale_blue;
+ } else {
+ bias_and_scale->scale_blue = 0x2000;
+ bias_and_scale->scale_red = 0x2000;
+ bias_and_scale->scale_green = 0x2000;
+ }
+}
- REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
- REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
+static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+{
+ struct dc_bias_and_scale bns_params = {0};
- REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
- PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
- REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
- PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
+ // program the input csc
+ dpp->funcs->dpp_setup(dpp,
+ plane_state->format,
+ EXPANSION_MODE_ZERO,
+ plane_state->input_csc_color_matrix,
+ COLOR_SPACE_YCBCR601_LIMITED);
- REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
- LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
- REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
- LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
+ //set scale and bias registers
+ build_prescale_params(&bns_params, plane_state);
+ if (dpp->funcs->dpp_program_bias_and_scale)
+ dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+}
- REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
- LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
- REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
- LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
+static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct mpcc_blnd_cfg blnd_cfg;
+ bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
+ int mpcc_id;
+ struct mpcc *new_mpcc;
+ struct mpc *mpc = dc->res_pool->mpc;
+ struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
- REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
- PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
- REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
- PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
+ /* TODO: proper fix once fpga works */
+
+ if (dc->debug.surface_visual_confirm)
+ dcn10_get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ else
+ color_space_to_black_color(
+ dc, pipe_ctx->stream->output_color_space,
+ &blnd_cfg.black_color);
+
+ if (per_pixel_alpha)
+ blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
+ else
+ blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
+
+ blnd_cfg.overlap_only = false;
+ blnd_cfg.global_alpha = 0xff;
+ blnd_cfg.global_gain = 0xff;
+
+ /* DCN1.0 has output CM before MPC which seems to screw with
+ * pre-multiplied alpha.
+ */
+ blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
+ pipe_ctx->stream->output_color_space)
+ && per_pixel_alpha;
/*
- * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
- * Therefore we need to do
- * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
- * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
+ * TODO: remove hack
+ * Note: currently there is a bug in init_hw such that
+ * on resume from hibernate, BIOS sets up MPCC0, and
+ * we do mpcc_remove but the mpcc cannot go to idle
+ * after remove. This cause us to pick mpcc1 here,
+ * which causes a pstate hang for yet unknown reason.
*/
- fb_base.quad_part = (uint64_t)fb_base_value << 24;
- fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
- vm0->pte_base.quad_part += fb_base.quad_part;
- vm0->pte_base.quad_part -= fb_offset.quad_part;
+ mpcc_id = hubp->inst;
+
+ /* check if this MPCC is already being used */
+ new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
+ /* remove MPCC if being used */
+ if (new_mpcc != NULL)
+ mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
+ else
+ if (dc->debug.sanity_checks)
+ mpc->funcs->assert_mpcc_idle_before_connect(
+ dc->res_pool->mpc, mpcc_id);
+
+ /* Call MPC to insert new plane */
+ new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
+ mpc_tree_params,
+ &blnd_cfg,
+ NULL,
+ NULL,
+ hubp->inst,
+ mpcc_id);
+
+ ASSERT(new_mpcc != NULL);
+
+ hubp->opp_id = pipe_ctx->stream_res.opp->inst;
+ hubp->mpcc_id = mpcc_id;
}
-static void dcn10_program_pte_vm(struct hubp *hubp,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- enum dc_rotation_angle rotation,
- struct dce_hwseq *hws)
+static void update_scaler(struct pipe_ctx *pipe_ctx)
{
- struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
- struct vm_system_aperture_param apt = { {{ 0 } } };
- struct vm_context0_param vm0 = { { { 0 } } };
+ bool per_pixel_alpha =
+ pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
+ /* TODO: proper fix once fpga works */
- mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
- mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
-
- hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
- hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
+ pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
+ pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+ /* scaler configuration */
+ pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
+ pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
}
static void update_dchubp_dpp(
@@ -2285,95 +1731,94 @@
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
union plane_size size = plane_state->plane_size;
- struct mpcc_cfg mpcc_cfg = {0};
- struct pipe_ctx *top_pipe;
- bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
- /* TODO: proper fix once fpga works */
/* depends on DML calculation, DPP clock value may change dynamically */
- enable_dppclk(
- dc->hwseq,
- pipe_ctx->pipe_idx,
- pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
- context->bw.dcn.calc_clk.dppclk_div);
- dc->current_state->bw.dcn.cur_clk.dppclk_div =
- context->bw.dcn.calc_clk.dppclk_div;
- context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
+ if (plane_state->update_flags.bits.full_update) {
+ enable_dppclk(
+ dc->hwseq,
+ pipe_ctx->pipe_idx,
+ pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
+ context->bw.dcn.calc_clk.dppclk_div);
+ dc->current_state->bw.dcn.cur_clk.dppclk_div =
+ context->bw.dcn.calc_clk.dppclk_div;
+ context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
+ }
/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
* VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
* VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
*/
- REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
+ if (plane_state->update_flags.bits.full_update) {
+ REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
- hubp->funcs->hubp_setup(
- hubp,
- &pipe_ctx->dlg_regs,
- &pipe_ctx->ttu_regs,
- &pipe_ctx->rq_regs,
- &pipe_ctx->pipe_dlg_param);
+ hubp->funcs->hubp_setup(
+ hubp,
+ &pipe_ctx->dlg_regs,
+ &pipe_ctx->ttu_regs,
+ &pipe_ctx->rq_regs,
+ &pipe_ctx->pipe_dlg_param);
+ }
size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
- if (dc->config.gpu_vm_support)
- dcn10_program_pte_vm(
- pipe_ctx->plane_res.hubp,
- plane_state->format,
- &plane_state->tiling_info,
- plane_state->rotation,
- hws
- );
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.bpp_change)
+ update_dpp(dpp, plane_state);
- dpp->funcs->ipp_setup(dpp,
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.per_pixel_alpha_change)
+ update_mpcc(dc, pipe_ctx);
+
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.per_pixel_alpha_change ||
+ plane_state->update_flags.bits.scaling_change ||
+ plane_state->update_flags.bits.position_change) {
+ update_scaler(pipe_ctx);
+ }
+
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.scaling_change ||
+ plane_state->update_flags.bits.position_change) {
+ hubp->funcs->mem_program_viewport(
+ hubp,
+ &pipe_ctx->plane_res.scl_data.viewport,
+ &pipe_ctx->plane_res.scl_data.viewport_c);
+ }
+
+ if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
+ dc->hwss.set_cursor_position(pipe_ctx);
+ dc->hwss.set_cursor_attribute(pipe_ctx);
+ }
+
+ if (plane_state->update_flags.bits.full_update) {
+ /*gamut remap*/
+ program_gamut_remap(pipe_ctx);
+
+ program_output_csc(dc,
+ pipe_ctx,
+ pipe_ctx->stream->output_color_space,
+ pipe_ctx->stream->csc_color_matrix.matrix,
+ hubp->opp_id);
+ }
+
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.horizontal_mirror_change ||
+ plane_state->update_flags.bits.rotation_change ||
+ plane_state->update_flags.bits.swizzle_change ||
+ plane_state->update_flags.bits.dcc_change ||
+ plane_state->update_flags.bits.bpp_change ||
+ plane_state->update_flags.bits.scaling_change) {
+ hubp->funcs->hubp_program_surface_config(
+ hubp,
plane_state->format,
- EXPANSION_MODE_ZERO);
+ &plane_state->tiling_info,
+ &size,
+ plane_state->rotation,
+ &plane_state->dcc,
+ plane_state->horizontal_mirror);
+ }
- mpcc_cfg.dpp_id = hubp->inst;
- mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
- mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree);
- for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
- mpcc_cfg.z_index++;
- if (dc->debug.surface_visual_confirm)
- dcn10_get_surface_visual_confirm_color(
- pipe_ctx, &mpcc_cfg.black_color);
- else
- color_space_to_black_color(
- dc, pipe_ctx->stream->output_color_space,
- &mpcc_cfg.black_color);
- mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
- /* DCN1.0 has output CM before MPC which seems to screw with
- * pre-multiplied alpha.
- */
- mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
- pipe_ctx->stream->output_color_space)
- && per_pixel_alpha;
- hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
- hubp->opp_id = mpcc_cfg.opp_id;
-
- pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
- pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
- /* scaler configuration */
- pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
- pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
-
- hubp->funcs->mem_program_viewport(hubp,
- &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);
-
- /*gamut remap*/
- program_gamut_remap(pipe_ctx);
-
- program_csc_matrix(pipe_ctx,
- pipe_ctx->stream->output_color_space,
- pipe_ctx->stream->csc_color_matrix.matrix);
-
- hubp->funcs->hubp_program_surface_config(
- hubp,
- plane_state->format,
- &plane_state->tiling_info,
- &size,
- plane_state->rotation,
- &plane_state->dcc,
- plane_state->horizontal_mirror);
+ hubp->power_gated = false;
dc->hwss.update_plane_addr(dc, pipe_ctx);
@@ -2387,23 +1832,9 @@
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
- unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
if (pipe_ctx->top_pipe == NULL) {
- /* lock otg_master_update to process all pipes associated with
- * this OTG. this is done only one time.
- */
- /* watermark is for all pipes */
- program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
-
- if (dc->debug.sanity_checks) {
- /* pstate stuck check after watermark update */
- verify_allow_pstate_change_high(dc->hwseq);
- }
-
- pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
-
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
@@ -2412,46 +1843,32 @@
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg);
- pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
+
+ if (pipe_ctx->stream_res.tg->funcs->set_blank)
+ pipe_ctx->stream_res.tg->funcs->set_blank(
+ pipe_ctx->stream_res.tg,
+ !is_pipe_tree_visible(pipe_ctx));
}
if (pipe_ctx->plane_state != NULL) {
- struct dc_cursor_position position = { 0 };
- struct pipe_ctx *cur_pipe_ctx =
- &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-
- dcn10_power_on_fe(dc, pipe_ctx, context);
-
- /* temporary dcn1 wa:
- * watermark update requires toggle after a/b/c/d sets are programmed
- * if hubp is pg then wm value doesn't get properaged to hubp
- * need to toggle after ungate to ensure wm gets to hubp.
- *
- * final solution: we need to get SMU to do the toggle as
- * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
- * both driver and fw accessing same register
- */
- toggle_watermark_change_req(dc->hwseq);
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ dcn10_enable_plane(dc, pipe_ctx, context);
update_dchubp_dpp(dc, pipe_ctx, context);
- /* TODO: this is a hack w/a for switching from mpo to pipe split */
- dc_stream_set_cursor_position(pipe_ctx->stream, &position);
+ if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+ dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
- dc_stream_set_cursor_attributes(pipe_ctx->stream,
- &pipe_ctx->stream->cursor_attributes);
-
- if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
- dc->hwss.set_input_transfer_func(
- pipe_ctx, pipe_ctx->plane_state);
- dc->hwss.set_output_transfer_func(
- pipe_ctx, pipe_ctx->stream);
- }
- }
-
- if (dc->debug.sanity_checks) {
- /* pstate stuck check after each pipe is programmed */
- verify_allow_pstate_change_high(dc->hwseq);
+ /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ * only do gamma programming for full update.
+ * TODO: This can be further optimized/cleaned up
+ * Always call this for now since it does memcmp inside before
+ * doing heavy calculation and programming
+ */
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
}
if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
@@ -2488,7 +1905,6 @@
static void optimize_shared_resources(struct dc *dc)
{
if (dc->current_state->stream_count == 0) {
- apply_DEGVIDCN10_253_wa(dc);
/* S0i2 message */
dcn10_pplib_apply_display_requirements(dc, dc->current_state);
}
@@ -2499,51 +1915,19 @@
static void ready_shared_resources(struct dc *dc, struct dc_state *context)
{
- if (dc->current_state->stream_count == 0 &&
- !dc->debug.disable_stutter)
- undo_DEGVIDCN10_253_wa(dc);
-
/* S0i2 message */
if (dc->current_state->stream_count == 0 &&
context->stream_count != 0)
dcn10_pplib_apply_display_requirements(dc, context);
}
-static void dcn10_apply_ctx_for_surface(
+static struct pipe_ctx *find_top_pipe_for_stream(
struct dc *dc,
- const struct dc_stream_state *stream,
- int num_planes,
- struct dc_state *context)
+ struct dc_state *context,
+ const struct dc_stream_state *stream)
{
- int i, be_idx;
+ int i;
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
-
- be_idx = -1;
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if (stream == context->res_ctx.pipe_ctx[i].stream) {
- be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
- break;
- }
- }
-
- ASSERT(be_idx != -1);
-
- if (num_planes == 0) {
- for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
- struct pipe_ctx *old_pipe_ctx =
- &dc->current_state->res_ctx.pipe_ctx[i];
-
- if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) {
- old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true);
- dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx);
- }
- }
- return;
- }
-
- /* reset unused mpcc */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe_ctx =
@@ -2552,14 +1936,63 @@
if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
continue;
+ if (pipe_ctx->stream != stream)
+ continue;
+
+ if (!pipe_ctx->top_pipe)
+ return pipe_ctx;
+ }
+ return NULL;
+}
+
+static void dcn10_apply_ctx_for_surface(
+ struct dc *dc,
+ const struct dc_stream_state *stream,
+ int num_planes,
+ struct dc_state *context)
+{
+ int i;
+ struct timing_generator *tg;
+ struct output_pixel_processor *opp;
+ bool removed_pipe[4] = { false };
+ unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
+ bool program_water_mark = false;
+
+ struct pipe_ctx *top_pipe_to_program =
+ find_top_pipe_for_stream(dc, context, stream);
+
+ if (!top_pipe_to_program)
+ return;
+
+ opp = top_pipe_to_program->stream_res.opp;
+
+ tg = top_pipe_to_program->stream_res.tg;
+
+ tg->funcs->lock(tg);
+
+ if (num_planes == 0) {
+
+ /* OTG blank before remove all front end */
+ if (tg->funcs->set_blank)
+ tg->funcs->set_blank(tg, true);
+ }
+
+ /* Disconnect unused mpcc */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe_ctx =
+ &dc->current_state->res_ctx.pipe_ctx[i];
/*
* Powergate reused pipes that are not powergated
* fairly hacky right now, using opp_id as indicator
+ * TODO: After move dc_post to dc_update, this will
+ * be removed.
*/
-
if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
- if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
- dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
+ if (old_pipe_ctx->stream_res.tg == tg &&
+ old_pipe_ctx->plane_res.hubp &&
+ old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
+ dcn10_disable_plane(dc, pipe_ctx);
/*
* power down fe will unlock when calling reset, need
* to lock it back here. Messy, need rework.
@@ -2568,36 +2001,12 @@
}
}
+ if (!pipe_ctx->plane_state &&
+ old_pipe_ctx->plane_state &&
+ old_pipe_ctx->stream_res.tg == tg) {
- if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state)
- || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
- if (old_pipe_ctx->stream_res.tg->inst != be_idx)
- continue;
-
- if (!old_pipe_ctx->top_pipe) {
- ASSERT(0);
- continue;
- }
-
- /* reset mpc */
- dc->res_pool->mpc->funcs->remove(
- dc->res_pool->mpc,
- &(old_pipe_ctx->stream_res.opp->mpc_tree),
- old_pipe_ctx->stream_res.opp->inst,
- old_pipe_ctx->pipe_idx);
- old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true;
-
- /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
- "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
- old_pipe_ctx->mpcc->inst);*/
-
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
-
- old_pipe_ctx->top_pipe = NULL;
- old_pipe_ctx->bottom_pipe = NULL;
- old_pipe_ctx->plane_state = NULL;
- old_pipe_ctx->stream = NULL;
+ plane_atomic_disconnect(dc, old_pipe_ctx);
+ removed_pipe[i] = true;
dm_logger_write(dc->ctx->logger, LOG_DC,
"Reset mpcc for pipe %d\n",
@@ -2605,18 +2014,44 @@
}
}
+ if (num_planes > 0)
+ program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+
+ tg->funcs->unlock(tg);
+
+ if (num_planes == 0)
+ false_optc_underflow_wa(dc, stream, tg);
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *old_pipe_ctx =
+ &dc->current_state->res_ctx.pipe_ctx[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- if (pipe_ctx->stream != stream)
- continue;
+ if (pipe_ctx->stream == stream &&
+ pipe_ctx->plane_state &&
+ pipe_ctx->plane_state->update_flags.bits.full_update)
+ program_water_mark = true;
- /* looking for top pipe to program */
- if (!pipe_ctx->top_pipe)
- program_all_pipe_in_tree(dc, pipe_ctx, context);
+ if (removed_pipe[i])
+ dcn10_disable_plane(dc, old_pipe_ctx);
}
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ if (program_water_mark) {
+ if (dc->debug.sanity_checks) {
+ /* pstate stuck check after watermark update */
+ dcn10_verify_allow_pstate_change_high(dc);
+ }
+
+ /* watermark is for all pipes */
+ hubbub1_program_watermarks(dc->res_pool->hubbub,
+ &context->bw.dcn.watermarks, ref_clk_mhz);
+
+ if (dc->debug.sanity_checks) {
+ /* pstate stuck check after watermark update */
+ dcn10_verify_allow_pstate_change_high(dc);
+ }
+ }
+/* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
"\n============== Watermark parameters ==============\n"
"a.urgent_ns: %d \n"
"a.cstate_enter_plus_exit: %d \n"
@@ -2662,9 +2097,7 @@
context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
context->bw.dcn.watermarks.d.pte_meta_urgent_ns
);
-
- if (dc->debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
+*/
}
static void dcn10_set_bandwidth(
@@ -2678,7 +2111,7 @@
struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
if (dc->debug.sanity_checks) {
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
@@ -2734,7 +2167,7 @@
dcn10_pplib_apply_display_requirements(dc, context);
if (dc->debug.sanity_checks) {
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
/* need to fix this function. not doing the right thing here */
@@ -2838,10 +2271,10 @@
dcn10_config_stereo_parameters(stream, &flags);
- pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
+ pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
pipe_ctx->stream_res.opp,
flags.PROGRAM_STEREO == 1 ? true:false,
- stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
+ &stream->timing);
pipe_ctx->stream_res.tg->funcs->program_stereo(
pipe_ctx->stream_res.tg,
@@ -2859,7 +2292,7 @@
int i;
if (dc->debug.sanity_checks) {
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
if (!pipe_ctx->stream_res.opp)
@@ -2877,7 +2310,7 @@
}
if (dc->debug.sanity_checks) {
- verify_allow_pstate_change_high(dc->hwseq);
+ dcn10_verify_allow_pstate_change_high(dc);
}
}
@@ -2891,7 +2324,7 @@
return true;
}
-void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
{
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct timing_generator *tg = pipe_ctx->stream_res.tg;
@@ -2911,7 +2344,45 @@
}
}
+static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+{
+ if (hws->ctx->dc->res_pool->hubbub != NULL)
+ hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+}
+static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+{
+ struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ struct dc_cursor_mi_param param = {
+ .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
+ .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
+ .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
+ .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
+ .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
+ };
+
+ if (pipe_ctx->plane_state->address.type
+ == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+ pos_cpy.enable = false;
+
+ if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
+ pos_cpy.enable = false;
+
+ hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
+ dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width);
+}
+
+static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+{
+ struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+
+ pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
+ pipe_ctx->plane_res.hubp, attributes);
+ pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
+ pipe_ctx->plane_res.dpp, attributes->color_format);
+}
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
@@ -2928,13 +2399,13 @@
.power_down = dce110_power_down,
.enable_accelerated_mode = dce110_enable_accelerated_mode,
.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
.update_info_frame = dce110_update_info_frame,
.enable_stream = dce110_enable_stream,
.disable_stream = dce110_disable_stream,
.unblank_stream = dce110_unblank_stream,
.enable_display_power_gating = dcn10_dummy_display_power_gating,
- .power_down_front_end = dcn10_power_down_fe,
- .power_on_front_end = dcn10_power_on_fe,
+ .disable_plane = dcn10_disable_plane,
.pipe_control_lock = dcn10_pipe_control_lock,
.set_bandwidth = dcn10_set_bandwidth,
.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
@@ -2948,8 +2419,13 @@
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
.ready_shared_resources = ready_shared_resources,
.optimize_shared_resources = optimize_shared_resources,
+ .pplib_apply_display_requirements =
+ dcn10_pplib_apply_display_requirements,
.edp_backlight_control = hwss_edp_backlight_control,
- .edp_power_control = hwss_edp_power_control
+ .edp_power_control = hwss_edp_power_control,
+ .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
+ .set_cursor_position = dcn10_set_cursor_position,
+ .set_cursor_attribute = dcn10_set_cursor_attribute
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index ca53dc1c..b9d3260 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -35,4 +35,5 @@
const struct dc_state *context,
struct dm_pp_display_configuration *pp_display_cfg);
+
#endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 76573e1..179890b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -25,8 +25,6 @@
#include "reg_helper.h"
#include "dcn10_mpc.h"
-#include "dc.h"
-#include "mem_input.h"
#define REG(reg)\
mpc10->mpc_regs->reg
@@ -38,17 +36,13 @@
#define FN(reg_name, field_name) \
mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
-#define MODE_TOP_ONLY 1
-#define MODE_BLEND 3
-#define BLND_PP_ALPHA 0
-#define BLND_GLOBAL_ALPHA 2
-
-static void mpc10_set_bg_color(
- struct dcn10_mpc *mpc10,
+void mpc1_set_bg_color(struct mpc *mpc,
struct tg_color *bg_color,
- int id)
+ int mpcc_id)
{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+
/* mpc color is 12 bit. tg_color is 10 bit */
/* todo: might want to use 16 bit to represent color and have each
* hw block translate to correct color depth.
@@ -57,15 +51,47 @@
uint32_t bg_g_y = bg_color->color_g_y << 2;
uint32_t bg_b_cb = bg_color->color_b_cb << 2;
- REG_SET(MPCC_BG_R_CR[id], 0,
+ REG_SET(MPCC_BG_R_CR[mpcc_id], 0,
MPCC_BG_R_CR, bg_r_cr);
- REG_SET(MPCC_BG_G_Y[id], 0,
+ REG_SET(MPCC_BG_G_Y[mpcc_id], 0,
MPCC_BG_G_Y, bg_g_y);
- REG_SET(MPCC_BG_B_CB[id], 0,
+ REG_SET(MPCC_BG_B_CB[mpcc_id], 0,
MPCC_BG_B_CB, bg_b_cb);
}
-void mpc10_assert_idle_mpcc(struct mpc *mpc, int id)
+static void mpc1_update_blending(
+ struct mpc *mpc,
+ struct mpcc_blnd_cfg *blnd_cfg,
+ int mpcc_id)
+{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+
+ REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
+ MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
+ MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,
+ MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only,
+ MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha,
+ MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);
+
+ mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
+}
+
+void mpc1_update_stereo_mix(
+ struct mpc *mpc,
+ struct mpcc_sm_cfg *sm_cfg,
+ int mpcc_id)
+{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+
+ REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
+ MPCC_SM_EN, sm_cfg->enable,
+ MPCC_SM_MODE, sm_cfg->sm_mode,
+ MPCC_SM_FRAME_ALT, sm_cfg->frame_alt,
+ MPCC_SM_FIELD_ALT, sm_cfg->field_alt,
+ MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity,
+ MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity);
+}
+void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
@@ -75,39 +101,52 @@
1, 100000);
}
-static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10)
+struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
{
- int i;
- int last_free_mpcc_id = -1;
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- for (i = 0; i < mpc10->num_mpcc; i++) {
- uint32_t is_idle = 0;
-
- if (mpc10->mpcc_in_use_mask & 1 << i)
- continue;
-
- last_free_mpcc_id = i;
- REG_GET(MPCC_STATUS[i], MPCC_IDLE, &is_idle);
- if (is_idle)
- return i;
- }
-
- /* This assert should never trigger, we have mpcc leak if it does */
- ASSERT(last_free_mpcc_id != -1);
-
- mpc10_assert_idle_mpcc(&mpc10->base, last_free_mpcc_id);
- return last_free_mpcc_id;
+ ASSERT(mpcc_id < mpc10->num_mpcc);
+ return &(mpc->mpcc_array[mpcc_id]);
}
-static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int id)
+struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
{
+ struct mpcc *tmp_mpcc = tree->opp_list;
+
+ while (tmp_mpcc != NULL) {
+ if (tmp_mpcc->dpp_id == dpp_id)
+ return tmp_mpcc;
+ tmp_mpcc = tmp_mpcc->mpcc_bot;
+ }
+ return NULL;
+}
+
+bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)
+{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+ unsigned int top_sel;
+ unsigned int opp_id;
+ unsigned int idle;
+
+ REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
+ REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
+ REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);
+ if (top_sel == 0xf && opp_id == 0xf && idle)
+ return true;
+ else
+ return false;
+}
+
+void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
+{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
unsigned int top_sel, mpc_busy, mpc_idle;
- REG_GET(MPCC_TOP_SEL[id],
+ REG_GET(MPCC_TOP_SEL[mpcc_id],
MPCC_TOP_SEL, &top_sel);
if (top_sel == 0xf) {
- REG_GET_2(MPCC_STATUS[id],
+ REG_GET_2(MPCC_STATUS[mpcc_id],
MPCC_BUSY, &mpc_busy,
MPCC_IDLE, &mpc_idle);
@@ -116,230 +155,269 @@
}
}
-void mpc10_mpcc_remove(
- struct mpc *mpc,
- struct mpc_tree_cfg *tree_cfg,
- int opp_id,
- int dpp_id)
-{
- struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- int mpcc_id, z_idx;
-
- /* find z_idx for the dpp to be removed */
- for (z_idx = 0; z_idx < tree_cfg->num_pipes; z_idx++)
- if (tree_cfg->dpp[z_idx] == dpp_id)
- break;
-
- if (z_idx == tree_cfg->num_pipes) {
- /* In case of resume from S3/S4, remove mpcc from bios left over */
- REG_SET(MPCC_OPP_ID[dpp_id], 0,
- MPCC_OPP_ID, 0xf);
- REG_SET(MPCC_TOP_SEL[dpp_id], 0,
- MPCC_TOP_SEL, 0xf);
- REG_SET(MPCC_BOT_SEL[dpp_id], 0,
- MPCC_BOT_SEL, 0xf);
- return;
- }
-
- mpcc_id = tree_cfg->mpcc[z_idx];
-
- REG_SET(MPCC_OPP_ID[mpcc_id], 0,
- MPCC_OPP_ID, 0xf);
- REG_SET(MPCC_TOP_SEL[mpcc_id], 0,
- MPCC_TOP_SEL, 0xf);
- REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
- MPCC_BOT_SEL, 0xf);
-
- if (z_idx > 0) {
- int top_mpcc_id = tree_cfg->mpcc[z_idx - 1];
-
- if (z_idx + 1 < tree_cfg->num_pipes)
- /* mpcc to be removed is in the middle of the tree */
- REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0,
- MPCC_BOT_SEL, tree_cfg->mpcc[z_idx + 1]);
- else {
- /* mpcc to be removed is at the bottom of the tree */
- REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0,
- MPCC_BOT_SEL, 0xf);
- REG_UPDATE(MPCC_CONTROL[top_mpcc_id],
- MPCC_MODE, MODE_TOP_ONLY);
- }
- } else if (tree_cfg->num_pipes > 1)
- /* mpcc to be removed is at the top of the tree */
- REG_SET(MUX[opp_id], 0,
- MPC_OUT_MUX, tree_cfg->mpcc[z_idx + 1]);
- else
- /* mpcc to be removed is the only one in the tree */
- REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf);
-
- /* mark this mpcc as not in use */
- mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
- tree_cfg->num_pipes--;
- for (; z_idx < tree_cfg->num_pipes; z_idx++) {
- tree_cfg->dpp[z_idx] = tree_cfg->dpp[z_idx + 1];
- tree_cfg->mpcc[z_idx] = tree_cfg->mpcc[z_idx + 1];
- }
- tree_cfg->dpp[tree_cfg->num_pipes] = 0xdeadbeef;
- tree_cfg->mpcc[tree_cfg->num_pipes] = 0xdeadbeef;
-}
-
-static void mpc10_add_to_tree_cfg(
+/*
+ * Insert DPP into MPC tree based on specified blending position.
+ * Only used for planes that are part of blending chain for OPP output
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ * [in/out] tree - MPC tree structure that plane will be added to.
+ * [in] blnd_cfg - MPCC blending configuration for the new blending layer.
+ * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer.
+ * stereo mix must disable for the very bottom layer of the tree config.
+ * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.
+ * [in] dpp_id - DPP instance for the plane to be added.
+ * [in] mpcc_id - The MPCC physical instance to use for blending.
+ *
+ * Return: struct mpcc* - MPCC that was added.
+ */
+struct mpcc *mpc1_insert_plane(
struct mpc *mpc,
- struct mpcc_cfg *cfg,
+ struct mpc_tree *tree,
+ struct mpcc_blnd_cfg *blnd_cfg,
+ struct mpcc_sm_cfg *sm_cfg,
+ struct mpcc *insert_above_mpcc,
+ int dpp_id,
int mpcc_id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- int mpcc_mode = MODE_TOP_ONLY;
- int position = cfg->z_index;
- struct mpc_tree_cfg *tree_cfg = cfg->tree_cfg;
- int alpha_blnd_mode = cfg->per_pixel_alpha ?
- BLND_PP_ALPHA : BLND_GLOBAL_ALPHA;
- int z_idx;
+ struct mpcc *new_mpcc = NULL;
- REG_SET(MPCC_OPP_ID[mpcc_id], 0,
- MPCC_OPP_ID, cfg->opp_id);
+ /* sanity check parameters */
+ ASSERT(mpcc_id < mpc10->num_mpcc);
+ ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
- REG_SET(MPCC_TOP_SEL[mpcc_id], 0,
- MPCC_TOP_SEL, cfg->dpp_id);
+ if (insert_above_mpcc) {
+ /* check insert_above_mpcc exist in tree->opp_list */
+ struct mpcc *temp_mpcc = tree->opp_list;
- if (position == 0) {
- /* idle dpp/mpcc is added to the top layer of tree */
+ while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
+ temp_mpcc = temp_mpcc->mpcc_bot;
+ if (temp_mpcc == NULL)
+ return NULL;
+ }
- if (tree_cfg->num_pipes > 0) {
- /* get instance of previous top mpcc */
- int prev_top_mpcc_id = tree_cfg->mpcc[0];
+ /* Get and update MPCC struct parameters */
+ new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
+ new_mpcc->dpp_id = dpp_id;
- REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
- MPCC_BOT_SEL, prev_top_mpcc_id);
- mpcc_mode = MODE_BLEND;
+ /* program mux and MPCC_MODE */
+ if (insert_above_mpcc) {
+ new_mpcc->mpcc_bot = insert_above_mpcc;
+ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
+ REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
+ } else {
+ new_mpcc->mpcc_bot = NULL;
+ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
+ REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
+ }
+ REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
+ REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
+
+ /* update mpc tree mux setting */
+ if (tree->opp_list == insert_above_mpcc) {
+ /* insert the toppest mpcc */
+ tree->opp_list = new_mpcc;
+ REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
+ } else {
+ /* find insert position */
+ struct mpcc *temp_mpcc = tree->opp_list;
+
+ while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
+ temp_mpcc = temp_mpcc->mpcc_bot;
+ if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {
+ REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
+ temp_mpcc->mpcc_bot = new_mpcc;
+ if (!insert_above_mpcc)
+ REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
+ MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
}
-
- /* opp will get new output. from new added mpcc */
- REG_SET(MUX[cfg->opp_id], 0, MPC_OUT_MUX, mpcc_id);
-
- } else if (position == tree_cfg->num_pipes) {
- /* idle dpp/mpcc is added to the bottom layer of tree */
-
- /* get instance of previous bottom mpcc, set to middle layer */
- int prev_bot_mpcc_id = tree_cfg->mpcc[tree_cfg->num_pipes - 1];
-
- REG_SET(MPCC_BOT_SEL[prev_bot_mpcc_id], 0,
- MPCC_BOT_SEL, mpcc_id);
- REG_UPDATE(MPCC_CONTROL[prev_bot_mpcc_id],
- MPCC_MODE, MODE_BLEND);
-
- /* mpcc_id become new bottom mpcc*/
- REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
- MPCC_BOT_SEL, 0xf);
-
- } else {
- /* idle dpp/mpcc is added to middle of tree */
- int above_mpcc_id = tree_cfg->mpcc[position - 1];
- int below_mpcc_id = tree_cfg->mpcc[position];
-
- /* mpcc above new mpcc_id has new bottom mux*/
- REG_SET(MPCC_BOT_SEL[above_mpcc_id], 0,
- MPCC_BOT_SEL, mpcc_id);
- REG_UPDATE(MPCC_CONTROL[above_mpcc_id],
- MPCC_MODE, MODE_BLEND);
-
- /* mpcc_id bottom mux is from below mpcc*/
- REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
- MPCC_BOT_SEL, below_mpcc_id);
- mpcc_mode = MODE_BLEND;
}
- REG_SET_4(MPCC_CONTROL[mpcc_id], 0xffffffff,
- MPCC_MODE, mpcc_mode,
- MPCC_ALPHA_BLND_MODE, alpha_blnd_mode,
- MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha,
- MPCC_BLND_ACTIVE_OVERLAP_ONLY, false);
+ /* update the blending configuration */
+ new_mpcc->blnd_cfg = *blnd_cfg;
+ mpc->funcs->update_blending(mpc, &new_mpcc->blnd_cfg, mpcc_id);
- /* update mpc_tree_cfg with new mpcc */
- for (z_idx = tree_cfg->num_pipes; z_idx > position; z_idx--) {
- tree_cfg->dpp[z_idx] = tree_cfg->dpp[z_idx - 1];
- tree_cfg->mpcc[z_idx] = tree_cfg->mpcc[z_idx - 1];
+ /* update the stereo mix settings, if provided */
+ if (sm_cfg != NULL) {
+ new_mpcc->sm_cfg = *sm_cfg;
+ mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
}
- tree_cfg->dpp[position] = cfg->dpp_id;
- tree_cfg->mpcc[position] = mpcc_id;
- tree_cfg->num_pipes++;
-}
-
-int mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg)
-{
- struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- int mpcc_id, z_idx;
-
- ASSERT(cfg->z_index < mpc10->num_mpcc);
-
- /* check in dpp already exists in mpc tree */
- for (z_idx = 0; z_idx < cfg->tree_cfg->num_pipes; z_idx++)
- if (cfg->tree_cfg->dpp[z_idx] == cfg->dpp_id)
- break;
- if (z_idx == cfg->tree_cfg->num_pipes) {
- ASSERT(cfg->z_index <= cfg->tree_cfg->num_pipes);
- mpcc_id = mpc10_get_idle_mpcc_id(mpc10);
-
- /*
- * TODO: remove hack
- * Note: currently there is a bug in init_hw such that
- * on resume from hibernate, BIOS sets up MPCC0, and
- * we do mpcc_remove but the mpcc cannot go to idle
- * after remove. This cause us to pick mpcc1 here,
- * which causes a pstate hang for yet unknown reason.
- */
- mpcc_id = cfg->dpp_id;
- /* end hack*/
-
- ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
-
- if (mpc->ctx->dc->debug.sanity_checks)
- mpc10_assert_mpcc_idle_before_connect(mpc10, mpcc_id);
- } else {
- ASSERT(cfg->z_index < cfg->tree_cfg->num_pipes);
- mpcc_id = cfg->tree_cfg->mpcc[z_idx];
- mpc10_mpcc_remove(mpc, cfg->tree_cfg, cfg->opp_id, cfg->dpp_id);
- }
-
- /* add dpp/mpcc pair to mpc_tree_cfg and update mpcc registers */
- mpc10_add_to_tree_cfg(mpc, cfg, mpcc_id);
-
- /* set background color */
- mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id);
/* mark this mpcc as in use */
mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
- return mpcc_id;
+ return new_mpcc;
}
-void mpc10_update_blend_mode(
- struct mpc *mpc,
- struct mpcc_cfg *cfg)
+/*
+ * Remove a specified MPCC from the MPC tree.
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ * [in/out] tree - MPC tree structure that plane will be removed from.
+ * [in/out] mpcc - MPCC to be removed from tree.
+ *
+ * Return: void
+ */
+void mpc1_remove_mpcc(
+ struct mpc *mpc,
+ struct mpc_tree *tree,
+ struct mpcc *mpcc_to_remove)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- int mpcc_id, z_idx;
- int alpha_blnd_mode = cfg->per_pixel_alpha ?
- BLND_PP_ALPHA : BLND_GLOBAL_ALPHA;
+ bool found = false;
+ int mpcc_id = mpcc_to_remove->mpcc_id;
- /* find z_idx for the dpp that requires blending mode update*/
- for (z_idx = 0; z_idx < cfg->tree_cfg->num_pipes; z_idx++)
- if (cfg->tree_cfg->dpp[z_idx] == cfg->dpp_id)
- break;
+ if (tree->opp_list == mpcc_to_remove) {
+ found = true;
+ /* remove MPCC from top of tree */
+ if (mpcc_to_remove->mpcc_bot) {
+ /* set the next MPCC in list to be the top MPCC */
+ tree->opp_list = mpcc_to_remove->mpcc_bot;
+ REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
+ } else {
+ /* there are no other MPCC is list */
+ tree->opp_list = NULL;
+ REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
+ }
+ } else {
+ /* find mpcc to remove MPCC list */
+ struct mpcc *temp_mpcc = tree->opp_list;
- ASSERT(z_idx < cfg->tree_cfg->num_pipes);
- mpcc_id = cfg->tree_cfg->mpcc[z_idx];
+ while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)
+ temp_mpcc = temp_mpcc->mpcc_bot;
- REG_UPDATE_2(MPCC_CONTROL[mpcc_id],
- MPCC_ALPHA_BLND_MODE, alpha_blnd_mode,
- MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha);
+ if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {
+ found = true;
+ temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;
+ if (mpcc_to_remove->mpcc_bot) {
+ /* remove MPCC in middle of list */
+ REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
+ MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id);
+ } else {
+ /* remove MPCC from bottom of list */
+ REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
+ MPCC_BOT_SEL, 0xf);
+ REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
+ MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
+ }
+ }
+ }
+
+ if (found) {
+ /* turn off MPCC mux registers */
+ REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
+ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
+ REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
+
+ /* mark this mpcc as not in use */
+ mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
+ mpcc_to_remove->dpp_id = 0xf;
+ mpcc_to_remove->mpcc_bot = NULL;
+ } else {
+ /* In case of resume from S3/S4, remove mpcc from bios left over */
+ REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
+ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
+ REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
+ }
+}
+
+static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+{
+ mpcc->mpcc_id = mpcc_inst;
+ mpcc->dpp_id = 0xf;
+ mpcc->mpcc_bot = NULL;
+ mpcc->blnd_cfg.overlap_only = false;
+ mpcc->blnd_cfg.global_alpha = 0xff;
+ mpcc->blnd_cfg.global_gain = 0xff;
+ mpcc->sm_cfg.enable = false;
+}
+
+/*
+ * Reset the MPCC HW status by disconnecting all muxes.
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ *
+ * Return: void
+ */
+void mpc1_mpc_init(struct mpc *mpc)
+{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+ int mpcc_id;
+ int opp_id;
+
+ mpc10->mpcc_in_use_mask = 0;
+ for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
+ REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
+ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
+ REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
+
+ mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
+ }
+
+ for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
+ if (REG(MUX[opp_id]))
+ REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
+ }
+}
+
+void mpc1_init_mpcc_list_from_hw(
+ struct mpc *mpc,
+ struct mpc_tree *tree)
+{
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+ unsigned int opp_id;
+ unsigned int top_sel;
+ unsigned int bot_sel;
+ unsigned int out_mux;
+ struct mpcc *mpcc;
+ int mpcc_id;
+ int bot_mpcc_id;
+
+ REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
+
+ if (out_mux != 0xf) {
+ for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
+ REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
+ REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
+ REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);
+
+ if (bot_sel == mpcc_id)
+ bot_sel = 0xf;
+
+ if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
+ mpcc = mpc1_get_mpcc(mpc, mpcc_id);
+ mpcc->dpp_id = top_sel;
+ mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
+
+ if (out_mux == mpcc_id)
+ tree->opp_list = mpcc;
+ if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {
+ bot_mpcc_id = bot_sel;
+ REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);
+ REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
+ if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
+ struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
+
+ mpcc->mpcc_bot = mpcc_bottom;
+ }
+ }
+ }
+ }
+ }
}
const struct mpc_funcs dcn10_mpc_funcs = {
- .add = mpc10_mpcc_add,
- .remove = mpc10_mpcc_remove,
- .wait_for_idle = mpc10_assert_idle_mpcc,
- .update_blend_mode = mpc10_update_blend_mode,
+ .insert_plane = mpc1_insert_plane,
+ .remove_mpcc = mpc1_remove_mpcc,
+ .mpc_init = mpc1_mpc_init,
+ .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
+ .wait_for_idle = mpc1_assert_idle_mpcc,
+ .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
+ .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
+ .update_blending = mpc1_update_blending,
};
void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
@@ -349,6 +427,8 @@
const struct dcn_mpc_mask *mpc_mask,
int num_mpcc)
{
+ int i;
+
mpc10->base.ctx = ctx;
mpc10->base.funcs = &dcn10_mpc_funcs;
@@ -359,5 +439,8 @@
mpc10->mpcc_in_use_mask = 0;
mpc10->num_mpcc = num_mpcc;
+
+ for (i = 0; i < MAX_MPCC; i++)
+ mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 683ce4a..267a299 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -30,9 +30,6 @@
#define TO_DCN10_MPC(mpc_base) \
container_of(mpc_base, struct dcn10_mpc, base)
-#define MAX_MPCC 6
-#define MAX_OPP 6
-
#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
SRII(MPCC_TOP_SEL, MPCC, inst),\
SRII(MPCC_BOT_SEL, MPCC, inst),\
@@ -42,7 +39,8 @@
SRII(MPCC_BG_G_Y, MPCC, inst),\
SRII(MPCC_BG_R_CR, MPCC, inst),\
SRII(MPCC_BG_B_CB, MPCC, inst),\
- SRII(MPCC_BG_B_CB, MPCC, inst)
+ SRII(MPCC_BG_B_CB, MPCC, inst),\
+ SRII(MPCC_SM_CONTROL, MPCC, inst)
#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
SRII(MUX, MPC_OUT, inst)
@@ -56,6 +54,7 @@
uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
+ uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
uint32_t MUX[MAX_OPP];
#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
@@ -65,12 +64,20 @@
SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
+ SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
+ SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
+ SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
+ SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
+ SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
+ SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
+ SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
+ SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh)
#define MPC_REG_FIELD_LIST(type) \
@@ -80,12 +87,20 @@
type MPCC_ALPHA_BLND_MODE;\
type MPCC_ALPHA_MULTIPLIED_MODE;\
type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
+ type MPCC_GLOBAL_ALPHA;\
+ type MPCC_GLOBAL_GAIN;\
type MPCC_IDLE;\
type MPCC_BUSY;\
type MPCC_OPP_ID;\
type MPCC_BG_G_Y;\
type MPCC_BG_R_CR;\
type MPCC_BG_B_CB;\
+ type MPCC_SM_EN;\
+ type MPCC_SM_MODE;\
+ type MPCC_SM_FRAME_ALT;\
+ type MPCC_SM_FIELD_ALT;\
+ type MPCC_SM_FORCE_NEXT_FRAME_POL;\
+ type MPCC_SM_FORCE_NEXT_TOP_POL;\
type MPC_OUT_MUX;
struct dcn_mpc_registers {
@@ -117,22 +132,55 @@
const struct dcn_mpc_mask *mpc_mask,
int num_mpcc);
-int mpc10_mpcc_add(
- struct mpc *mpc,
- struct mpcc_cfg *cfg);
+struct mpcc *mpc1_insert_plane(
+ struct mpc *mpc,
+ struct mpc_tree *tree,
+ struct mpcc_blnd_cfg *blnd_cfg,
+ struct mpcc_sm_cfg *sm_cfg,
+ struct mpcc *insert_above_mpcc,
+ int dpp_id,
+ int mpcc_id);
-void mpc10_mpcc_remove(
- struct mpc *mpc,
- struct mpc_tree_cfg *tree_cfg,
- int opp_id,
- int dpp_id);
+void mpc1_remove_mpcc(
+ struct mpc *mpc,
+ struct mpc_tree *tree,
+ struct mpcc *mpcc);
-void mpc10_assert_idle_mpcc(
- struct mpc *mpc,
- int id);
+void mpc1_mpc_init(
+ struct mpc *mpc);
-void mpc10_update_blend_mode(
- struct mpc *mpc,
- struct mpcc_cfg *cfg);
+void mpc1_assert_idle_mpcc(
+ struct mpc *mpc,
+ int id);
+
+void mpc1_set_bg_color(
+ struct mpc *mpc,
+ struct tg_color *bg_color,
+ int id);
+
+void mpc1_update_stereo_mix(
+ struct mpc *mpc,
+ struct mpcc_sm_cfg *sm_cfg,
+ int mpcc_id);
+
+bool mpc1_is_mpcc_idle(
+ struct mpc *mpc,
+ int mpcc_id);
+
+void mpc1_assert_mpcc_idle_before_connect(
+ struct mpc *mpc,
+ int mpcc_id);
+
+void mpc1_init_mpcc_list_from_hw(
+ struct mpc *mpc,
+ struct mpc_tree *tree);
+
+struct mpcc *mpc1_get_mpcc(
+ struct mpc *mpc,
+ int mpcc_id);
+
+struct mpcc *mpc1_get_mpcc_for_dpp(
+ struct mpc_tree *tree,
+ int dpp_id);
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index a136f70..f6ba0ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -38,7 +38,6 @@
oppn10->base.ctx
-
/************* FORMATTER ************/
/**
@@ -47,7 +46,7 @@
* 2) enable truncation
* 3) HW remove 12bit FMT support for DCE11 power saving reason.
*/
-static void set_truncation(
+static void opp1_set_truncation(
struct dcn10_opp *oppn10,
const struct bit_depth_reduction_params *params)
{
@@ -57,7 +56,7 @@
FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
}
-static void set_spatial_dither(
+static void opp1_set_spatial_dither(
struct dcn10_opp *oppn10,
const struct bit_depth_reduction_params *params)
{
@@ -136,14 +135,14 @@
FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
}
-static void oppn10_program_bit_depth_reduction(
+void opp1_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
- set_truncation(oppn10, params);
- set_spatial_dither(oppn10, params);
+ opp1_set_truncation(oppn10, params);
+ opp1_set_spatial_dither(oppn10, params);
/* TODO
* set_temporal_dither(oppn10, params);
*/
@@ -156,7 +155,7 @@
* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
* 1: YCbCr 4:2:2
*/
-static void set_pixel_encoding(
+static void opp1_set_pixel_encoding(
struct dcn10_opp *oppn10,
const struct clamping_and_pixel_encoding_params *params)
{
@@ -186,7 +185,7 @@
* 7 for programable
* 2) Enable clamp if Limited range requested
*/
-static void opp_set_clamping(
+static void opp1_set_clamping(
struct dcn10_opp *oppn10,
const struct clamping_and_pixel_encoding_params *params)
{
@@ -224,7 +223,7 @@
}
-static void oppn10_set_dyn_expansion(
+void opp1_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
@@ -264,17 +263,17 @@
}
}
-static void opp_program_clamping_and_pixel_encoding(
+static void opp1_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
- opp_set_clamping(oppn10, params);
- set_pixel_encoding(oppn10, params);
+ opp1_set_clamping(oppn10, params);
+ opp1_set_pixel_encoding(oppn10, params);
}
-static void oppn10_program_fmt(
+void opp1_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)
@@ -286,44 +285,104 @@
/* dithering is affected by <CrtcSourceSelect>, hence should be
* programmed afterwards */
- oppn10_program_bit_depth_reduction(
+ opp1_program_bit_depth_reduction(
opp,
fmt_bit_depth);
- opp_program_clamping_and_pixel_encoding(
+ opp1_program_clamping_and_pixel_encoding(
opp,
clamping);
return;
}
-
-
-static void oppn10_set_stereo_polarity(
- struct output_pixel_processor *opp,
- bool enable, bool rightEyePolarity)
+void opp1_program_stereo(
+ struct output_pixel_processor *opp,
+ bool enable,
+ const struct dc_crtc_timing *timing)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
- REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable);
+ uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;
+ uint32_t space1_size = timing->v_total - timing->v_addressable;
+ /* TODO: confirm computation of space2_size */
+ uint32_t space2_size = timing->v_total - timing->v_addressable;
+
+ if (!enable) {
+ active_width = 0;
+ space1_size = 0;
+ space2_size = 0;
+ }
+
+ /* TODO: for which cases should FMT_STEREOSYNC_OVERRIDE be set? */
+ REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
+
+ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);
+
+ /* Program OPPBUF_3D_VACT_SPACE1_SIZE and OPPBUF_VACT_SPACE2_SIZE registers
+ * In 3D progressive frames, Vactive space happens only in between the 2 frames,
+ * so only need to program OPPBUF_3D_VACT_SPACE1_SIZE
+ * In 3D alternative frames, left and right frames, top and bottom field.
+ */
+ if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE)
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);
+ else
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
+
+ /* TODO: Is programming of OPPBUF_DUMMY_DATA_R/G/B needed? */
+ /*
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
+ OPPBUF_DUMMY_DATA_R, data_r);
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
+ OPPBUF_DUMMY_DATA_G, data_g);
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
+ OPPBUF_DUMMY_DATA_B, _data_b);
+ */
+}
+
+void opp1_program_oppbuf(
+ struct output_pixel_processor *opp,
+ struct oppbuf_params *oppbuf)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ /* Program the oppbuf active width to be the frame width from mpc */
+ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width);
+
+ /* Specifies the number of segments in multi-segment mode (DP-MSO operation)
+ * description "In 1/2/4 segment mode, specifies the horizontal active width in pixels of the display panel.
+ * In 4 segment split left/right mode, specifies the horizontal 1/2 active width in pixels of the display panel.
+ * Used to determine segment boundaries in multi-segment mode. Used to determine the width of the vertical active space in 3D frame packed modes.
+ * OPPBUF_ACTIVE_WIDTH must be integer divisible by the total number of segments."
+ */
+ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation);
+
+ /* description "Specifies the number of overlap pixels (1-8 overlapping pixels supported), used in multi-segment mode (DP-MSO operation)" */
+ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num);
+
+ /* description "Specifies the number of times a pixel is replicated (0-15 pixel replications supported).
+ * A value of 0 disables replication. The total number of times a pixel is output is OPPBUF_PIXEL_REPETITION + 1."
+ */
+ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
+
}
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
-static void dcn10_opp_destroy(struct output_pixel_processor **opp)
+void opp1_destroy(struct output_pixel_processor **opp)
{
kfree(TO_DCN10_OPP(*opp));
*opp = NULL;
}
static struct opp_funcs dcn10_opp_funcs = {
- .opp_set_dyn_expansion = oppn10_set_dyn_expansion,
- .opp_program_fmt = oppn10_program_fmt,
- .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction,
- .opp_set_stereo_polarity = oppn10_set_stereo_polarity,
- .opp_destroy = dcn10_opp_destroy
+ .opp_set_dyn_expansion = opp1_set_dyn_expansion,
+ .opp_program_fmt = opp1_program_fmt,
+ .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
+ .opp_program_stereo = opp1_program_stereo,
+ .opp_destroy = opp1_destroy
};
void dcn10_opp_construct(struct dcn10_opp *oppn10,
@@ -333,19 +392,12 @@
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask)
{
- int i;
+
oppn10->base.ctx = ctx;
oppn10->base.inst = inst;
oppn10->base.funcs = &dcn10_opp_funcs;
- oppn10->base.mpc_tree.dpp[0] = inst;
- oppn10->base.mpc_tree.mpcc[0] = inst;
- oppn10->base.mpc_tree.num_pipes = 1;
- for (i = 0; i < MAX_PIPES; i++)
- oppn10->base.mpcc_disconnect_pending[i] = false;
-
oppn10->regs = regs;
oppn10->opp_shift = opp_shift;
oppn10->opp_mask = opp_mask;
}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index 790ce60..bc5058a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -41,11 +41,28 @@
SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
SRI(FMT_CLAMP_CNTL, FMT, id), \
SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
- SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id)
+ SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
+ SRI(OPPBUF_CONTROL, OPPBUF, id),\
+ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \
+ SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id)
#define OPP_REG_LIST_DCN10(id) \
OPP_REG_LIST_DCN(id)
+#define OPP_COMMON_REG_VARIABLE_LIST \
+ uint32_t FMT_BIT_DEPTH_CONTROL; \
+ uint32_t FMT_CONTROL; \
+ uint32_t FMT_DITHER_RAND_R_SEED; \
+ uint32_t FMT_DITHER_RAND_G_SEED; \
+ uint32_t FMT_DITHER_RAND_B_SEED; \
+ uint32_t FMT_CLAMP_CNTL; \
+ uint32_t FMT_DYNAMIC_EXP_CNTL; \
+ uint32_t FMT_MAP420_MEMORY_CONTROL; \
+ uint32_t OPPBUF_CONTROL; \
+ uint32_t OPPBUF_CONTROL1; \
+ uint32_t OPPBUF_3D_PARAMETERS_0; \
+ uint32_t OPPBUF_3D_PARAMETERS_1
+
#define OPP_MASK_SH_LIST_DCN(mask_sh) \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
@@ -68,46 +85,18 @@
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
- OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh)
+ OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \
+ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
+ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\
+ OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \
+ OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh)
#define OPP_MASK_SH_LIST_DCN10(mask_sh) \
- OPP_MASK_SH_LIST_DCN(mask_sh)
+ OPP_MASK_SH_LIST_DCN(mask_sh), \
+ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\
+ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh)
#define OPP_DCN10_REG_FIELD_LIST(type) \
- type DPG_EN; \
- type DPG_MODE; \
- type DPG_VRES; \
- type DPG_HRES; \
- type DPG_COLOUR0_R_CR; \
- type DPG_COLOUR1_R_CR; \
- type DPG_COLOUR0_B_CB; \
- type DPG_COLOUR1_B_CB; \
- type DPG_COLOUR0_G_Y; \
- type DPG_COLOUR1_G_Y; \
- type CM_OCSC_C11; \
- type CM_OCSC_C12; \
- type CM_OCSC_C13; \
- type CM_OCSC_C14; \
- type CM_OCSC_C21; \
- type CM_OCSC_C22; \
- type CM_OCSC_C23; \
- type CM_OCSC_C24; \
- type CM_OCSC_C31; \
- type CM_OCSC_C32; \
- type CM_OCSC_C33; \
- type CM_OCSC_C34; \
- type CM_COMB_C11; \
- type CM_COMB_C12; \
- type CM_COMB_C13; \
- type CM_COMB_C14; \
- type CM_COMB_C21; \
- type CM_COMB_C22; \
- type CM_COMB_C23; \
- type CM_COMB_C24; \
- type CM_COMB_C31; \
- type CM_COMB_C32; \
- type CM_COMB_C33; \
- type CM_COMB_C34; \
type FMT_TRUNCATE_EN; \
type FMT_TRUNCATE_DEPTH; \
type FMT_TRUNCATE_MODE; \
@@ -129,7 +118,18 @@
type FMT_DYNAMIC_EXP_EN; \
type FMT_DYNAMIC_EXP_MODE; \
type FMT_MAP420MEM_PWR_FORCE; \
- type FMT_STEREOSYNC_OVERRIDE
+ type FMT_STEREOSYNC_OVERRIDE; \
+ type OPPBUF_ACTIVE_WIDTH;\
+ type OPPBUF_PIXEL_REPETITION;\
+ type OPPBUF_DISPLAY_SEGMENTATION;\
+ type OPPBUF_OVERLAP_PIXEL_NUM;\
+ type OPPBUF_NUM_SEGMENT_PADDED_PIXELS; \
+ type OPPBUF_3D_VACT_SPACE1_SIZE; \
+ type OPPBUF_3D_VACT_SPACE2_SIZE
+
+struct dcn10_opp_registers {
+ OPP_COMMON_REG_VARIABLE_LIST;
+};
struct dcn10_opp_shift {
OPP_DCN10_REG_FIELD_LIST(uint8_t);
@@ -139,33 +139,6 @@
OPP_DCN10_REG_FIELD_LIST(uint32_t);
};
-struct dcn10_opp_registers {
- uint32_t DPG_CONTROL;
- uint32_t DPG_COLOUR_B_CB;
- uint32_t DPG_COLOUR_G_Y;
- uint32_t DPG_COLOUR_R_CR;
- uint32_t CM_OCSC_C11_C12;
- uint32_t CM_OCSC_C13_C14;
- uint32_t CM_OCSC_C21_C22;
- uint32_t CM_OCSC_C23_C24;
- uint32_t CM_OCSC_C31_C32;
- uint32_t CM_OCSC_C33_C34;
- uint32_t CM_COMB_C11_C12;
- uint32_t CM_COMB_C13_C14;
- uint32_t CM_COMB_C21_C22;
- uint32_t CM_COMB_C23_C24;
- uint32_t CM_COMB_C31_C32;
- uint32_t CM_COMB_C33_C34;
- uint32_t FMT_BIT_DEPTH_CONTROL;
- uint32_t FMT_CONTROL;
- uint32_t FMT_DITHER_RAND_R_SEED;
- uint32_t FMT_DITHER_RAND_G_SEED;
- uint32_t FMT_DITHER_RAND_B_SEED;
- uint32_t FMT_CLAMP_CNTL;
- uint32_t FMT_DYNAMIC_EXP_CNTL;
- uint32_t FMT_MAP420_MEMORY_CONTROL;
-};
-
struct dcn10_opp {
struct output_pixel_processor base;
@@ -183,4 +156,26 @@
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask);
+void opp1_set_dyn_expansion(
+ struct output_pixel_processor *opp,
+ enum dc_color_space color_sp,
+ enum dc_color_depth color_dpth,
+ enum signal_type signal);
+
+void opp1_program_fmt(
+ struct output_pixel_processor *opp,
+ struct bit_depth_reduction_params *fmt_bit_depth,
+ struct clamping_and_pixel_encoding_params *clamping);
+
+void opp1_program_bit_depth_reduction(
+ struct output_pixel_processor *opp,
+ const struct bit_depth_reduction_params *params);
+
+void opp1_program_stereo(
+ struct output_pixel_processor *opp,
+ bool enable,
+ const struct dc_crtc_timing *timing);
+
+void opp1_destroy(struct output_pixel_processor **opp);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
similarity index 72%
rename from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
rename to drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index fced178..4bf64d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -23,19 +23,20 @@
*
*/
+
#include "reg_helper.h"
-#include "dcn10_timing_generator.h"
+#include "dcn10_optc.h"
#include "dc.h"
#define REG(reg)\
- tgn10->tg_regs->reg
+ optc1->tg_regs->reg
#define CTX \
- tgn10->base.ctx
+ optc1->base.ctx
#undef FN
#define FN(reg_name, field_name) \
- tgn10->tg_shift->field_name, tgn10->tg_mask->field_name
+ optc1->tg_shift->field_name, optc1->tg_mask->field_name
#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
@@ -45,8 +46,8 @@
* This is a workaround for a bug that has existed since R5xx and has not been
* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
*/
-static void tgn10_apply_front_porch_workaround(
- struct timing_generator *tg,
+static void optc1_apply_front_porch_workaround(
+ struct timing_generator *optc,
struct dc_crtc_timing *timing)
{
if (timing->flags.INTERLACE == 1) {
@@ -58,30 +59,30 @@
}
}
-static void tgn10_program_global_sync(
- struct timing_generator *tg)
+void optc1_program_global_sync(
+ struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
- if (tg->dlg_otg_param.vstartup_start == 0) {
+ if (optc->dlg_otg_param.vstartup_start == 0) {
BREAK_TO_DEBUGGER();
return;
}
REG_SET(OTG_VSTARTUP_PARAM, 0,
- VSTARTUP_START, tg->dlg_otg_param.vstartup_start);
+ VSTARTUP_START, optc->dlg_otg_param.vstartup_start);
REG_SET_2(OTG_VUPDATE_PARAM, 0,
- VUPDATE_OFFSET, tg->dlg_otg_param.vupdate_offset,
- VUPDATE_WIDTH, tg->dlg_otg_param.vupdate_width);
+ VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset,
+ VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width);
REG_SET(OTG_VREADY_PARAM, 0,
- VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
+ VREADY_OFFSET, optc->dlg_otg_param.vready_offset);
}
-static void tgn10_disable_stereo(struct timing_generator *tg)
+static void optc1_disable_stereo(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_SET(OTG_STEREO_CONTROL, 0,
OTG_STEREO_EN, 0);
@@ -90,11 +91,6 @@
OTG_3D_STRUCTURE_EN, 0,
OTG_3D_STRUCTURE_V_UPDATE_MODE, 0,
OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
-
- REG_UPDATE(OPPBUF_CONTROL,
- OPPBUF_ACTIVE_WIDTH, 0);
- REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
- OPPBUF_3D_VACT_SPACE1_SIZE, 0);
}
/**
@@ -102,8 +98,8 @@
* Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
* Including SYNC. Call BIOS command table to program Timings.
*/
-static void tgn10_program_timing(
- struct timing_generator *tg,
+void optc1_program_timing(
+ struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing,
bool use_vbios)
{
@@ -121,10 +117,10 @@
uint32_t h_div_2;
int32_t vertical_line_start;
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
patched_crtc_timing = *dc_crtc_timing;
- tgn10_apply_front_porch_workaround(tg, &patched_crtc_timing);
+ optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
/* Load horizontal timing */
@@ -217,7 +213,7 @@
/* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
* program the reg for interrupt postition.
*/
- vertical_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1;
+ vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
if (vertical_line_start < 0) {
ASSERT(0);
vertical_line_start = 0;
@@ -233,26 +229,25 @@
OTG_V_SYNC_A_POL, v_sync_polarity);
v_init = asic_blank_start;
- if (tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
- tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
- tg->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
+ if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
+ optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
+ optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
start_point = 1;
if (patched_crtc_timing.flags.INTERLACE == 1)
field_num = 1;
}
v_fp2 = 0;
- if (tg->dlg_otg_param.vstartup_start > asic_blank_end)
- v_fp2 = tg->dlg_otg_param.vstartup_start > asic_blank_end;
+ if (optc->dlg_otg_param.vstartup_start > asic_blank_end)
+ v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end;
/* Interlace */
if (patched_crtc_timing.flags.INTERLACE == 1) {
REG_UPDATE(OTG_INTERLACE_CONTROL,
OTG_INTERLACE_ENABLE, 1);
v_init = v_init / 2;
- if ((tg->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
+ if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
v_fp2 = v_fp2 / 2;
- }
- else
+ } else
REG_UPDATE(OTG_INTERLACE_CONTROL,
OTG_INTERLACE_ENABLE, 0);
@@ -270,13 +265,13 @@
OTG_START_POINT_CNTL, start_point,
OTG_FIELD_NUMBER_CNTL, field_num);
- tgn10_program_global_sync(tg);
+ optc1_program_global_sync(optc);
/* TODO
* patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
* program_horz_count_by_2
* for DVI 30bpp mode, 0 otherwise
- * program_horz_count_by_2(tg, &patched_crtc_timing);
+ * program_horz_count_by_2(optc, &patched_crtc_timing);
*/
/* Enable stereo - only when we need to pack 3D frame. Other types
@@ -290,13 +285,23 @@
}
+static void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
+
+ REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+ OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
+}
+
/**
* unblank_crtc
* Call ASIC Control Object to UnBlank CRTC.
*/
-static void tgn10_unblank_crtc(struct timing_generator *tg)
+static void optc1_unblank_crtc(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t vertical_interrupt_enable = 0;
REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
@@ -306,8 +311,7 @@
* this check will be removed.
*/
if (vertical_interrupt_enable)
- REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
- OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 1);
+ optc1_set_blank_data_double_buffer(optc, true);
REG_UPDATE_2(OTG_BLANK_CONTROL,
OTG_BLANK_DATA_EN, 0,
@@ -319,37 +323,29 @@
* Call ASIC Control Object to Blank CRTC.
*/
-static void tgn10_blank_crtc(struct timing_generator *tg)
+static void optc1_blank_crtc(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_UPDATE_2(OTG_BLANK_CONTROL,
OTG_BLANK_DATA_EN, 1,
OTG_BLANK_DE_MODE, 0);
- /* todo: why are we waiting for BLANK_DATA_EN? shouldn't we be waiting
- * for status?
- */
- REG_WAIT(OTG_BLANK_CONTROL,
- OTG_BLANK_DATA_EN, 1,
- 1, 100000);
-
- REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
- OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
+ optc1_set_blank_data_double_buffer(optc, false);
}
-static void tgn10_set_blank(struct timing_generator *tg,
+void optc1_set_blank(struct timing_generator *optc,
bool enable_blanking)
{
if (enable_blanking)
- tgn10_blank_crtc(tg);
+ optc1_blank_crtc(optc);
else
- tgn10_unblank_crtc(tg);
+ optc1_unblank_crtc(optc);
}
-static bool tgn10_is_blanked(struct timing_generator *tg)
+bool optc1_is_blanked(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t blank_en;
uint32_t blank_state;
@@ -360,9 +356,9 @@
return blank_en && blank_state;
}
-static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
+void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
if (enable) {
REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
@@ -385,19 +381,9 @@
OTG_CLOCK_GATE_DIS, 0,
OTG_CLOCK_EN, 0);
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_CLOCK_CONTROL,
- OTG_CLOCK_ON, 0,
- 1, 1000);
-
REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
OPTC_INPUT_CLK_GATE_DIS, 0,
OPTC_INPUT_CLK_EN, 0);
-
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
- OPTC_INPUT_CLK_ON, 0,
- 1, 1000);
}
}
@@ -405,19 +391,19 @@
* Enable CRTC
* Enable CRTC - call ASIC Control Object to enable Timing generator.
*/
-static bool tgn10_enable_crtc(struct timing_generator *tg)
+static bool optc1_enable_crtc(struct timing_generator *optc)
{
/* TODO FPGA wait for answer
* OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
* OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
*/
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
/* opp instance for OTG. For DCN1.0, ODM is remoed.
* OPP and OPTC should 1:1 mapping
*/
REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
- OPTC_SRC_SEL, tg->inst);
+ OPTC_SRC_SEL, optc->inst);
/* VTG enable first is for HW workaround */
REG_UPDATE(CONTROL,
@@ -432,9 +418,9 @@
}
/* disable_crtc - call ASIC Control Object to disable Timing generator. */
-static bool tgn10_disable_crtc(struct timing_generator *tg)
+bool optc1_disable_crtc(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
/* disable otg request until end of the first line
* in the vertical blank region
@@ -455,11 +441,11 @@
}
-static void tgn10_program_blank_color(
- struct timing_generator *tg,
+void optc1_program_blank_color(
+ struct timing_generator *optc,
const struct tg_color *black_color)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_SET_3(OTG_BLACK_COLOR, 0,
OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
@@ -467,15 +453,15 @@
OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
}
-static bool tgn10_validate_timing(
- struct timing_generator *tg,
+bool optc1_validate_timing(
+ struct timing_generator *optc,
const struct dc_crtc_timing *timing)
{
uint32_t interlace_factor;
uint32_t v_blank;
uint32_t h_blank;
uint32_t min_v_blank;
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
ASSERT(timing != NULL);
@@ -505,19 +491,19 @@
* needs more than 8192 horizontal and
* more than 8192 vertical total pixels)
*/
- if (timing->h_total > tgn10->max_h_total ||
- timing->v_total > tgn10->max_v_total)
+ if (timing->h_total > optc1->max_h_total ||
+ timing->v_total > optc1->max_v_total)
return false;
- if (h_blank < tgn10->min_h_blank)
+ if (h_blank < optc1->min_h_blank)
return false;
- if (timing->h_sync_width < tgn10->min_h_sync_width ||
- timing->v_sync_width < tgn10->min_v_sync_width)
+ if (timing->h_sync_width < optc1->min_h_sync_width ||
+ timing->v_sync_width < optc1->min_v_sync_width)
return false;
- min_v_blank = timing->flags.INTERLACE?tgn10->min_v_blank_interlace:tgn10->min_v_blank;
+ min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
if (v_blank < min_v_blank)
return false;
@@ -534,15 +520,15 @@
* holds the counter of frames.
*
* @param
- * struct timing_generator *tg - [in] timing generator which controls the
+ * struct timing_generator *optc - [in] timing generator which controls the
* desired CRTC
*
* @return
* Counter of frames, which should equal to number of vblanks.
*/
-static uint32_t tgn10_get_vblank_counter(struct timing_generator *tg)
+uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t frame_count;
REG_GET(OTG_STATUS_FRAME_COUNT,
@@ -551,38 +537,34 @@
return frame_count;
}
-static void tgn10_lock(struct timing_generator *tg)
+void optc1_lock(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_SET(OTG_GLOBAL_CONTROL0, 0,
- OTG_MASTER_UPDATE_LOCK_SEL, tg->inst);
+ OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+ /* Should be fast, status does not update on maximus */
+ if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
- 1, 100);
+ 1, 10);
}
-static void tgn10_unlock(struct timing_generator *tg)
+void optc1_unlock(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 0);
-
- /* why are we waiting here? */
- REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL,
- OTG_UPDATE_PENDING, 0,
- 1, 100000);
}
-static void tgn10_get_position(struct timing_generator *tg,
+void optc1_get_position(struct timing_generator *optc,
struct crtc_position *position)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_GET_2(OTG_STATUS_POSITION,
OTG_HORZ_COUNT, &position->horizontal_count,
@@ -592,12 +574,12 @@
OTG_VERT_COUNT_NOM, &position->nominal_vcount);
}
-static bool tgn10_is_counter_moving(struct timing_generator *tg)
+bool optc1_is_counter_moving(struct timing_generator *optc)
{
struct crtc_position position1, position2;
- tg->funcs->get_position(tg, &position1);
- tg->funcs->get_position(tg, &position2);
+ optc->funcs->get_position(optc, &position1);
+ optc->funcs->get_position(optc, &position2);
if (position1.horizontal_count == position2.horizontal_count &&
position1.vertical_count == position2.vertical_count)
@@ -606,21 +588,37 @@
return true;
}
-static bool tgn10_did_triggered_reset_occur(
- struct timing_generator *tg)
+bool optc1_did_triggered_reset_occur(
+ struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
- uint32_t occurred;
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t occurred_force, occurred_vsync;
REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
- OTG_FORCE_COUNT_NOW_OCCURRED, &occurred);
+ OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
- return occurred != 0;
+ REG_GET(OTG_VERT_SYNC_CONTROL,
+ OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
+
+ return occurred_vsync != 0 || occurred_force != 0;
}
-static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst)
+void optc1_disable_reset_trigger(struct timing_generator *optc)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_WRITE(OTG_TRIGA_CNTL, 0);
+
+ REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+ OTG_FORCE_COUNT_NOW_CLEAR, 1);
+
+ REG_SET(OTG_VERT_SYNC_CONTROL, 0,
+ OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
+}
+
+void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t falling_edge;
REG_GET(OTG_V_SYNC_A_CNTL,
@@ -652,20 +650,55 @@
OTG_FORCE_COUNT_NOW_MODE, 2);
}
-static void tgn10_disable_reset_trigger(struct timing_generator *tg)
+void optc1_enable_crtc_reset(
+ struct timing_generator *optc,
+ int source_tg_inst,
+ struct crtc_trigger_info *crtc_tp)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t falling_edge = 0;
+ uint32_t rising_edge = 0;
- REG_WRITE(OTG_TRIGA_CNTL, 0);
+ switch (crtc_tp->event) {
- REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
- OTG_FORCE_COUNT_NOW_CLEAR, 1);
+ case CRTC_EVENT_VSYNC_RISING:
+ rising_edge = 1;
+ break;
+
+ case CRTC_EVENT_VSYNC_FALLING:
+ falling_edge = 1;
+ break;
+ }
+
+ REG_SET_4(OTG_TRIGA_CNTL, 0,
+ /* vsync signal from selected OTG pipe based
+ * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+ */
+ OTG_TRIGA_SOURCE_SELECT, 20,
+ OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+ /* always detect falling edge */
+ OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
+ OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
+
+ switch (crtc_tp->delay) {
+ case TRIGGER_DELAY_NEXT_LINE:
+ REG_SET(OTG_VERT_SYNC_CONTROL, 0,
+ OTG_AUTO_FORCE_VSYNC_MODE, 1);
+ break;
+ case TRIGGER_DELAY_NEXT_PIXEL:
+ REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+ /* force H count to H_TOTAL and V count to V_TOTAL in
+ * progressive mode and V_TOTAL-1 in interlaced mode
+ */
+ OTG_FORCE_COUNT_NOW_MODE, 2);
+ break;
+ }
}
-static void tgn10_wait_for_state(struct timing_generator *tg,
+void optc1_wait_for_state(struct timing_generator *optc,
enum crtc_state state)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
switch (state) {
case CRTC_STATE_VBLANK:
@@ -685,8 +718,8 @@
}
}
-static void tgn10_set_early_control(
- struct timing_generator *tg,
+void optc1_set_early_control(
+ struct timing_generator *optc,
uint32_t early_cntl)
{
/* asic design change, do not need this control
@@ -695,11 +728,11 @@
}
-static void tgn10_set_static_screen_control(
- struct timing_generator *tg,
+void optc1_set_static_screen_control(
+ struct timing_generator *optc,
uint32_t value)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
/* Bit 8 is no longer applicable in RV for PSR case,
* set bit 8 to 0 if given
@@ -724,11 +757,11 @@
*
*****************************************************************************
*/
-static void tgn10_set_drr(
- struct timing_generator *tg,
+void optc1_set_drr(
+ struct timing_generator *optc,
const struct drr_params *params)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
if (params != NULL &&
params->vertical_total_max > 0 &&
@@ -761,15 +794,15 @@
}
}
-static void tgn10_set_test_pattern(
- struct timing_generator *tg,
+static void optc1_set_test_pattern(
+ struct timing_generator *optc,
/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
* because this is not DP-specific (which is probably somewhere in DP
* encoder) */
enum controller_dp_test_pattern test_pattern,
enum dc_color_depth color_depth)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
enum test_pattern_color_format bit_depth;
enum test_pattern_dyn_range dyn_range;
enum test_pattern_mode mode;
@@ -1020,35 +1053,30 @@
}
}
-static void tgn10_get_crtc_scanoutpos(
- struct timing_generator *tg,
+void optc1_get_crtc_scanoutpos(
+ struct timing_generator *optc,
uint32_t *v_blank_start,
uint32_t *v_blank_end,
uint32_t *h_position,
uint32_t *v_position)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
struct crtc_position position;
REG_GET_2(OTG_V_BLANK_START_END,
OTG_V_BLANK_START, v_blank_start,
OTG_V_BLANK_END, v_blank_end);
- tgn10_get_position(tg, &position);
+ optc1_get_position(optc, &position);
*h_position = position.horizontal_count;
*v_position = position.vertical_count;
}
-
-
-static void tgn10_enable_stereo(struct timing_generator *tg,
+static void optc1_enable_stereo(struct timing_generator *optc,
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
{
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-
- uint32_t active_width = timing->h_addressable;
- uint32_t space1_size = timing->v_total - timing->v_addressable;
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
if (flags) {
uint32_t stereo_en;
@@ -1076,29 +1104,23 @@
OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
}
-
- REG_UPDATE(OPPBUF_CONTROL,
- OPPBUF_ACTIVE_WIDTH, active_width);
-
- REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
- OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
}
-static void tgn10_program_stereo(struct timing_generator *tg,
+void optc1_program_stereo(struct timing_generator *optc,
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
{
if (flags->PROGRAM_STEREO)
- tgn10_enable_stereo(tg, timing, flags);
+ optc1_enable_stereo(optc, timing, flags);
else
- tgn10_disable_stereo(tg);
+ optc1_disable_stereo(optc);
}
-static bool tgn10_is_stereo_left_eye(struct timing_generator *tg)
+bool optc1_is_stereo_left_eye(struct timing_generator *optc)
{
bool ret = false;
uint32_t left_eye = 0;
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_GET(OTG_STEREO_STATUS,
OTG_STEREO_CURRENT_EYE, &left_eye);
@@ -1110,7 +1132,7 @@
return ret;
}
-void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
+void optc1_read_otg_state(struct optc *optc1,
struct dcn_otg_state *s)
{
REG_GET(OTG_CONTROL,
@@ -1154,47 +1176,88 @@
OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
}
+static void optc1_clear_optc_underflow(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
+}
+
+static void optc1_tg_init(struct timing_generator *optc)
+{
+ optc1_set_blank_data_double_buffer(optc, true);
+ optc1_clear_optc_underflow(optc);
+}
+
+static bool optc1_is_tg_enabled(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t otg_enabled = 0;
+
+ REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
+
+ return (otg_enabled != 0);
+
+}
+
+static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t underflow_occurred = 0;
+
+ REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
+ OPTC_UNDERFLOW_OCCURRED_STATUS,
+ &underflow_occurred);
+
+ return (underflow_occurred == 1);
+}
static const struct timing_generator_funcs dcn10_tg_funcs = {
- .validate_timing = tgn10_validate_timing,
- .program_timing = tgn10_program_timing,
- .program_global_sync = tgn10_program_global_sync,
- .enable_crtc = tgn10_enable_crtc,
- .disable_crtc = tgn10_disable_crtc,
+ .validate_timing = optc1_validate_timing,
+ .program_timing = optc1_program_timing,
+ .program_global_sync = optc1_program_global_sync,
+ .enable_crtc = optc1_enable_crtc,
+ .disable_crtc = optc1_disable_crtc,
/* used by enable_timing_synchronization. Not need for FPGA */
- .is_counter_moving = tgn10_is_counter_moving,
- .get_position = tgn10_get_position,
- .get_frame_count = tgn10_get_vblank_counter,
- .get_scanoutpos = tgn10_get_crtc_scanoutpos,
- .set_early_control = tgn10_set_early_control,
+ .is_counter_moving = optc1_is_counter_moving,
+ .get_position = optc1_get_position,
+ .get_frame_count = optc1_get_vblank_counter,
+ .get_scanoutpos = optc1_get_crtc_scanoutpos,
+ .set_early_control = optc1_set_early_control,
/* used by enable_timing_synchronization. Not need for FPGA */
- .wait_for_state = tgn10_wait_for_state,
- .set_blank = tgn10_set_blank,
- .is_blanked = tgn10_is_blanked,
- .set_blank_color = tgn10_program_blank_color,
- .did_triggered_reset_occur = tgn10_did_triggered_reset_occur,
- .enable_reset_trigger = tgn10_enable_reset_trigger,
- .disable_reset_trigger = tgn10_disable_reset_trigger,
- .lock = tgn10_lock,
- .unlock = tgn10_unlock,
- .enable_optc_clock = tgn10_enable_optc_clock,
- .set_drr = tgn10_set_drr,
- .set_static_screen_control = tgn10_set_static_screen_control,
- .set_test_pattern = tgn10_set_test_pattern,
- .program_stereo = tgn10_program_stereo,
- .is_stereo_left_eye = tgn10_is_stereo_left_eye
+ .wait_for_state = optc1_wait_for_state,
+ .set_blank = optc1_set_blank,
+ .is_blanked = optc1_is_blanked,
+ .set_blank_color = optc1_program_blank_color,
+ .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+ .enable_reset_trigger = optc1_enable_reset_trigger,
+ .enable_crtc_reset = optc1_enable_crtc_reset,
+ .disable_reset_trigger = optc1_disable_reset_trigger,
+ .lock = optc1_lock,
+ .unlock = optc1_unlock,
+ .enable_optc_clock = optc1_enable_optc_clock,
+ .set_drr = optc1_set_drr,
+ .set_static_screen_control = optc1_set_static_screen_control,
+ .set_test_pattern = optc1_set_test_pattern,
+ .program_stereo = optc1_program_stereo,
+ .is_stereo_left_eye = optc1_is_stereo_left_eye,
+ .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
+ .tg_init = optc1_tg_init,
+ .is_tg_enabled = optc1_is_tg_enabled,
+ .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+ .clear_optc_underflow = optc1_clear_optc_underflow,
};
-void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
+void dcn10_timing_generator_init(struct optc *optc1)
{
- tgn10->base.funcs = &dcn10_tg_funcs;
+ optc1->base.funcs = &dcn10_tg_funcs;
- tgn10->max_h_total = tgn10->tg_mask->OTG_H_TOTAL + 1;
- tgn10->max_v_total = tgn10->tg_mask->OTG_V_TOTAL + 1;
+ optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+ optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
- tgn10->min_h_blank = 32;
- tgn10->min_v_blank = 3;
- tgn10->min_v_blank_interlace = 5;
- tgn10->min_h_sync_width = 8;
- tgn10->min_v_sync_width = 1;
+ optc1->min_h_blank = 32;
+ optc1->min_v_blank = 3;
+ optc1->min_v_blank_interlace = 5;
+ optc1->min_h_sync_width = 8;
+ optc1->min_v_sync_width = 1;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
similarity index 76%
rename from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
rename to drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 7d4818d..a3c7c20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -29,7 +29,7 @@
#include "timing_generator.h"
#define DCN10TG_FROM_TG(tg)\
- container_of(tg, struct dcn10_timing_generator, base)
+ container_of(tg, struct optc, base)
#define TG_COMMON_REG_LIST_DCN(inst) \
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
@@ -70,9 +70,10 @@
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
- SRI(OPPBUF_CONTROL, OPPBUF, inst),\
- SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\
- SRI(CONTROL, VTG, inst)
+ SRI(CONTROL, VTG, inst),\
+ SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+ SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
+ SRI(OTG_GSL_CONTROL, OTG, inst)
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
TG_COMMON_REG_LIST_DCN(inst),\
@@ -81,7 +82,10 @@
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
-struct dcn_tg_registers {
+struct dcn_optc_registers {
+ uint32_t OTG_VERT_SYNC_CONTROL;
+ uint32_t OTG_MASTER_UPDATE_MODE;
+ uint32_t OTG_GSL_CONTROL;
uint32_t OTG_VSTARTUP_PARAM;
uint32_t OTG_VUPDATE_PARAM;
uint32_t OTG_VREADY_PARAM;
@@ -123,9 +127,11 @@
uint32_t OPTC_INPUT_CLOCK_CONTROL;
uint32_t OPTC_DATA_SOURCE_SELECT;
uint32_t OPTC_INPUT_GLOBAL_CONTROL;
- uint32_t OPPBUF_CONTROL;
- uint32_t OPPBUF_3D_PARAMETERS_0;
uint32_t CONTROL;
+ uint32_t OTG_GSL_WINDOW_X;
+ uint32_t OTG_GSL_WINDOW_Y;
+ uint32_t OTG_VUPDATE_KEEPOUT;
+ uint32_t OTG_DSC_START_POSITION;
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -204,11 +210,21 @@
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
- SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
- SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
+ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
- SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh)
+ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+ SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+ SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+ SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+ SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
+ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh)
+
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
@@ -313,26 +329,48 @@
type OPTC_SRC_SEL;\
type OPTC_SEG0_SRC_SEL;\
type OPTC_UNDERFLOW_OCCURRED_STATUS;\
- type OPPBUF_ACTIVE_WIDTH;\
- type OPPBUF_3D_VACT_SPACE1_SIZE;\
+ type OPTC_UNDERFLOW_CLEAR;\
type VTG0_ENABLE;\
type VTG0_FP2;\
- type VTG0_VCOUNT_INIT;
+ type VTG0_VCOUNT_INIT;\
+ type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
+ type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
+ type OTG_AUTO_FORCE_VSYNC_MODE;\
+ type MASTER_UPDATE_INTERLACED_MODE;\
+ type OTG_GSL0_EN;\
+ type OTG_GSL1_EN;\
+ type OTG_GSL2_EN;\
+ type OTG_GSL_MASTER_EN;\
+ type OTG_GSL_FORCE_DELAY;\
+ type OTG_GSL_CHECK_ALL_FIELDS;\
+ type OTG_GSL_WINDOW_START_X;\
+ type OTG_GSL_WINDOW_END_X;\
+ type OTG_GSL_WINDOW_START_Y;\
+ type OTG_GSL_WINDOW_END_Y;\
+ type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\
+ type OTG_GSL_MASTER_MODE;\
+ type OTG_MASTER_UPDATE_LOCK_GSL_EN;\
+ type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\
+ type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\
+ type OTG_DSC_START_POSITION_X;\
+ type OTG_DSC_START_POSITION_LINE_NUM;\
+ type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;
-struct dcn_tg_shift {
+
+struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
};
-struct dcn_tg_mask {
+struct dcn_optc_mask {
TG_REG_FIELD_LIST(uint32_t)
};
-struct dcn10_timing_generator {
+struct optc {
struct timing_generator base;
- const struct dcn_tg_registers *tg_regs;
- const struct dcn_tg_shift *tg_shift;
- const struct dcn_tg_mask *tg_mask;
+ const struct dcn_optc_registers *tg_regs;
+ const struct dcn_optc_shift *tg_shift;
+ const struct dcn_optc_mask *tg_mask;
enum controller_id controller_id;
@@ -347,7 +385,7 @@
uint32_t min_v_blank_interlace;
};
-void dcn10_timing_generator_init(struct dcn10_timing_generator *tg);
+void dcn10_timing_generator_init(struct optc *optc);
struct dcn_otg_state {
uint32_t v_blank_start;
@@ -368,7 +406,77 @@
uint32_t otg_enabled;
};
-void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
+void optc1_read_otg_state(struct optc *optc1,
struct dcn_otg_state *s);
+bool optc1_validate_timing(
+ struct timing_generator *optc,
+ const struct dc_crtc_timing *timing);
+
+void optc1_program_timing(
+ struct timing_generator *optc,
+ const struct dc_crtc_timing *dc_crtc_timing,
+ bool use_vbios);
+
+void optc1_program_global_sync(
+ struct timing_generator *optc);
+
+bool optc1_disable_crtc(struct timing_generator *optc);
+
+bool optc1_is_counter_moving(struct timing_generator *optc);
+
+void optc1_get_position(struct timing_generator *optc,
+ struct crtc_position *position);
+
+uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
+
+void optc1_get_crtc_scanoutpos(
+ struct timing_generator *optc,
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position);
+
+void optc1_set_early_control(
+ struct timing_generator *optc,
+ uint32_t early_cntl);
+
+void optc1_wait_for_state(struct timing_generator *optc,
+ enum crtc_state state);
+
+void optc1_set_blank(struct timing_generator *optc,
+ bool enable_blanking);
+
+bool optc1_is_blanked(struct timing_generator *optc);
+
+void optc1_program_blank_color(
+ struct timing_generator *optc,
+ const struct tg_color *black_color);
+
+bool optc1_did_triggered_reset_occur(
+ struct timing_generator *optc);
+
+void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
+
+void optc1_disable_reset_trigger(struct timing_generator *optc);
+
+void optc1_lock(struct timing_generator *optc);
+
+void optc1_unlock(struct timing_generator *optc);
+
+void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
+
+void optc1_set_drr(
+ struct timing_generator *optc,
+ const struct drr_params *params);
+
+void optc1_set_static_screen_control(
+ struct timing_generator *optc,
+ uint32_t value);
+
+void optc1_program_stereo(struct timing_generator *optc,
+ const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
+
+bool optc1_is_stereo_left_eye(struct timing_generator *optc);
+
#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 9fc8f82..44825e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -34,7 +34,7 @@
#include "dcn10/dcn10_mpc.h"
#include "irq/dcn10/irq_service_dcn10.h"
#include "dcn10/dcn10_dpp.h"
-#include "dcn10/dcn10_timing_generator.h"
+#include "dcn10_optc.h"
#include "dcn10/dcn10_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
#include "dcn10/dcn10_opp.h"
@@ -48,16 +48,17 @@
#include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h"
#include "dcn10_hubp.h"
+#include "dcn10_hubbub.h"
-#include "vega10/soc15ip.h"
+#include "soc15ip.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
-#include "raven1/NBIO/nbio_7_0_offset.h"
+#include "nbio/nbio_7_0_offset.h"
-#include "raven1/MMHUB/mmhub_9_1_offset.h"
-#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
+#include "mmhub/mmhub_9_1_offset.h"
+#include "mmhub/mmhub_9_1_sh_mask.h"
#include "reg_helper.h"
#include "dce/dce_abm.h"
@@ -347,18 +348,18 @@
#define tg_regs(id)\
[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
-static const struct dcn_tg_registers tg_regs[] = {
+static const struct dcn_optc_registers tg_regs[] = {
tg_regs(0),
tg_regs(1),
tg_regs(2),
tg_regs(3),
};
-static const struct dcn_tg_shift tg_shift = {
+static const struct dcn_optc_shift tg_shift = {
TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
};
-static const struct dcn_tg_mask tg_mask = {
+static const struct dcn_optc_mask tg_mask = {
TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
};
@@ -367,25 +368,38 @@
NBIO_SR(BIOS_SCRATCH_6)
};
-#define mi_regs(id)\
+#define hubp_regs(id)\
[id] = {\
- MI_REG_LIST_DCN10(id)\
+ HUBP_REG_LIST_DCN10(id)\
}
-static const struct dcn_mi_registers mi_regs[] = {
- mi_regs(0),
- mi_regs(1),
- mi_regs(2),
- mi_regs(3),
+static const struct dcn_mi_registers hubp_regs[] = {
+ hubp_regs(0),
+ hubp_regs(1),
+ hubp_regs(2),
+ hubp_regs(3),
};
-static const struct dcn_mi_shift mi_shift = {
- MI_MASK_SH_LIST_DCN10(__SHIFT)
+static const struct dcn_mi_shift hubp_shift = {
+ HUBP_MASK_SH_LIST_DCN10(__SHIFT)
};
-static const struct dcn_mi_mask mi_mask = {
- MI_MASK_SH_LIST_DCN10(_MASK)
+static const struct dcn_mi_mask hubp_mask = {
+ HUBP_MASK_SH_LIST_DCN10(_MASK)
+};
+
+
+static const struct dcn_hubbub_registers hubbub_reg = {
+ HUBBUB_REG_LIST_DCN10(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+ HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+ HUBBUB_MASK_SH_LIST_DCN10(_MASK)
};
#define clk_src_regs(index, pllid)\
@@ -519,12 +533,28 @@
return &mpc10->base;
}
+static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
+{
+ struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
+ GFP_KERNEL);
+
+ if (!hubbub)
+ return NULL;
+
+ hubbub1_construct(hubbub, ctx,
+ &hubbub_reg,
+ &hubbub_shift,
+ &hubbub_mask);
+
+ return hubbub;
+}
+
static struct timing_generator *dcn10_timing_generator_create(
struct dc_context *ctx,
uint32_t instance)
{
- struct dcn10_timing_generator *tgn10 =
- kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL);
+ struct optc *tgn10 =
+ kzalloc(sizeof(struct optc), GFP_KERNEL);
if (!tgn10)
return NULL;
@@ -647,6 +677,8 @@
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
+ hws->wa.DEGVIDCN10_253 = true;
+ hws->wa.false_optc_underflow = true;
}
return hws;
}
@@ -700,6 +732,12 @@
kfree(TO_DCN10_MPC(pool->base.mpc));
pool->base.mpc = NULL;
}
+
+ if (pool->base.hubbub != NULL) {
+ kfree(pool->base.hubbub);
+ pool->base.hubbub = NULL;
+ }
+
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
@@ -768,7 +806,7 @@
return NULL;
dcn10_hubp_construct(hubp1, ctx, inst,
- &mi_regs[inst], &mi_shift, &mi_mask);
+ &hubp_regs[inst], &hubp_shift, &hubp_mask);
return &hubp1->base;
}
@@ -1233,8 +1271,8 @@
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 256;
-
dc->caps.max_slave_planes = 1;
+ dc->caps.is_apu = true;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
@@ -1274,7 +1312,7 @@
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
- goto clock_source_create_fail;
+ goto fail;
}
}
@@ -1283,7 +1321,7 @@
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
- goto disp_clk_create_fail;
+ goto fail;
}
}
@@ -1294,7 +1332,7 @@
if (pool->base.dmcu == NULL) {
dm_error("DC: failed to create dmcu!\n");
BREAK_TO_DEBUGGER();
- goto res_create_fail;
+ goto fail;
}
pool->base.abm = dce_abm_create(ctx,
@@ -1304,7 +1342,7 @@
if (pool->base.abm == NULL) {
dm_error("DC: failed to create abm!\n");
BREAK_TO_DEBUGGER();
- goto res_create_fail;
+ goto fail;
}
dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
@@ -1344,13 +1382,11 @@
}
{
- #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
if (!pool->base.irqs)
- goto irqs_create_fail;
- #endif
+ goto fail;
}
/* index to valid pipe resource */
@@ -1368,7 +1404,7 @@
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create memory input!\n");
- goto mi_create_fail;
+ goto fail;
}
pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
@@ -1376,7 +1412,7 @@
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create input pixel processor!\n");
- goto ipp_create_fail;
+ goto fail;
}
pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
@@ -1384,7 +1420,7 @@
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create dpp!\n");
- goto dpp_create_fail;
+ goto fail;
}
pool->base.opps[j] = dcn10_opp_create(ctx, i);
@@ -1392,7 +1428,7 @@
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create output pixel processor!\n");
- goto opp_create_fail;
+ goto fail;
}
pool->base.timing_generators[j] = dcn10_timing_generator_create(
@@ -1400,8 +1436,9 @@
if (pool->base.timing_generators[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create tg!\n");
- goto otg_create_fail;
+ goto fail;
}
+
/* check next valid pipe */
j++;
}
@@ -1419,13 +1456,20 @@
if (pool->base.mpc == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create mpc!\n");
- goto mpc_create_fail;
+ goto fail;
+ }
+
+ pool->base.hubbub = dcn10_hubbub_create(ctx);
+ if (pool->base.hubbub == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create hubbub!\n");
+ goto fail;
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
- goto res_create_fail;
+ goto fail;
dcn10_hw_sequencer_construct(dc);
dc->caps.max_planes = pool->base.pipe_count;
@@ -1434,16 +1478,7 @@
return true;
-disp_clk_create_fail:
-mpc_create_fail:
-otg_create_fail:
-opp_create_fail:
-dpp_create_fail:
-ipp_create_fail:
-mi_create_fail:
-irqs_create_fail:
-res_create_fail:
-clock_source_create_fail:
+fail:
destruct(pool);
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index d491703..225b7bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -373,6 +373,13 @@
unsigned long long dm_get_timestamp(struct dc_context *ctx);
/*
+ * performance tracing
+ */
+void dm_perf_trace_timestamp(const char *func_name, unsigned int line);
+#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__)
+
+
+/*
* Debug and verification hooks
*/
bool dm_helpers_dc_conn_log(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 4c31fa5..c109b2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -35,35 +35,6 @@
soc->writeback_latency_us = 12.0;
soc->ideal_dram_bw_after_urgent_percent = 80.0;
soc->max_request_size_bytes = 256;
-
- soc->vmin.dcfclk_mhz = 300.0;
- soc->vmin.dispclk_mhz = 608.0;
- soc->vmin.dppclk_mhz = 435.0;
- soc->vmin.dram_bw_per_chan_gbps = 12.8;
- soc->vmin.phyclk_mhz = 540.0;
- soc->vmin.socclk_mhz = 208.0;
-
- soc->vmid.dcfclk_mhz = 600.0;
- soc->vmid.dispclk_mhz = 661.0;
- soc->vmid.dppclk_mhz = 661.0;
- soc->vmid.dram_bw_per_chan_gbps = 12.8;
- soc->vmid.phyclk_mhz = 540.0;
- soc->vmid.socclk_mhz = 208.0;
-
- soc->vnom.dcfclk_mhz = 600.0;
- soc->vnom.dispclk_mhz = 661.0;
- soc->vnom.dppclk_mhz = 661.0;
- soc->vnom.dram_bw_per_chan_gbps = 38.4;
- soc->vnom.phyclk_mhz = 810;
- soc->vnom.socclk_mhz = 208.0;
-
- soc->vmax.dcfclk_mhz = 600.0;
- soc->vmax.dispclk_mhz = 1086.0;
- soc->vmax.dppclk_mhz = 661.0;
- soc->vmax.dram_bw_per_chan_gbps = 38.4;
- soc->vmax.phyclk_mhz = 810.0;
- soc->vmax.socclk_mhz = 208.0;
-
soc->downspread_percent = 0.5;
soc->dram_page_open_time_ns = 50.0;
soc->dram_rw_turnaround_time_ns = 17.5;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index baf1821..aeebd8b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -79,10 +79,6 @@
double writeback_latency_us;
double ideal_dram_bw_after_urgent_percent;
unsigned int max_request_size_bytes;
- struct _vcs_dpi_voltage_scaling_st vmin;
- struct _vcs_dpi_voltage_scaling_st vmid;
- struct _vcs_dpi_voltage_scaling_st vnom;
- struct _vcs_dpi_voltage_scaling_st vmax;
double downspread_percent;
double dram_page_open_time_ns;
double dram_rw_turnaround_time_ns;
@@ -229,7 +225,7 @@
int output_bpp;
int dsc_enable;
int wb_enable;
- int output_bpc;
+ int opp_input_bpc;
int output_type;
int output_format;
int output_standard;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index ea661ee..260e113f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -28,6 +28,17 @@
#include "dml_inline_defs.h"
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
static void fetch_socbb_params(struct display_mode_lib *mode_lib);
@@ -587,7 +598,7 @@
mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] =
dout->dsc_slices;
mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] =
- dout->output_bpc == 0 ? 12 : dout->output_bpc;
+ dout->opp_input_bpc == 0 ? 12 : dout->opp_input_bpc;
mode_lib->vba.WritebackEnable[mode_lib->vba.NumberOfActivePlanes] = dout->wb_enable;
mode_lib->vba.WritebackSourceHeight[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_src_height;
@@ -3928,7 +3939,7 @@
else if (DecimalBPP >= 12)
return 12;
else
- return 0;
+ return BPP_INVALID;
} else if (Format == dm_444) {
if (DecimalBPP >= 36)
return 36;
@@ -3937,7 +3948,7 @@
else if (DecimalBPP >= 24)
return 24;
else
- return 0;
+ return BPP_INVALID;
} else {
if (DecimalBPP / 1.5 >= 24)
return 24;
@@ -3946,27 +3957,27 @@
else if (DecimalBPP / 1.5 >= 16)
return 16;
else
- return 0;
+ return BPP_INVALID;
}
} else {
if (DSCEnabled) {
if (Format == dm_420) {
if (DecimalBPP < 6)
- return 0;
+ return BPP_INVALID;
else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16)
return 1.5 * DSCInputBitPerComponent - 1 / 16;
else
return dml_floor(16 * DecimalBPP, 1) / 16;
} else if (Format == dm_n422) {
if (DecimalBPP < 7)
- return 0;
+ return BPP_INVALID;
else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16)
return 2 * DSCInputBitPerComponent - 1 / 16;
else
return dml_floor(16 * DecimalBPP, 1) / 16;
} else {
if (DecimalBPP < 8)
- return 0;
+ return BPP_INVALID;
else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16)
return 3 * DSCInputBitPerComponent - 1 / 16;
else
@@ -3980,7 +3991,7 @@
else if (DecimalBPP >= 12)
return 12;
else
- return 0;
+ return BPP_INVALID;
} else if (Format == dm_s422 || Format == dm_n422) {
if (DecimalBPP >= 24)
return 24;
@@ -3989,7 +4000,7 @@
else if (DecimalBPP >= 16)
return 16;
else
- return 0;
+ return BPP_INVALID;
} else {
if (DecimalBPP >= 36)
return 36;
@@ -3998,7 +4009,7 @@
else if (DecimalBPP >= 24)
return 24;
else
- return 0;
+ return BPP_INVALID;
}
}
}
@@ -4922,11 +4933,7 @@
mode_lib->vba.ViewportSizeSupport[i] = true;
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == true) {
- if (dml_min(
- mode_lib->vba.SwathWidthYSingleDPP[k],
- dml_round(
- mode_lib->vba.HActive[k] / 2.0
- * mode_lib->vba.HRatio[k]))
+ if (dml_min(mode_lib->vba.SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
> mode_lib->vba.MaximumSwathWidth[k]) {
mode_lib->vba.ViewportSizeSupport[i] = false;
}
@@ -4980,12 +4987,8 @@
mode_lib->vba.RequiresDSC[i][k] = 0;
mode_lib->vba.RequiresFEC[i][k] = 0;
mode_lib->vba.OutputBppPerState[i][k] =
- TruncToValidBPP(
- dml_min(
- 600.0,
- mode_lib->vba.PHYCLKPerState[i])
- / mode_lib->vba.PixelClockBackEnd[k]
- * 24,
+ TruncToValidBPP(dml_min(600.0, mode_lib->vba.PHYCLKPerState[i])
+ / mode_lib->vba.PixelClockBackEnd[k] * 24,
false,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
@@ -5000,30 +5003,16 @@
}
if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
mode_lib->vba.Outbpp =
- TruncToValidBPP(
- (1.0
- - mode_lib->vba.Downspreading
- / 100.0)
- * 270.0
- * mode_lib->vba.OutputLinkDPLanes[k]
- / mode_lib->vba.PixelClockBackEnd[k]
- * 8.0,
+ TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0
+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
false,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
mode_lib->vba.DSCInputBitPerComponent[k]);
mode_lib->vba.OutbppDSC =
- TruncToValidBPP(
- (1.0
- - mode_lib->vba.Downspreading
- / 100.0)
- * (1.0
- - mode_lib->vba.EffectiveFECOverhead
- / 100.0)
- * 270.0
- * mode_lib->vba.OutputLinkDPLanes[k]
- / mode_lib->vba.PixelClockBackEnd[k]
- * 8.0,
+ TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0)
+ * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0
+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
true,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
@@ -5046,32 +5035,18 @@
mode_lib->vba.OutputBppPerState[i][k] =
mode_lib->vba.Outbpp;
}
- if (mode_lib->vba.Outbpp == 0) {
+ if (mode_lib->vba.Outbpp == BPP_INVALID) {
mode_lib->vba.Outbpp =
- TruncToValidBPP(
- (1.0
- - mode_lib->vba.Downspreading
- / 100.0)
- * 540.0
- * mode_lib->vba.OutputLinkDPLanes[k]
- / mode_lib->vba.PixelClockBackEnd[k]
- * 8.0,
+ TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0
+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
false,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
mode_lib->vba.DSCInputBitPerComponent[k]);
mode_lib->vba.OutbppDSC =
- TruncToValidBPP(
- (1.0
- - mode_lib->vba.Downspreading
- / 100.0)
- * (1.0
- - mode_lib->vba.EffectiveFECOverhead
- / 100.0)
- * 540.0
- * mode_lib->vba.OutputLinkDPLanes[k]
- / mode_lib->vba.PixelClockBackEnd[k]
- * 8.0,
+ TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0)
+ * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0
+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
true,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
@@ -5094,40 +5069,26 @@
mode_lib->vba.OutputBppPerState[i][k] =
mode_lib->vba.Outbpp;
}
- if (mode_lib->vba.Outbpp == 0
+ if (mode_lib->vba.Outbpp == BPP_INVALID
&& mode_lib->vba.PHYCLKPerState[i]
>= 810.0) {
mode_lib->vba.Outbpp =
- TruncToValidBPP(
- (1.0
- - mode_lib->vba.Downspreading
- / 100.0)
- * 810.0
- * mode_lib->vba.OutputLinkDPLanes[k]
- / mode_lib->vba.PixelClockBackEnd[k]
- * 8.0,
+ TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0
+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
false,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
mode_lib->vba.DSCInputBitPerComponent[k]);
mode_lib->vba.OutbppDSC =
- TruncToValidBPP(
- (1.0
- - mode_lib->vba.Downspreading
- / 100.0)
- * (1.0
- - mode_lib->vba.EffectiveFECOverhead
- / 100.0)
- * 810.0
- * mode_lib->vba.OutputLinkDPLanes[k]
- / mode_lib->vba.PixelClockBackEnd[k]
- * 8.0,
+ TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0)
+ * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0
+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
true,
mode_lib->vba.Output[k],
mode_lib->vba.OutputFormat[k],
mode_lib->vba.DSCInputBitPerComponent[k]);
if (mode_lib->vba.DSCEnabled[k] == true
- || mode_lib->vba.Outbpp == 0) {
+ || mode_lib->vba.Outbpp == BPP_INVALID) {
mode_lib->vba.RequiresDSC[i][k] = true;
if (mode_lib->vba.Output[k] == dm_dp) {
mode_lib->vba.RequiresFEC[i][k] =
@@ -5147,14 +5108,14 @@
}
}
} else {
- mode_lib->vba.OutputBppPerState[i][k] = 0;
+ mode_lib->vba.OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
}
}
}
for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
mode_lib->vba.DIOSupport[i] = true;
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
- if (mode_lib->vba.OutputBppPerState[i][k] == 0
+ if (mode_lib->vba.OutputBppPerState[i][k] == BPP_INVALID
|| (mode_lib->vba.OutputFormat[k] == dm_420
&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP
== true)) {
@@ -5243,8 +5204,8 @@
} else {
mode_lib->vba.slices = 1.0;
}
- if (mode_lib->vba.OutputBppPerState[i][k] == 0
- || mode_lib->vba.OutputBppPerState[i][k] == 0) {
+ if (mode_lib->vba.OutputBppPerState[i][k] == BPP_BLENDED_PIPE
+ || mode_lib->vba.OutputBppPerState[i][k] == BPP_INVALID) {
mode_lib->vba.bpp = 0.0;
} else {
mode_lib->vba.bpp = mode_lib->vba.OutputBppPerState[i][k];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
index 8ba962df..325dd2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
@@ -27,6 +27,15 @@
#include "display_mode_vba.h"
#include "display_rq_dlg_calc.h"
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
double *refcyc_per_req_delivery_pre_cur,
double *refcyc_per_req_delivery_cur,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
index 1e4b1e3..c2037da 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
@@ -28,6 +28,15 @@
#include "dml_inline_defs.h"
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
{
unsigned int ret_val = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
index bc7d8c7..324239c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
@@ -27,6 +27,16 @@
#include "dc_features.h"
#include "dml_inline_defs.h"
+
+/*
+ * NOTE:
+ * This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box)
{
to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
index 4ced9a7..0c2314e 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
@@ -34,9 +34,9 @@
#include "hw_factory_dce120.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
#define block HPD
#define reg_num 0
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
index af3843a..a225b02c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
@@ -33,9 +33,9 @@
#include "include/gpio_types.h"
#include "../hw_translate.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
index 409763c..5235f69 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
@@ -34,9 +34,9 @@
#include "hw_factory_dcn10.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
+#include "soc15ip.h"
#define block HPD
#define reg_num 0
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
index 64a6915..3478648 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
@@ -33,9 +33,9 @@
#include "include/gpio_types.h"
#include "../hw_translate.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
+#include "soc15ip.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
index 668981a..a401636 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
@@ -36,9 +36,9 @@
#include "../dce110/aux_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
index 13b807d..bed7cc3 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
@@ -36,9 +36,9 @@
#include "../dce110/i2c_hw_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
+#include "soc15ip.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index b69f321..d697105 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -139,6 +139,7 @@
struct timing_generator *timing_generators[MAX_PIPES];
struct stream_encoder *stream_enc[MAX_PIPES * 2];
+ struct hubbub *hubbub;
struct mpc *mpc;
struct pp_smu_funcs_rv *pp_smu;
struct pp_smu_display_requirement_rv pp_smu_req;
@@ -211,7 +212,6 @@
struct _vcs_dpi_display_rq_regs_st rq_regs;
struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
#endif
- struct dwbc *dwbc;
};
struct resource_context {
@@ -240,6 +240,7 @@
struct dcn_bw_clocks {
int dispclk_khz;
+ int dppclk_khz;
bool dppclk_div;
int dcfclk_khz;
int dcfclk_deep_sleep_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 1e231f6..132d18d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -349,10 +349,10 @@
float dst_x_after_scaler;
float dst_y_after_scaler;
float time_calc;
- float v_update_offset[number_of_planes_minus_one + 1];
+ float v_update_offset[number_of_planes_minus_one + 1][2];
float total_repeater_delay;
- float v_update_width[number_of_planes_minus_one + 1];
- float v_ready_offset[number_of_planes_minus_one + 1];
+ float v_update_width[number_of_planes_minus_one + 1][2];
+ float v_ready_offset[number_of_planes_minus_one + 1][2];
float time_setup;
float extra_latency;
float maximum_vstartup;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index c93b9b9..a83a484 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -27,9 +27,19 @@
#include "dm_services_types.h"
+struct abm_backlight_registers {
+ unsigned int BL_PWM_CNTL;
+ unsigned int BL_PWM_CNTL2;
+ unsigned int BL_PWM_PERIOD_CNTL;
+ unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
+};
+
struct abm {
struct dc_context *ctx;
const struct abm_funcs *funcs;
+
+ /* registers setting needs to be saved and restored at InitBacklight */
+ struct abm_backlight_registers stored_backlight_registers;
};
struct abm_funcs {
@@ -40,9 +50,9 @@
bool (*set_backlight_level)(struct abm *abm,
unsigned int backlight_level,
unsigned int frame_ramp,
- unsigned int controller_id);
+ unsigned int controller_id,
+ bool use_smooth_brightness);
unsigned int (*get_current_backlight_8_bit)(struct abm *abm);
- bool (*is_dmcu_initialized)(struct abm *abm);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 0574c29..ce2063554 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -27,12 +27,29 @@
#include "dm_services_types.h"
+enum dmcu_state {
+ DMCU_NOT_INITIALIZED = 0,
+ DMCU_RUNNING = 1
+};
+
+struct dmcu_version {
+ unsigned int day;
+ unsigned int month;
+ unsigned int year;
+ unsigned int interface_version;
+};
+
struct dmcu {
struct dc_context *ctx;
const struct dmcu_funcs *funcs;
+
+ enum dmcu_state dmcu_state;
+ struct dmcu_version dmcu_version;
+ unsigned int cached_wait_loop_number;
};
struct dmcu_funcs {
+ bool (*dmcu_init)(struct dmcu *dmcu);
bool (*load_iram)(struct dmcu *dmcu,
unsigned int start_offset,
const char *src,
@@ -44,7 +61,9 @@
void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
void (*set_psr_wait_loop)(struct dmcu *dmcu,
unsigned int wait_loop_number);
- void (*get_psr_wait_loop)(unsigned int *psr_wait_loop_number);
+ void (*get_psr_wait_loop)(struct dmcu *dmcu,
+ unsigned int *psr_wait_loop_number);
+ bool (*is_dmcu_initialized)(struct dmcu *dmcu);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 9420dfb..25edbde 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -62,63 +62,67 @@
struct dpp *dpp,
const struct dpp_grph_csc_adjustment *adjust);
- void (*opp_set_csc_default)(
+ void (*dpp_set_csc_default)(
struct dpp *dpp,
enum dc_color_space colorspace);
- void (*opp_set_csc_adjustment)(
+ void (*dpp_set_csc_adjustment)(
struct dpp *dpp,
- const struct out_csc_color_matrix *tbl_entry);
+ const uint16_t *regval);
- void (*opp_power_on_regamma_lut)(
+ void (*dpp_power_on_regamma_lut)(
struct dpp *dpp,
bool power_on);
- void (*opp_program_regamma_lut)(
+ void (*dpp_program_regamma_lut)(
struct dpp *dpp,
const struct pwl_result_data *rgb,
uint32_t num);
- void (*opp_configure_regamma_lut)(
+ void (*dpp_configure_regamma_lut)(
struct dpp *dpp,
bool is_ram_a);
- void (*opp_program_regamma_lutb_settings)(
+ void (*dpp_program_regamma_lutb_settings)(
struct dpp *dpp,
const struct pwl_params *params);
- void (*opp_program_regamma_luta_settings)(
+ void (*dpp_program_regamma_luta_settings)(
struct dpp *dpp,
const struct pwl_params *params);
- void (*opp_program_regamma_pwl)(
- struct dpp *dpp, const struct pwl_params *params);
+ void (*dpp_program_regamma_pwl)(
+ struct dpp *dpp,
+ const struct pwl_params *params,
+ enum opp_regamma mode);
- void (*opp_set_regamma_mode)(
- struct dpp *dpp_base,
- enum opp_regamma mode);
+ void (*dpp_program_bias_and_scale)(
+ struct dpp *dpp,
+ struct dc_bias_and_scale *params);
- void (*ipp_set_degamma)(
+ void (*dpp_set_degamma)(
struct dpp *dpp_base,
enum ipp_degamma_mode mode);
- void (*ipp_program_input_lut)(
+ void (*dpp_program_input_lut)(
struct dpp *dpp_base,
const struct dc_gamma *gamma);
- void (*ipp_program_degamma_pwl)(struct dpp *dpp_base,
+ void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
const struct pwl_params *params);
- void (*ipp_setup)(
+ void (*dpp_setup)(
struct dpp *dpp_base,
- enum surface_pixel_format input_format,
- enum expansion_mode mode);
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct csc_transform input_csc_color_matrix,
+ enum dc_color_space input_color_space);
- void (*ipp_full_bypass)(struct dpp *dpp_base);
+ void (*dpp_full_bypass)(struct dpp *dpp_base);
void (*set_cursor_attributes)(
struct dpp *dpp_base,
- const struct dc_cursor_attributes *attr);
+ enum dc_cursor_color_format color_format);
void (*set_cursor_position)(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 0d186be..b7c7e70 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -28,15 +28,32 @@
#include "mem_input.h"
+
+enum cursor_pitch {
+ CURSOR_PITCH_64_PIXELS = 0,
+ CURSOR_PITCH_128_PIXELS,
+ CURSOR_PITCH_256_PIXELS
+};
+
+enum cursor_lines_per_chunk {
+ CURSOR_LINE_PER_CHUNK_2 = 1,
+ CURSOR_LINE_PER_CHUNK_4,
+ CURSOR_LINE_PER_CHUNK_8,
+ CURSOR_LINE_PER_CHUNK_16
+};
+
struct hubp {
struct hubp_funcs *funcs;
struct dc_context *ctx;
struct dc_plane_address request_address;
struct dc_plane_address current_address;
int inst;
+
+ /* run time states */
int opp_id;
int mpcc_id;
struct dc_cursor_attributes curs_attr;
+ bool power_gated;
};
@@ -100,6 +117,8 @@
const struct dc_cursor_position *pos,
const struct dc_cursor_mi_param *param);
+ void (*hubp_disconnect)(struct hubp *hubp);
+
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 9602f26..e3f0b40 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -73,7 +73,7 @@
struct pwl_params {
struct gamma_curve arr_curve_points[34];
- struct curve_points arr_points[3];
+ struct curve_points arr_points[2];
struct pwl_result_data rgb_resulted[256 + 3];
uint32_t hw_points_num;
};
@@ -126,11 +126,13 @@
bool force_hw_default;
};
+
struct out_csc_color_matrix {
enum dc_color_space color_space;
uint16_t regval[12];
};
+
enum opp_regamma {
OPP_REGAMMA_BYPASS = 0,
OPP_REGAMMA_SRGB,
@@ -138,4 +140,55 @@
OPP_REGAMMA_USER
};
+struct csc_transform {
+ uint16_t matrix[12];
+ bool enable_adjustment;
+};
+
+struct dc_bias_and_scale {
+ uint16_t scale_red;
+ uint16_t bias_red;
+ uint16_t scale_green;
+ uint16_t bias_green;
+ uint16_t scale_blue;
+ uint16_t bias_blue;
+};
+
+enum test_pattern_dyn_range {
+ TEST_PATTERN_DYN_RANGE_VESA = 0,
+ TEST_PATTERN_DYN_RANGE_CEA
+};
+
+enum test_pattern_mode {
+ TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
+ TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
+ TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
+ TEST_PATTERN_MODE_VERTICALBARS,
+ TEST_PATTERN_MODE_HORIZONTALBARS,
+ TEST_PATTERN_MODE_SINGLERAMP_RGB,
+ TEST_PATTERN_MODE_DUALRAMP_RGB
+};
+
+enum test_pattern_color_format {
+ TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
+ TEST_PATTERN_COLOR_FORMAT_BPC_8,
+ TEST_PATTERN_COLOR_FORMAT_BPC_10,
+ TEST_PATTERN_COLOR_FORMAT_BPC_12
+};
+
+enum controller_dp_test_pattern {
+ CONTROLLER_DP_TEST_PATTERN_D102 = 0,
+ CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
+ CONTROLLER_DP_TEST_PATTERN_PRBS7,
+ CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
+ CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
+ CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
+ CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
+ CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
+ CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
+ CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
+};
+
#endif /* __DAL_HW_SHARED_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
index f11aa48..2109eac 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
@@ -85,8 +85,10 @@
/* setup ipp to expand/convert input to pixel processor internal format */
void (*ipp_setup)(
struct input_pixel_processor *ipp,
- enum surface_pixel_format input_format,
- enum expansion_mode mode);
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct csc_transform input_csc_color_matrix,
+ enum dc_color_space input_color_space);
/* DCE function to setup IPP. TODO: see if we can consolidate to setup */
void (*ipp_program_prescale)(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 498b7f0..54d8a13 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -123,8 +123,7 @@
void (*enable_tmds_output)(struct link_encoder *enc,
enum clock_source_id clock_source,
enum dc_color_depth color_depth,
- bool hdmi,
- bool dual_link,
+ enum signal_type signal,
uint32_t pixel_clock);
void (*enable_dp_output)(struct link_encoder *enc,
const struct dc_link_settings *link_settings,
@@ -133,7 +132,7 @@
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source);
void (*disable_output)(struct link_encoder *link_enc,
- enum signal_type signal, struct dc_link *link);
+ enum signal_type signal);
void (*dp_set_lane_settings)(struct link_encoder *enc,
const struct link_training_settings *link_settings);
void (*dp_set_phy_pattern)(struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index d4188b2..23a8d5e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -26,35 +26,162 @@
#define __DC_MPCC_H__
#include "dc_hw_types.h"
-#include "opp.h"
+#include "hw_shared.h"
-struct mpcc_cfg {
- int dpp_id;
- int opp_id;
- struct mpc_tree_cfg *tree_cfg;
- unsigned int z_index;
+#define MAX_MPCC 6
+#define MAX_OPP 6
- struct tg_color black_color;
- bool per_pixel_alpha;
- bool pre_multiplied_alpha;
+enum mpc_output_csc_mode {
+ MPC_OUTPUT_CSC_DISABLE = 0,
+ MPC_OUTPUT_CSC_COEF_A,
+ MPC_OUTPUT_CSC_COEF_B
+};
+
+
+enum mpcc_blend_mode {
+ MPCC_BLEND_MODE_BYPASS,
+ MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH,
+ MPCC_BLEND_MODE_TOP_LAYER_ONLY,
+ MPCC_BLEND_MODE_TOP_BOT_BLENDING
+};
+
+enum mpcc_alpha_blend_mode {
+ MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA,
+ MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN,
+ MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA
+};
+
+/*
+ * MPCC blending configuration
+ */
+struct mpcc_blnd_cfg {
+ struct tg_color black_color; /* background color */
+ enum mpcc_alpha_blend_mode alpha_mode; /* alpha blend mode */
+ bool pre_multiplied_alpha; /* alpha pre-multiplied mode flag */
+ int global_gain;
+ int global_alpha;
+ bool overlap_only;
+
+};
+
+struct mpcc_sm_cfg {
+ bool enable;
+ /* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */
+ int sm_mode;
+ /* 0- disable frame alternate, 1- enable frame alternate */
+ bool frame_alt;
+ /* 0- disable field alternate, 1- enable field alternate */
+ bool field_alt;
+ /* 0-no force,2-force frame polarity from top,3-force frame polarity from bottom */
+ int force_next_frame_porlarity;
+ /* 0-no force,2-force field polarity from top,3-force field polarity from bottom */
+ int force_next_field_polarity;
+};
+
+/*
+ * MPCC connection and blending configuration for a single MPCC instance.
+ * This struct is used as a node in an MPC tree.
+ */
+struct mpcc {
+ int mpcc_id; /* MPCC physical instance */
+ int dpp_id; /* DPP input to this MPCC */
+ struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */
+ struct mpcc_blnd_cfg blnd_cfg; /* The blending configuration for this MPCC */
+ struct mpcc_sm_cfg sm_cfg; /* stereo mix setting for this MPCC */
+};
+
+/*
+ * MPC tree represents all MPCC connections for a pipe.
+ */
+struct mpc_tree {
+ int opp_id; /* The OPP instance that owns this MPC tree */
+ struct mpcc *opp_list; /* The top MPCC layer of the MPC tree that outputs to OPP endpoint */
};
struct mpc {
const struct mpc_funcs *funcs;
struct dc_context *ctx;
+
+ struct mpcc mpcc_array[MAX_MPCC];
};
struct mpc_funcs {
- int (*add)(struct mpc *mpc, struct mpcc_cfg *cfg);
+ /*
+ * Insert DPP into MPC tree based on specified blending position.
+ * Only used for planes that are part of blending chain for OPP output
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ * [in/out] tree - MPC tree structure that plane will be added to.
+ * [in] blnd_cfg - MPCC blending configuration for the new blending layer.
+ * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer.
+ * stereo mix must disable for the very bottom layer of the tree config.
+ * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.
+ * [in] dpp_id - DPP instance for the plane to be added.
+ * [in] mpcc_id - The MPCC physical instance to use for blending.
+ *
+ * Return: struct mpcc* - MPCC that was added.
+ */
+ struct mpcc* (*insert_plane)(
+ struct mpc *mpc,
+ struct mpc_tree *tree,
+ struct mpcc_blnd_cfg *blnd_cfg,
+ struct mpcc_sm_cfg *sm_cfg,
+ struct mpcc *insert_above_mpcc,
+ int dpp_id,
+ int mpcc_id);
- void (*remove)(struct mpc *mpc,
- struct mpc_tree_cfg *tree_cfg,
- int opp_id,
- int mpcc_inst);
+ /*
+ * Remove a specified MPCC from the MPC tree.
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ * [in/out] tree - MPC tree structure that plane will be removed from.
+ * [in/out] mpcc - MPCC to be removed from tree.
+ *
+ * Return: void
+ */
+ void (*remove_mpcc)(
+ struct mpc *mpc,
+ struct mpc_tree *tree,
+ struct mpcc *mpcc);
+
+ /*
+ * Reset the MPCC HW status by disconnecting all muxes.
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ *
+ * Return: void
+ */
+ void (*mpc_init)(struct mpc *mpc);
+
+ /*
+ * Update the blending configuration for a specified MPCC.
+ *
+ * Parameters:
+ * [in/out] mpc - MPC context.
+ * [in] blnd_cfg - MPCC blending configuration.
+ * [in] mpcc_id - The MPCC physical instance.
+ *
+ * Return: void
+ */
+ void (*update_blending)(
+ struct mpc *mpc,
+ struct mpcc_blnd_cfg *blnd_cfg,
+ int mpcc_id);
+
+ struct mpcc* (*get_mpcc_for_dpp)(
+ struct mpc_tree *tree,
+ int dpp_id);
void (*wait_for_idle)(struct mpc *mpc, int id);
- void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg);
+ void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
+
+ void (*init_mpcc_list_from_hw)(
+ struct mpc *mpc,
+ struct mpc_tree *tree);
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 75adb8f..ab8fb77f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -29,6 +29,7 @@
#include "hw_shared.h"
#include "dc_hw_types.h"
#include "transform.h"
+#include "mpc.h"
struct fixed31_32;
@@ -204,7 +205,7 @@
struct dc_context *ctx;
uint32_t inst;
struct pwl_params regamma_params;
- struct mpc_tree_cfg mpc_tree;
+ struct mpc_tree mpc_tree_params;
bool mpcc_disconnect_pending[MAX_PIPES];
const struct opp_funcs *funcs;
};
@@ -248,6 +249,21 @@
OVERLAY_COLOR_TEMPERATURE
};
+enum oppbuf_display_segmentation {
+ OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0,
+ OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1,
+ OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2,
+ OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3,
+ OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4
+};
+
+struct oppbuf_params {
+ uint32_t active_width;
+ enum oppbuf_display_segmentation mso_segmentation;
+ uint32_t mso_overlap_pixel_num;
+ uint32_t pixel_repetition;
+};
+
struct opp_funcs {
@@ -276,14 +292,11 @@
void (*opp_destroy)(struct output_pixel_processor **opp);
- void (*opp_set_stereo_polarity)(
- struct output_pixel_processor *opp,
- bool enable,
- bool rightEyePolarity);
+ void (*opp_program_stereo)(
+ struct output_pixel_processor *opp,
+ bool enable,
+ const struct dc_crtc_timing *timing);
- void (*opp_set_test_pattern)(
- struct output_pixel_processor *opp,
- bool enable);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index c6ab38c..ec312f1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -26,6 +26,8 @@
#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
#define __DAL_TIMING_GENERATOR_TYPES_H__
+#include "hw_shared.h"
+
struct dc_bios;
/* Contains CRTC vertical/horizontal pixel counters */
@@ -40,6 +42,19 @@
int gsl_master;
};
+struct gsl_params {
+ int gsl0_en;
+ int gsl1_en;
+ int gsl2_en;
+ int gsl_master_en;
+ int gsl_master_mode;
+ int master_update_lock_gsl_en;
+ int gsl_window_start_x;
+ int gsl_window_end_x;
+ int gsl_window_start_y;
+ int gsl_window_end_y;
+};
+
/* define the structure of Dynamic Refresh Mode */
struct drr_params {
uint32_t vertical_total_min;
@@ -50,43 +65,6 @@
#define LEFT_EYE_3D_PRIMARY_SURFACE 1
#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
-enum test_pattern_dyn_range {
- TEST_PATTERN_DYN_RANGE_VESA = 0,
- TEST_PATTERN_DYN_RANGE_CEA
-};
-
-enum test_pattern_mode {
- TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
- TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
- TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
- TEST_PATTERN_MODE_VERTICALBARS,
- TEST_PATTERN_MODE_HORIZONTALBARS,
- TEST_PATTERN_MODE_SINGLERAMP_RGB,
- TEST_PATTERN_MODE_DUALRAMP_RGB
-};
-
-enum test_pattern_color_format {
- TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
- TEST_PATTERN_COLOR_FORMAT_BPC_8,
- TEST_PATTERN_COLOR_FORMAT_BPC_10,
- TEST_PATTERN_COLOR_FORMAT_BPC_12
-};
-
-enum controller_dp_test_pattern {
- CONTROLLER_DP_TEST_PATTERN_D102 = 0,
- CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
- CONTROLLER_DP_TEST_PATTERN_PRBS7,
- CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
- CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
- CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
- CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
- CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
- CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
- CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
- CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
- CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-};
-
enum crtc_state {
CRTC_STATE_VBLANK = 0,
CRTC_STATE_VACTIVE
@@ -100,6 +78,12 @@
enum signal_type signal;
};
+struct vupdate_keepout_params {
+ int start_offset;
+ int end_offset;
+ int enable;
+};
+
struct crtc_stereo_flags {
uint8_t PROGRAM_STEREO : 1;
uint8_t PROGRAM_POLARITY : 1;
@@ -158,7 +142,11 @@
const struct dcp_gsl_params *gsl_params);
void (*unlock)(struct timing_generator *tg);
void (*lock)(struct timing_generator *tg);
- void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst);
+ void (*enable_reset_trigger)(struct timing_generator *tg,
+ int source_tg_inst);
+ void (*enable_crtc_reset)(struct timing_generator *tg,
+ int source_tg_inst,
+ struct crtc_trigger_info *crtc_tp);
void (*disable_reset_trigger)(struct timing_generator *tg);
void (*tear_down_global_swap_lock)(struct timing_generator *tg);
void (*enable_advanced_request)(struct timing_generator *tg,
@@ -178,6 +166,13 @@
void (*program_stereo)(struct timing_generator *tg,
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
bool (*is_stereo_left_eye)(struct timing_generator *tg);
+
+ void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
+
+ void (*tg_init)(struct timing_generator *tg);
+ bool (*is_tg_enabled)(struct timing_generator *tg);
+ bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
+ void (*clear_optc_underflow)(struct timing_generator *tg);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index ea88997..6f6c02b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -250,8 +250,10 @@
void (*ipp_setup)(
struct transform *xfm_base,
- enum surface_pixel_format input_format,
- enum expansion_mode mode);
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct csc_transform input_csc_color_matrix,
+ enum dc_color_space input_color_space);
void (*ipp_full_bypass)(struct transform *xfm_base);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 8734689a..379c6ec 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -28,6 +28,7 @@
#include "dc_types.h"
#include "clock_source.h"
#include "inc/hw/timing_generator.h"
+#include "inc/hw/opp.h"
#include "inc/hw/link_encoder.h"
#include "core_status.h"
@@ -39,6 +40,12 @@
struct dce_hwseq_wa {
bool blnd_crtc_trigger;
+ bool DEGVIDCN10_253;
+ bool false_optc_underflow;
+};
+
+struct hwseq_wa_state {
+ bool DEGVIDCN10_253_applied;
};
struct dce_hwseq {
@@ -47,6 +54,7 @@
const struct dce_hwseq_shift *shifts;
const struct dce_hwseq_mask *masks;
struct dce_hwseq_wa wa;
+ struct hwseq_wa_state wa_state;
};
struct pipe_ctx;
@@ -114,6 +122,11 @@
int group_size,
struct pipe_ctx *grouped_pipes[]);
+ void (*enable_per_frame_crtc_position_reset)(
+ struct dc *dc,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[]);
+
void (*enable_display_pipe_clock_gating)(
struct dc_context *ctx,
bool clock_gating);
@@ -124,11 +137,7 @@
struct dc_bios *dcb,
enum pipe_gating_control power_gating);
- void (*power_down_front_end)(struct dc *dc, int fe_idx);
-
- void (*power_on_front_end)(struct dc *dc,
- struct pipe_ctx *pipe,
- struct dc_state *context);
+ void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
@@ -178,12 +187,20 @@
void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
void (*optimize_shared_resources)(struct dc *dc);
+ void (*pplib_apply_display_requirements)(
+ struct dc *dc,
+ struct dc_state *context);
void (*edp_power_control)(
- struct link_encoder *enc,
+ struct dc_link *link,
bool enable);
void (*edp_backlight_control)(
struct dc_link *link,
bool enable);
+ void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+
+ void (*set_cursor_position)(struct pipe_ctx *pipe);
+ void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+
};
void color_space_to_black_color(
@@ -194,4 +211,8 @@
bool hwss_wait_for_blank_complete(
struct timing_generator *tg);
+const uint16_t *find_color_matrix(
+ enum dc_color_space color_space,
+ uint32_t *array_size);
+
#endif /* __DC_HW_SEQUENCER_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index f7e40b2..d3e1923 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -217,7 +217,7 @@
core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
if (enable) {
- if (!tg->funcs->arm_vert_intr(tg, 2)) {
+ if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
DC_ERROR("Failed to get VBLANK!\n");
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
index 2ad56b1..66d5258 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -30,9 +30,9 @@
#include "irq_service_dce120.h"
#include "../dce110/irq_service_dce110.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
+#include "soc15ip.h"
#include "ivsrcid/ivsrcid_vislands30.h"
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
index 74ad2471..7f7db66 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
@@ -29,9 +29,9 @@
#include "../dce110/irq_service_dce110.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
-#include "vega10/soc15ip.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
+#include "soc15ip.h"
#include "irq_service_dcn10.h"
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index a87c032..1fcbc99 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -26,8 +26,6 @@
#ifndef _OS_TYPES_H_
#define _OS_TYPES_H_
-#if defined __KERNEL__
-
#include <asm/byteorder.h>
#include <linux/types.h>
#include <drm/drmP.h>
@@ -46,14 +44,12 @@
#undef WRITE
#undef FRAME_SIZE
-#define dm_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
+#define dm_output_to_console(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-#define dm_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-
-#define dm_vlog(fmt, args) vprintk(fmt, args)
-
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include <asm/fpu/api.h>
#endif
/*
@@ -89,8 +85,4 @@
BREAK_TO_DEBUGGER(); \
} while (0)
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-#include <asm/fpu/api.h>
-#endif
-
#endif /* _OS_TYPES_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index 88c2bde..1c079ba 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -42,8 +42,7 @@
struct link_encoder *enc,
enum clock_source_id clock_source,
enum dc_color_depth color_depth,
- bool hdmi,
- bool dual_link,
+ enum signal_type signal,
uint32_t pixel_clock) {}
static void virtual_link_encoder_enable_dp_output(
@@ -58,8 +57,7 @@
static void virtual_link_encoder_disable_output(
struct link_encoder *link_enc,
- enum signal_type signal,
- struct dc_link *link) {}
+ enum signal_type signal) {}
static void virtual_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 0ff2a89..019e7a09 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -27,12 +27,8 @@
#define DP_BRANCH_DEVICE_ID_1 0x0010FA
#define DP_BRANCH_DEVICE_ID_2 0x0022B9
-#define DP_SINK_DEVICE_ID_1 0x4CE000
#define DP_BRANCH_DEVICE_ID_3 0x00001A
#define DP_BRANCH_DEVICE_ID_4 0x0080e1
-#define DP_BRANCH_DEVICE_ID_5 0x006037
-#define DP_SINK_DEVICE_ID_2 0x001CF8
-
enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
@@ -115,40 +111,11 @@
uint8_t aud_del_ins3;/* DPCD 0002Dh */
};
-/*DP to VGA converter*/
-static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa";
-/*DP to Dual link DVI converter*/
-static const uint8_t DP_DVI_CONVERTER_ID_1[] = "m2DVIa";
/*Travis*/
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
/*Nutmeg*/
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
-/*DP to VGA converter*/
-static const uint8_t DP_VGA_CONVERTER_ID_4[] = "DpVga";
/*DP to Dual link DVI converter*/
static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
-/*DP to Dual link DVI converter 2*/
-static const uint8_t DP_DVI_CONVERTER_ID_42[] = "v2DVIa";
-
-static const uint8_t DP_SINK_DEV_STRING_ID2_REV0[] = "\0\0\0\0\0\0";
-
-/* Identifies second generation PSR TCON from Parade: Device ID string:
- * yy-xx-**-**-**-**
- */
-/* xx - Hw ID high byte */
-static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_HIGH_BYTE =
- 0x06;
-
-/* yy - HW ID low byte, the same silicon has several package/feature flavors */
-static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE1 =
- 0x61;
-static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE2 =
- 0x62;
-static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE3 =
- 0x63;
-static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE4 =
- 0x72;
-static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE5 =
- 0x73;
#endif /* __DAL_DDC_SERVICE_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 3248f69..4badaed 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -463,4 +463,11 @@
uint32_t dal_fixed31_32_u0d19(
struct fixed31_32 arg);
+
+uint32_t dal_fixed31_32_clamp_u0d14(
+ struct fixed31_32 arg);
+
+uint32_t dal_fixed31_32_clamp_u0d10(
+ struct fixed31_32 arg);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index 7a9b43f..36bbad5 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -419,11 +419,6 @@
bool backlight_changed;
};
-enum {
- HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
- TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
-};
-
/*
* DFS-bypass flag
*/
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h
index 5eb2b4d..c419743 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_id.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h
@@ -233,10 +233,6 @@
return result;
}
-bool dal_graphics_object_id_is_equal(
- struct graphics_object_id id1,
- struct graphics_object_id id2);
-
/* Based on internal data members memory layout */
static inline uint32_t dal_graphics_object_id_to_uint(
struct graphics_object_id id)
@@ -248,7 +244,7 @@
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_CONTROLLER)
- return id.id;
+ return (enum controller_id) id.id;
return CONTROLLER_ID_UNDEFINED;
}
@@ -256,7 +252,7 @@
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
- return id.id;
+ return (enum clock_source_id) id.id;
return CLOCK_SOURCE_ID_UNDEFINED;
}
@@ -264,7 +260,7 @@
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_ENCODER)
- return id.id;
+ return (enum encoder_id) id.id;
return ENCODER_ID_UNKNOWN;
}
@@ -272,7 +268,7 @@
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_CONNECTOR)
- return id.id;
+ return (enum connector_id) id.id;
return CONNECTOR_ID_UNKNOWN;
}
@@ -280,7 +276,7 @@
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_AUDIO)
- return id.id;
+ return (enum audio_id) id.id;
return AUDIO_ID_UNKNOWN;
}
@@ -288,7 +284,7 @@
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_ENGINE)
- return id.id;
+ return (enum engine_id) id.id;
return ENGINE_ID_UNKNOWN;
}
#endif
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 8e1fe70..28dee96 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -57,6 +57,11 @@
const char *msg,
...);
+void dm_logger_append_va(
+ struct log_entry *entry,
+ const char *msg,
+ va_list args);
+
void dm_logger_open(
struct dal_logger *logger,
struct log_entry *entry,
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
index b5ebde6..199c5db 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -26,6 +26,11 @@
#ifndef __DC_SIGNAL_TYPES_H__
#define __DC_SIGNAL_TYPES_H__
+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
+#define TMDS_MIN_PIXEL_CLOCK 25000
+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
+#define TMDS_MAX_PIXEL_CLOCK 165000
+
enum signal_type {
SIGNAL_TYPE_NONE = 0L, /* no signal */
SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4d7db4a..b4723af 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -132,14 +132,6 @@
#define MOD_FREESYNC_TO_CORE(mod_freesync)\
container_of(mod_freesync, struct core_freesync, public)
-static bool check_dc_support(const struct dc *dc)
-{
- if (dc->stream_funcs.adjust_vmin_vmax == NULL)
- return false;
-
- return true;
-}
-
struct mod_freesync *mod_freesync_create(struct dc *dc)
{
struct core_freesync *core_freesync =
@@ -169,9 +161,6 @@
core_freesync->dc = dc;
- if (!check_dc_support(dc))
- goto fail_construct;
-
/* Create initial module folder in registry for freesync enable data */
flag.save_per_edid = true;
flag.save_per_link = false;
@@ -599,10 +588,9 @@
update_stream_freesync_context(core_freesync,
streams[stream_idx]);
- core_freesync->dc->stream_funcs.
- adjust_vmin_vmax(core_freesync->dc, streams,
- num_streams, v_total_min,
- v_total_max);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+ num_streams, v_total_min,
+ v_total_max);
return true;
@@ -625,8 +613,7 @@
core_freesync,
streams[stream_idx]);
- core_freesync->dc->stream_funcs.
- adjust_vmin_vmax(
+ dc_stream_adjust_vmin_vmax(
core_freesync->dc, streams,
num_streams, v_total_nominal,
v_total_nominal);
@@ -645,11 +632,9 @@
core_freesync,
streams[stream_idx]);
- core_freesync->dc->stream_funcs.
- adjust_vmin_vmax(
- core_freesync->dc, streams,
- num_streams, v_total_nominal,
- v_total_nominal);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+ num_streams, v_total_nominal,
+ v_total_nominal);
/* Reset the cached variables */
reset_freesync_state_variables(state);
@@ -665,11 +650,9 @@
* not support freesync because a former stream has
* be programmed
*/
- core_freesync->dc->stream_funcs.
- adjust_vmin_vmax(
- core_freesync->dc, streams,
- num_streams, v_total_nominal,
- v_total_nominal);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+ num_streams, v_total_nominal,
+ v_total_nominal);
/* Reset the cached variables */
reset_freesync_state_variables(state);
}
@@ -786,9 +769,8 @@
vmin = inserted_frame_v_total;
/* Program V_TOTAL */
- core_freesync->dc->stream_funcs.adjust_vmin_vmax(
- core_freesync->dc, streams,
- num_streams, vmin, vmax);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+ num_streams, vmin, vmax);
}
if (state->btr.frame_counter > 0)
@@ -822,17 +804,15 @@
update_stream_freesync_context(core_freesync, streams[0]);
/* Program static screen ramp values */
- core_freesync->dc->stream_funcs.adjust_vmin_vmax(
- core_freesync->dc, streams,
- num_streams, v_total,
- v_total);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+ num_streams, v_total,
+ v_total);
triggers.overlay_update = true;
triggers.surface_update = true;
- core_freesync->dc->stream_funcs.set_static_screen_events(
- core_freesync->dc, streams, num_streams,
- &triggers);
+ dc_stream_set_static_screen_events(core_freesync->dc, streams,
+ num_streams, &triggers);
}
}
@@ -916,9 +896,8 @@
triggers.overlay_update = true;
triggers.surface_update = true;
- core_freesync->dc->stream_funcs.set_static_screen_events(
- core_freesync->dc, streams, num_streams,
- &triggers);
+ dc_stream_set_static_screen_events(core_freesync->dc, streams,
+ num_streams, &triggers);
if (freesync_program_required)
/* Program freesync according to current state*/
@@ -1084,10 +1063,9 @@
max_refresh);
/* Program vtotal min/max */
- core_freesync->dc->stream_funcs.adjust_vmin_vmax(
- core_freesync->dc, &streams, 1,
- state->freesync_range.vmin,
- state->freesync_range.vmax);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, &streams, 1,
+ state->freesync_range.vmin,
+ state->freesync_range.vmax);
}
if (min_refresh != 0 &&
@@ -1163,9 +1141,9 @@
core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
index = map_index_from_stream(core_freesync, stream);
- if (core_freesync->dc->stream_funcs.get_crtc_position(
- core_freesync->dc, &stream, 1,
- &position.vertical_count, &position.nominal_vcount)) {
+ if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
+ &position.vertical_count,
+ &position.nominal_vcount)) {
*nom_v_pos = position.nominal_vcount;
*v_pos = position.vertical_count;
@@ -1223,9 +1201,9 @@
triggers.overlay_update = true;
triggers.surface_update = true;
- core_freesync->dc->stream_funcs.set_static_screen_events(
- core_freesync->dc, streams, num_streams,
- &triggers);
+ dc_stream_set_static_screen_events(core_freesync->dc,
+ streams, num_streams,
+ &triggers);
}
}
@@ -1424,10 +1402,8 @@
vmax = vmin;
- core_freesync->dc->stream_funcs.adjust_vmin_vmax(
- core_freesync->dc, &stream,
- 1, vmin,
- vmax);
+ dc_stream_adjust_vmin_vmax(core_freesync->dc, &stream,
+ 1, vmin, vmax);
}
}
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 869c806..f235cab 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -59,71 +59,12 @@
AMD_CG_STATE_UNGATE,
};
-enum amd_dpm_forced_level {
- AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
- AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
- AMD_DPM_FORCED_LEVEL_LOW = 0x4,
- AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
- AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
- AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
- AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
-};
enum amd_powergating_state {
AMD_PG_STATE_GATE = 0,
AMD_PG_STATE_UNGATE,
};
-struct amd_vce_state {
- /* vce clocks */
- u32 evclk;
- u32 ecclk;
- /* gpu clocks */
- u32 sclk;
- u32 mclk;
- u8 clk_idx;
- u8 pstate;
-};
-
-
-#define AMD_MAX_VCE_LEVELS 6
-
-enum amd_vce_level {
- AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
- AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
- AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
- AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
- AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
- AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
-};
-
-enum amd_pp_profile_type {
- AMD_PP_GFX_PROFILE,
- AMD_PP_COMPUTE_PROFILE,
-};
-
-struct amd_pp_profile {
- enum amd_pp_profile_type type;
- uint32_t min_sclk;
- uint32_t min_mclk;
- uint16_t activity_threshold;
- uint8_t up_hyst;
- uint8_t down_hyst;
-};
-
-enum amd_fan_ctrl_mode {
- AMD_FAN_CTRL_NONE = 0,
- AMD_FAN_CTRL_MANUAL = 1,
- AMD_FAN_CTRL_AUTO = 2,
-};
-
-enum pp_clock_type {
- PP_SCLK,
- PP_MCLK,
- PP_PCIE,
-};
/* CG flags */
#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
@@ -167,27 +108,6 @@
#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
#define AMD_PG_SUPPORT_MMHUB (1 << 13)
-enum amd_pm_state_type {
- /* not used for dpm */
- POWER_STATE_TYPE_DEFAULT,
- POWER_STATE_TYPE_POWERSAVE,
- /* user selectable states */
- POWER_STATE_TYPE_BATTERY,
- POWER_STATE_TYPE_BALANCED,
- POWER_STATE_TYPE_PERFORMANCE,
- /* internal states */
- POWER_STATE_TYPE_INTERNAL_UVD,
- POWER_STATE_TYPE_INTERNAL_UVD_SD,
- POWER_STATE_TYPE_INTERNAL_UVD_HD,
- POWER_STATE_TYPE_INTERNAL_UVD_HD2,
- POWER_STATE_TYPE_INTERNAL_UVD_MVC,
- POWER_STATE_TYPE_INTERNAL_BOOT,
- POWER_STATE_TYPE_INTERNAL_THERMAL,
- POWER_STATE_TYPE_INTERNAL_ACPI,
- POWER_STATE_TYPE_INTERNAL_ULV,
- POWER_STATE_TYPE_INTERNAL_3DPERF,
-};
-
struct amd_ip_funcs {
/* Name of IP block */
char *name;
@@ -231,95 +151,4 @@
};
-enum amd_pp_task;
-enum amd_pp_clock_type;
-struct pp_states_info;
-struct amd_pp_simple_clock_info;
-struct amd_pp_display_configuration;
-struct amd_pp_clock_info;
-struct pp_display_clock_request;
-struct pp_wm_sets_with_clock_ranges_soc15;
-struct pp_clock_levels_with_voltage;
-struct pp_clock_levels_with_latency;
-struct amd_pp_clocks;
-
-struct amd_pm_funcs {
-/* export for dpm on ci and si */
- int (*pre_set_power_state)(void *handle);
- int (*set_power_state)(void *handle);
- void (*post_set_power_state)(void *handle);
- void (*display_configuration_changed)(void *handle);
- void (*print_power_state)(void *handle, void *ps);
- bool (*vblank_too_short)(void *handle);
- void (*enable_bapm)(void *handle, bool enable);
- int (*check_state_equal)(void *handle,
- void *cps,
- void *rps,
- bool *equal);
-/* export for sysfs */
- int (*get_temperature)(void *handle);
- void (*set_fan_control_mode)(void *handle, u32 mode);
- u32 (*get_fan_control_mode)(void *handle);
- int (*set_fan_speed_percent)(void *handle, u32 speed);
- int (*get_fan_speed_percent)(void *handle, u32 *speed);
- int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
- int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
- int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
- int (*get_sclk_od)(void *handle);
- int (*set_sclk_od)(void *handle, uint32_t value);
- int (*get_mclk_od)(void *handle);
- int (*set_mclk_od)(void *handle, uint32_t value);
- int (*read_sensor)(void *handle, int idx, void *value, int *size);
- enum amd_dpm_forced_level (*get_performance_level)(void *handle);
- enum amd_pm_state_type (*get_current_power_state)(void *handle);
- int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
- int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
- int (*get_pp_table)(void *handle, char **table);
- int (*set_pp_table)(void *handle, const char *buf, size_t size);
- void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
-
- int (*reset_power_profile_state)(void *handle,
- struct amd_pp_profile *request);
- int (*get_power_profile_state)(void *handle,
- struct amd_pp_profile *query);
- int (*set_power_profile_state)(void *handle,
- struct amd_pp_profile *request);
- int (*switch_power_profile)(void *handle,
- enum amd_pp_profile_type type);
-/* export to amdgpu */
- void (*powergate_uvd)(void *handle, bool gate);
- void (*powergate_vce)(void *handle, bool gate);
- struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx);
- int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
- void *input, void *output);
- int (*load_firmware)(void *handle);
- int (*wait_for_fw_loading_complete)(void *handle);
- int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
-/* export to DC */
- u32 (*get_sclk)(void *handle, bool low);
- u32 (*get_mclk)(void *handle, bool low);
- int (*display_configuration_change)(void *handle,
- const struct amd_pp_display_configuration *input);
- int (*get_display_power_level)(void *handle,
- struct amd_pp_simple_clock_info *output);
- int (*get_current_clocks)(void *handle,
- struct amd_pp_clock_info *clocks);
- int (*get_clock_by_type)(void *handle,
- enum amd_pp_clock_type type,
- struct amd_pp_clocks *clocks);
- int (*get_clock_by_type_with_latency)(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_latency *clocks);
- int (*get_clock_by_type_with_voltage)(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_voltage *clocks);
- int (*set_watermarks_for_clocks_ranges)(void *handle,
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
- int (*display_clock_voltage_request)(void *handle,
- struct pp_display_clock_request *clock);
- int (*get_display_mode_validation_clocks)(void *handle,
- struct amd_pp_simple_clock_info *clocks);
-};
-
-
#endif /* __AMD_SHARED_H__ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h
new file mode 100644
index 0000000..b1e878ec
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_1_0_OFFSET_HEADER
+#define _athub_1_0_OFFSET_HEADER
+
+
+
+// addressBlock: athub_atsdec
+// base address: 0x3080
+#define mmATC_ATS_CNTL 0x0000
+#define mmATC_ATS_CNTL_BASE_IDX 0
+#define mmATC_ATS_STATUS 0x0003
+#define mmATC_ATS_STATUS_BASE_IDX 0
+#define mmATC_ATS_FAULT_CNTL 0x0004
+#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
+#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
+#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
+#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
+#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
+#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
+#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
+#define mmATHUB_MISC_CNTL 0x000a
+#define mmATHUB_MISC_CNTL_BASE_IDX 0
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
+#define mmATC_VMID0_PASID_MAPPING 0x000c
+#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID1_PASID_MAPPING 0x000d
+#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID2_PASID_MAPPING 0x000e
+#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID3_PASID_MAPPING 0x000f
+#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID4_PASID_MAPPING 0x0010
+#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID5_PASID_MAPPING 0x0011
+#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID6_PASID_MAPPING 0x0012
+#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID7_PASID_MAPPING 0x0013
+#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID8_PASID_MAPPING 0x0014
+#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID9_PASID_MAPPING 0x0015
+#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID10_PASID_MAPPING 0x0016
+#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID11_PASID_MAPPING 0x0017
+#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID12_PASID_MAPPING 0x0018
+#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID13_PASID_MAPPING 0x0019
+#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID14_PASID_MAPPING 0x001a
+#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID15_PASID_MAPPING 0x001b
+#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
+#define mmATC_ATS_VMID_STATUS 0x001c
+#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
+#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
+#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
+#define mmATC_PERFCOUNTER0_CFG 0x001e
+#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER1_CFG 0x001f
+#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER2_CFG 0x0020
+#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER3_CFG 0x0021
+#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
+#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmATC_PERFCOUNTER_LO 0x0023
+#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
+#define mmATC_PERFCOUNTER_HI 0x0024
+#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL 0x0025
+#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_PASID_CNTL 0x0026
+#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
+#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
+#define mmATHUB_COMMAND 0x0029
+#define mmATHUB_COMMAND_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
+#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
+#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
+#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
+#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
+#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
+#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
+#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
+#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
+#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
+#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
+#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
+#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
+#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
+#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
+#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
+#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
+#define mmATHUB_MEM_POWER_LS 0x003a
+#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
+#define mmATS_IH_CREDIT 0x003b
+#define mmATS_IH_CREDIT_BASE_IDX 0
+#define mmATHUB_IH_CREDIT 0x003c
+#define mmATHUB_IH_CREDIT_BASE_IDX 0
+#define mmATC_VMID16_PASID_MAPPING 0x003d
+#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID17_PASID_MAPPING 0x003e
+#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID18_PASID_MAPPING 0x003f
+#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID19_PASID_MAPPING 0x0040
+#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID20_PASID_MAPPING 0x0041
+#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID21_PASID_MAPPING 0x0042
+#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID22_PASID_MAPPING 0x0043
+#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID23_PASID_MAPPING 0x0044
+#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID24_PASID_MAPPING 0x0045
+#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID25_PASID_MAPPING 0x0046
+#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID26_PASID_MAPPING 0x0047
+#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID27_PASID_MAPPING 0x0048
+#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID28_PASID_MAPPING 0x0049
+#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID29_PASID_MAPPING 0x004a
+#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID30_PASID_MAPPING 0x004b
+#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID31_PASID_MAPPING 0x004c
+#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
+#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d
+#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
+#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e
+#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f
+#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmATC_ATS_SDPPORT_CNTL 0x0050
+#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
+
+
+// addressBlock: athub_xpbdec
+// base address: 0x31f0
+#define mmXPB_RTR_SRC_APRTR0 0x005c
+#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR1 0x005d
+#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR2 0x005e
+#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR3 0x005f
+#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR4 0x0060
+#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR5 0x0061
+#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR6 0x0062
+#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR7 0x0063
+#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR8 0x0064
+#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR9 0x0065
+#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066
+#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067
+#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068
+#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069
+#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP0 0x006a
+#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP1 0x006b
+#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP2 0x006c
+#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP3 0x006d
+#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP4 0x006e
+#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP5 0x006f
+#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP6 0x0070
+#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP7 0x0071
+#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP8 0x0072
+#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP9 0x0073
+#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074
+#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075
+#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076
+#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077
+#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
+#define mmXPB_CLG_CFG0 0x0078
+#define mmXPB_CLG_CFG0_BASE_IDX 0
+#define mmXPB_CLG_CFG1 0x0079
+#define mmXPB_CLG_CFG1_BASE_IDX 0
+#define mmXPB_CLG_CFG2 0x007a
+#define mmXPB_CLG_CFG2_BASE_IDX 0
+#define mmXPB_CLG_CFG3 0x007b
+#define mmXPB_CLG_CFG3_BASE_IDX 0
+#define mmXPB_CLG_CFG4 0x007c
+#define mmXPB_CLG_CFG4_BASE_IDX 0
+#define mmXPB_CLG_CFG5 0x007d
+#define mmXPB_CLG_CFG5_BASE_IDX 0
+#define mmXPB_CLG_CFG6 0x007e
+#define mmXPB_CLG_CFG6_BASE_IDX 0
+#define mmXPB_CLG_CFG7 0x007f
+#define mmXPB_CLG_CFG7_BASE_IDX 0
+#define mmXPB_CLG_EXTRA 0x0080
+#define mmXPB_CLG_EXTRA_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_MSK 0x0081
+#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
+#define mmXPB_LB_ADDR 0x0082
+#define mmXPB_LB_ADDR_BASE_IDX 0
+#define mmXPB_WCB_STS 0x0083
+#define mmXPB_WCB_STS_BASE_IDX 0
+#define mmXPB_HST_CFG 0x0084
+#define mmXPB_HST_CFG_BASE_IDX 0
+#define mmXPB_P2P_BAR_CFG 0x0085
+#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
+#define mmXPB_P2P_BAR0 0x0086
+#define mmXPB_P2P_BAR0_BASE_IDX 0
+#define mmXPB_P2P_BAR1 0x0087
+#define mmXPB_P2P_BAR1_BASE_IDX 0
+#define mmXPB_P2P_BAR2 0x0088
+#define mmXPB_P2P_BAR2_BASE_IDX 0
+#define mmXPB_P2P_BAR3 0x0089
+#define mmXPB_P2P_BAR3_BASE_IDX 0
+#define mmXPB_P2P_BAR4 0x008a
+#define mmXPB_P2P_BAR4_BASE_IDX 0
+#define mmXPB_P2P_BAR5 0x008b
+#define mmXPB_P2P_BAR5_BASE_IDX 0
+#define mmXPB_P2P_BAR6 0x008c
+#define mmXPB_P2P_BAR6_BASE_IDX 0
+#define mmXPB_P2P_BAR7 0x008d
+#define mmXPB_P2P_BAR7_BASE_IDX 0
+#define mmXPB_P2P_BAR_SETUP 0x008e
+#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
+#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090
+#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
+#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091
+#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR0 0x0092
+#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR1 0x0093
+#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR2 0x0094
+#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR3 0x0095
+#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR4 0x0096
+#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR5 0x0097
+#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR6 0x0098
+#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR7 0x0099
+#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR8 0x009a
+#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR9 0x009b
+#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c
+#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d
+#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e
+#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f
+#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
+#define mmXPB_CLK_GAT 0x00a0
+#define mmXPB_CLK_GAT_BASE_IDX 0
+#define mmXPB_INTF_CFG 0x00a1
+#define mmXPB_INTF_CFG_BASE_IDX 0
+#define mmXPB_INTF_STS 0x00a2
+#define mmXPB_INTF_STS_BASE_IDX 0
+#define mmXPB_PIPE_STS 0x00a3
+#define mmXPB_PIPE_STS_BASE_IDX 0
+#define mmXPB_SUB_CTRL 0x00a4
+#define mmXPB_SUB_CTRL_BASE_IDX 0
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
+#define mmXPB_PERF_KNOBS 0x00a6
+#define mmXPB_PERF_KNOBS_BASE_IDX 0
+#define mmXPB_STICKY 0x00a7
+#define mmXPB_STICKY_BASE_IDX 0
+#define mmXPB_STICKY_W1C 0x00a8
+#define mmXPB_STICKY_W1C_BASE_IDX 0
+#define mmXPB_MISC_CFG 0x00a9
+#define mmXPB_MISC_CFG_BASE_IDX 0
+#define mmXPB_INTF_CFG2 0x00aa
+#define mmXPB_INTF_CFG2_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_RD 0x00ab
+#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac
+#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
+#define mmXPB_CLG_GFX_MATCH 0x00ad
+#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
+#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae
+#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_MM_MATCH 0x00af
+#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
+#define mmXPB_CLG_MM_MATCH_MSK 0x00b0
+#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1
+#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2
+#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3
+#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4
+#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5
+#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6
+#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7
+#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8
+#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9
+#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba
+#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb
+#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc
+#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
+
+
+// addressBlock: athub_rpbdec
+// base address: 0x33b0
+#define mmRPB_PASSPW_CONF 0x00cc
+#define mmRPB_PASSPW_CONF_BASE_IDX 0
+#define mmRPB_BLOCKLEVEL_CONF 0x00cd
+#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
+#define mmRPB_TAG_CONF 0x00cf
+#define mmRPB_TAG_CONF_BASE_IDX 0
+#define mmRPB_EFF_CNTL 0x00d1
+#define mmRPB_EFF_CNTL_BASE_IDX 0
+#define mmRPB_ARB_CNTL 0x00d2
+#define mmRPB_ARB_CNTL_BASE_IDX 0
+#define mmRPB_ARB_CNTL2 0x00d3
+#define mmRPB_ARB_CNTL2_BASE_IDX 0
+#define mmRPB_BIF_CNTL 0x00d4
+#define mmRPB_BIF_CNTL_BASE_IDX 0
+#define mmRPB_WR_SWITCH_CNTL 0x00d5
+#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
+#define mmRPB_RD_SWITCH_CNTL 0x00d7
+#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
+#define mmRPB_CID_QUEUE_WR 0x00d8
+#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
+#define mmRPB_CID_QUEUE_RD 0x00d9
+#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
+#define mmRPB_CID_QUEUE_EX 0x00dc
+#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
+#define mmRPB_CID_QUEUE_EX_DATA 0x00dd
+#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
+#define mmRPB_SWITCH_CNTL2 0x00de
+#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
+#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df
+#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
+#define mmRPB_VC_SWITCH_RDWR 0x00e0
+#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_LO 0x00e1
+#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_HI 0x00e2
+#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
+#define mmRPB_PERFCOUNTER0_CFG 0x00e3
+#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER1_CFG 0x00e4
+#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER2_CFG 0x00e5
+#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER3_CFG 0x00e6
+#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7
+#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmRPB_RD_QUEUE_CNTL 0x00e9
+#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
+#define mmRPB_RD_QUEUE_CNTL2 0x00ea
+#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
+#define mmRPB_WR_QUEUE_CNTL 0x00eb
+#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
+#define mmRPB_WR_QUEUE_CNTL2 0x00ec
+#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
+#define mmRPB_EA_QUEUE_WR 0x00ed
+#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
+#define mmRPB_ATS_CNTL 0x00ee
+#define mmRPB_ATS_CNTL_BASE_IDX 0
+#define mmRPB_ATS_CNTL2 0x00ef
+#define mmRPB_ATS_CNTL2_BASE_IDX 0
+#define mmRPB_SDPPORT_CNTL 0x00f0
+#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h
new file mode 100644
index 0000000..2968c6e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h
@@ -0,0 +1,2045 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_1_0_SH_MASK_HEADER
+#define _athub_1_0_SH_MASK_HEADER
+
+
+// addressBlock: athub_atsdec
+//ATC_ATS_CNTL
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
+#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
+#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
+#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L
+#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L
+#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
+//ATC_ATS_STATUS
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
+#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
+#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L
+#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L
+//ATC_ATS_FAULT_CNTL
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L
+//ATC_ATS_FAULT_STATUS_INFO
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L
+//ATC_ATS_FAULT_STATUS_ADDR
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL
+//ATC_ATS_DEFAULT_PAGE_LOW
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL
+//ATC_TRANS_FAULT_RSPCNTRL
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L
+//ATC_ATS_FAULT_STATUS_INFO2
+#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9
+#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL
+#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L
+//ATHUB_MISC_CNTL
+#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6
+#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12
+#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13
+#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14
+#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15
+#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b
+#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c
+#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L
+#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L
+#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L
+#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L
+#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L
+#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L
+#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L
+//ATC_VMID_PASID_MAPPING_UPDATE_STATUS
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L
+//ATC_VMID0_PASID_MAPPING
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID1_PASID_MAPPING
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID2_PASID_MAPPING
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID3_PASID_MAPPING
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID4_PASID_MAPPING
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID5_PASID_MAPPING
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID6_PASID_MAPPING
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID7_PASID_MAPPING
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID8_PASID_MAPPING
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID9_PASID_MAPPING
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID10_PASID_MAPPING
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID11_PASID_MAPPING
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID12_PASID_MAPPING
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID13_PASID_MAPPING
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID14_PASID_MAPPING
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID15_PASID_MAPPING
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_ATS_VMID_STATUS
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
+#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10
+#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11
+#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12
+#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13
+#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14
+#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15
+#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16
+#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17
+#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18
+#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19
+#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a
+#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b
+#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c
+#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d
+#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e
+#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L
+#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L
+#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L
+#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L
+#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L
+#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L
+#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L
+#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L
+#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L
+#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L
+#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L
+#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L
+#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L
+#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L
+#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L
+#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L
+#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L
+//ATC_ATS_GFX_ATCL2_STATUS
+#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
+#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
+//ATC_PERFCOUNTER0_CFG
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER1_CFG
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER2_CFG
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER3_CFG
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER_RSLT_CNTL
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//ATC_PERFCOUNTER_LO
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_PERFCOUNTER_HI
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//ATHUB_PCIE_ATS_CNTL
+#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_PASID_CNTL
+#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10
+#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11
+#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12
+#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L
+#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L
+#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L
+//ATHUB_PCIE_PAGE_REQ_CNTL
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L
+//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//ATHUB_COMMAND
+#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L
+//ATHUB_PCIE_ATS_CNTL_VF_0
+#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_1
+#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_2
+#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_3
+#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_4
+#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_5
+#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_6
+#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_7
+#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_8
+#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_9
+#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_10
+#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_11
+#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_12
+#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_13
+#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_14
+#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_15
+#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_MEM_POWER_LS
+#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATS_IH_CREDIT
+#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//ATHUB_IH_CREDIT
+#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//ATC_VMID16_PASID_MAPPING
+#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID17_PASID_MAPPING
+#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID18_PASID_MAPPING
+#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID19_PASID_MAPPING
+#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID20_PASID_MAPPING
+#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID21_PASID_MAPPING
+#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID22_PASID_MAPPING
+#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID23_PASID_MAPPING
+#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID24_PASID_MAPPING
+#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID25_PASID_MAPPING
+#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID26_PASID_MAPPING
+#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID27_PASID_MAPPING
+#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID28_PASID_MAPPING
+#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID29_PASID_MAPPING
+#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID30_PASID_MAPPING
+#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID31_PASID_MAPPING
+#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_ATS_MMHUB_ATCL2_STATUS
+#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
+#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
+//ATHUB_SHARED_VIRT_RESET_REQ
+#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//ATHUB_SHARED_ACTIVE_FCN_ID
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//ATC_ATS_SDPPORT_CNTL
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L
+//ATC_ATS_VMID_SNAPSHOT_GFX_STAT
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L
+//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L
+
+
+// addressBlock: athub_xpbdec
+//XPB_RTR_SRC_APRTR0
+#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR1
+#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR2
+#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR3
+#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR4
+#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR5
+#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR6
+#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR7
+#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR8
+#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR9
+#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR0
+#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR1
+#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR2
+#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR3
+#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_DEST_MAP0
+#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP1
+#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP2
+#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP3
+#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP4
+#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP5
+#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP6
+#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP7
+#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP8
+#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP9
+#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP0
+#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP1
+#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP2
+#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP3
+#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
+//XPB_CLG_CFG0
+#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG1
+#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG2
+#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG3
+#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG4
+#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG5
+#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG6
+#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG7
+#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_EXTRA
+#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb
+#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc
+#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf
+#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15
+#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a
+#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b
+#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L
+#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L
+#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L
+#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L
+#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L
+#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L
+//XPB_CLG_EXTRA_MSK
+#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb
+#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11
+#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L
+#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L
+//XPB_LB_ADDR
+#define XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL
+#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L
+#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L
+#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L
+//XPB_WCB_STS
+#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL
+#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L
+#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L
+//XPB_HST_CFG
+#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0
+#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L
+//XPB_P2P_BAR_CFG
+#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL
+#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L
+#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L
+#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L
+#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L
+#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L
+#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L
+#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L
+#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L
+//XPB_P2P_BAR0
+#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR0__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR1
+#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR1__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR2
+#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR2__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR3
+#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR3__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR4
+#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR4__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR5
+#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR5__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR6
+#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR6__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR7
+#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR7__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR_SETUP
+#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL
+#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR_DELTA_ABOVE
+#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL
+#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L
+//XPB_P2P_BAR_DELTA_BELOW
+#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL
+#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L
+//XPB_PEER_SYS_BAR0
+#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR1
+#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR2
+#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR3
+#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR4
+#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR5
+#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR6
+#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR7
+#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR8
+#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR9
+#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR0
+#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR1
+#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR2
+#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR3
+#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
+//XPB_CLK_GAT
+#define XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL
+#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L
+#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L
+#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L
+#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L
+//XPB_INTF_CFG
+#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL
+#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L
+#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L
+#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L
+#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L
+#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L
+#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L
+#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L
+#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L
+//XPB_INTF_STS
+#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL
+#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L
+#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L
+#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L
+#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L
+#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L
+#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L
+//XPB_PIPE_STS
+#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L
+#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL
+#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L
+#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L
+#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L
+#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L
+#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L
+#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L
+#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L
+#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L
+#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L
+#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L
+#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L
+//XPB_SUB_CTRL
+#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L
+#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L
+#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L
+#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L
+#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L
+#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L
+#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L
+#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L
+#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L
+#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L
+#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L
+#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L
+#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L
+#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L
+#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L
+#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L
+#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L
+#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L
+#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L
+#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L
+//XPB_MAP_INVERT_FLUSH_NUM_LSB
+#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL
+//XPB_PERF_KNOBS
+#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL
+#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L
+#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L
+//XPB_STICKY
+#define XPB_STICKY__BITS__SHIFT 0x0
+#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL
+//XPB_STICKY_W1C
+#define XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL
+//XPB_MISC_CFG
+#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL
+#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L
+#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L
+#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L
+#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L
+//XPB_INTF_CFG2
+#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL
+//XPB_CLG_EXTRA_RD
+#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb
+#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc
+#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf
+#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15
+#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a
+#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b
+#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L
+#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L
+#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L
+#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L
+#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L
+#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L
+//XPB_CLG_EXTRA_MSK_RD
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L
+//XPB_CLG_GFX_MATCH
+#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6
+#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc
+#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12
+#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18
+#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19
+#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a
+#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b
+#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
+#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L
+#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
+#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L
+//XPB_CLG_GFX_MATCH_MSK
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
+//XPB_CLG_MM_MATCH
+#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6
+#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc
+#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12
+#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18
+#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19
+#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a
+#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b
+#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
+#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L
+#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
+#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L
+#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L
+#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L
+#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L
+//XPB_CLG_MM_MATCH_MSK
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
+//XPB_CLG_GFX_UNITID_MAPPING0
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING1
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING2
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING3
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING4
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING5
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING6
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING7
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING0
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING1
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING2
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING3
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+
+
+// addressBlock: athub_rpbdec
+//RPB_PASSPW_CONF
+#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0
+#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3
+#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4
+#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5
+#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6
+#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8
+#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9
+#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11
+#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L
+#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L
+#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L
+#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L
+#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L
+#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L
+#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L
+#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L
+//RPB_BLOCKLEVEL_CONF
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0
+#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2
+#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4
+#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L
+#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL
+#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L
+#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L
+//RPB_TAG_CONF
+#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0
+#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8
+#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10
+#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL
+#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L
+#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L
+//RPB_EFF_CNTL
+#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL
+#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L
+//RPB_ARB_CNTL
+#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0
+#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8
+#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10
+#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18
+#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19
+#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L
+#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L
+#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L
+//RPB_ARB_CNTL2
+#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0
+#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8
+#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10
+#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L
+//RPB_BIF_CNTL
+#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0
+#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8
+#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10
+#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11
+#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12
+#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13
+#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b
+#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c
+#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d
+#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e
+#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L
+#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L
+#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L
+#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L
+#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L
+#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L
+#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L
+#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L
+//RPB_WR_SWITCH_CNTL
+#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
+#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
+#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
+#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
+#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
+#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
+//RPB_RD_SWITCH_CNTL
+#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
+#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
+#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
+#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
+#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
+#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
+//RPB_CID_QUEUE_WR
+#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0
+#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5
+#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb
+#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc
+#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf
+#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12
+#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL
+#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L
+#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L
+#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L
+#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L
+#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L
+//RPB_CID_QUEUE_RD
+#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0
+#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5
+#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb
+#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe
+#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL
+#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L
+#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L
+#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L
+//RPB_CID_QUEUE_EX
+#define RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L
+#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL
+//RPB_CID_QUEUE_EX_DATA
+#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL
+#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L
+//RPB_SWITCH_CNTL2
+#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0
+#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7
+#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe
+#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15
+#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L
+//RPB_DEINTRLV_COMBINE_CNTL
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L
+//RPB_VC_SWITCH_RDWR
+#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0
+#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2
+#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa
+#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L
+#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL
+#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L
+//RPB_PERFCOUNTER_LO
+#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//RPB_PERFCOUNTER_HI
+#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//RPB_PERFCOUNTER0_CFG
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER1_CFG
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER2_CFG
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER3_CFG
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER_RSLT_CNTL
+#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//RPB_RD_QUEUE_CNTL
+#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
+#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
+#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
+#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
+#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
+#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
+#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
+#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
+#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
+#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
+//RPB_RD_QUEUE_CNTL2
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
+//RPB_WR_QUEUE_CNTL
+#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
+#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
+#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
+#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
+#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
+#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
+#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
+#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
+#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
+#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
+//RPB_WR_QUEUE_CNTL2
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
+//RPB_EA_QUEUE_WR
+#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0
+#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5
+#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8
+#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb
+#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL
+#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L
+#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L
+#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L
+//RPB_ATS_CNTL
+#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0
+#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1
+#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2
+#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7
+#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf
+#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13
+#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17
+#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19
+#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L
+#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L
+#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL
+#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L
+#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L
+#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L
+#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L
+#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L
+//RPB_ATS_CNTL2
+#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0
+#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6
+#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc
+#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf
+#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12
+#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL
+#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L
+#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L
+#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L
+#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L
+//RPB_SDPPORT_CNTL
+#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0
+#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5
+#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6
+#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa
+#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf
+#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10
+#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14
+#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b
+#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L
+#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L
+#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
similarity index 99%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
index 663d3af..5bf84c6 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
@@ -436,7 +436,6 @@
#define mmTA_CNTL_DEFAULT 0x8004d850
#define mmTA_CNTL_AUX_DEFAULT 0x00000000
#define mmTA_RESERVED_010C_DEFAULT 0x00000000
-#define mmTA_GRAD_ADJ_DEFAULT 0x40000040
#define mmTA_STATUS_DEFAULT 0x00000000
#define mmTA_SCRATCH_DEFAULT 0x00000000
@@ -1700,7 +1699,6 @@
#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000
#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000
-#define mmDB_RENDER_FILTER_DEFAULT 0x00000000
#define mmDB_Z_INFO2_DEFAULT 0x00000000
#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000
#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000
@@ -1806,8 +1804,6 @@
#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000
#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000
#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000
-#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000
-#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000
#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000
#define mmCB_BLEND_RED_DEFAULT 0x00000000
#define mmCB_BLEND_GREEN_DEFAULT 0x00000000
@@ -2072,7 +2068,6 @@
#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000
#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000
#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000
-#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000
#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000
#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000
#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000
@@ -2490,7 +2485,6 @@
#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000
#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000
#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff
-#define mmVGT_OBJECT_ID_DEFAULT 0x00000000
#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000
#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000
#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000
@@ -2534,7 +2528,6 @@
#define mmSQC_WRITEBACK_DEFAULT 0x00000000
#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000
#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040
#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000
#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000
#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
similarity index 99%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index e6d6171..4ce090d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -841,8 +841,6 @@
#define mmTA_CNTL_AUX_BASE_IDX 0
#define mmTA_RESERVED_010C 0x0543
#define mmTA_RESERVED_010C_BASE_IDX 0
-#define mmTA_GRAD_ADJ 0x0544
-#define mmTA_GRAD_ADJ_BASE_IDX 0
#define mmTA_STATUS 0x0548
#define mmTA_STATUS_BASE_IDX 0
#define mmTA_SCRATCH 0x0564
@@ -3330,8 +3328,6 @@
#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
#define mmDB_DFSM_CONTROL 0x0018
#define mmDB_DFSM_CONTROL_BASE_IDX 1
-#define mmDB_RENDER_FILTER 0x0019
-#define mmDB_RENDER_FILTER_BASE_IDX 1
#define mmDB_Z_INFO2 0x001a
#define mmDB_Z_INFO2_BASE_IDX 1
#define mmDB_STENCIL_INFO2 0x001b
@@ -3542,10 +3538,6 @@
#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
#define mmPA_SC_HORIZ_GRID 0x00ea
#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
-#define mmPA_SC_FOV_WINDOW_LR 0x00eb
-#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1
-#define mmPA_SC_FOV_WINDOW_TB 0x00ec
-#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1
#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
#define mmCB_BLEND_RED 0x0105
@@ -4074,8 +4066,6 @@
#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
-#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7
-#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1
#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
@@ -4908,8 +4898,6 @@
#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1
#define mmIA_MULTI_VGT_PARAM 0x2258
#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1
-#define mmVGT_OBJECT_ID 0x2259
-#define mmVGT_OBJECT_ID_BASE_IDX 1
#define mmVGT_INSTANCE_BASE_ID 0x225a
#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1
#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280
@@ -4996,8 +4984,6 @@
#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1
#define mmTA_CS_BC_BASE_ADDR_HI 0x2381
#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1
-#define mmTA_GRAD_ADJ_UCONFIG 0x2382
-#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1
#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0
#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
#define mmDB_OCCLUSION_COUNT0_HI 0x23c1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
similarity index 99%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
index 5c5e9b4..2e1214b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
@@ -4576,15 +4576,6 @@
//TA_RESERVED_010C
#define TA_RESERVED_010C__Unused__SHIFT 0x0
#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
-//TA_GRAD_ADJ
-#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0
-#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8
-#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10
-#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18
-#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL
-#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L
-#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L
-#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L
//TA_STATUS
#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
@@ -14459,9 +14450,6 @@
#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
-//DB_RENDER_FILTER
-#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0
-#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL
//DB_Z_INFO2
#define DB_Z_INFO2__EPITCH__SHIFT 0x0
#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
@@ -14959,11 +14947,9 @@
#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
-#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8
#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
-#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L
//CP_PERFMON_CNTX_CNTL
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
@@ -15003,20 +14989,6 @@
#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
-//PA_SC_FOV_WINDOW_LR
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L
-//PA_SC_FOV_WINDOW_TB
-#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0
-#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8
-#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL
-#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L
//VGT_MULTI_PRIM_IB_RESET_INDX
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
@@ -17010,13 +16982,11 @@
#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5
#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L
//PA_CL_OBJPRIM_ID_CNTL
#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
@@ -17345,9 +17315,6 @@
#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
-//VGT_INDEX_PAYLOAD_CNTL
-#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0
-#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L
//VGT_INSTANCE_STEP_RATE_0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
@@ -19849,9 +19816,6 @@
#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
-//VGT_OBJECT_ID
-#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0
-#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL
//VGT_INSTANCE_BASE_ID
#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
@@ -20067,15 +20031,6 @@
//TA_CS_BC_BASE_ADDR_HI
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
-//TA_GRAD_ADJ_UCONFIG
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L
//DB_OCCLUSION_COUNT0_LOW
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
similarity index 99%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index db7ef5e..030e002 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -815,8 +815,6 @@
#define mmTA_CNTL_AUX_BASE_IDX 0
#define mmTA_RESERVED_010C 0x0543
#define mmTA_RESERVED_010C_BASE_IDX 0
-#define mmTA_GRAD_ADJ 0x0544
-#define mmTA_GRAD_ADJ_BASE_IDX 0
#define mmTA_STATUS 0x0548
#define mmTA_STATUS_BASE_IDX 0
#define mmTA_SCRATCH 0x0564
@@ -3617,8 +3615,6 @@
#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
#define mmDB_DFSM_CONTROL 0x0018
#define mmDB_DFSM_CONTROL_BASE_IDX 1
-#define mmDB_RENDER_FILTER 0x0019
-#define mmDB_RENDER_FILTER_BASE_IDX 1
#define mmDB_Z_INFO2 0x001a
#define mmDB_Z_INFO2_BASE_IDX 1
#define mmDB_STENCIL_INFO2 0x001b
@@ -3829,10 +3825,6 @@
#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
#define mmPA_SC_HORIZ_GRID 0x00ea
#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
-#define mmPA_SC_FOV_WINDOW_LR 0x00eb
-#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1
-#define mmPA_SC_FOV_WINDOW_TB 0x00ec
-#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1
#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
#define mmCB_BLEND_RED 0x0105
@@ -4361,8 +4353,6 @@
#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
-#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7
-#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1
#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
@@ -5195,8 +5185,6 @@
#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1
#define mmIA_MULTI_VGT_PARAM 0x2258
#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1
-#define mmVGT_OBJECT_ID 0x2259
-#define mmVGT_OBJECT_ID_BASE_IDX 1
#define mmVGT_INSTANCE_BASE_ID 0x225a
#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1
#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280
@@ -5283,8 +5271,6 @@
#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1
#define mmTA_CS_BC_BASE_ADDR_HI 0x2381
#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1
-#define mmTA_GRAD_ADJ_UCONFIG 0x2382
-#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1
#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0
#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
#define mmDB_OCCLUSION_COUNT0_HI 0x23c1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h
new file mode 100644
index 0000000..94325fc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_4_0_OFFSET_HEADER
+#define _hdp_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: hdp_hdpdec
+// base address: 0x3c80
+#define mmHDP_MMHUB_TLVL 0x0000
+#define mmHDP_MMHUB_TLVL_BASE_IDX 0
+#define mmHDP_MMHUB_UNITID 0x0001
+#define mmHDP_MMHUB_UNITID_BASE_IDX 0
+#define mmHDP_NONSURFACE_BASE 0x0040
+#define mmHDP_NONSURFACE_BASE_BASE_IDX 0
+#define mmHDP_NONSURFACE_INFO 0x0041
+#define mmHDP_NONSURFACE_INFO_BASE_IDX 0
+#define mmHDP_NONSURFACE_BASE_HI 0x0042
+#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0
+#define mmHDP_NONSURF_FLAGS 0x00c8
+#define mmHDP_NONSURF_FLAGS_BASE_IDX 0
+#define mmHDP_NONSURF_FLAGS_CLR 0x00c9
+#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
+#define mmHDP_HOST_PATH_CNTL 0x00cc
+#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0
+#define mmHDP_SW_SEMAPHORE 0x00cd
+#define mmHDP_SW_SEMAPHORE_BASE_IDX 0
+#define mmHDP_DEBUG0 0x00ce
+#define mmHDP_DEBUG0_BASE_IDX 0
+#define mmHDP_LAST_SURFACE_HIT 0x00d0
+#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0
+#define mmHDP_READ_CACHE_INVALIDATE 0x00d1
+#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0
+#define mmHDP_OUTSTANDING_REQ 0x00d2
+#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0
+#define mmHDP_MISC_CNTL 0x00d3
+#define mmHDP_MISC_CNTL_BASE_IDX 0
+#define mmHDP_MEM_POWER_LS 0x00d4
+#define mmHDP_MEM_POWER_LS_BASE_IDX 0
+#define mmHDP_MMHUB_CNTL 0x00d5
+#define mmHDP_MMHUB_CNTL_BASE_IDX 0
+#define mmHDP_EDC_CNT 0x00d6
+#define mmHDP_EDC_CNT_BASE_IDX 0
+#define mmHDP_VERSION 0x00d7
+#define mmHDP_VERSION_BASE_IDX 0
+#define mmHDP_CLK_CNTL 0x00d8
+#define mmHDP_CLK_CNTL_BASE_IDX 0
+#define mmHDP_MEMIO_CNTL 0x00f6
+#define mmHDP_MEMIO_CNTL_BASE_IDX 0
+#define mmHDP_MEMIO_ADDR 0x00f7
+#define mmHDP_MEMIO_ADDR_BASE_IDX 0
+#define mmHDP_MEMIO_STATUS 0x00f8
+#define mmHDP_MEMIO_STATUS_BASE_IDX 0
+#define mmHDP_MEMIO_WR_DATA 0x00f9
+#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0
+#define mmHDP_MEMIO_RD_DATA 0x00fa
+#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100
+#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
+#define mmHDP_XDP_D2H_FLUSH 0x0101
+#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0
+#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102
+#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_3 0x0103
+#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_4 0x0104
+#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_5 0x0105
+#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_6 0x0106
+#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_7 0x0107
+#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_8 0x0108
+#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_9 0x0109
+#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_10 0x010a
+#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_11 0x010b
+#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_12 0x010c
+#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_13 0x010d
+#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_14 0x010e
+#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_15 0x010f
+#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_16 0x0110
+#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_17 0x0111
+#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_18 0x0112
+#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_19 0x0113
+#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_20 0x0114
+#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_21 0x0115
+#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_22 0x0116
+#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_23 0x0117
+#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_24 0x0118
+#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_25 0x0119
+#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_26 0x011a
+#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_27 0x011b
+#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_28 0x011c
+#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_29 0x011d
+#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_30 0x011e
+#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_31 0x011f
+#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_32 0x0120
+#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_33 0x0121
+#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_34 0x0122
+#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0
+#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123
+#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR_CFG 0x0124
+#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125
+#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126
+#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127
+#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128
+#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129
+#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a
+#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b
+#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c
+#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d
+#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
+#define mmHDP_XDP_HDP_MC_CFG 0x012e
+#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0
+#define mmHDP_XDP_HST_CFG 0x012f
+#define mmHDP_XDP_HST_CFG_BASE_IDX 0
+#define mmHDP_XDP_HDP_IPH_CFG 0x0131
+#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR0 0x0134
+#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR1 0x0135
+#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR2 0x0136
+#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR3 0x0137
+#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR4 0x0138
+#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR5 0x0139
+#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR6 0x013a
+#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR7 0x013b
+#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0
+#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c
+#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d
+#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
+#define mmHDP_XDP_BUSY_STS 0x013e
+#define mmHDP_XDP_BUSY_STS_BASE_IDX 0
+#define mmHDP_XDP_STICKY 0x013f
+#define mmHDP_XDP_STICKY_BASE_IDX 0
+#define mmHDP_XDP_CHKN 0x0140
+#define mmHDP_XDP_CHKN_BASE_IDX 0
+#define mmHDP_XDP_BARS_ADDR_39_36 0x0144
+#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmHDP_XDP_MMHUB_ERROR 0x0149
+#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
new file mode 100644
index 0000000..25e2869
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
@@ -0,0 +1,601 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_4_0_SH_MASK_HEADER
+#define _hdp_4_0_SH_MASK_HEADER
+
+
+// addressBlock: hdp_hdpdec
+//HDP_MMHUB_TLVL
+#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
+#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
+#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
+#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
+#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
+#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
+#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
+#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
+#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
+#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
+//HDP_MMHUB_UNITID
+#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0
+#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8
+#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
+#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL
+#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L
+#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L
+//HDP_NONSURFACE_BASE
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
+//HDP_NONSURFACE_INFO
+#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
+#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
+#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L
+#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L
+//HDP_NONSURFACE_BASE_HI
+#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
+#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
+//HDP_NONSURF_FLAGS
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
+//HDP_NONSURF_FLAGS_CLR
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
+//HDP_HOST_PATH_CNTL
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
+//HDP_SW_SEMAPHORE
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL
+//HDP_DEBUG0
+#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
+#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL
+//HDP_LAST_SURFACE_HIT
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L
+//HDP_READ_CACHE_INVALIDATE
+#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0
+#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L
+//HDP_OUTSTANDING_REQ
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L
+//HDP_MISC_CNTL
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
+#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
+#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19
+#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a
+#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b
+#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c
+#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d
+#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
+#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
+#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
+#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L
+#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L
+#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L
+#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L
+#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L
+#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L
+#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L
+//HDP_MEM_POWER_LS
+#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
+#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
+#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L
+#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L
+//HDP_MMHUB_CNTL
+#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0
+#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1
+#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2
+#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L
+#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L
+#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L
+//HDP_EDC_CNT
+#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0
+#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2
+#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L
+#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL
+//HDP_VERSION
+#define HDP_VERSION__MINVER__SHIFT 0x0
+#define HDP_VERSION__MAJVER__SHIFT 0x8
+#define HDP_VERSION__REV__SHIFT 0x10
+#define HDP_VERSION__MINVER_MASK 0x000000FFL
+#define HDP_VERSION__MAJVER_MASK 0x0000FF00L
+#define HDP_VERSION__REV_MASK 0x00FF0000L
+//HDP_CLK_CNTL
+#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4
+#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c
+#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
+#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e
+#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
+#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL
+#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L
+#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L
+#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
+#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L
+#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
+//HDP_MEMIO_CNTL
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
+#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
+#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L
+#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L
+//HDP_MEMIO_ADDR
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL
+//HDP_MEMIO_STATUS
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
+//HDP_MEMIO_WR_DATA
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL
+//HDP_MEMIO_RD_DATA
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL
+//HDP_XDP_DIRECT2HDP_FIRST
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_FLUSH
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
+//HDP_XDP_D2H_BAR_UPDATE
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
+//HDP_XDP_D2H_RSVD_3
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_4
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_5
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_6
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_7
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_8
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_9
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_10
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_11
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_12
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_13
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_14
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_15
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_16
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_17
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_18
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_19
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_20
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_21
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_22
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_23
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_24
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_25
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_26
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_27
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_28
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_29
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_30
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_31
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_32
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_33
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_34
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_DIRECT2HDP_LAST
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_P2P_BAR_CFG
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
+//HDP_XDP_P2P_MBX_OFFSET
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL
+//HDP_XDP_P2P_MBX_ADDR0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR2
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR3
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR4
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR5
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR6
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_HDP_MBX_MC_CFG
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L
+//HDP_XDP_HDP_MC_CFG
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L
+//HDP_XDP_HST_CFG
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L
+//HDP_XDP_HDP_IPH_CFG
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
+//HDP_XDP_P2P_BAR0
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR1
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR2
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR3
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR4
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR5
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR6
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR7
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
+//HDP_XDP_FLUSH_ARMED_STS
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL
+//HDP_XDP_FLUSH_CNTR0_STS
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL
+//HDP_XDP_BUSY_STS
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL
+//HDP_XDP_STICKY
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L
+//HDP_XDP_CHKN
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L
+//HDP_XDP_BARS_ADDR_39_36
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L
+//HDP_XDP_MC_VM_FB_LOCATION_BASE
+#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL
+//HDP_XDP_GPU_IOV_VIOLATION_LOG
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//HDP_XDP_MMHUB_ERROR
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h
new file mode 100644
index 0000000..299e526
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_9_0_OFFSET_HEADER
+#define _mp_9_0_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define mmMP0_SMN_C2PMSG_32 0x0060
+#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_33 0x0061
+#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_34 0x0062
+#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_35 0x0063
+#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_36 0x0064
+#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_37 0x0065
+#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_38 0x0066
+#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_39 0x0067
+#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_40 0x0068
+#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_41 0x0069
+#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_42 0x006a
+#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_43 0x006b
+#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_44 0x006c
+#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_45 0x006d
+#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_46 0x006e
+#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_47 0x006f
+#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_48 0x0070
+#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_49 0x0071
+#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_50 0x0072
+#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_51 0x0073
+#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_52 0x0074
+#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_53 0x0075
+#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_54 0x0076
+#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_55 0x0077
+#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_56 0x0078
+#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_57 0x0079
+#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_58 0x007a
+#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_59 0x007b
+#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_60 0x007c
+#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_61 0x007d
+#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_62 0x007e
+#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_63 0x007f
+#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_64 0x0080
+#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_65 0x0081
+#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_66 0x0082
+#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_67 0x0083
+#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_68 0x0084
+#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_69 0x0085
+#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_70 0x0086
+#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_71 0x0087
+#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_72 0x0088
+#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_73 0x0089
+#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_74 0x008a
+#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_75 0x008b
+#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_76 0x008c
+#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_77 0x008d
+#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_78 0x008e
+#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_79 0x008f
+#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_80 0x0090
+#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_81 0x0091
+#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_82 0x0092
+#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_83 0x0093
+#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_84 0x0094
+#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_85 0x0095
+#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_86 0x0096
+#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_87 0x0097
+#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_88 0x0098
+#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_89 0x0099
+#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_90 0x009a
+#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_91 0x009b
+#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_92 0x009c
+#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_93 0x009d
+#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_94 0x009e
+#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_95 0x009f
+#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_96 0x00a0
+#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_97 0x00a1
+#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_98 0x00a2
+#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_99 0x00a3
+#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_100 0x00a4
+#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_101 0x00a5
+#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_102 0x00a6
+#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_103 0x00a7
+#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0
+#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0
+#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmMP0_SMN_IH_CREDIT 0x00c1
+#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0
+#define mmMP0_SMN_IH_SW_INT 0x00c2
+#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0
+#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3
+#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+// base address: 0x0
+#define mmMP1_SMN_ACP2MP_RESP 0x0240
+#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_DC2MP_RESP 0x0241
+#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_UVD2MP_RESP 0x0242
+#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_VCE2MP_RESP 0x0243
+#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_RLC2MP_RESP 0x0244
+#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_32 0x0260
+#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_33 0x0261
+#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_34 0x0262
+#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_35 0x0263
+#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_36 0x0264
+#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_37 0x0265
+#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_38 0x0266
+#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_39 0x0267
+#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_40 0x0268
+#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_41 0x0269
+#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_42 0x026a
+#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_43 0x026b
+#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_44 0x026c
+#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_45 0x026d
+#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_46 0x026e
+#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_47 0x026f
+#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_48 0x0270
+#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_49 0x0271
+#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_50 0x0272
+#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_51 0x0273
+#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_52 0x0274
+#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_53 0x0275
+#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_54 0x0276
+#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_55 0x0277
+#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_56 0x0278
+#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_57 0x0279
+#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_58 0x027a
+#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_59 0x027b
+#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_60 0x027c
+#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_61 0x027d
+#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_62 0x027e
+#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_63 0x027f
+#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_64 0x0280
+#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_65 0x0281
+#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_67 0x0283
+#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_68 0x0284
+#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_69 0x0285
+#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_70 0x0286
+#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_71 0x0287
+#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_72 0x0288
+#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_73 0x0289
+#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_74 0x028a
+#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_75 0x028b
+#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_76 0x028c
+#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_77 0x028d
+#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_78 0x028e
+#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_79 0x028f
+#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_80 0x0290
+#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_81 0x0291
+#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_83 0x0293
+#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_84 0x0294
+#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_85 0x0295
+#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_86 0x0296
+#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_87 0x0297
+#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_88 0x0298
+#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_89 0x0299
+#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_91 0x029b
+#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_92 0x029c
+#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_93 0x029d
+#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_94 0x029e
+#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_95 0x029f
+#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_96 0x02a0
+#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_97 0x02a1
+#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_98 0x02a2
+#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_99 0x02a3
+#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_100 0x02a4
+#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_101 0x02a5
+#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_102 0x02a6
+#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_103 0x02a7
+#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0
+#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0
+#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmMP1_SMN_IH_CREDIT 0x02c1
+#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0
+#define mmMP1_SMN_IH_SW_INT 0x02c2
+#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0
+#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3
+#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
+#define mmMP1_SMN_FPS_CNT 0x02c4
+#define mmMP1_SMN_FPS_CNT_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH0 0x03c0
+#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH1 0x03c1
+#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH2 0x03c2
+#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH3 0x03c3
+#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH4 0x03c4
+#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH5 0x03c5
+#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH6 0x03c6
+#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH7 0x03c7
+#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH8 0x03c8
+#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+// base address: 0x0
+#define mmMP1_SMN_PUB_CTRL 0x02c5
+#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h
new file mode 100644
index 0000000..d5a623d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h
@@ -0,0 +1,1463 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_9_0_SH_MASK_HEADER
+#define _mp_9_0_SH_MASK_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+//MP0_SMN_C2PMSG_32
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_33
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_34
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_35
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_36
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_37
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_38
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_39
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_40
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_41
+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_42
+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_43
+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_44
+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_45
+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_46
+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_47
+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_48
+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_49
+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_50
+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_51
+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_52
+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_53
+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_54
+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_55
+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_56
+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_57
+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_58
+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_59
+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_60
+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_61
+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_62
+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_63
+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_64
+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_65
+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_66
+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_67
+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_68
+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_69
+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_70
+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_71
+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_72
+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_73
+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_74
+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_75
+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_76
+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_77
+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_78
+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_79
+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_80
+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_81
+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_82
+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_83
+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_84
+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_85
+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_86
+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_87
+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_88
+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_89
+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_90
+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_91
+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_92
+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_93
+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_94
+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_95
+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_96
+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_97
+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_98
+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_99
+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_100
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_101
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_102
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_103
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_ACTIVE_FCN_ID
+#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP0_SMN_IH_CREDIT
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP0_SMN_IH_SW_INT
+#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0
+#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1
+#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L
+#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL
+//MP0_SMN_IH_SW_INT_CTRL
+#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
+#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
+#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
+#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+//MP1_SMN_ACP2MP_RESP
+#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_DC2MP_RESP
+#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_UVD2MP_RESP
+#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_VCE2MP_RESP
+#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_RLC2MP_RESP
+#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_32
+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_33
+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_34
+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_35
+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_36
+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_37
+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_38
+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_39
+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_40
+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_41
+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_42
+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_43
+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_44
+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_45
+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_46
+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_47
+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_48
+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_49
+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_50
+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_51
+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_52
+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_53
+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_54
+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_55
+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_56
+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_57
+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_58
+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_59
+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_60
+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_61
+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_62
+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_63
+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_64
+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_65
+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_66
+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_67
+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_68
+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_69
+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_70
+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_71
+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_72
+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_73
+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_74
+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_75
+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_76
+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_77
+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_78
+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_79
+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_80
+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_81
+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_82
+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_83
+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_84
+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_85
+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_86
+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_87
+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_88
+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_89
+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_90
+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_91
+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_92
+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_93
+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_94
+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_95
+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_96
+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_97
+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_98
+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_99
+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_100
+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_101
+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_102
+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_103
+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_ACTIVE_FCN_ID
+#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP1_SMN_IH_CREDIT
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP1_SMN_IH_SW_INT
+#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0
+#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1
+#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L
+#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL
+//MP1_SMN_IH_SW_INT_CTRL
+#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
+#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
+#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
+#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
+//MP1_SMN_FPS_CNT
+#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
+#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH0
+#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH1
+#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH2
+#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH3
+#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH4
+#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH5
+#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH6
+#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH7
+#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH8
+#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
+
+
+
+
+// addressBlock: mp_SmuMp0Pub_CruDec
+//MP0_SOC_INFO
+#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0
+#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2
+#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L
+#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL
+//MP0_PUB_SCRATCH0
+#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP0_PUB_SCRATCH1
+#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP0_PUB_SCRATCH2
+#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP0_PUB_SCRATCH3
+#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP0_FW_INTF
+#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13
+#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L
+//MP0_C2PMSG_0
+#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_1
+#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_2
+#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_3
+#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_4
+#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_5
+#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_6
+#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_7
+#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_8
+#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_9
+#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_10
+#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_11
+#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_12
+#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_13
+#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_14
+#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_15
+#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_16
+#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_17
+#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_18
+#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_19
+#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_20
+#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_21
+#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_22
+#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_23
+#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_24
+#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_25
+#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_26
+#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_27
+#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_28
+#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_29
+#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_30
+#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_31
+#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_0
+#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_1
+#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_2
+#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_3
+#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_INTEN
+#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0
+#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
+//MP0_P2CMSG_INTSTS
+#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP0_C2PMSG_ATTR_0
+#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_1
+#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_2
+#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_3
+#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_4
+#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_5
+#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_6
+#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL
+//MP0_P2CMSG_ATTR
+#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0
+#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
+//MP0_P2SMSG_0
+#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_1
+#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_2
+#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_3
+#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_ATTR
+#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0
+#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
+//MP0_S2PMSG_ATTR
+#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0
+#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L
+//MP0_P2SMSG_INTSTS
+#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP0_S2PMSG_0
+#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0
+#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_32
+#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_33
+#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_34
+#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_35
+#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_36
+#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_37
+#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_38
+#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_39
+#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_40
+#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_41
+#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_42
+#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_43
+#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_44
+#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_45
+#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_46
+#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_47
+#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_48
+#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_49
+#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_50
+#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_51
+#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_52
+#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_53
+#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_54
+#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_55
+#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_56
+#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_57
+#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_58
+#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_59
+#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_60
+#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_61
+#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_62
+#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_63
+#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_64
+#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_65
+#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_66
+#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_67
+#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_68
+#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_69
+#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_70
+#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_71
+#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_72
+#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_73
+#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_74
+#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_75
+#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_76
+#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_77
+#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_78
+#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_79
+#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_80
+#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_81
+#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_82
+#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_83
+#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_84
+#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_85
+#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_86
+#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_87
+#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_88
+#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_89
+#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_90
+#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_91
+#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_92
+#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_93
+#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_94
+#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_95
+#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_96
+#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_97
+#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_98
+#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_99
+#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_100
+#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_101
+#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_102
+#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_103
+#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP0_ACTIVE_FCN_ID
+#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP0_IH_CREDIT
+#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP0_IH_SW_INT
+#define MP0_IH_SW_INT__ID__SHIFT 0x0
+#define MP0_IH_SW_INT__VALID__SHIFT 0x8
+#define MP0_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP0_IH_SW_INT__VALID_MASK 0x00000100L
+//MP0_IH_SW_INT_CTRL
+#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+
+
+//CGTT_DRM_CLK_CTRL0
+#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//DRM_LIGHT_SLEEP_CTRL
+#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0
+#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+//MP1_SMN_PUB_CTRL
+#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0
+#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L
+//MP1_FIRMWARE_FLAGS
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
+//MP1_PUB_SCRATCH0
+#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH1
+#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH2
+#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH3
+#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_0
+#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_1
+#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_2
+#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_3
+#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_4
+#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_5
+#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_6
+#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_7
+#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_8
+#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_9
+#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_10
+#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_11
+#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_12
+#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_13
+#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_14
+#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_15
+#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_16
+#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_17
+#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_18
+#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_19
+#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_20
+#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_21
+#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_22
+#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_23
+#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_24
+#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_25
+#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_26
+#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_27
+#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_28
+#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_29
+#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_30
+#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_31
+#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_0
+#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_1
+#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_2
+#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_3
+#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_INTEN
+#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
+#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
+//MP1_P2CMSG_INTSTS
+#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP1_P2SMSG_0
+#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_1
+#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_2
+#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_3
+#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_INTSTS
+#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP1_S2PMSG_0
+#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
+#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_ACP2MP_RESP
+#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_DC2MP_RESP
+#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_UVD2MP_RESP
+#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_VCE2MP_RESP
+#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_RLC2MP_RESP
+#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_32
+#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_33
+#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_34
+#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_35
+#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_36
+#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_37
+#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_38
+#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_39
+#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_40
+#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_41
+#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_42
+#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_43
+#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_44
+#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_45
+#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_46
+#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_47
+#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_48
+#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_49
+#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_50
+#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_51
+#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_52
+#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_53
+#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_54
+#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_55
+#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_56
+#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_57
+#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_58
+#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_59
+#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_60
+#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_61
+#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_62
+#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_63
+#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_64
+#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_65
+#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_66
+#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_67
+#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_68
+#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_69
+#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_70
+#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_71
+#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_72
+#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_73
+#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_74
+#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_75
+#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_76
+#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_77
+#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_78
+#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_79
+#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_80
+#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_81
+#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_82
+#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_83
+#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_84
+#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_85
+#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_86
+#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_87
+#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_88
+#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_89
+#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_90
+#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_91
+#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_92
+#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_93
+#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_94
+#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_95
+#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_96
+#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_97
+#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_98
+#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_99
+#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_100
+#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_101
+#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_102
+#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_103
+#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_ACTIVE_FCN_ID
+#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP1_IH_CREDIT
+#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP1_IH_SW_INT
+#define MP1_IH_SW_INT__ID__SHIFT 0x0
+#define MP1_IH_SW_INT__VALID__SHIFT 0x8
+#define MP1_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP1_IH_SW_INT__VALID_MASK 0x00000100L
+//MP1_IH_SW_INT_CTRL
+#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+//MP1_FPS_CNT
+#define MP1_FPS_CNT__COUNT__SHIFT 0x0
+#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
+//MP1_PUB_CTRL
+#define MP1_PUB_CTRL__RESET__SHIFT 0x0
+#define MP1_PUB_CTRL__RESET_MASK 0x00000001L
+//MP1_EXT_SCRATCH0
+#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH1
+#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH2
+#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH3
+#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH4
+#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH5
+#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH6
+#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH7
+#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
deleted file mode 100644
index eac125c..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
+++ /dev/null
@@ -1,7988 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _dcn_1_0_DEFAULT_HEADER
-#define _dcn_1_0_DEFAULT_HEADER
-
-
-// addressBlock: dce_dc_hda_azcontroller_azdec
-#define smnAZCONTROLLER0_GLOBAL_CAPABILITIES_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_MINOR_VERSION_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_MAJOR_VERSION_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_WAKE_ENABLE_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_STATE_CHANGE_STATUS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_GLOBAL_STATUS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_STREAM_SYNCHRONIZATION_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_WRITE_POINTER_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_READ_POINTER_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_CONTROL_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_STATUS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_CORB_SIZE_DEFAULT 0x00000002
-#define smnAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_RIRB_WRITE_POINTER_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_RIRB_CONTROL_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_RIRB_STATUS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_RIRB_SIZE_DEFAULT 0x00000002
-#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azendpoint_azdec
-#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azinputendpoint_azdec
-#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azroot_azdec
-#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream0_azdec
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream1_azdec
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream2_azdec
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream3_azdec
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream4_azdec
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream5_azdec
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream6_azdec
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream7_azdec
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
-#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
-#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
-#define mmCRTC8_IDX_DEFAULT 0x00000000
-#define mmCRTC8_DATA_DEFAULT 0x00000000
-#define mmGENFC_WT_DEFAULT 0x00000000
-#define mmGENS1_DEFAULT 0x00000000
-#define mmATTRDW_DEFAULT 0x00000000
-#define mmATTRX_DEFAULT 0x00000000
-#define mmATTRDR_DEFAULT 0x00000000
-#define mmGENMO_WT_DEFAULT 0x00000000
-#define mmGENS0_DEFAULT 0x00000000
-#define mmGENENB_DEFAULT 0x00000000
-#define mmSEQ8_IDX_DEFAULT 0x00000000
-#define mmSEQ8_DATA_DEFAULT 0x00000000
-#define mmDAC_MASK_DEFAULT 0x00000000
-#define mmDAC_R_INDEX_DEFAULT 0x00000000
-#define mmDAC_W_INDEX_DEFAULT 0x00000000
-#define mmDAC_DATA_DEFAULT 0x00000000
-#define mmGENFC_RD_DEFAULT 0x00000000
-#define mmGENMO_RD_DEFAULT 0x00000000
-#define mmGRPH8_IDX_DEFAULT 0x00000000
-#define mmGRPH8_DATA_DEFAULT 0x00000000
-#define mmCRTC8_IDX_1_DEFAULT 0x00000000
-#define mmCRTC8_DATA_1_DEFAULT 0x00000000
-#define mmGENFC_WT_1_DEFAULT 0x00000000
-#define mmGENS1_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azcontroller_azdec
-#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000
-#define mmCORB_READ_POINTER_DEFAULT 0x00000000
-#define mmCORB_CONTROL_DEFAULT 0x00000000
-#define mmCORB_STATUS_DEFAULT 0x00000000
-#define mmCORB_SIZE_DEFAULT 0x00000002
-#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000
-#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000
-#define mmRIRB_CONTROL_DEFAULT 0x00000000
-#define mmRIRB_STATUS_DEFAULT 0x00000000
-#define mmRIRB_SIZE_DEFAULT 0x00000002
-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000
-#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azendpoint_azdec
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azinputendpoint_azdec
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azroot_azdec
-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream0_azdec
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream1_azdec
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream2_azdec
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream3_azdec
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream4_azdec
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream5_azdec
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream6_azdec
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azstream7_azdec
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
-
-
-// addressBlock: dce_dc_mmhubbub_vga_dispdec
-#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f
-#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f
-#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000
-#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002
-#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000
-#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000
-#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000
-#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000
-#define mmD1VGA_CONTROL_DEFAULT 0x00000000
-#define mmD2VGA_CONTROL_DEFAULT 0x00000000
-#define mmVGA_STATUS_DEFAULT 0x00000000
-#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000
-#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018
-#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000
-#define mmVGA_QOS_CTRL_DEFAULT 0x00000000
-#define mmD3VGA_CONTROL_DEFAULT 0x00000000
-#define mmD4VGA_CONTROL_DEFAULT 0x00000000
-#define mmD5VGA_CONTROL_DEFAULT 0x00000000
-#define mmD6VGA_CONTROL_DEFAULT 0x00000000
-#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100
-
-
-// addressBlock: dce_dc_dccg_dccg_dispdec
-#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO_DBUF_EN_DEFAULT 0x00000000
-#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmREFCLK_CNTL_DEFAULT 0x00000000
-#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000
-#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003
-#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000
-#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000
-#define mmDCCG_DS_CNTL_DEFAULT 0x00000000
-#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680
-#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600
-#define mmDPREFCLK_CNTL_DEFAULT 0x00000000
-#define mmAOMCLK0_CNTL_DEFAULT 0x00000000
-#define mmAOMCLK1_CNTL_DEFAULT 0x00000000
-#define mmAOMCLK2_CNTL_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001
-#define mmDCE_VERSION_DEFAULT 0x00000000
-#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000
-#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000
-#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000
-#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000
-#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000
-#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000
-#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000
-#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000
-#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000
-#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000
-#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000
-#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0
-#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028
-#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001
-#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800
-#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee02dd
-#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmSOCCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000
-#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464
-#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x007f007f
-#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000
-#define mmOTG0_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO0_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO0_MODULO_DEFAULT 0x00000000
-#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmOTG1_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO1_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO1_MODULO_DEFAULT 0x00000000
-#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmOTG2_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO2_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO2_MODULO_DEFAULT 0x00000000
-#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmOTG3_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO3_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO3_MODULO_DEFAULT 0x00000000
-#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmOTG4_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO4_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO4_MODULO_DEFAULT 0x00000000
-#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmOTG5_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO5_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO5_MODULO_DEFAULT 0x00000000
-#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDPPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000
-#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100
-#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200
-#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300
-#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400
-#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500
-#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000
-#define mmDVOACLKD_CNTL_DEFAULT 0x00070000
-#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000
-#define mmDVOACLKC_CNTL_DEFAULT 0x00030000
-#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030
-#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001
-#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001
-#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_CNT_CTRL_DEFAULT 0x00000000
-#define mmDCCG_VSYNC_CNT_INT_CTRL_DEFAULT 0x00000000
-#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff
-
-
-// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
-#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064
-
-
-// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
-#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
-#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dccg_dccg_pll_dispdec
-#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmu_rbbmif_dispdec
-#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00
-#define mmRBBMIF_STATUS_DEFAULT 0x00000000
-#define mmRBBMIF_INT_STATUS_DEFAULT 0x80000000
-#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000
-#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmu_dc_pg_dispdec
-#define mmDOMAIN0_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN0_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN1_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN1_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN2_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN2_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN3_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN3_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN4_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN4_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN5_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN5_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN6_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN6_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN7_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN7_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN8_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN8_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN9_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN9_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN10_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN10_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN11_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN11_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN12_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN12_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN13_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN13_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN14_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN14_PG_STATUS_DEFAULT 0x00000000
-#define mmDOMAIN15_PG_CONFIG_DEFAULT 0x00000001
-#define mmDOMAIN15_PG_STATUS_DEFAULT 0x00000000
-#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCPG_INTERRUPT_CONTROL_1_DEFAULT 0x00000000
-#define mmDCPG_INTERRUPT_CONTROL_2_DEFAULT 0x00000000
-#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000
-#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmu_dmu_misc_dispdec
-#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000
-#define mmDMU_CLK_CNTL_DEFAULT 0x00000000
-#define mmDMU_MEM_PWR_CNTL_DEFAULT 0x00000000
-#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmu_dmcu_dispdec
-#define mmDMCU_CTRL_DEFAULT 0xffff0101
-#define mmDMCU_STATUS_DEFAULT 0x00000001
-#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000
-#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000
-#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000
-#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004
-#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000
-#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000
-#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000
-#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000
-#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000
-#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000
-#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000
-#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000
-#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000
-#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000
-#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000
-#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000
-#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000
-#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000
-#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000
-#define mmDMCU_INT_CNT_DEFAULT 0x00000000
-#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000
-#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102
-#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000
-#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000
-#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000
-#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000
-#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000
-#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000
-#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000
-#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000
-#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000
-#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000
-#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000
-#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
-#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_DEFAULT 0x00000000
-#define mmDMCU_INT_CNT_CONTINUE_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmu_ihc_dispdec
-#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE12_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE13_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE14_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE15_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE16_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE17_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE18_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE19_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE20_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE21_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE22_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_VREADY_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_FLIP_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
-#define mmCNV0_WB_ENABLE_DEFAULT 0x00000000
-#define mmCNV0_WB_EC_CONFIG_DEFAULT 0x55000000
-#define mmCNV0_CNV_MODE_DEFAULT 0x00000000
-#define mmCNV0_CNV_WINDOW_START_DEFAULT 0x00000000
-#define mmCNV0_CNV_WINDOW_SIZE_DEFAULT 0x00100010
-#define mmCNV0_CNV_UPDATE_DEFAULT 0x00000000
-#define mmCNV0_CNV_SOURCE_SIZE_DEFAULT 0x00100010
-#define mmCNV0_CNV_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_C11_C12_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_C13_C14_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_C21_C22_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_C23_C24_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_C31_C32_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_C33_C34_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000
-#define mmCNV0_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff
-#define mmCNV0_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff
-#define mmCNV0_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff
-#define mmCNV0_CNV_TEST_CNTL_DEFAULT 0x00000000
-#define mmCNV0_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0
-#define mmCNV0_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0
-#define mmCNV0_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0
-#define mmCNV0_CNV_INPUT_SELECT_DEFAULT 0x00000001
-#define mmCNV0_WB_SOFT_RESET_DEFAULT 0x00000000
-#define mmCNV0_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100
-#define mmCNV0_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100
-
-
-// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
-#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_MODE_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_TAP_CONTROL_DEFAULT 0x00001111
-#define mmWBSCL0_WBSCL_DEST_SIZE_DEFAULT 0x00010001
-#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000
-#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
-#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000
-#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000
-#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
-#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000
-#define mmWBSCL0_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010
-#define mmWBSCL0_WBSCL_CLAMP_DEFAULT 0x01fe01fe
-#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000
-#define mmWBSCL0_WBSCL_TEST_CNTL_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00
-#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff
-#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00
-#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000
-#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000
-#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec
-#define mmCNV1_WB_ENABLE_DEFAULT 0x00000000
-#define mmCNV1_WB_EC_CONFIG_DEFAULT 0x55000000
-#define mmCNV1_CNV_MODE_DEFAULT 0x00000000
-#define mmCNV1_CNV_WINDOW_START_DEFAULT 0x00000000
-#define mmCNV1_CNV_WINDOW_SIZE_DEFAULT 0x00100010
-#define mmCNV1_CNV_UPDATE_DEFAULT 0x00000000
-#define mmCNV1_CNV_SOURCE_SIZE_DEFAULT 0x00100010
-#define mmCNV1_CNV_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_C11_C12_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_C13_C14_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_C21_C22_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_C23_C24_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_C31_C32_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_C33_C34_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000
-#define mmCNV1_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff
-#define mmCNV1_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff
-#define mmCNV1_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff
-#define mmCNV1_CNV_TEST_CNTL_DEFAULT 0x00000000
-#define mmCNV1_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0
-#define mmCNV1_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0
-#define mmCNV1_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0
-#define mmCNV1_CNV_INPUT_SELECT_DEFAULT 0x00000001
-#define mmCNV1_WB_SOFT_RESET_DEFAULT 0x00000000
-#define mmCNV1_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100
-#define mmCNV1_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100
-
-
-// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec
-#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_MODE_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_TAP_CONTROL_DEFAULT 0x00001111
-#define mmWBSCL1_WBSCL_DEST_SIZE_DEFAULT 0x00010001
-#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000
-#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
-#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000
-#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000
-#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
-#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000
-#define mmWBSCL1_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010
-#define mmWBSCL1_WBSCL_CLAMP_DEFAULT 0x01fe01fe
-#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000
-#define mmWBSCL1_WBSCL_TEST_CNTL_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00
-#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff
-#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00
-#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000
-#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000
-#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
-#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
-#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
-#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
-#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
-#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
-
-
-// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
-#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
-#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
-#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
-#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
-#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
-
-
-// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
-#define mmWBIF0_MISC_CTRL_DEFAULT 0x00010001
-#define mmWBIF0_SMU_WM_CONTROL_DEFAULT 0x00000000
-#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmWBIF1_MISC_CTRL_DEFAULT 0x00010001
-#define mmWBIF1_SMU_WM_CONTROL_DEFAULT 0x00000000
-#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmVGA_SRC_SPLIT_CNTL_DEFAULT 0x00000000
-#define mmMMHUBBUB_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmMMHUBBUB_MEM_PWR_CNTL_DEFAULT 0x0000c180
-#define mmMMHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000
-#define mmMMHUBBUB_SOFT_RESET_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
-#define mmMCIF_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080
-#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream0_dispdec
-#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream1_dispdec
-#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream2_dispdec
-#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream3_dispdec
-#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream4_dispdec
-#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream5_dispdec
-#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream6_dispdec
-#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream7_dispdec
-#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_az_misc_dispdec
-#define mmAZ_CLOCK_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0controller_dispdec
-#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000
-#define mmAZALIA_AUDIO_DTO_DEFAULT 0x00300018
-#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001
-#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000
-#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a
-#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a
-#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000
-#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000
-#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000
-#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060
-#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008
-#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080
-#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0root_dispdec
-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01
-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700
-#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
-#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000
-#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream8_dispdec
-#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream9_dispdec
-#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream10_dispdec
-#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream11_dispdec
-#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream12_dispdec
-#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream13_dispdec
-#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream14_dispdec
-#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0stream15_dispdec
-#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
-#define mmDCHUBBUB_SDPIF_CFG0_DEFAULT 0x00cd3001
-#define mmDCHUBBUB_SDPIF_CFG1_DEFAULT 0x0000005c
-#define mmDCHUBBUB_FORCE_IO_STATUS_0_DEFAULT 0x00000002
-#define mmDCHUBBUB_FORCE_IO_STATUS_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_FB_BASE_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_FB_TOP_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_FB_OFFSET_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_AGP_BOT_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_AGP_TOP_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_AGP_BASE_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_APER_BASE_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_APER_TOP_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_APER_DEF_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_APER_DEF_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
-#define mmDCHUBBUB_RET_PATH_DCC_CFG_DEFAULT 0x00000001
-#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCHUBBUB_CRC_CTRL_DEFAULT 0x00000000
-#define mmDCHUBBUB_CRC0_VAL_R_G_DEFAULT 0x00000000
-#define mmDCHUBBUB_CRC0_VAL_B_A_DEFAULT 0x00000000
-#define mmDCHUBBUB_CRC1_VAL_R_G_DEFAULT 0x00000000
-#define mmDCHUBBUB_CRC1_VAL_B_A_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dchubbub_hubbub_dispdec
-#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_DEFAULT 0x01000100
-#define mmDCHUBBUB_ARB_SAT_LEVEL_DEFAULT 0xffffffff
-#define mmDCHUBBUB_ARB_QOS_FORCE_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_DEFAULT 0x00000000
-#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_DEFAULT 0x00000010
-#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_DEFAULT 0x00000000
-#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_DEFAULT 0x00000000
-#define mmSURFACE_CHECK0_ADDRESS_LSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK0_ADDRESS_MSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK1_ADDRESS_LSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK1_ADDRESS_MSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK2_ADDRESS_LSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK2_ADDRESS_MSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK3_ADDRESS_LSB_DEFAULT 0x00000000
-#define mmSURFACE_CHECK3_ADDRESS_MSB_DEFAULT 0x00000000
-#define mmVTG0_CONTROL_DEFAULT 0x00000000
-#define mmVTG1_CONTROL_DEFAULT 0x00000000
-#define mmVTG2_CONTROL_DEFAULT 0x00000000
-#define mmVTG3_CONTROL_DEFAULT 0x00000000
-#define mmVTG4_CONTROL_DEFAULT 0x00000000
-#define mmVTG5_CONTROL_DEFAULT 0x00000000
-#define mmDCHUBBUB_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000
-#define mmDCFCLK_CNTL_DEFAULT 0x80000200
-#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_DEFAULT 0x00000000
-#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_DEFAULT 0x00000000
-#define mmDCHUBBUB_VLINE_SNAPSHOT_DEFAULT 0x00000000
-#define mmDCHUBBUB_SPARE_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
-#define mmHUBP0_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008
-#define mmHUBP0_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_TILING_CONFIG_DEFAULT 0x00000080
-#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000
-#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000
-#define mmHUBP0_DCHUBP_CNTL_DEFAULT 0x00001001
-#define mmHUBP0_HUBP_CLK_CNTL_DEFAULT 0x00000000
-#define mmHUBP0_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000
-#define mmHUBP0_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000
-#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000
-#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
-#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040
-#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000
-#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_EXPANSION_MODE_DEFAULT 0x00000055
-#define mmHUBPREQ0_DCN_TTU_QOS_WM_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010
-#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ0_BLANK_OFFSET_0_DEFAULT 0x00000000
-#define mmHUBPREQ0_BLANK_OFFSET_1_DEFAULT 0x00000000
-#define mmHUBPREQ0_DST_DIMENSIONS_DEFAULT 0x00000000
-#define mmHUBPREQ0_DST_AFTER_SCALER_DEFAULT 0x00000000
-#define mmHUBPREQ0_PREFETCH_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ0_PREFETCH_SETTINS_C_DEFAULT 0x00000000
-#define mmHUBPREQ0_VBLANK_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ0_VBLANK_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ0_VBLANK_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ0_VBLANK_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ0_VBLANK_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_5_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_6_DEFAULT 0x00000000
-#define mmHUBPREQ0_NOM_PARAMETERS_7_DEFAULT 0x00000000
-#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000
-#define mmHUBPREQ0_PER_LINE_DELIVERY_DEFAULT 0x00000000
-#define mmHUBPREQ0_CURSOR_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000
-#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
-#define mmHUBPRET0_HUBPRET_CONTROL_DEFAULT 0x00e40000
-#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_READ_LINE0_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_READ_LINE1_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000
-#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421
-
-
-// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec
-#define mmCURSOR0_CURSOR_CONTROL_DEFAULT 0x01000000
-#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_SIZE_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_POSITION_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_HOT_SPOT_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_DST_OFFSET_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
-#define mmHUBP1_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008
-#define mmHUBP1_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_TILING_CONFIG_DEFAULT 0x00000080
-#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000
-#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000
-#define mmHUBP1_DCHUBP_CNTL_DEFAULT 0x00001001
-#define mmHUBP1_HUBP_CLK_CNTL_DEFAULT 0x00000000
-#define mmHUBP1_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000
-#define mmHUBP1_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000
-#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000
-#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
-#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040
-#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000
-#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_EXPANSION_MODE_DEFAULT 0x00000055
-#define mmHUBPREQ1_DCN_TTU_QOS_WM_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010
-#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ1_BLANK_OFFSET_0_DEFAULT 0x00000000
-#define mmHUBPREQ1_BLANK_OFFSET_1_DEFAULT 0x00000000
-#define mmHUBPREQ1_DST_DIMENSIONS_DEFAULT 0x00000000
-#define mmHUBPREQ1_DST_AFTER_SCALER_DEFAULT 0x00000000
-#define mmHUBPREQ1_PREFETCH_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ1_PREFETCH_SETTINS_C_DEFAULT 0x00000000
-#define mmHUBPREQ1_VBLANK_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ1_VBLANK_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ1_VBLANK_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ1_VBLANK_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ1_VBLANK_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_5_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_6_DEFAULT 0x00000000
-#define mmHUBPREQ1_NOM_PARAMETERS_7_DEFAULT 0x00000000
-#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000
-#define mmHUBPREQ1_PER_LINE_DELIVERY_DEFAULT 0x00000000
-#define mmHUBPREQ1_CURSOR_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000
-#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
-#define mmHUBPRET1_HUBPRET_CONTROL_DEFAULT 0x00e40000
-#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_READ_LINE0_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_READ_LINE1_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000
-#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421
-
-
-// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec
-#define mmCURSOR1_CURSOR_CONTROL_DEFAULT 0x01000000
-#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_SIZE_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_POSITION_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_HOT_SPOT_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_DST_OFFSET_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
-#define mmHUBP2_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008
-#define mmHUBP2_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_TILING_CONFIG_DEFAULT 0x00000080
-#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000
-#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000
-#define mmHUBP2_DCHUBP_CNTL_DEFAULT 0x00001001
-#define mmHUBP2_HUBP_CLK_CNTL_DEFAULT 0x00000000
-#define mmHUBP2_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000
-#define mmHUBP2_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000
-#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000
-#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
-#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040
-#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000
-#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_EXPANSION_MODE_DEFAULT 0x00000055
-#define mmHUBPREQ2_DCN_TTU_QOS_WM_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010
-#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ2_BLANK_OFFSET_0_DEFAULT 0x00000000
-#define mmHUBPREQ2_BLANK_OFFSET_1_DEFAULT 0x00000000
-#define mmHUBPREQ2_DST_DIMENSIONS_DEFAULT 0x00000000
-#define mmHUBPREQ2_DST_AFTER_SCALER_DEFAULT 0x00000000
-#define mmHUBPREQ2_PREFETCH_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ2_PREFETCH_SETTINS_C_DEFAULT 0x00000000
-#define mmHUBPREQ2_VBLANK_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ2_VBLANK_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ2_VBLANK_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ2_VBLANK_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ2_VBLANK_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_5_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_6_DEFAULT 0x00000000
-#define mmHUBPREQ2_NOM_PARAMETERS_7_DEFAULT 0x00000000
-#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000
-#define mmHUBPREQ2_PER_LINE_DELIVERY_DEFAULT 0x00000000
-#define mmHUBPREQ2_CURSOR_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000
-#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
-#define mmHUBPRET2_HUBPRET_CONTROL_DEFAULT 0x00e40000
-#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_READ_LINE0_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_READ_LINE1_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000
-#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421
-
-
-// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec
-#define mmCURSOR2_CURSOR_CONTROL_DEFAULT 0x01000000
-#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_SIZE_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_POSITION_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_HOT_SPOT_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_DST_OFFSET_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
-#define mmHUBP3_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008
-#define mmHUBP3_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_TILING_CONFIG_DEFAULT 0x00000080
-#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000
-#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000
-#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000
-#define mmHUBP3_DCHUBP_CNTL_DEFAULT 0x00001001
-#define mmHUBP3_HUBP_CLK_CNTL_DEFAULT 0x00000000
-#define mmHUBP3_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000
-#define mmHUBP3_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000
-#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000
-#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
-#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040
-#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000
-#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_EXPANSION_MODE_DEFAULT 0x00000055
-#define mmHUBPREQ3_DCN_TTU_QOS_WM_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010
-#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000
-#define mmHUBPREQ3_BLANK_OFFSET_0_DEFAULT 0x00000000
-#define mmHUBPREQ3_BLANK_OFFSET_1_DEFAULT 0x00000000
-#define mmHUBPREQ3_DST_DIMENSIONS_DEFAULT 0x00000000
-#define mmHUBPREQ3_DST_AFTER_SCALER_DEFAULT 0x00000000
-#define mmHUBPREQ3_PREFETCH_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ3_PREFETCH_SETTINS_C_DEFAULT 0x00000000
-#define mmHUBPREQ3_VBLANK_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ3_VBLANK_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ3_VBLANK_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ3_VBLANK_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ3_VBLANK_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_0_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_1_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_2_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_3_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_4_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_5_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_6_DEFAULT 0x00000000
-#define mmHUBPREQ3_NOM_PARAMETERS_7_DEFAULT 0x00000000
-#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000
-#define mmHUBPREQ3_PER_LINE_DELIVERY_DEFAULT 0x00000000
-#define mmHUBPREQ3_CURSOR_SETTINS_DEFAULT 0x00000000
-#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000
-#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
-#define mmHUBPRET3_HUBPRET_CONTROL_DEFAULT 0x00e40000
-#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_READ_LINE0_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_READ_LINE1_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_INTERRUPT_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000
-#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421
-
-
-// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec
-#define mmCURSOR3_CURSOR_CONTROL_DEFAULT 0x01000000
-#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_SIZE_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_POSITION_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_HOT_SPOT_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_DST_OFFSET_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
-#define mmDPP_TOP0_DPP_CONTROL_DEFAULT 0x70000000
-#define mmDPP_TOP0_DPP_SOFT_RESET_DEFAULT 0x00000000
-#define mmDPP_TOP0_DPP_CRC_VAL_R_G_DEFAULT 0x00000000
-#define mmDPP_TOP0_DPP_CRC_VAL_B_A_DEFAULT 0x00000000
-#define mmDPP_TOP0_DPP_CRC_CTRL_DEFAULT 0x00000000
-#define mmDPP_TOP0_HOST_READ_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
-#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008
-#define mmCNVC_CFG0_FORMAT_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00
-#define mmCNVC_CFG0_DENORM_CONTROL_DEFAULT 0x00002000
-#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_DEFAULT 0x00000000
-#define mmCNVC_CFG0_COLOR_KEYER_RED_DEFAULT 0x00000000
-#define mmCNVC_CFG0_COLOR_KEYER_GREEN_DEFAULT 0x00000000
-#define mmCNVC_CFG0_COLOR_KEYER_BLUE_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
-#define mmCNVC_CUR0_CURSOR0_CONTROL_DEFAULT 0x0003ff00
-#define mmCNVC_CUR0_CURSOR0_COLOR0_DEFAULT 0x00000000
-#define mmCNVC_CUR0_CURSOR0_COLOR1_DEFAULT 0x00000000
-#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00
-
-
-// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
-#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000
-#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmDSCL0_SCL_MODE_DEFAULT 0x00000000
-#define mmDSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_CONTROL_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_2TAP_CONTROL_DEFAULT 0x01000100
-#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL0_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-#define mmDSCL0_SCL_BLACK_OFFSET_DEFAULT 0x80000000
-#define mmDSCL0_DSCL_UPDATE_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_AUTOCAL_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmDSCL0_OTG_H_BLANK_DEFAULT 0x00000000
-#define mmDSCL0_OTG_V_BLANK_DEFAULT 0x00000000
-#define mmDSCL0_RECOUT_START_DEFAULT 0x00000000
-#define mmDSCL0_RECOUT_SIZE_DEFAULT 0x00000000
-#define mmDSCL0_MPC_SIZE_DEFAULT 0x00000000
-#define mmDSCL0_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmDSCL0_LB_MEMORY_CTRL_DEFAULT 0x00003f00
-#define mmDSCL0_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDSCL0_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDSCL0_OBUF_CONTROL_DEFAULT 0xe0000000
-#define mmDSCL0_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
-#define mmCM0_CM_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_COMA_C11_C12_DEFAULT 0x00002000
-#define mmCM0_CM_COMA_C13_C14_DEFAULT 0x00000000
-#define mmCM0_CM_COMA_C21_C22_DEFAULT 0x20000000
-#define mmCM0_CM_COMA_C23_C24_DEFAULT 0x00000000
-#define mmCM0_CM_COMA_C31_C32_DEFAULT 0x00000000
-#define mmCM0_CM_COMA_C33_C34_DEFAULT 0x00002000
-#define mmCM0_CM_COMB_C11_C12_DEFAULT 0x00002000
-#define mmCM0_CM_COMB_C13_C14_DEFAULT 0x00000000
-#define mmCM0_CM_COMB_C21_C22_DEFAULT 0x20000000
-#define mmCM0_CM_COMB_C23_C24_DEFAULT 0x00000000
-#define mmCM0_CM_COMB_C31_C32_DEFAULT 0x00000000
-#define mmCM0_CM_COMB_C33_C34_DEFAULT 0x00002000
-#define mmCM0_CM_IGAM_CONTROL_DEFAULT 0x08000002
-#define mmCM0_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070
-#define mmCM0_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmCM0_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmCM0_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmCM0_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000
-#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000
-#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000
-#define mmCM0_CM_ICSC_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_ICSC_C11_C12_DEFAULT 0x00002000
-#define mmCM0_CM_ICSC_C13_C14_DEFAULT 0x00000000
-#define mmCM0_CM_ICSC_C21_C22_DEFAULT 0x20000000
-#define mmCM0_CM_ICSC_C23_C24_DEFAULT 0x00000000
-#define mmCM0_CM_ICSC_C31_C32_DEFAULT 0x00000000
-#define mmCM0_CM_ICSC_C33_C34_DEFAULT 0x00002000
-#define mmCM0_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmCM0_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmCM0_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmCM0_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmCM0_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmCM0_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmCM0_CM_OCSC_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_OCSC_C11_C12_DEFAULT 0x00002000
-#define mmCM0_CM_OCSC_C13_C14_DEFAULT 0x00000000
-#define mmCM0_CM_OCSC_C21_C22_DEFAULT 0x20000000
-#define mmCM0_CM_OCSC_C23_C24_DEFAULT 0x00000000
-#define mmCM0_CM_OCSC_C31_C32_DEFAULT 0x00000000
-#define mmCM0_CM_OCSC_C33_C34_DEFAULT 0x00002000
-#define mmCM0_CM_BNS_VALUES_R_DEFAULT 0x20000000
-#define mmCM0_CM_BNS_VALUES_G_DEFAULT 0x20000000
-#define mmCM0_CM_BNS_VALUES_B_DEFAULT 0x20000000
-#define mmCM0_CM_DGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM0_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000
-#define mmCM0_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000
-#define mmCM0_CM_HDR_MULT_COEF_DEFAULT 0x0001f000
-#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff
-#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff
-#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff
-#define mmCM0_CM_DENORM_CONTROL_DEFAULT 0x00000000
-#define mmCM0_CM_CMOUT_CONTROL_DEFAULT 0x0000000a
-#define mmCM0_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmCM0_CM_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCM0_CM_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
-#define mmDPP_TOP1_DPP_CONTROL_DEFAULT 0x70000000
-#define mmDPP_TOP1_DPP_SOFT_RESET_DEFAULT 0x00000000
-#define mmDPP_TOP1_DPP_CRC_VAL_R_G_DEFAULT 0x00000000
-#define mmDPP_TOP1_DPP_CRC_VAL_B_A_DEFAULT 0x00000000
-#define mmDPP_TOP1_DPP_CRC_CTRL_DEFAULT 0x00000000
-#define mmDPP_TOP1_HOST_READ_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
-#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008
-#define mmCNVC_CFG1_FORMAT_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00
-#define mmCNVC_CFG1_DENORM_CONTROL_DEFAULT 0x00002000
-#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_DEFAULT 0x00000000
-#define mmCNVC_CFG1_COLOR_KEYER_RED_DEFAULT 0x00000000
-#define mmCNVC_CFG1_COLOR_KEYER_GREEN_DEFAULT 0x00000000
-#define mmCNVC_CFG1_COLOR_KEYER_BLUE_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
-#define mmCNVC_CUR1_CURSOR0_CONTROL_DEFAULT 0x0003ff00
-#define mmCNVC_CUR1_CURSOR0_COLOR0_DEFAULT 0x00000000
-#define mmCNVC_CUR1_CURSOR0_COLOR1_DEFAULT 0x00000000
-#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00
-
-
-// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
-#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000
-#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmDSCL1_SCL_MODE_DEFAULT 0x00000000
-#define mmDSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_CONTROL_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_2TAP_CONTROL_DEFAULT 0x01000100
-#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL1_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-#define mmDSCL1_SCL_BLACK_OFFSET_DEFAULT 0x80000000
-#define mmDSCL1_DSCL_UPDATE_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_AUTOCAL_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmDSCL1_OTG_H_BLANK_DEFAULT 0x00000000
-#define mmDSCL1_OTG_V_BLANK_DEFAULT 0x00000000
-#define mmDSCL1_RECOUT_START_DEFAULT 0x00000000
-#define mmDSCL1_RECOUT_SIZE_DEFAULT 0x00000000
-#define mmDSCL1_MPC_SIZE_DEFAULT 0x00000000
-#define mmDSCL1_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmDSCL1_LB_MEMORY_CTRL_DEFAULT 0x00003f00
-#define mmDSCL1_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDSCL1_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDSCL1_OBUF_CONTROL_DEFAULT 0xe0000000
-#define mmDSCL1_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
-#define mmCM1_CM_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_COMA_C11_C12_DEFAULT 0x00002000
-#define mmCM1_CM_COMA_C13_C14_DEFAULT 0x00000000
-#define mmCM1_CM_COMA_C21_C22_DEFAULT 0x20000000
-#define mmCM1_CM_COMA_C23_C24_DEFAULT 0x00000000
-#define mmCM1_CM_COMA_C31_C32_DEFAULT 0x00000000
-#define mmCM1_CM_COMA_C33_C34_DEFAULT 0x00002000
-#define mmCM1_CM_COMB_C11_C12_DEFAULT 0x00002000
-#define mmCM1_CM_COMB_C13_C14_DEFAULT 0x00000000
-#define mmCM1_CM_COMB_C21_C22_DEFAULT 0x20000000
-#define mmCM1_CM_COMB_C23_C24_DEFAULT 0x00000000
-#define mmCM1_CM_COMB_C31_C32_DEFAULT 0x00000000
-#define mmCM1_CM_COMB_C33_C34_DEFAULT 0x00002000
-#define mmCM1_CM_IGAM_CONTROL_DEFAULT 0x08000002
-#define mmCM1_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070
-#define mmCM1_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmCM1_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmCM1_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmCM1_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000
-#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000
-#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000
-#define mmCM1_CM_ICSC_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_ICSC_C11_C12_DEFAULT 0x00002000
-#define mmCM1_CM_ICSC_C13_C14_DEFAULT 0x00000000
-#define mmCM1_CM_ICSC_C21_C22_DEFAULT 0x20000000
-#define mmCM1_CM_ICSC_C23_C24_DEFAULT 0x00000000
-#define mmCM1_CM_ICSC_C31_C32_DEFAULT 0x00000000
-#define mmCM1_CM_ICSC_C33_C34_DEFAULT 0x00002000
-#define mmCM1_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmCM1_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmCM1_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmCM1_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmCM1_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmCM1_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmCM1_CM_OCSC_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_OCSC_C11_C12_DEFAULT 0x00002000
-#define mmCM1_CM_OCSC_C13_C14_DEFAULT 0x00000000
-#define mmCM1_CM_OCSC_C21_C22_DEFAULT 0x20000000
-#define mmCM1_CM_OCSC_C23_C24_DEFAULT 0x00000000
-#define mmCM1_CM_OCSC_C31_C32_DEFAULT 0x00000000
-#define mmCM1_CM_OCSC_C33_C34_DEFAULT 0x00002000
-#define mmCM1_CM_BNS_VALUES_R_DEFAULT 0x20000000
-#define mmCM1_CM_BNS_VALUES_G_DEFAULT 0x20000000
-#define mmCM1_CM_BNS_VALUES_B_DEFAULT 0x20000000
-#define mmCM1_CM_DGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM1_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000
-#define mmCM1_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000
-#define mmCM1_CM_HDR_MULT_COEF_DEFAULT 0x0001f000
-#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff
-#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff
-#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff
-#define mmCM1_CM_DENORM_CONTROL_DEFAULT 0x00000000
-#define mmCM1_CM_CMOUT_CONTROL_DEFAULT 0x0000000a
-#define mmCM1_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmCM1_CM_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCM1_CM_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
-#define mmDPP_TOP2_DPP_CONTROL_DEFAULT 0x70000000
-#define mmDPP_TOP2_DPP_SOFT_RESET_DEFAULT 0x00000000
-#define mmDPP_TOP2_DPP_CRC_VAL_R_G_DEFAULT 0x00000000
-#define mmDPP_TOP2_DPP_CRC_VAL_B_A_DEFAULT 0x00000000
-#define mmDPP_TOP2_DPP_CRC_CTRL_DEFAULT 0x00000000
-#define mmDPP_TOP2_HOST_READ_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
-#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008
-#define mmCNVC_CFG2_FORMAT_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00
-#define mmCNVC_CFG2_DENORM_CONTROL_DEFAULT 0x00002000
-#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_DEFAULT 0x00000000
-#define mmCNVC_CFG2_COLOR_KEYER_RED_DEFAULT 0x00000000
-#define mmCNVC_CFG2_COLOR_KEYER_GREEN_DEFAULT 0x00000000
-#define mmCNVC_CFG2_COLOR_KEYER_BLUE_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
-#define mmCNVC_CUR2_CURSOR0_CONTROL_DEFAULT 0x0003ff00
-#define mmCNVC_CUR2_CURSOR0_COLOR0_DEFAULT 0x00000000
-#define mmCNVC_CUR2_CURSOR0_COLOR1_DEFAULT 0x00000000
-#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00
-
-
-// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
-#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000
-#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmDSCL2_SCL_MODE_DEFAULT 0x00000000
-#define mmDSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_CONTROL_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_2TAP_CONTROL_DEFAULT 0x01000100
-#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL2_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-#define mmDSCL2_SCL_BLACK_OFFSET_DEFAULT 0x80000000
-#define mmDSCL2_DSCL_UPDATE_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_AUTOCAL_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmDSCL2_OTG_H_BLANK_DEFAULT 0x00000000
-#define mmDSCL2_OTG_V_BLANK_DEFAULT 0x00000000
-#define mmDSCL2_RECOUT_START_DEFAULT 0x00000000
-#define mmDSCL2_RECOUT_SIZE_DEFAULT 0x00000000
-#define mmDSCL2_MPC_SIZE_DEFAULT 0x00000000
-#define mmDSCL2_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmDSCL2_LB_MEMORY_CTRL_DEFAULT 0x00003f00
-#define mmDSCL2_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDSCL2_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDSCL2_OBUF_CONTROL_DEFAULT 0xe0000000
-#define mmDSCL2_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
-#define mmCM2_CM_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_COMA_C11_C12_DEFAULT 0x00002000
-#define mmCM2_CM_COMA_C13_C14_DEFAULT 0x00000000
-#define mmCM2_CM_COMA_C21_C22_DEFAULT 0x20000000
-#define mmCM2_CM_COMA_C23_C24_DEFAULT 0x00000000
-#define mmCM2_CM_COMA_C31_C32_DEFAULT 0x00000000
-#define mmCM2_CM_COMA_C33_C34_DEFAULT 0x00002000
-#define mmCM2_CM_COMB_C11_C12_DEFAULT 0x00002000
-#define mmCM2_CM_COMB_C13_C14_DEFAULT 0x00000000
-#define mmCM2_CM_COMB_C21_C22_DEFAULT 0x20000000
-#define mmCM2_CM_COMB_C23_C24_DEFAULT 0x00000000
-#define mmCM2_CM_COMB_C31_C32_DEFAULT 0x00000000
-#define mmCM2_CM_COMB_C33_C34_DEFAULT 0x00002000
-#define mmCM2_CM_IGAM_CONTROL_DEFAULT 0x08000002
-#define mmCM2_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070
-#define mmCM2_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmCM2_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmCM2_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmCM2_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000
-#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000
-#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000
-#define mmCM2_CM_ICSC_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_ICSC_C11_C12_DEFAULT 0x00002000
-#define mmCM2_CM_ICSC_C13_C14_DEFAULT 0x00000000
-#define mmCM2_CM_ICSC_C21_C22_DEFAULT 0x20000000
-#define mmCM2_CM_ICSC_C23_C24_DEFAULT 0x00000000
-#define mmCM2_CM_ICSC_C31_C32_DEFAULT 0x00000000
-#define mmCM2_CM_ICSC_C33_C34_DEFAULT 0x00002000
-#define mmCM2_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmCM2_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmCM2_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmCM2_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmCM2_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmCM2_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmCM2_CM_OCSC_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_OCSC_C11_C12_DEFAULT 0x00002000
-#define mmCM2_CM_OCSC_C13_C14_DEFAULT 0x00000000
-#define mmCM2_CM_OCSC_C21_C22_DEFAULT 0x20000000
-#define mmCM2_CM_OCSC_C23_C24_DEFAULT 0x00000000
-#define mmCM2_CM_OCSC_C31_C32_DEFAULT 0x00000000
-#define mmCM2_CM_OCSC_C33_C34_DEFAULT 0x00002000
-#define mmCM2_CM_BNS_VALUES_R_DEFAULT 0x20000000
-#define mmCM2_CM_BNS_VALUES_G_DEFAULT 0x20000000
-#define mmCM2_CM_BNS_VALUES_B_DEFAULT 0x20000000
-#define mmCM2_CM_DGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM2_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000
-#define mmCM2_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000
-#define mmCM2_CM_HDR_MULT_COEF_DEFAULT 0x0001f000
-#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff
-#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff
-#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff
-#define mmCM2_CM_DENORM_CONTROL_DEFAULT 0x00000000
-#define mmCM2_CM_CMOUT_CONTROL_DEFAULT 0x0000000a
-#define mmCM2_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmCM2_CM_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCM2_CM_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON14_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON14_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON14_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
-#define mmDPP_TOP3_DPP_CONTROL_DEFAULT 0x70000000
-#define mmDPP_TOP3_DPP_SOFT_RESET_DEFAULT 0x00000000
-#define mmDPP_TOP3_DPP_CRC_VAL_R_G_DEFAULT 0x00000000
-#define mmDPP_TOP3_DPP_CRC_VAL_B_A_DEFAULT 0x00000000
-#define mmDPP_TOP3_DPP_CRC_CTRL_DEFAULT 0x00000000
-#define mmDPP_TOP3_HOST_READ_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
-#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008
-#define mmCNVC_CFG3_FORMAT_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00
-#define mmCNVC_CFG3_DENORM_CONTROL_DEFAULT 0x00002000
-#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_DEFAULT 0x00000000
-#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_DEFAULT 0x00000000
-#define mmCNVC_CFG3_COLOR_KEYER_RED_DEFAULT 0x00000000
-#define mmCNVC_CFG3_COLOR_KEYER_GREEN_DEFAULT 0x00000000
-#define mmCNVC_CFG3_COLOR_KEYER_BLUE_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
-#define mmCNVC_CUR3_CURSOR0_CONTROL_DEFAULT 0x0003ff00
-#define mmCNVC_CUR3_CURSOR0_COLOR0_DEFAULT 0x00000000
-#define mmCNVC_CUR3_CURSOR0_COLOR1_DEFAULT 0x00000000
-#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00
-
-
-// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
-#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000
-#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmDSCL3_SCL_MODE_DEFAULT 0x00000000
-#define mmDSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_CONTROL_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_2TAP_CONTROL_DEFAULT 0x01000100
-#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmDSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmDSCL3_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-#define mmDSCL3_SCL_BLACK_OFFSET_DEFAULT 0x80000000
-#define mmDSCL3_DSCL_UPDATE_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_AUTOCAL_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmDSCL3_OTG_H_BLANK_DEFAULT 0x00000000
-#define mmDSCL3_OTG_V_BLANK_DEFAULT 0x00000000
-#define mmDSCL3_RECOUT_START_DEFAULT 0x00000000
-#define mmDSCL3_RECOUT_SIZE_DEFAULT 0x00000000
-#define mmDSCL3_MPC_SIZE_DEFAULT 0x00000000
-#define mmDSCL3_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmDSCL3_LB_MEMORY_CTRL_DEFAULT 0x00003f00
-#define mmDSCL3_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDSCL3_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDSCL3_OBUF_CONTROL_DEFAULT 0xe0000000
-#define mmDSCL3_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
-#define mmCM3_CM_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_COMA_C11_C12_DEFAULT 0x00002000
-#define mmCM3_CM_COMA_C13_C14_DEFAULT 0x00000000
-#define mmCM3_CM_COMA_C21_C22_DEFAULT 0x20000000
-#define mmCM3_CM_COMA_C23_C24_DEFAULT 0x00000000
-#define mmCM3_CM_COMA_C31_C32_DEFAULT 0x00000000
-#define mmCM3_CM_COMA_C33_C34_DEFAULT 0x00002000
-#define mmCM3_CM_COMB_C11_C12_DEFAULT 0x00002000
-#define mmCM3_CM_COMB_C13_C14_DEFAULT 0x00000000
-#define mmCM3_CM_COMB_C21_C22_DEFAULT 0x20000000
-#define mmCM3_CM_COMB_C23_C24_DEFAULT 0x00000000
-#define mmCM3_CM_COMB_C31_C32_DEFAULT 0x00000000
-#define mmCM3_CM_COMB_C33_C34_DEFAULT 0x00002000
-#define mmCM3_CM_IGAM_CONTROL_DEFAULT 0x08000002
-#define mmCM3_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070
-#define mmCM3_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmCM3_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmCM3_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmCM3_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000
-#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000
-#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000
-#define mmCM3_CM_ICSC_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_ICSC_C11_C12_DEFAULT 0x00002000
-#define mmCM3_CM_ICSC_C13_C14_DEFAULT 0x00000000
-#define mmCM3_CM_ICSC_C21_C22_DEFAULT 0x20000000
-#define mmCM3_CM_ICSC_C23_C24_DEFAULT 0x00000000
-#define mmCM3_CM_ICSC_C31_C32_DEFAULT 0x00000000
-#define mmCM3_CM_ICSC_C33_C34_DEFAULT 0x00002000
-#define mmCM3_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmCM3_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmCM3_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmCM3_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmCM3_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmCM3_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmCM3_CM_OCSC_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_OCSC_C11_C12_DEFAULT 0x00002000
-#define mmCM3_CM_OCSC_C13_C14_DEFAULT 0x00000000
-#define mmCM3_CM_OCSC_C21_C22_DEFAULT 0x20000000
-#define mmCM3_CM_OCSC_C23_C24_DEFAULT 0x00000000
-#define mmCM3_CM_OCSC_C31_C32_DEFAULT 0x00000000
-#define mmCM3_CM_OCSC_C33_C34_DEFAULT 0x00002000
-#define mmCM3_CM_BNS_VALUES_R_DEFAULT 0x20000000
-#define mmCM3_CM_BNS_VALUES_G_DEFAULT 0x20000000
-#define mmCM3_CM_BNS_VALUES_B_DEFAULT 0x20000000
-#define mmCM3_CM_DGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM3_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_LUT_DATA_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000
-#define mmCM3_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000
-#define mmCM3_CM_HDR_MULT_COEF_DEFAULT 0x0001f000
-#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff
-#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff
-#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff
-#define mmCM3_CM_DENORM_CONTROL_DEFAULT 0x00000000
-#define mmCM3_CM_CMOUT_CONTROL_DEFAULT 0x0000000a
-#define mmCM3_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmCM3_CM_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmCM3_CM_MEM_PWR_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON15_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON15_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON15_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mpc_mpcc0_dispdec
-#define mmMPCC0_MPCC_TOP_SEL_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_BOT_SEL_DEFAULT 0x0000000f
-#define mmMPCC0_MPCC_OPP_ID_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_CONTROL_DEFAULT 0xffff0061
-#define mmMPCC0_MPCC_SM_CONTROL_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f
-#define mmMPCC0_MPCC_TOP_OFFSET_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_BOT_OFFSET_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_OFFSET_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_BG_R_CR_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_BG_G_Y_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_BG_B_CB_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_STALL_STATUS_DEFAULT 0x00000000
-#define mmMPCC0_MPCC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mpc_mpcc1_dispdec
-#define mmMPCC1_MPCC_TOP_SEL_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_BOT_SEL_DEFAULT 0x0000000f
-#define mmMPCC1_MPCC_OPP_ID_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_CONTROL_DEFAULT 0xffff0061
-#define mmMPCC1_MPCC_SM_CONTROL_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f
-#define mmMPCC1_MPCC_TOP_OFFSET_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_BOT_OFFSET_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_OFFSET_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_BG_R_CR_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_BG_G_Y_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_BG_B_CB_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_STALL_STATUS_DEFAULT 0x00000000
-#define mmMPCC1_MPCC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mpc_mpcc2_dispdec
-#define mmMPCC2_MPCC_TOP_SEL_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_BOT_SEL_DEFAULT 0x0000000f
-#define mmMPCC2_MPCC_OPP_ID_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_CONTROL_DEFAULT 0xffff0061
-#define mmMPCC2_MPCC_SM_CONTROL_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f
-#define mmMPCC2_MPCC_TOP_OFFSET_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_BOT_OFFSET_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_OFFSET_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_BG_R_CR_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_BG_G_Y_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_BG_B_CB_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_STALL_STATUS_DEFAULT 0x00000000
-#define mmMPCC2_MPCC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mpc_mpcc3_dispdec
-#define mmMPCC3_MPCC_TOP_SEL_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_BOT_SEL_DEFAULT 0x0000000f
-#define mmMPCC3_MPCC_OPP_ID_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_CONTROL_DEFAULT 0xffff0061
-#define mmMPCC3_MPCC_SM_CONTROL_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f
-#define mmMPCC3_MPCC_TOP_OFFSET_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_BOT_OFFSET_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_OFFSET_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_BG_R_CR_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_BG_G_Y_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_BG_B_CB_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_STALL_STATUS_DEFAULT 0x00000000
-#define mmMPCC3_MPCC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
-#define mmMPC_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmMPC_SOFT_RESET_DEFAULT 0x00000000
-#define mmMPC_CRC_CTRL_DEFAULT 0x00000000
-#define mmMPC_CRC_SEL_CONTROL_DEFAULT 0x00000000
-#define mmMPC_CRC_RESULT_AR_DEFAULT 0x00000000
-#define mmMPC_CRC_RESULT_GB_DEFAULT 0x00000000
-#define mmMPC_CRC_RESULT_C_DEFAULT 0x00000000
-#define mmMPC_PERFMON_EVENT_CTRL_DEFAULT 0x00000000
-#define mmMPC_BYPASS_BG_AR_DEFAULT 0x00000000
-#define mmMPC_BYPASS_BG_GB_DEFAULT 0x00000000
-#define mmMPC_OUT0_MUX_DEFAULT 0x0000000f
-#define mmMPC_OUT1_MUX_DEFAULT 0x0000000f
-#define mmMPC_OUT2_MUX_DEFAULT 0x0000000f
-#define mmMPC_OUT3_MUX_DEFAULT 0x0000000f
-#define mmMPC_STALL_GRACE_WINDOW_DEFAULT 0x00000000
-#define mmADR_CFG_VUPDATE_LOCK_SET0_DEFAULT 0x00000000
-#define mmADR_VUPDATE_LOCK_SET0_DEFAULT 0x00000000
-#define mmCUR0_VUPDATE_LOCK_SET0_DEFAULT 0x00000000
-#define mmCUR1_VUPDATE_LOCK_SET0_DEFAULT 0x00000000
-#define mmADR_CFG_VUPDATE_LOCK_SET1_DEFAULT 0x00000000
-#define mmADR_VUPDATE_LOCK_SET1_DEFAULT 0x00000000
-#define mmCUR0_VUPDATE_LOCK_SET1_DEFAULT 0x00000000
-#define mmCUR1_VUPDATE_LOCK_SET1_DEFAULT 0x00000000
-#define mmADR_CFG_VUPDATE_LOCK_SET2_DEFAULT 0x00000000
-#define mmADR_VUPDATE_LOCK_SET2_DEFAULT 0x00000000
-#define mmCUR0_VUPDATE_LOCK_SET2_DEFAULT 0x00000000
-#define mmCUR1_VUPDATE_LOCK_SET2_DEFAULT 0x00000000
-#define mmADR_CFG_VUPDATE_LOCK_SET3_DEFAULT 0x00000000
-#define mmADR_VUPDATE_LOCK_SET3_DEFAULT 0x00000000
-#define mmCUR0_VUPDATE_LOCK_SET3_DEFAULT 0x00000000
-#define mmCUR1_VUPDATE_LOCK_SET3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON16_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON16_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON16_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_abm0_dispdec
-#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmABM0_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_CNTL_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400
-#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400
-#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400
-#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400
-#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400
-#define mmABM0_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000
-#define mmABM0_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_abm1_dispdec
-#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmABM1_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_CNTL_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400
-#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400
-#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400
-#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400
-#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400
-#define mmABM1_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000
-#define mmABM1_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_fmt0_dispdec
-#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_oppbuf0_dispdec
-#define mmOPPBUF0_OPPBUF_CONTROL_DEFAULT 0x00000000
-#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000
-#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe0_dispdec
-#define mmOPP_PIPE0_OPP_PIPE_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
-#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff
-#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_fmt1_dispdec
-#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_oppbuf1_dispdec
-#define mmOPPBUF1_OPPBUF_CONTROL_DEFAULT 0x00000000
-#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000
-#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe1_dispdec
-#define mmOPP_PIPE1_OPP_PIPE_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
-#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff
-#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_fmt2_dispdec
-#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_oppbuf2_dispdec
-#define mmOPPBUF2_OPPBUF_CONTROL_DEFAULT 0x00000000
-#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000
-#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe2_dispdec
-#define mmOPP_PIPE2_OPP_PIPE_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
-#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff
-#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_fmt3_dispdec
-#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_oppbuf3_dispdec
-#define mmOPPBUF3_OPPBUF_CONTROL_DEFAULT 0x00000000
-#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000
-#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe3_dispdec
-#define mmOPP_PIPE3_OPP_PIPE_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
-#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff
-#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_fmt4_dispdec
-#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_oppbuf4_dispdec
-#define mmOPPBUF4_OPPBUF_CONTROL_DEFAULT 0x00000000
-#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000
-#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe4_dispdec
-#define mmOPP_PIPE4_OPP_PIPE_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
-#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff
-#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_fmt5_dispdec
-#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_oppbuf5_dispdec
-#define mmOPPBUF5_OPPBUF_CONTROL_DEFAULT 0x00000000
-#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000
-#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe5_dispdec
-#define mmOPP_PIPE5_OPP_PIPE_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
-#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff
-#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000
-#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_top_dispdec
-#define mmOPP_TOP_CLK_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON17_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON17_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON17_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_odm0_dispdec
-#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define mmODM0_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmODM0_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_odm1_dispdec
-#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define mmODM1_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmODM1_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_odm2_dispdec
-#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define mmODM2_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmODM2_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_odm3_dispdec
-#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define mmODM3_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmODM3_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_odm4_dispdec
-#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define mmODM4_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmODM4_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_odm5_dispdec
-#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000
-#define mmODM5_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmODM5_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_otg0_dispdec
-#define mmOTG0_OTG_H_TOTAL_DEFAULT 0x00000000
-#define mmOTG0_OTG_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG0_OTG_H_SYNC_A_DEFAULT 0x00000000
-#define mmOTG0_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_H_TIMING_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_TOTAL_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_TOTAL_MID_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_SYNC_A_DEFAULT 0x00000000
-#define mmOTG0_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG0_OTG_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmOTG0_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmOTG0_OTG_CONTROL_DEFAULT 0x80000110
-#define mmOTG0_OTG_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmOTG0_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmOTG0_OTG_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_STATUS_POSITION_DEFAULT 0x00000000
-#define mmOTG0_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmOTG0_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmOTG0_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmOTG0_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmOTG0_OTG_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_COUNT_RESET_DEFAULT 0x00000000
-#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_STEREO_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmOTG0_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmOTG0_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmOTG0_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmOTG0_OTG_MASTER_EN_DEFAULT 0x00000000
-#define mmOTG0_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG0_OTG_BLACK_COLOR_DEFAULT 0x00000000
-#define mmOTG0_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC_CNTL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC2_DATA_RG_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC2_DATA_B_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC3_DATA_RG_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC3_DATA_B_DEFAULT 0x00000000
-#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff
-#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmOTG0_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmOTG0_OTG_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000
-#define mmOTG0_OTG_VUPDATE_PARAM_DEFAULT 0x00010000
-#define mmOTG0_OTG_VREADY_PARAM_DEFAULT 0x00000000
-#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG0_OTG_GSL_CONTROL_DEFAULT 0x00020000
-#define mmOTG0_OTG_GSL_WINDOW_X_DEFAULT 0x00000000
-#define mmOTG0_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000
-#define mmOTG0_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000
-#define mmOTG0_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000
-#define mmOTG0_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000
-#define mmOTG0_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000
-#define mmOTG0_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000
-#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG0_OTG_DRR_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_REQUEST_CONTROL_DEFAULT 0x00000000
-#define mmOTG0_OTG_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_otg1_dispdec
-#define mmOTG1_OTG_H_TOTAL_DEFAULT 0x00000000
-#define mmOTG1_OTG_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG1_OTG_H_SYNC_A_DEFAULT 0x00000000
-#define mmOTG1_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_H_TIMING_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_TOTAL_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_TOTAL_MID_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_SYNC_A_DEFAULT 0x00000000
-#define mmOTG1_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG1_OTG_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmOTG1_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmOTG1_OTG_CONTROL_DEFAULT 0x80000110
-#define mmOTG1_OTG_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmOTG1_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmOTG1_OTG_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_STATUS_POSITION_DEFAULT 0x00000000
-#define mmOTG1_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmOTG1_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmOTG1_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmOTG1_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmOTG1_OTG_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_COUNT_RESET_DEFAULT 0x00000000
-#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_STEREO_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmOTG1_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmOTG1_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmOTG1_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmOTG1_OTG_MASTER_EN_DEFAULT 0x00000000
-#define mmOTG1_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG1_OTG_BLACK_COLOR_DEFAULT 0x00000000
-#define mmOTG1_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC_CNTL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC2_DATA_RG_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC2_DATA_B_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC3_DATA_RG_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC3_DATA_B_DEFAULT 0x00000000
-#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff
-#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmOTG1_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmOTG1_OTG_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000
-#define mmOTG1_OTG_VUPDATE_PARAM_DEFAULT 0x00010000
-#define mmOTG1_OTG_VREADY_PARAM_DEFAULT 0x00000000
-#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG1_OTG_GSL_CONTROL_DEFAULT 0x00020000
-#define mmOTG1_OTG_GSL_WINDOW_X_DEFAULT 0x00000000
-#define mmOTG1_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000
-#define mmOTG1_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000
-#define mmOTG1_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000
-#define mmOTG1_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000
-#define mmOTG1_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000
-#define mmOTG1_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000
-#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG1_OTG_DRR_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_REQUEST_CONTROL_DEFAULT 0x00000000
-#define mmOTG1_OTG_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_otg2_dispdec
-#define mmOTG2_OTG_H_TOTAL_DEFAULT 0x00000000
-#define mmOTG2_OTG_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG2_OTG_H_SYNC_A_DEFAULT 0x00000000
-#define mmOTG2_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_H_TIMING_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_TOTAL_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_TOTAL_MID_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_SYNC_A_DEFAULT 0x00000000
-#define mmOTG2_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG2_OTG_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmOTG2_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmOTG2_OTG_CONTROL_DEFAULT 0x80000110
-#define mmOTG2_OTG_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmOTG2_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmOTG2_OTG_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_STATUS_POSITION_DEFAULT 0x00000000
-#define mmOTG2_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmOTG2_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmOTG2_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmOTG2_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmOTG2_OTG_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_COUNT_RESET_DEFAULT 0x00000000
-#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_STEREO_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmOTG2_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmOTG2_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmOTG2_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmOTG2_OTG_MASTER_EN_DEFAULT 0x00000000
-#define mmOTG2_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG2_OTG_BLACK_COLOR_DEFAULT 0x00000000
-#define mmOTG2_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC_CNTL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC2_DATA_RG_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC2_DATA_B_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC3_DATA_RG_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC3_DATA_B_DEFAULT 0x00000000
-#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff
-#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmOTG2_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmOTG2_OTG_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000
-#define mmOTG2_OTG_VUPDATE_PARAM_DEFAULT 0x00010000
-#define mmOTG2_OTG_VREADY_PARAM_DEFAULT 0x00000000
-#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG2_OTG_GSL_CONTROL_DEFAULT 0x00020000
-#define mmOTG2_OTG_GSL_WINDOW_X_DEFAULT 0x00000000
-#define mmOTG2_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000
-#define mmOTG2_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000
-#define mmOTG2_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000
-#define mmOTG2_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000
-#define mmOTG2_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000
-#define mmOTG2_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000
-#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG2_OTG_DRR_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_REQUEST_CONTROL_DEFAULT 0x00000000
-#define mmOTG2_OTG_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_otg3_dispdec
-#define mmOTG3_OTG_H_TOTAL_DEFAULT 0x00000000
-#define mmOTG3_OTG_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG3_OTG_H_SYNC_A_DEFAULT 0x00000000
-#define mmOTG3_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_H_TIMING_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_TOTAL_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_TOTAL_MID_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_SYNC_A_DEFAULT 0x00000000
-#define mmOTG3_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG3_OTG_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmOTG3_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmOTG3_OTG_CONTROL_DEFAULT 0x80000110
-#define mmOTG3_OTG_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmOTG3_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmOTG3_OTG_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_STATUS_POSITION_DEFAULT 0x00000000
-#define mmOTG3_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmOTG3_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmOTG3_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmOTG3_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmOTG3_OTG_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_COUNT_RESET_DEFAULT 0x00000000
-#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_STEREO_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmOTG3_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmOTG3_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmOTG3_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmOTG3_OTG_MASTER_EN_DEFAULT 0x00000000
-#define mmOTG3_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG3_OTG_BLACK_COLOR_DEFAULT 0x00000000
-#define mmOTG3_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC_CNTL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC2_DATA_RG_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC2_DATA_B_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC3_DATA_RG_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC3_DATA_B_DEFAULT 0x00000000
-#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff
-#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmOTG3_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmOTG3_OTG_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000
-#define mmOTG3_OTG_VUPDATE_PARAM_DEFAULT 0x00010000
-#define mmOTG3_OTG_VREADY_PARAM_DEFAULT 0x00000000
-#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG3_OTG_GSL_CONTROL_DEFAULT 0x00020000
-#define mmOTG3_OTG_GSL_WINDOW_X_DEFAULT 0x00000000
-#define mmOTG3_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000
-#define mmOTG3_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000
-#define mmOTG3_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000
-#define mmOTG3_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000
-#define mmOTG3_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000
-#define mmOTG3_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000
-#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG3_OTG_DRR_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_REQUEST_CONTROL_DEFAULT 0x00000000
-#define mmOTG3_OTG_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_otg4_dispdec
-#define mmOTG4_OTG_H_TOTAL_DEFAULT 0x00000000
-#define mmOTG4_OTG_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG4_OTG_H_SYNC_A_DEFAULT 0x00000000
-#define mmOTG4_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_H_TIMING_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_TOTAL_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_TOTAL_MID_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_SYNC_A_DEFAULT 0x00000000
-#define mmOTG4_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG4_OTG_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmOTG4_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmOTG4_OTG_CONTROL_DEFAULT 0x80000110
-#define mmOTG4_OTG_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmOTG4_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmOTG4_OTG_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_STATUS_POSITION_DEFAULT 0x00000000
-#define mmOTG4_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmOTG4_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmOTG4_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmOTG4_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmOTG4_OTG_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_COUNT_RESET_DEFAULT 0x00000000
-#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_STEREO_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmOTG4_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmOTG4_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmOTG4_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmOTG4_OTG_MASTER_EN_DEFAULT 0x00000000
-#define mmOTG4_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG4_OTG_BLACK_COLOR_DEFAULT 0x00000000
-#define mmOTG4_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC_CNTL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC2_DATA_RG_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC2_DATA_B_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC3_DATA_RG_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC3_DATA_B_DEFAULT 0x00000000
-#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff
-#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmOTG4_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmOTG4_OTG_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000
-#define mmOTG4_OTG_VUPDATE_PARAM_DEFAULT 0x00010000
-#define mmOTG4_OTG_VREADY_PARAM_DEFAULT 0x00000000
-#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG4_OTG_GSL_CONTROL_DEFAULT 0x00020000
-#define mmOTG4_OTG_GSL_WINDOW_X_DEFAULT 0x00000000
-#define mmOTG4_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000
-#define mmOTG4_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000
-#define mmOTG4_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000
-#define mmOTG4_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000
-#define mmOTG4_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000
-#define mmOTG4_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000
-#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG4_OTG_DRR_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_REQUEST_CONTROL_DEFAULT 0x00000000
-#define mmOTG4_OTG_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_otg5_dispdec
-#define mmOTG5_OTG_H_TOTAL_DEFAULT 0x00000000
-#define mmOTG5_OTG_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG5_OTG_H_SYNC_A_DEFAULT 0x00000000
-#define mmOTG5_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_H_TIMING_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_TOTAL_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_TOTAL_MID_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_SYNC_A_DEFAULT 0x00000000
-#define mmOTG5_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG5_OTG_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmOTG5_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmOTG5_OTG_CONTROL_DEFAULT 0x80000110
-#define mmOTG5_OTG_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmOTG5_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmOTG5_OTG_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_STATUS_POSITION_DEFAULT 0x00000000
-#define mmOTG5_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmOTG5_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmOTG5_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmOTG5_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmOTG5_OTG_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_COUNT_RESET_DEFAULT 0x00000000
-#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_STEREO_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmOTG5_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmOTG5_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmOTG5_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmOTG5_OTG_MASTER_EN_DEFAULT 0x00000000
-#define mmOTG5_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG5_OTG_BLACK_COLOR_DEFAULT 0x00000000
-#define mmOTG5_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC_CNTL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC2_DATA_RG_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC2_DATA_B_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC3_DATA_RG_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC3_DATA_B_DEFAULT 0x00000000
-#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff
-#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmOTG5_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmOTG5_OTG_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000
-#define mmOTG5_OTG_VUPDATE_PARAM_DEFAULT 0x00010000
-#define mmOTG5_OTG_VREADY_PARAM_DEFAULT 0x00000000
-#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmOTG5_OTG_GSL_CONTROL_DEFAULT 0x00020000
-#define mmOTG5_OTG_GSL_WINDOW_X_DEFAULT 0x00000000
-#define mmOTG5_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000
-#define mmOTG5_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000
-#define mmOTG5_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000
-#define mmOTG5_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000
-#define mmOTG5_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000
-#define mmOTG5_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000
-#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmOTG5_OTG_DRR_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_REQUEST_CONTROL_DEFAULT 0x00000000
-#define mmOTG5_OTG_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_optc_misc_dispdec
-#define mmDWB_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmGSL_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmOPTC_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmOPTC_MISC_SPARE_REGISTER_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON18_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON18_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON18_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dac_dispdec
-#define mmDAC_ENABLE_DEFAULT 0x00000004
-#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmDAC_CRC_EN_DEFAULT 0x00000000
-#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff
-#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f
-#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff
-#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f
-#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000
-#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000
-#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000
-#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b
-#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519
-#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000
-#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000
-#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000
-#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6
-#define mmDAC_POWERDOWN_DEFAULT 0x01010100
-#define mmDAC_CONTROL_DEFAULT 0x00000000
-#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000
-#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000
-#define mmDAC_PWR_CNTL_DEFAULT 0x00000000
-#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000
-#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dout_i2c_dispdec
-#define mmDC_I2C_CONTROL_DEFAULT 0x00000000
-#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001
-#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000
-#define mmDC_I2C_DATA_DEFAULT 0x00000000
-#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4
-#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000
-
-
-// addressBlock: dce_dc_dio_generic_i2c_dispdec
-#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000
-#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000
-#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002
-#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000
-#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000
-#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000
-#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dio_misc_dispdec
-#define mmDIO_SCRATCH0_DEFAULT 0x00000000
-#define mmDIO_SCRATCH1_DEFAULT 0x00000000
-#define mmDIO_SCRATCH2_DEFAULT 0x00000000
-#define mmDIO_SCRATCH3_DEFAULT 0x00000000
-#define mmDIO_SCRATCH4_DEFAULT 0x00000000
-#define mmDIO_SCRATCH5_DEFAULT 0x00000000
-#define mmDIO_SCRATCH6_DEFAULT 0x00000000
-#define mmDIO_SCRATCH7_DEFAULT 0x00000000
-#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000
-#define mmDIO_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDIO_MEM_PWR_CTRL_DEFAULT 0x6db6d800
-#define mmDIO_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDIO_CLK_CNTL_DEFAULT 0x00000000
-#define mmDIO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000
-#define mmDIO_STEREOSYNC_SEL_DEFAULT 0x00000000
-#define mmDIO_SOFT_RESET_DEFAULT 0x00000000
-#define mmDIG_SOFT_RESET_DEFAULT 0x00000000
-#define mmDIO_MEM_PWR_STATUS1_DEFAULT 0x00000000
-#define mmDIO_CLK_CNTL2_DEFAULT 0x00000000
-#define mmDIO_CLK_CNTL3_DEFAULT 0x00000000
-#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000
-#define mmDIO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000
-#define mmDIO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000
-#define mmDIO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_hpd0_dispdec
-#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_hpd1_dispdec
-#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_hpd2_dispdec
-#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_hpd3_dispdec
-#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_hpd4_dispdec
-#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_hpd5_dispdec
-#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
-#define mmDC_PERFMON19_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON19_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON19_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux0_dispdec
-#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux1_dispdec
-#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux2_dispdec
-#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux3_dispdec
-#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux4_dispdec
-#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux5_dispdec
-#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp_aux6_dispdec
-#define mmDP_AUX6_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX6_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig0_dispdec
-#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG0_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp0_dispdec
-#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP0_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP0_DP_VID_N_DEFAULT 0x00002000
-#define mmDP0_DP_VID_M_DEFAULT 0x00000000
-#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP0_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP0_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP0_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP0_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig1_dispdec
-#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG1_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp1_dispdec
-#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP1_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP1_DP_VID_N_DEFAULT 0x00002000
-#define mmDP1_DP_VID_M_DEFAULT 0x00000000
-#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP1_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP1_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP1_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP1_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig2_dispdec
-#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG2_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp2_dispdec
-#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP2_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP2_DP_VID_N_DEFAULT 0x00002000
-#define mmDP2_DP_VID_M_DEFAULT 0x00000000
-#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP2_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP2_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP2_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP2_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig3_dispdec
-#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG3_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp3_dispdec
-#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP3_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP3_DP_VID_N_DEFAULT 0x00002000
-#define mmDP3_DP_VID_M_DEFAULT 0x00000000
-#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP3_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP3_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP3_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP3_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig4_dispdec
-#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG4_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp4_dispdec
-#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP4_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP4_DP_VID_N_DEFAULT 0x00002000
-#define mmDP4_DP_VID_M_DEFAULT 0x00000000
-#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP4_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP4_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP4_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP4_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig5_dispdec
-#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG5_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp5_dispdec
-#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP5_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP5_DP_VID_N_DEFAULT 0x00002000
-#define mmDP5_DP_VID_M_DEFAULT 0x00000000
-#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP5_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP5_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP5_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP5_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dig6_dispdec
-#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000
-#define mmDIG6_HDMI_DB_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000
-#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dio_dp6_dispdec
-#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP6_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP6_DP_VID_N_DEFAULT 0x00002000
-#define mmDP6_DP_VID_M_DEFAULT 0x00000000
-#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000
-#define mmDP6_DP_MSO_CNTL_DEFAULT 0xfffffff0
-#define mmDP6_DP_MSO_CNTL1_DEFAULT 0xffffffff
-#define mmDP6_DP_DSC_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL2_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL3_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL4_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL5_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL6_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL7_DEFAULT 0x00000000
-#define mmDP6_DP_DB_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_VBID_MISC_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_dcio_dispdec
-#define mmDC_GENERICA_DEFAULT 0x00000000
-#define mmDC_GENERICB_DEFAULT 0x00000000
-#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000
-#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101
-#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01000100
-#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333
-#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000
-#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000
-#define mmBL_PWM_CNTL_DEFAULT 0x00000000
-#define mmBL_PWM_CNTL2_DEFAULT 0x00000000
-#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001
-#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000
-#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000
-#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000
-#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000
-#define mmDIO_OTG_EXT_VSYNC_CNTL_DEFAULT 0x00000000
-#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4
-#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000
-#define mmAUXP_IMPCAL_DEFAULT 0x0a000000
-#define mmAUXN_IMPCAL_DEFAULT 0x04000000
-#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000
-#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000
-#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000
-#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000
-#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000
-#define mmDCIO_USBC_FLIP_EN_SEL_DEFAULT 0x00543210
-
-
-// addressBlock: dce_dc_dcio_dcio_chip_dispdec
-#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444
-#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000
-#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040
-#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000
-#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10
-#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000
-#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440
-#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000
-#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202
-#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040
-#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000
-#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47fc470f
-#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147
-#define mmPHY_AUX_CNTL_DEFAULT 0x00010001
-#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c
-#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060
-#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000
-#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000
-#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202
-#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000
-#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000
-#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000
-#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f
-#define mmDC_GPIO_PULLUPEN_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_dcio_dac_dispdec
-#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec
-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x1c010000
-#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_DEFAULT 0x00010520
-
-
-// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec
-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x1c010000
-#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_DEFAULT 0x00010520
-
-
-// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec
-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x1c010000
-#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_DEFAULT 0x00010520
-
-
-// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec
-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x1c010000
-#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_DEFAULT 0x00010520
-
-
-// addressBlock: dce_dc_dcio_dcio_zcal_dispdec
-#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec
-#define mmCOMP_EN_CTL_DEFAULT 0x00080000
-#define mmCOMP_EN_DFX_DEFAULT 0x00000000
-#define mmZCAL_FUSES_DEFAULT 0x00000000
-
-
-// addressBlock: vga_vgaseqind
-#define ixSEQ00_DEFAULT 0x00000003
-#define ixSEQ01_DEFAULT 0x00000021
-#define ixSEQ02_DEFAULT 0x00000000
-#define ixSEQ03_DEFAULT 0x00000000
-#define ixSEQ04_DEFAULT 0x00000000
-
-
-// addressBlock: vga_vgacrtind
-#define ixCRT00_DEFAULT 0x00000000
-#define ixCRT01_DEFAULT 0x00000000
-#define ixCRT02_DEFAULT 0x00000000
-#define ixCRT03_DEFAULT 0x00000000
-#define ixCRT04_DEFAULT 0x00000000
-#define ixCRT05_DEFAULT 0x00000000
-#define ixCRT06_DEFAULT 0x00000000
-#define ixCRT07_DEFAULT 0x00000000
-#define ixCRT08_DEFAULT 0x00000000
-#define ixCRT09_DEFAULT 0x00000000
-#define ixCRT0A_DEFAULT 0x00000000
-#define ixCRT0B_DEFAULT 0x00000000
-#define ixCRT0C_DEFAULT 0x00000000
-#define ixCRT0D_DEFAULT 0x00000000
-#define ixCRT0E_DEFAULT 0x00000000
-#define ixCRT0F_DEFAULT 0x00000000
-#define ixCRT10_DEFAULT 0x00000000
-#define ixCRT11_DEFAULT 0x00000000
-#define ixCRT12_DEFAULT 0x00000000
-#define ixCRT13_DEFAULT 0x00000000
-#define ixCRT14_DEFAULT 0x00000000
-#define ixCRT15_DEFAULT 0x00000000
-#define ixCRT16_DEFAULT 0x00000000
-#define ixCRT17_DEFAULT 0x00000000
-#define ixCRT18_DEFAULT 0x00000000
-#define ixCRT1E_DEFAULT 0x00000000
-#define ixCRT1F_DEFAULT 0x00000000
-#define ixCRT22_DEFAULT 0x00000000
-
-
-// addressBlock: vga_vgagrphind
-#define ixGRA00_DEFAULT 0x00000000
-#define ixGRA01_DEFAULT 0x00000000
-#define ixGRA02_DEFAULT 0x00000000
-#define ixGRA03_DEFAULT 0x00000000
-#define ixGRA04_DEFAULT 0x00000000
-#define ixGRA05_DEFAULT 0x00000000
-#define ixGRA06_DEFAULT 0x00000000
-#define ixGRA07_DEFAULT 0x00000000
-#define ixGRA08_DEFAULT 0x00000000
-
-
-// addressBlock: vga_vgaattrind
-#define ixATTR00_DEFAULT 0x00000000
-#define ixATTR01_DEFAULT 0x00000000
-#define ixATTR02_DEFAULT 0x00000000
-#define ixATTR03_DEFAULT 0x00000000
-#define ixATTR04_DEFAULT 0x00000000
-#define ixATTR05_DEFAULT 0x00000000
-#define ixATTR06_DEFAULT 0x00000000
-#define ixATTR07_DEFAULT 0x00000000
-#define ixATTR08_DEFAULT 0x00000000
-#define ixATTR09_DEFAULT 0x00000000
-#define ixATTR0A_DEFAULT 0x00000000
-#define ixATTR0B_DEFAULT 0x00000000
-#define ixATTR0C_DEFAULT 0x00000000
-#define ixATTR0D_DEFAULT 0x00000000
-#define ixATTR0E_DEFAULT 0x00000000
-#define ixATTR0F_DEFAULT 0x00000000
-#define ixATTR10_DEFAULT 0x00000000
-#define ixATTR11_DEFAULT 0x00000000
-#define ixATTR12_DEFAULT 0x00000000
-#define ixATTR13_DEFAULT 0x00000000
-#define ixATTR14_DEFAULT 0x00000000
-
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-// addressBlock: azendpoint_f2codecind
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000
-
-
-// addressBlock: azendpoint_descriptorind
-#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-
-
-// addressBlock: azendpoint_sinkinfoind
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000
-
-
-// addressBlock: azf0controller_azinputcrc0resultind
-#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azf0controller_azinputcrc1resultind
-#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azf0controller_azcrc0resultind
-#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azf0controller_azcrc1resultind
-#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azinputendpoint_f2codecind
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
-
-
-// addressBlock: azroot_f2codecind
-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream0_streamind
-#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream1_streamind
-#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream2_streamind
-#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream3_streamind
-#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream4_streamind
-#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream5_streamind
-#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream6_streamind
-#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream7_streamind
-#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream8_streamind
-#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream9_streamind
-#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream10_streamind
-#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream11_streamind
-#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream12_streamind
-#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream13_streamind
-#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream14_streamind
-#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream15_streamind
-#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint0_endpointind
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint1_endpointind
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint2_endpointind
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint3_endpointind
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint4_endpointind
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint5_endpointind
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint6_endpointind
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint7_endpointind
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint0_inputendpointind
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint1_inputendpointind
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint2_inputendpointind
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint3_inputendpointind
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint4_inputendpointind
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint5_inputendpointind
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint6_inputendpointind
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint7_inputendpointind
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
deleted file mode 100644
index 582f1a6..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
+++ /dev/null
@@ -1,4005 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _gc_9_1_DEFAULT_HEADER
-#define _gc_9_1_DEFAULT_HEADER
-
-
-// addressBlock: gc_grbmdec
-#define mmGRBM_CNTL_DEFAULT 0x00000018
-#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
-#define mmGRBM_STATUS2_DEFAULT 0x00000000
-#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
-#define mmGRBM_STATUS_DEFAULT 0x00000000
-#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
-#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
-#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
-#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
-#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
-#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030
-#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000
-#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000
-#define mmGRBM_READ_ERROR_DEFAULT 0x00000000
-#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000
-#define mmGRBM_INT_CNTL_DEFAULT 0x00000000
-#define mmGRBM_TRAP_OP_DEFAULT 0x00000000
-#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000
-#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff
-#define mmGRBM_TRAP_WD_DEFAULT 0x00000000
-#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff
-#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000
-#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000
-#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000
-#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000
-#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000
-#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000
-#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000
-#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000
-#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891
-#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea
-#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000
-#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000
-#define mmGRBM_NOWHERE_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cpdec
-#define mmCP_CPC_STATUS_DEFAULT 0x00000000
-#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000
-#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000
-#define mmCP_CPF_STATUS_DEFAULT 0x00000000
-#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000
-#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000
-#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008
-#define mmCP_MEC_CNTL_DEFAULT 0x50000000
-#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000
-#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004
-#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002
-#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000
-#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000
-#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000
-#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000
-#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000
-#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000
-#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000
-#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000
-#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000
-#define mmCP_STALLED_STAT3_DEFAULT 0x00000000
-#define mmCP_STALLED_STAT1_DEFAULT 0x00000000
-#define mmCP_STALLED_STAT2_DEFAULT 0x00000000
-#define mmCP_BUSY_STAT_DEFAULT 0x00000000
-#define mmCP_STAT_DEFAULT 0x00000000
-#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808
-#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_CSF_STAT_DEFAULT 0x00000000
-#define mmCP_ME_CNTL_DEFAULT 0x15000000
-#define mmCP_CNTX_STAT_DEFAULT 0x00000000
-#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000
-#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010
-#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010
-#define mmCP_RB2_RPTR_DEFAULT 0x00000000
-#define mmCP_RB1_RPTR_DEFAULT 0x00000000
-#define mmCP_RB0_RPTR_DEFAULT 0x00000000
-#define mmCP_RB_RPTR_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100
-#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x30101010
-#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x40403030
-#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000
-#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16
-#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040
-#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000
-#define mmCP_STQ_AVAIL_DEFAULT 0x00000000
-#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000
-#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000
-#define mmCP_CMD_INDEX_DEFAULT 0x00000000
-#define mmCP_CMD_DATA_DEFAULT 0x00000000
-#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000
-#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000
-#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000
-#define mmCP_STQ_STAT_DEFAULT 0x00000000
-#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000
-#define mmCP_MEQ_STAT_DEFAULT 0x00000000
-#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000
-#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000
-#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000
-#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000
-#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_padec
-#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d
-#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00040180
-#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020
-#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020
-#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000
-#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000
-#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092410
-#define mmVGT_FIFO_DEPTHS_DEFAULT 0x08000040
-#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010
-#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe
-#define mmIA_CNTL_STATUS_DEFAULT 0x00000000
-#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000
-#define mmWD_CNTL_STATUS_DEFAULT 0x00000000
-#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x0e020000
-#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000
-#define mmWD_QOS_DEFAULT 0x00000000
-#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011
-#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x0000007f
-#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000000ff
-#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000
-#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xf8000000
-#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000
-#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000
-#define mmVGT_DMA_CONTROL_DEFAULT 0x000000ff
-#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000
-#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000
-#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000
-#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000
-#define mmPA_CL_ENHANCE_DEFAULT 0x00000007
-#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000
-#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000018
-#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
-#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff
-#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402
-#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x8a000008
-#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aaa8
-#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0x82400025
-#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000
-#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000
-#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000
-#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000
-#define mmPA_UTCL1_CNTL1_DEFAULT 0x00000600
-#define mmPA_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020
-#define mmPA_SC_ENHANCE_DEFAULT 0x00000001
-#define mmPA_SC_ENHANCE_1_DEFAULT 0x00040000
-#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_sqdec
-#define mmSQ_CONFIG_DEFAULT 0x01180000
-#define mmSQC_CONFIG_DEFAULT 0x010a2000
-#define mmLDS_CONFIG_DEFAULT 0x00000000
-#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f
-#define mmSQ_REG_CREDITS_DEFAULT 0x00000820
-#define mmSQ_FIFO_SIZES_DEFAULT 0x00000f01
-#define mmSQ_DSM_CNTL_DEFAULT 0x00000000
-#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000
-#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000
-#define mmSH_MEM_BASES_DEFAULT 0x00000000
-#define mmSH_MEM_CONFIG_DEFAULT 0x00000000
-#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000
-#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000
-#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff
-#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000
-#define mmSQ_UTCL1_CNTL1_DEFAULT 0x00000580
-#define mmSQ_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmSQ_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000
-#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000
-#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000
-#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTLA_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTLB_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL2_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmSQC_EDC_FUE_CNTL_DEFAULT 0x00000000
-#define mmSQC_EDC_CNT2_DEFAULT 0x00000000
-#define mmSQC_EDC_CNT3_DEFAULT 0x00000000
-#define mmSQ_REG_TIMESTAMP_DEFAULT 0x00000000
-#define mmSQ_CMD_TIMESTAMP_DEFAULT 0x00000000
-#define mmSQ_IND_INDEX_DEFAULT 0x00000000
-#define mmSQ_IND_DATA_DEFAULT 0x00000000
-#define mmSQ_CMD_DEFAULT 0x00000000
-#define mmSQ_TIME_HI_DEFAULT 0x00000000
-#define mmSQ_TIME_LO_DEFAULT 0x00000000
-#define mmSQ_DS_0_DEFAULT 0x00000000
-#define mmSQ_DS_1_DEFAULT 0x00000000
-#define mmSQ_EXP_0_DEFAULT 0x00000000
-#define mmSQ_EXP_1_DEFAULT 0x00000000
-#define mmSQ_FLAT_0_DEFAULT 0x00000000
-#define mmSQ_FLAT_1_DEFAULT 0x00000000
-#define mmSQ_GLBL_0_DEFAULT 0x00000000
-#define mmSQ_GLBL_1_DEFAULT 0x00000000
-#define mmSQ_INST_DEFAULT 0x00000000
-#define mmSQ_MIMG_0_DEFAULT 0x00000000
-#define mmSQ_MIMG_1_DEFAULT 0x00000000
-#define mmSQ_MTBUF_0_DEFAULT 0x00000000
-#define mmSQ_MTBUF_1_DEFAULT 0x00000000
-#define mmSQ_MUBUF_0_DEFAULT 0x00000000
-#define mmSQ_MUBUF_1_DEFAULT 0x00000000
-#define mmSQ_SCRATCH_0_DEFAULT 0x00000000
-#define mmSQ_SCRATCH_1_DEFAULT 0x00000000
-#define mmSQ_SMEM_0_DEFAULT 0x00000000
-#define mmSQ_SMEM_1_DEFAULT 0x00000000
-#define mmSQ_SOP1_DEFAULT 0x00000000
-#define mmSQ_SOP2_DEFAULT 0x00000000
-#define mmSQ_SOPC_DEFAULT 0x00000000
-#define mmSQ_SOPK_DEFAULT 0x00000000
-#define mmSQ_SOPP_DEFAULT 0x00000000
-#define mmSQ_VINTRP_DEFAULT 0x00000000
-#define mmSQ_VOP1_DEFAULT 0x00000000
-#define mmSQ_VOP2_DEFAULT 0x00000000
-#define mmSQ_VOP3P_0_DEFAULT 0x00000000
-#define mmSQ_VOP3P_1_DEFAULT 0x00000000
-#define mmSQ_VOP3_0_DEFAULT 0x00000000
-#define mmSQ_VOP3_0_SDST_ENC_DEFAULT 0x00000000
-#define mmSQ_VOP3_1_DEFAULT 0x00000000
-#define mmSQ_VOPC_DEFAULT 0x00000000
-#define mmSQ_VOP_DPP_DEFAULT 0x00000000
-#define mmSQ_VOP_SDWA_DEFAULT 0x00000000
-#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT 0x00000000
-#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000
-#define mmSQ_LB_DATA0_DEFAULT 0x00000000
-#define mmSQ_LB_DATA1_DEFAULT 0x00000000
-#define mmSQ_LB_DATA2_DEFAULT 0x00000000
-#define mmSQ_LB_DATA3_DEFAULT 0x00000000
-#define mmSQ_LB_CTR_SEL_DEFAULT 0x00000000
-#define mmSQ_LB_CTR0_CU_DEFAULT 0xffffffff
-#define mmSQ_LB_CTR1_CU_DEFAULT 0xffffffff
-#define mmSQ_LB_CTR2_CU_DEFAULT 0xffffffff
-#define mmSQ_LB_CTR3_CU_DEFAULT 0xffffffff
-#define mmSQC_EDC_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_SEC_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_DED_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_INFO_DEFAULT 0x00000000
-#define mmSQ_EDC_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000
-#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD0_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD1_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD2_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD3_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD0_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD1_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD2_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD3_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD4_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD5_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD6_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD7_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD0_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD1_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD2_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD3_DEFAULT 0x00000000
-#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT 0x00000000
-#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT 0x00000000
-#define mmSQ_M0_GPR_IDX_WORD_DEFAULT 0x00000000
-#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT 0x00000480
-#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT 0x00000500
-#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: gc_shsdec
-#define mmSX_DEBUG_1_DEFAULT 0x00000020
-#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff
-#define mmSPI_START_PHASE_DEFAULT 0x00000000
-#define mmSPI_GFX_CNTL_DEFAULT 0x00000000
-#define mmSPI_DSM_CNTL_DEFAULT 0x00000000
-#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000
-#define mmSPI_EDC_CNT_DEFAULT 0x00000000
-#define mmSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000
-#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000
-#define mmSPI_LB_CU_MASK_DEFAULT 0x0000ffff
-#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000
-#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT 0x0000ffff
-#define mmSPI_GDS_CREDITS_DEFAULT 0x00001080
-#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x08000800
-#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00200040
-#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
-
-
-// addressBlock: gc_tpdec
-#define mmTD_CNTL_DEFAULT 0x00000000
-#define mmTD_STATUS_DEFAULT 0x00000000
-#define mmTD_DSM_CNTL_DEFAULT 0x00000000
-#define mmTD_DSM_CNTL2_DEFAULT 0x00000000
-#define mmTD_SCRATCH_DEFAULT 0x00000000
-#define mmTA_CNTL_DEFAULT 0x8004d850
-#define mmTA_CNTL_AUX_DEFAULT 0x00000000
-#define mmTA_RESERVED_010C_DEFAULT 0x00000000
-#define mmTA_GRAD_ADJ_DEFAULT 0x40000040
-#define mmTA_STATUS_DEFAULT 0x00000000
-#define mmTA_SCRATCH_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gdsdec
-#define mmGDS_CONFIG_DEFAULT 0x00000000
-#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000
-#define mmGDS_ENHANCE2_DEFAULT 0x00000000
-#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000
-#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000
-#define mmGDS_EDC_CNT_DEFAULT 0x00000000
-#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000
-#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000
-#define mmGDS_DSM_CNTL_DEFAULT 0x00000000
-#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000
-#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000
-#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000
-#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000
-
-
-// addressBlock: gc_rbdec
-#define mmDB_DEBUG_DEFAULT 0x00000000
-#define mmDB_DEBUG2_DEFAULT 0x00000000
-#define mmDB_DEBUG3_DEFAULT 0x00000000
-#define mmDB_DEBUG4_DEFAULT 0x00000000
-#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000
-#define mmDB_WATERMARKS_DEFAULT 0x01020204
-#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000
-#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000
-#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000
-#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000
-#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000
-#define mmDB_RING_CONTROL_DEFAULT 0x00000001
-#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404
-#define mmDB_RMI_CACHE_POLICY_DEFAULT 0x0f0f0f07
-#define mmDB_DFSM_CONFIG_DEFAULT 0x00007f00
-#define mmDB_DFSM_WATERMARK_DEFAULT 0x00640064
-#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x05dc03e8
-#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x00fa00c8
-#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240
-#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000003ff
-#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000
-#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000
-#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000
-#define mmGB_ADDR_CONFIG_DEFAULT 0x26010011
-#define mmGB_BACKEND_MAP_DEFAULT 0x33221100
-#define mmGB_GPU_ID_DEFAULT 0x00000000
-#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210
-#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x26010011
-#define mmGB_TILE_MODE0_DEFAULT 0x00000000
-#define mmGB_TILE_MODE1_DEFAULT 0x00000000
-#define mmGB_TILE_MODE2_DEFAULT 0x00000000
-#define mmGB_TILE_MODE3_DEFAULT 0x00000000
-#define mmGB_TILE_MODE4_DEFAULT 0x00000000
-#define mmGB_TILE_MODE5_DEFAULT 0x00000000
-#define mmGB_TILE_MODE6_DEFAULT 0x00000000
-#define mmGB_TILE_MODE7_DEFAULT 0x00000000
-#define mmGB_TILE_MODE8_DEFAULT 0x00000000
-#define mmGB_TILE_MODE9_DEFAULT 0x00000000
-#define mmGB_TILE_MODE10_DEFAULT 0x00000000
-#define mmGB_TILE_MODE11_DEFAULT 0x00000000
-#define mmGB_TILE_MODE12_DEFAULT 0x00000000
-#define mmGB_TILE_MODE13_DEFAULT 0x00000000
-#define mmGB_TILE_MODE14_DEFAULT 0x00000000
-#define mmGB_TILE_MODE15_DEFAULT 0x00000000
-#define mmGB_TILE_MODE16_DEFAULT 0x00000000
-#define mmGB_TILE_MODE17_DEFAULT 0x00000000
-#define mmGB_TILE_MODE18_DEFAULT 0x00000000
-#define mmGB_TILE_MODE19_DEFAULT 0x00000000
-#define mmGB_TILE_MODE20_DEFAULT 0x00000000
-#define mmGB_TILE_MODE21_DEFAULT 0x00000000
-#define mmGB_TILE_MODE22_DEFAULT 0x00000000
-#define mmGB_TILE_MODE23_DEFAULT 0x00000000
-#define mmGB_TILE_MODE24_DEFAULT 0x00000000
-#define mmGB_TILE_MODE25_DEFAULT 0x00000000
-#define mmGB_TILE_MODE26_DEFAULT 0x00000000
-#define mmGB_TILE_MODE27_DEFAULT 0x00000000
-#define mmGB_TILE_MODE28_DEFAULT 0x00000000
-#define mmGB_TILE_MODE29_DEFAULT 0x00000000
-#define mmGB_TILE_MODE30_DEFAULT 0x00000000
-#define mmGB_TILE_MODE31_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE0_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE1_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE2_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE3_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE8_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE9_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE10_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE11_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000
-#define mmCB_HW_CONTROL_DEFAULT 0x00014107
-#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000
-#define mmCB_HW_CONTROL_2_DEFAULT 0x00000000
-#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000
-#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000
-#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000
-#define mmCB_DCC_CONFIG_DEFAULT 0x04000000
-#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000
-#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_ea_gceadec2
-#define mmGCEA_EDC_CNT_DEFAULT 0x00000000
-#define mmGCEA_EDC_CNT2_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTLA_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTLB_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL2_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmGCEA_TCC_XBR_CREDITS_DEFAULT 0x637f637f
-#define mmGCEA_TCC_XBR_MAXBURST_DEFAULT 0x00003333
-#define mmGCEA_PROBE_CNTL_DEFAULT 0x00000000
-#define mmGCEA_PROBE_MAP_DEFAULT 0x0000aaaa
-#define mmGCEA_ERR_STATUS_DEFAULT 0x00000000
-#define mmGCEA_MISC2_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000
-#define mmGCEA_SDP_ENABLE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_rmi_rmidec
-#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000
-#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00001a03
-#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000
-#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00
-#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000300c0
-#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564
-#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200
-#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000
-#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000
-#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000
-#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e
-#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e
-#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00
-#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000
-#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000
-#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000
-#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800
-#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff
-#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822
-#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmRMI_SPARE_DEFAULT 0x00000001
-#define mmRMI_SPARE_1_DEFAULT 0x00000000
-#define mmRMI_SPARE_2_DEFAULT 0x00000000
-
-
-// addressBlock: gc_dbgu_gfx_dbgudec
-#define mmport_a_addr_DEFAULT 0x00000000
-#define mmport_a_data_lo_DEFAULT 0x00000000
-#define mmport_a_data_hi_DEFAULT 0x00000000
-#define mmport_b_addr_DEFAULT 0x00000000
-#define mmport_b_data_lo_DEFAULT 0x00000000
-#define mmport_b_data_hi_DEFAULT 0x00000000
-#define mmport_c_addr_DEFAULT 0x00000000
-#define mmport_c_data_lo_DEFAULT 0x00000000
-#define mmport_c_data_hi_DEFAULT 0x00000000
-#define mmport_d_addr_DEFAULT 0x00000000
-#define mmport_d_data_lo_DEFAULT 0x00000000
-#define mmport_d_data_hi_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_atcl2dec
-#define mmATC_L2_CNTL_DEFAULT 0x000001c9
-#define mmATC_L2_CNTL2_DEFAULT 0x00000100
-#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000
-#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000
-#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000
-#define mmATC_L2_CNTL3_DEFAULT 0x000001f8
-#define mmATC_L2_STATUS_DEFAULT 0x00000000
-#define mmATC_L2_STATUS2_DEFAULT 0x00000000
-#define mmATC_L2_MISC_CG_DEFAULT 0x00000200
-#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: gc_utcl2_vml2pfdec
-#define mmVM_L2_CNTL_DEFAULT 0x00080602
-#define mmVM_L2_CNTL2_DEFAULT 0x00000000
-#define mmVM_L2_CNTL3_DEFAULT 0x80100007
-#define mmVM_L2_STATUS_DEFAULT 0x00000000
-#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
-#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
-#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CNTL4_DEFAULT 0x000000c1
-#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
-#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
-#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
-#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
-#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: gc_utcl2_vml2vcdec
-#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_vmsharedpfdec
-#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
-#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
-#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
-#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
-#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
-#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
-#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
-#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmMC_VM_STEERING_DEFAULT 0x00000001
-#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
-#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000
-#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
-#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
-#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_vmsharedvcdec
-#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
-#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
-#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000
-#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000
-#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501
-
-
-// addressBlock: gc_ea_gceadec
-#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924
-#define mmGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324
-#define mmGCEA_DRAM_RD_LAZY_DEFAULT 0x00000924
-#define mmGCEA_DRAM_WR_LAZY_DEFAULT 0x00000924
-#define mmGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333
-#define mmGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333
-#define mmGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008
-#define mmGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
-#define mmGCEA_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03
-#define mmGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
-#define mmGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
-#define mmGCEA_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmGCEA_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_SDP_ARB_DRAM_DEFAULT 0x00102040
-#define mmGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff
-#define mmGCEA_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
-#define mmGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000
-#define mmGCEA_SDP_CREDITS_DEFAULT 0x000100bf
-#define mmGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000
-#define mmGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCD_RESERVE0_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCD_RESERVE1_DEFAULT 0x00000000
-#define mmGCEA_SDP_REQ_CNTL_DEFAULT 0x0000000f
-#define mmGCEA_MISC_DEFAULT 0x0de03ff0
-#define mmGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: gc_tcdec
-#define mmTCP_INVALIDATE_DEFAULT 0x00000000
-#define mmTCP_STATUS_DEFAULT 0x00000000
-#define mmTCP_CNTL_DEFAULT 0x2f9c0000
-#define mmTCP_CHAN_STEER_LO_DEFAULT 0x76543210
-#define mmTCP_CHAN_STEER_HI_DEFAULT 0xfedcba98
-#define mmTCP_ADDR_CONFIG_DEFAULT 0x000000f3
-#define mmTCP_CREDIT_DEFAULT 0x804001c0
-#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000
-#define mmTCP_EDC_CNT_DEFAULT 0x00000000
-#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT 0x00000000
-#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT 0x00000000
-#define mmTC_CFG_L1_STORE_POLICY_DEFAULT 0x00000000
-#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT 0x00000000
-#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT 0x00000000
-#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT 0x00000000
-#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT 0x00000000
-#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT 0x00000000
-#define mmTC_CFG_L1_VOLATILE_DEFAULT 0x00000000
-#define mmTC_CFG_L2_VOLATILE_DEFAULT 0x00000000
-#define mmTCI_STATUS_DEFAULT 0x00000000
-#define mmTCI_CNTL_1_DEFAULT 0x40080022
-#define mmTCI_CNTL_2_DEFAULT 0x00000041
-#define mmTCC_CTRL_DEFAULT 0xf30fff7f
-#define mmTCC_CTRL2_DEFAULT 0x0000000f
-#define mmTCC_EDC_CNT_DEFAULT 0x00000000
-#define mmTCC_EDC_CNT2_DEFAULT 0x00000000
-#define mmTCC_REDUNDANCY_DEFAULT 0x00000000
-#define mmTCC_EXE_DISABLE_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTLA_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL2_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmTCC_WBINVL2_DEFAULT 0x00000010
-#define mmTCC_SOFT_RESET_DEFAULT 0x00000000
-#define mmTCA_CTRL_DEFAULT 0x00000088
-#define mmTCA_BURST_MASK_DEFAULT 0xffffffff
-#define mmTCA_BURST_CTRL_DEFAULT 0x00000007
-#define mmTCA_DSM_CNTL_DEFAULT 0x00000000
-#define mmTCA_DSM_CNTL2_DEFAULT 0x00000000
-#define mmTCA_EDC_CNT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_shdec
-#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff
-#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff
-#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000800
-#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe
-#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000
-#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000
-#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000
-#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_START_X_DEFAULT 0x00000000
-#define mmCOMPUTE_START_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_START_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000
-#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001
-#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000
-#define mmCOMPUTE_VMID_DEFAULT 0x00000000
-#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff
-#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff
-#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000
-#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000
-#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000002
-#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000
-#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000
-#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000
-#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000
-#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cppdec
-#define mmCP_DFY_CNTL_DEFAULT 0x00000000
-#define mmCP_DFY_STAT_DEFAULT 0x00000000
-#define mmCP_DFY_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DFY_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_0_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_1_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_2_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_3_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_4_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_5_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_6_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_7_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_8_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_9_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_10_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_11_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_12_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_13_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_14_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_15_DEFAULT 0x00000000
-#define mmCP_DFY_CMD_DEFAULT 0x00000000
-#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c
-#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020
-#define mmCPC_INT_INFO_DEFAULT 0x00000000
-#define mmCP_VIRT_STATUS_DEFAULT 0x00000000
-#define mmCPC_INT_ADDR_DEFAULT 0x00000000
-#define mmCPC_INT_PASID_DEFAULT 0x00000000
-#define mmCP_GFX_ERROR_DEFAULT 0x00000000
-#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000
-#define mmCP_RB0_BASE_DEFAULT 0x00000000
-#define mmCP_RB_BASE_DEFAULT 0x00000000
-#define mmCP_RB0_CNTL_DEFAULT 0x00400000
-#define mmCP_RB_CNTL_DEFAULT 0x00400000
-#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000
-#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000
-#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmGC_PRIV_MODE_DEFAULT 0x00000000
-#define mmCP_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_DEVICE_ID_DEFAULT 0x00000000
-#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_FATAL_ERROR_DEFAULT 0x00000000
-#define mmCP_RB_VMID_DEFAULT 0x00000000
-#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000
-#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000
-#define mmCP_RB0_WPTR_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_DEFAULT 0x00000000
-#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmCP_RB1_WPTR_DEFAULT 0x00000000
-#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000
-#define mmCP_RB2_WPTR_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000044
-#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000048
-#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc
-#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000
-#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000
-#define mmCP_RB1_BASE_DEFAULT 0x00000000
-#define mmCP_RB1_CNTL_DEFAULT 0x00400000
-#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB2_BASE_DEFAULT 0x00000000
-#define mmCP_RB2_CNTL_DEFAULT 0x00400000
-#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB0_ACTIVE_DEFAULT 0x00000001
-#define mmCP_RB_ACTIVE_DEFAULT 0x00000001
-#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000
-#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000
-#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000
-#define mmCP_PWR_CNTL_DEFAULT 0x00000000
-#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200
-#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000
-#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000
-#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000
-#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000
-#define mmGB_EDC_MODE_DEFAULT 0x00000000
-#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001
-#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000
-#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002
-#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075
-#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007
-#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040
-#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040
-#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000
-#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000
-#define mmCP_VMID_RESET_DEFAULT 0x00000000
-#define mmCPC_INT_CNTL_DEFAULT 0x00000000
-#define mmCPC_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000
-#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000
-#define mmCP_PQ_STATUS_DEFAULT 0x00000000
-#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000000
-#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000
-#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000
-#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000
-#define mmCP_VMID_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cppdec2
-#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000
-#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
-#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB_STATUS_DEFAULT 0x00000000
-#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmCP_SD_CNTL_DEFAULT 0x0000001f
-#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000
-#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: gc_spipdec
-#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000
-#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000
-#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000
-#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
-#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f
-#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f
-#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000
-#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000
-#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cpphqddec
-#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000
-#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604
-#define mmCP_HPD_STATUS0_DEFAULT 0x01000000
-#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000
-#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000
-#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000
-#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000
-#define mmCP_HQD_VMID_DEFAULT 0x00000000
-#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301
-#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000
-#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
-#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
-#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000
-#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000
-#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000
-#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000
-#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000
-#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000
-#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000
-#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000
-#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000
-#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000
-#define mmCP_MQD_CONTROL_DEFAULT 0x00000100
-#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
-#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000
-#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000
-#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000
-#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000
-#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000
-#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000
-#define mmCP_HQD_ERROR_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000
-#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_didtdec
-#define mmDIDT_IND_INDEX_DEFAULT 0x00000000
-#define mmDIDT_IND_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gccacdec
-#define mmGC_CAC_CTRL_1_DEFAULT 0x01000000
-#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000
-#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000
-#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000
-#define mmGC_CAC_PG_AGGR_LOWER_DEFAULT 0x00000000
-#define mmGC_CAC_PG_AGGR_UPPER_DEFAULT 0x00000000
-#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000
-#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000
-#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000
-#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f
-#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000
-#define mmGC_EDC_CTRL_DEFAULT 0x00000000
-#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000
-#define mmGC_EDC_STATUS_DEFAULT 0x00000000
-#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000
-#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define mmGC_DIDT_DROOP_CTRL_DEFAULT 0x00000000
-#define mmGC_EDC_DROOP_CTRL_DEFAULT 0x00100000
-#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000
-#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000
-#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000
-#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: gc_tcpdec
-#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000
-#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000
-#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000
-#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000
-#define mmTCP_GATCL1_CNTL_DEFAULT 0x00000000
-#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT 0x00000000
-#define mmTCP_GATCL1_DSM_CNTL_DEFAULT 0x00000000
-#define mmTCP_CNTL2_DEFAULT 0x0000000a
-#define mmTCP_UTCL1_CNTL1_DEFAULT 0x00800400
-#define mmTCP_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmTCP_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gdspdec
-#define mmGDS_VMID0_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID1_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID2_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID3_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID4_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID5_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID6_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID7_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID8_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID9_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID10_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID11_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID12_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID13_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID14_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID15_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000
-#define mmGDS_GWS_VMID0_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID1_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID2_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID3_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID4_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID5_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID6_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID7_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID8_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID9_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID10_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID11_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID12_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID13_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID14_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID15_DEFAULT 0x00400000
-#define mmGDS_OA_VMID0_DEFAULT 0x00000000
-#define mmGDS_OA_VMID1_DEFAULT 0x00000000
-#define mmGDS_OA_VMID2_DEFAULT 0x00000000
-#define mmGDS_OA_VMID3_DEFAULT 0x00000000
-#define mmGDS_OA_VMID4_DEFAULT 0x00000000
-#define mmGDS_OA_VMID5_DEFAULT 0x00000000
-#define mmGDS_OA_VMID6_DEFAULT 0x00000000
-#define mmGDS_OA_VMID7_DEFAULT 0x00000000
-#define mmGDS_OA_VMID8_DEFAULT 0x00000000
-#define mmGDS_OA_VMID9_DEFAULT 0x00000000
-#define mmGDS_OA_VMID10_DEFAULT 0x00000000
-#define mmGDS_OA_VMID11_DEFAULT 0x00000000
-#define mmGDS_OA_VMID12_DEFAULT 0x00000000
-#define mmGDS_OA_VMID13_DEFAULT 0x00000000
-#define mmGDS_OA_VMID14_DEFAULT 0x00000000
-#define mmGDS_OA_VMID15_DEFAULT 0x00000000
-#define mmGDS_GWS_RESET0_DEFAULT 0x00000000
-#define mmGDS_GWS_RESET1_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000
-#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x0000015f
-#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000
-#define mmGDS_OA_RESET_DEFAULT 0x00000000
-#define mmGDS_ENHANCE_DEFAULT 0x00000000
-#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000
-
-
-// addressBlock: gc_rasdec
-#define mmRAS_SIGNATURE_CONTROL_DEFAULT 0x00000000
-#define mmRAS_SIGNATURE_MASK_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE2_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE3_DEFAULT 0x00000000
-#define mmRAS_DB_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_PA_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_VGT_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SQ_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE2_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE3_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE4_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE5_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE6_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE7_DEFAULT 0x00000000
-#define mmRAS_IA_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_IA_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_SPI_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SPI_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_TA_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_TD_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_CB_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_BCI_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_BCI_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_TA_SIGNATURE1_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gfxdec0
-#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000
-#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000
-#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000
-#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000
-#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000
-#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000
-#define mmDB_DEPTH_SIZE_DEFAULT 0x00000000
-#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000
-#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000
-#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000
-#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000
-#define mmDB_Z_INFO_DEFAULT 0x00000000
-#define mmDB_STENCIL_INFO_DEFAULT 0x00000000
-#define mmDB_Z_READ_BASE_DEFAULT 0x00000000
-#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000
-#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000
-#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000
-#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000
-#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000
-#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
-#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000
-#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000
-#define mmDB_RENDER_FILTER_DEFAULT 0x00000000
-#define mmDB_Z_INFO2_DEFAULT 0x00000000
-#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000
-#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000
-#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000
-#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000
-#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000
-#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000
-#define mmPA_SC_EDGERULE_DEFAULT 0x00000000
-#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000
-#define mmCB_TARGET_MASK_DEFAULT 0x00000000
-#define mmCB_SHADER_MASK_DEFAULT 0x00000000
-#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000
-#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000
-#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000
-#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000
-#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000
-#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000
-#define mmCP_PIPEID_DEFAULT 0x00000000
-#define mmCP_RINGID_DEFAULT 0x00000000
-#define mmCP_VMID_DEFAULT 0x00000000
-#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000
-#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000
-#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000
-#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000
-#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000
-#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000
-#define mmCB_BLEND_RED_DEFAULT 0x00000000
-#define mmCB_BLEND_GREEN_DEFAULT 0x00000000
-#define mmCB_BLEND_BLUE_DEFAULT 0x00000000
-#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000
-#define mmCB_DCC_CONTROL_DEFAULT 0x00000000
-#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000
-#define mmDB_STENCILREFMASK_DEFAULT 0x00000000
-#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000
-#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000
-#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000
-#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000
-#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000
-#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000
-#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000
-#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000
-#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000
-#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000
-#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000
-#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000
-#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000
-#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000
-#define mmCB_MRT0_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT1_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT2_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT3_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT4_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT5_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT6_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT7_EPITCH_DEFAULT 0x00000000
-#define mmCS_COPY_STATE_DEFAULT 0x00000000
-#define mmGFX_COPY_STATE_DEFAULT 0x00000000
-#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000
-#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000
-#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000
-#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000
-#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000
-#define mmVGT_DMA_BASE_DEFAULT 0x00000000
-#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000
-#define mmVGT_IMMED_DATA_DEFAULT 0x00000000
-#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000
-#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000
-#define mmDB_EQAA_DEFAULT 0x00000000
-#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000
-#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000
-#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000
-#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000
-#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000
-#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000
-#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000
-#define mmVGT_HOS_CNTL_DEFAULT 0x00000000
-#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000
-#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000
-#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000
-#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000
-#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000
-#define mmVGT_GROUP_DECR_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000
-#define mmVGT_GS_MODE_DEFAULT 0x00000000
-#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000
-#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000
-#define mmVGT_ENHANCE_DEFAULT 0x00000000
-#define mmVGT_GS_PER_ES_DEFAULT 0x00000000
-#define mmVGT_ES_PER_GS_DEFAULT 0x00000000
-#define mmVGT_GS_PER_VS_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000
-#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000
-#define mmIA_ENHANCE_DEFAULT 0x00000000
-#define mmVGT_DMA_SIZE_DEFAULT 0x00000000
-#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000
-#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000
-#define mmWD_ENHANCE_DEFAULT 0x00000000
-#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000
-#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000
-#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000
-#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000
-#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000
-#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000
-#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000
-#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000
-#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000
-#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000
-#define mmVGT_REUSE_OFF_DEFAULT 0x00000000
-#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000
-#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000
-#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000
-#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000
-#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000
-#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000
-#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000
-#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000
-#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000
-#define mmVGT_TF_PARAM_DEFAULT 0x00000000
-#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000
-#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000
-#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000
-#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000
-#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000
-#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000
-#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000
-#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000
-#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000
-#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000
-#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000
-#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000
-#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000
-#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000
-#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000
-#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000
-#define mmCB_COLOR0_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR0_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR1_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR2_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR3_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR4_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR5_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR6_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR7_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gfxudec
-#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000
-#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000
-#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000
-#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000
-#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000
-#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000
-#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000
-#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000
-#define mmSCRATCH_REG0_DEFAULT 0x00000000
-#define mmSCRATCH_REG1_DEFAULT 0x00000000
-#define mmSCRATCH_REG2_DEFAULT 0x00000000
-#define mmSCRATCH_REG3_DEFAULT 0x00000000
-#define mmSCRATCH_REG4_DEFAULT 0x00000000
-#define mmSCRATCH_REG5_DEFAULT 0x00000000
-#define mmSCRATCH_REG6_DEFAULT 0x00000000
-#define mmSCRATCH_REG7_DEFAULT 0x00000000
-#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000
-#define mmSCRATCH_UMSK_DEFAULT 0x00000000
-#define mmSCRATCH_ADDR_DEFAULT 0x00000000
-#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000
-#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000
-#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000
-#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000
-#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000
-#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000
-#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000
-#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000
-#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000
-#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000
-#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000
-#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000
-#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020
-#define mmCP_COHER_CNTL_DEFAULT 0x00000000
-#define mmCP_COHER_SIZE_DEFAULT 0x00000000
-#define mmCP_COHER_BASE_DEFAULT 0x00000000
-#define mmCP_COHER_STATUS_DEFAULT 0x00000000
-#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000
-#define mmCP_DMA_CNTL_DEFAULT 0x00080030
-#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000
-#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000
-#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000
-#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000
-#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000
-#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmCP_RB_OFFSET_DEFAULT 0x00000000
-#define mmCP_IB1_OFFSET_DEFAULT 0x00000000
-#define mmCP_IB2_OFFSET_DEFAULT 0x00000000
-#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000
-#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000
-#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000
-#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000
-#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000
-#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000
-#define mmCP_CE_COUNTER_DEFAULT 0x00000000
-#define mmCP_CE_RB_OFFSET_DEFAULT 0x00000000
-#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000
-#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000
-#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000
-#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000
-#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000
-#define mmCP_ST_BASE_LO_DEFAULT 0x00000000
-#define mmCP_ST_BASE_HI_DEFAULT 0x00000000
-#define mmCP_ST_BUFSZ_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000
-#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000
-#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000
-#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000
-#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000
-#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000
-#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_INDEX_TYPE_DEFAULT 0x00000000
-#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000
-#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000
-#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000
-#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000
-#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000
-#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000
-#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000
-#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000
-#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000
-#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000
-#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000
-#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000
-#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000
-#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000
-#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000
-#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000
-#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000
-#define mmVGT_NUM_INDICES_DEFAULT 0x00000000
-#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000
-#define mmVGT_TF_RING_SIZE_DEFAULT 0x00002000
-#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000
-#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000
-#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000
-#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000
-#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000
-#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000
-#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000
-#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000
-#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000
-#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff
-#define mmVGT_OBJECT_ID_DEFAULT 0x00000000
-#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000
-#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000
-#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff
-#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000
-#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff
-#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000
-#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_BASE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x0000cf80
-#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff
-#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff
-#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_MODE_DEFAULT 0x02049249
-#define mmSQ_THREAD_TRACE_BASE2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT 0xffffffff
-#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000
-#define mmSQC_CACHES_DEFAULT 0x00000000
-#define mmSQC_WRITEBACK_DEFAULT 0x00000000
-#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000
-#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040
-#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000
-#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000
-#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000
-#define mmGDS_RD_ADDR_DEFAULT 0x00000000
-#define mmGDS_RD_DATA_DEFAULT 0x00000000
-#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000
-#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000
-#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000
-#define mmGDS_WR_ADDR_DEFAULT 0x00000000
-#define mmGDS_WR_DATA_DEFAULT 0x00000000
-#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000
-#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000
-#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000
-#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000
-#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001
-#define mmGDS_ATOM_BASE_DEFAULT 0x00000000
-#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000
-#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000
-#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000
-#define mmGDS_ATOM_DST_DEFAULT 0x00000000
-#define mmGDS_ATOM_OP_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ0_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ1_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000
-#define mmGDS_OA_CNTL_DEFAULT 0x00000000
-#define mmGDS_OA_COUNTER_DEFAULT 0x00000000
-#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000
-#define mmGDS_OA_INCDEC_DEFAULT 0x00000000
-#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000
-#define mmSPI_CONFIG_CNTL_DEFAULT 0x0062c688
-#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x01000104
-#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011
-
-
-// addressBlock: gc_perfddec
-#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000
-#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000
-#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_atcl2pfcntrdec
-#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_vml2prdec
-#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_perfsdec
-#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
-#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
-#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
-#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
-#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
-#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
-#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
-#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
-#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
-#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
-#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
-#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000
-#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000
-#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000
-#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000
-#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007
-#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000000ff
-#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000000ff
-#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430
-#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER_MASK_DEFAULT 0xffffffff
-#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
-#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
-#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
-#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
-#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
-#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
-#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000
-#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000
-#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000
-#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000
-#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000
-#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000
-#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000
-#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001
-#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240
-
-
-// addressBlock: gc_utcl2_atcl2pfcntldec
-#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: gc_utcl2_vml2pldec
-#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: gc_rlcpdec
-#define mmRLC_CNTL_DEFAULT 0x00000001
-#define mmRLC_STAT_DEFAULT 0x00000000
-#define mmRLC_SAFE_MODE_DEFAULT 0x00000000
-#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200
-#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000
-#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000
-#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000
-#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000
-#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000
-#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000
-#define mmRLC_LB_CNTR_MAX_DEFAULT 0xffffffff
-#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT 0x00000000
-#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT 0x00000000
-#define mmRLC_INT_STAT_DEFAULT 0x00000000
-#define mmRLC_LB_CNTL_DEFAULT 0x00000010
-#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800
-#define mmRLC_LB_CNTR_INIT_DEFAULT 0x00000000
-#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT 0x00000000
-#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000
-#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004
-#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000
-#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000
-#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000
-#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x0000000f
-#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000
-#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000
-#define mmRLC_FIREWALL_VIOLATION_DEFAULT 0x00000000
-#define mmRLC_GPM_STAT_DEFAULT 0x00100016
-#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000
-#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000
-#define mmRLC_PG_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808
-#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001
-#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0xffffffff
-#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c
-#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711
-#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff
-#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff
-#define mmRLC_PG_DELAY_DEFAULT 0x00101010
-#define mmRLC_CU_STATUS_DEFAULT 0x00000000
-#define mmRLC_LB_INIT_CU_MASK_DEFAULT 0xffffffff
-#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT 0x00000001
-#define mmRLC_LB_PARAMS_DEFAULT 0x00601008
-#define mmRLC_THREAD1_DELAY_DEFAULT 0x00400401
-#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT 0x00000003
-#define mmRLC_MAX_PG_CU_DEFAULT 0x0000000b
-#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000
-#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_CTRL_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_DATA_DEFAULT 0x00000000
-#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT 0x00000000
-#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000
-#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff
-#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000
-#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000
-#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000
-#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000
-#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000
-#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000
-#define mmRLC_GPR_REG1_DEFAULT 0x00000000
-#define mmRLC_GPR_REG2_DEFAULT 0x00000000
-#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT 0x00000000
-#define mmRLC_SRM_CNTL_DEFAULT 0x00000002
-#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000
-#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000
-#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000
-#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000
-#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000
-#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000
-#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000
-#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000
-#define mmRLC_SRM_STAT_DEFAULT 0x00000000
-#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000
-#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000
-#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000
-#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000
-#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000
-#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840
-#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000
-#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080
-#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080
-#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080
-#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_2_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_3_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_4_DEFAULT 0x00000000
-#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_1_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c
-#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711
-#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000
-#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000
-#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000
-#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000
-#define mmRLC_SPARE_INT_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000
-#define mmRLC_DSM_TRIG_DEFAULT 0x00000000
-#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000
-#define mmRLC_UTCL2_CNTL_DEFAULT 0x00000000
-#define mmRLC_LBPW_CU_STAT_DEFAULT 0x00000000
-#define mmRLC_DS_CNTL_DEFAULT 0x00030003
-#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_pwrdec
-#define mmCGTS_SM_CTRL_REG_DEFAULT 0x00600200
-#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000
-#define mmCGTS_RD_REG_DEFAULT 0x00000000
-#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000
-#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000
-#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT 0x00000001
-#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100
-#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100
-#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100
-#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100
-#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100
-#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100
-#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000
-#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000
-#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000
-#define mmSQ_POWER_THROTTLE_DEFAULT 0x3fff3fff
-#define mmSQ_POWER_THROTTLE2_DEFAULT 0x18800004
-#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100
-#define mmTD_CGTT_CTRL_DEFAULT 0x00000100
-#define mmTA_CGTT_CTRL_DEFAULT 0x00000100
-#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100
-#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100
-#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmTCC_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmTCA_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100
-#define mmRLC_PWR_CTRL_DEFAULT 0x00000000
-#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100
-#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000
-#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000100
-
-
-// addressBlock: gc_ea_pwrdec
-#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100
-
-
-// addressBlock: gc_utcl2_vmsharedhvdec
-#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
-#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
-#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
-#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
-#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
-#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: gc_hypdec
-#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000
-#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000
-#define mmCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000
-#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_CE_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000
-#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000
-#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000
-#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000
-#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000
-#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000
-#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000
-#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000
-#define mmGRBM_CAM_DATA_DEFAULT 0x00000000
-#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000
-#define mmRLC_GFX_RM_CNTL_ADJ_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000
-#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000000
-#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000
-#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x0000ffff
-#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x00010001
-#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000
-#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000
-#define mmRLC_CLK_CNTL_DEFAULT 0x00000003
-#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: gccacind
-#define ixGC_CAC_CNTL_DEFAULT 0x000001fe
-#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000
-#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_IA_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_3_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_4_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_TCC_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCC_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCC_2_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_VGT_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_VGT_1_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_WD_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_3_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_4_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_5_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_IA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_PG_0_DEFAULT 0x00000001
-#define ixGC_CAC_ACC_PG0_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_PG_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001
-#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SXRB1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_VGT0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_VGT1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_VGT2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_WD0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU5_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU6_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU7_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU8_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU9_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU10_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_IA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TCC_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_VGT_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_WD_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000
-
-
-// addressBlock: secacind
-#define ixSE_CAC_CNTL_DEFAULT 0x000001fe
-#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000
-#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000
-
-
-// addressBlock: sqind
-#define ixSQ_WAVE_MODE_DEFAULT 0x00000000
-#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000
-#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000
-#define ixSQ_WAVE_HW_ID_DEFAULT 0x00000000
-#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000
-#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000
-#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000
-#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000
-#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000
-#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000
-#define ixSQ_WAVE_INST_DW1_DEFAULT 0x00000000
-#define ixSQ_WAVE_IB_DBG0_DEFAULT 0x00000000
-#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000
-#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000
-#define ixSQ_WAVE_M0_DEFAULT 0x00000000
-#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000
-#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_AUTO_CTXID_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_AUTO_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_AUTO_LO_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_CMN_CTXID_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_CMN_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_WAVE_CTXID_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_WAVE_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_WAVE_LO_DEFAULT 0x00000000
-
-
-
-
-
-
-
-
-// addressBlock: didtind
-#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_DBR_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_DBR_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_DBR_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_DBR_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_DBR_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_DBR_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_DBR_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DBR_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DBR_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DBR_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DBR_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_DBR_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_DBR_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_DBR_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DBR_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DBR_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_DBR_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-
-
-
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
deleted file mode 100644
index ab0a25e..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
+++ /dev/null
@@ -1,31191 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _gc_9_1_SH_MASK_HEADER
-#define _gc_9_1_SH_MASK_HEADER
-
-
-// addressBlock: gc_grbmdec
-//GRBM_CNTL
-#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
-#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
-#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
-#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
-//GRBM_SKEW_CNTL
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
-#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
-#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
-//GRBM_STATUS2
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
-#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
-#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
-#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
-#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
-#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
-#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
-#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
-#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
-#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
-#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
-#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
-#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
-#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
-#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
-#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
-#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
-#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
-#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
-#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
-#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
-#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
-#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
-#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
-#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
-#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
-#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
-//GRBM_PWR_CNTL
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
-#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
-#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
-#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
-#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
-//GRBM_STATUS
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
-#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
-#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
-#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
-#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
-#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
-#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
-#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
-#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
-#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
-#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
-#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
-#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
-#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
-#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
-#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
-#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
-#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
-#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
-#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
-#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
-#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
-#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
-#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
-#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
-#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
-#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
-#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
-#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
-#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
-#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
-#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
-#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
-#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
-#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
-//GRBM_STATUS_SE0
-#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
-//GRBM_STATUS_SE1
-#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
-//GRBM_SOFT_RESET
-#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
-#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
-#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
-#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
-#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
-//GRBM_CGTT_CLK_CNTL
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-//GRBM_GFX_CLKEN_CNTL
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
-//GRBM_WAIT_IDLE_CLOCKS
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
-//GRBM_STATUS_SE2
-#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
-//GRBM_STATUS_SE3
-#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
-//GRBM_READ_ERROR
-#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
-#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
-#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
-#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
-#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
-#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
-#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
-#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
-//GRBM_READ_ERROR2
-#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
-#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
-#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
-//GRBM_INT_CNTL
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
-//GRBM_TRAP_OP
-#define GRBM_TRAP_OP__RW__SHIFT 0x0
-#define GRBM_TRAP_OP__RW_MASK 0x00000001L
-//GRBM_TRAP_ADDR
-#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
-//GRBM_TRAP_ADDR_MSK
-#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
-//GRBM_TRAP_WD
-#define GRBM_TRAP_WD__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
-//GRBM_TRAP_WD_MSK
-#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
-//GRBM_DSM_BYPASS
-#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
-#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
-#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
-#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
-//GRBM_WRITE_ERROR
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
-#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
-#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
-#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
-#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
-#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
-#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
-#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
-#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
-#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
-#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
-#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
-#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
-#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
-#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
-//GRBM_IOV_ERROR
-#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
-#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
-#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
-#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
-#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
-#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
-#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
-#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
-#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
-#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
-//GRBM_CHIP_REVISION
-#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
-#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
-//GRBM_GFX_CNTL
-#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
-#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
-#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
-#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
-#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
-#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
-#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
-#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
-//GRBM_RSMU_CFG
-#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
-#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
-#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
-#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
-#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
-#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
-//GRBM_IH_CREDIT
-#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
-#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
-//GRBM_PWR_CNTL2
-#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
-#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
-#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
-#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
-//GRBM_UTCL2_INVAL_RANGE_START
-#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
-#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
-//GRBM_UTCL2_INVAL_RANGE_END
-#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
-#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
-//GRBM_RSMU_READ_ERROR
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
-//GRBM_CHICKEN_BITS
-#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
-#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
-//GRBM_NOWHERE
-#define GRBM_NOWHERE__DATA__SHIFT 0x0
-#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG1
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG2
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG3
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG4
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG5
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG6
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG7
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_cpdec
-//CP_CPC_STATUS
-#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
-#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
-#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
-#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
-#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
-#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
-#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
-#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
-#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
-#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
-#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
-#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
-#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
-#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
-#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
-#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
-#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
-#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
-#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
-#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
-#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
-#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
-#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
-#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
-#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
-#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
-#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
-#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
-#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
-#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
-//CP_CPC_BUSY_STAT
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
-//CP_CPC_STALLED_STAT1
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
-#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
-#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
-//CP_CPF_STATUS
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
-#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
-#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
-#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
-#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
-#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
-#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
-#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
-#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
-#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
-#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
-#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
-#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
-#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
-#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
-#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
-#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
-#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
-#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
-#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
-#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
-#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
-#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
-#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
-#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
-#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
-//CP_CPF_BUSY_STAT
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
-//CP_CPF_STALLED_STAT1
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
-#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
-#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
-#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
-#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
-#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
-#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
-//CP_CPC_GRBM_FREE_COUNT
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
-//CP_MEC_CNTL
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
-#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
-#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
-#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
-#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
-#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
-#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
-#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
-#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
-//CP_MEC_ME1_HEADER_DUMP
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_MEC_ME2_HEADER_DUMP
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_CPC_SCRATCH_INDEX
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
-//CP_CPC_SCRATCH_DATA
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
-//CP_CPF_GRBM_FREE_COUNT
-#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
-//CP_CPC_HALT_HYST_COUNT
-#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
-#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
-//CP_PRT_LOD_STATS_CNTL0
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL
-//CP_PRT_LOD_STATS_CNTL1
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL
-//CP_PRT_LOD_STATS_CNTL2
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL
-//CP_PRT_LOD_STATS_CNTL3
-#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2
-#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
-#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12
-#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13
-#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17
-#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c
-#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL
-#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L
-#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L
-#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L
-#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L
-#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L
-//CP_CE_COMPARE_COUNT
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
-//CP_CE_DE_COUNT
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_CE_COUNT
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_LAST_INVAL_COUNT
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_DE_COUNT
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_STALLED_STAT3
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
-#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
-#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
-//CP_STALLED_STAT1
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
-//CP_STALLED_STAT2
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
-//CP_BUSY_STAT
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
-#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
-#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
-#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
-#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
-#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
-#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
-#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
-#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
-#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
-#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
-#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
-#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
-#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
-#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
-#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
-#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
-#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
-#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
-//CP_STAT
-#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
-#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
-#define CP_STAT__DC_BUSY__SHIFT 0xd
-#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
-#define CP_STAT__PFP_BUSY__SHIFT 0xf
-#define CP_STAT__MEQ_BUSY__SHIFT 0x10
-#define CP_STAT__ME_BUSY__SHIFT 0x11
-#define CP_STAT__QUERY_BUSY__SHIFT 0x12
-#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
-#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
-#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
-#define CP_STAT__DMA_BUSY__SHIFT 0x16
-#define CP_STAT__RCIU_BUSY__SHIFT 0x17
-#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
-#define CP_STAT__CE_BUSY__SHIFT 0x1a
-#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
-#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
-#define CP_STAT__CP_BUSY__SHIFT 0x1f
-#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
-#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
-#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
-#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
-#define CP_STAT__DC_BUSY_MASK 0x00002000L
-#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
-#define CP_STAT__PFP_BUSY_MASK 0x00008000L
-#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
-#define CP_STAT__ME_BUSY_MASK 0x00020000L
-#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
-#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
-#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
-#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
-#define CP_STAT__DMA_BUSY_MASK 0x00400000L
-#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
-#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
-#define CP_STAT__CE_BUSY_MASK 0x04000000L
-#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
-#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
-#define CP_STAT__CP_BUSY_MASK 0x80000000L
-//CP_ME_HEADER_DUMP
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_PFP_HEADER_DUMP
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_GRBM_FREE_COUNT
-#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
-//CP_CE_HEADER_DUMP
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_PFP_INSTR_PNTR
-#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_ME_INSTR_PNTR
-#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_CE_INSTR_PNTR
-#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_MEC1_INSTR_PNTR
-#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_MEC2_INSTR_PNTR
-#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_CSF_STAT
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
-//CP_ME_CNTL
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
-#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
-#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
-#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
-#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
-#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
-#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
-#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
-#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
-#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
-#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
-#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
-#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
-#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
-#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
-#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
-#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
-#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
-#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
-#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
-#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
-#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
-#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
-#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
-#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
-//CP_CNTX_STAT
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
-//CP_ME_PREEMPTION
-#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
-#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
-//CP_ROQ_THRESHOLDS
-#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
-#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
-#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
-#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
-//CP_MEQ_STQ_THRESHOLD
-#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
-#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
-//CP_RB2_RPTR
-#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB1_RPTR
-#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB0_RPTR
-#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB_RPTR
-#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB_WPTR_DELAY
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
-//CP_RB_WPTR_POLL_CNTL
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//CP_ROQ1_THRESHOLDS
-#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
-#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
-#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
-#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
-//CP_ROQ2_THRESHOLDS
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
-//CP_STQ_THRESHOLDS
-#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
-#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
-#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
-#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
-#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
-#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
-//CP_QUEUE_THRESHOLDS
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
-//CP_MEQ_THRESHOLDS
-#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
-#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
-#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
-#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
-//CP_ROQ_AVAIL
-#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
-#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
-//CP_STQ_AVAIL
-#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
-#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
-//CP_ROQ2_AVAIL
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
-//CP_MEQ_AVAIL
-#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
-#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
-//CP_CMD_INDEX
-#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
-#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
-#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
-#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
-#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
-#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
-//CP_CMD_DATA
-#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
-#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
-//CP_ROQ_RB_STAT
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
-//CP_ROQ_IB1_STAT
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
-//CP_ROQ_IB2_STAT
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
-//CP_STQ_STAT
-#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
-#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
-//CP_STQ_WR_STAT
-#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
-#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
-//CP_MEQ_STAT
-#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
-#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
-#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
-#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
-//CP_CEQ1_AVAIL
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
-//CP_CEQ2_AVAIL
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
-//CP_CE_ROQ_RB_STAT
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
-//CP_CE_ROQ_IB1_STAT
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
-//CP_CE_ROQ_IB2_STAT
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-
-
-// addressBlock: gc_padec
-//VGT_VTX_VECT_EJECT_REG
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
-//VGT_DMA_DATA_FIFO_DEPTH
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
-//VGT_DMA_REQ_FIFO_DEPTH
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
-//VGT_DRAW_INIT_FIFO_DEPTH
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
-//VGT_LAST_COPY_STATE
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
-//VGT_CACHE_INVALIDATION
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
-#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
-#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
-#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
-#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
-//VGT_STRMOUT_DELAY
-#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
-#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
-//VGT_FIFO_DEPTHS
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
-#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
-#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
-//VGT_GS_VERTEX_REUSE
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
-//VGT_MC_LAT_CNTL
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
-//IA_CNTL_STATUS
-#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
-#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
-#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
-#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
-#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
-#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
-#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
-#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
-//VGT_CNTL_STATUS
-#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
-#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
-#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
-#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
-#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
-#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
-#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
-#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
-#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
-#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
-#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
-#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
-#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
-#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
-#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
-#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
-//WD_CNTL_STATUS
-#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
-#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
-#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
-#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
-//CC_GC_PRIM_CONFIG
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
-//GC_USER_PRIM_CONFIG
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
-//WD_QOS
-#define WD_QOS__DRAW_STALL__SHIFT 0x0
-#define WD_QOS__DRAW_STALL_MASK 0x00000001L
-//WD_UTCL1_CNTL
-#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-//WD_UTCL1_STATUS
-#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//IA_UTCL1_CNTL
-#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-//IA_UTCL1_STATUS
-#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//VGT_SYS_CONFIG
-#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
-#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
-//VGT_VS_MAX_WAVE_ID
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//VGT_GS_MAX_WAVE_ID
-#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//GFX_PIPE_CONTROL
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
-#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
-#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
-//CC_GC_SHADER_ARRAY_CONFIG
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
-//GC_USER_SHADER_ARRAY_CONFIG
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
-//VGT_DMA_PRIMITIVE_TYPE
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
-//VGT_DMA_CONTROL
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
-#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
-#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
-#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
-#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
-#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
-#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
-#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
-//VGT_DMA_LS_HS_CONFIG
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
-//WD_BUF_RESOURCE_1
-#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
-#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
-#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
-#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
-//WD_BUF_RESOURCE_2
-#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
-#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
-#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
-#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
-#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
-#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
-//PA_CL_CNTL_STATUS
-#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
-#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
-#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
-#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
-#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
-#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
-//PA_CL_ENHANCE
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
-#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
-#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
-#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
-#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
-#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
-#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
-#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
-#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
-#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
-#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
-#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
-#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
-#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
-#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
-#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
-#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
-#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
-#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
-#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
-#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
-#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
-#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
-//PA_SU_CNTL_STATUS
-#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
-#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
-//PA_SC_FIFO_DEPTH_CNTL
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
-//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_TRAP_SCREEN_HV_LOCK
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_FORCE_EOV_MAX_CNTS
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
-//PA_SC_BINNER_EVENT_CNTL_0
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_1
-#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_2
-#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_3
-#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
-//PA_SC_BINNER_TIMEOUT_COUNTER
-#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
-//PA_SC_BINNER_PERF_CNTL_0
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
-//PA_SC_BINNER_PERF_CNTL_1
-#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
-#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
-//PA_SC_BINNER_PERF_CNTL_2
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
-//PA_SC_BINNER_PERF_CNTL_3
-#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
-//PA_SC_FIFO_SIZE
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
-//PA_SC_IF_FIFO_SIZE
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
-//PA_SC_PKR_WAVE_TABLE_CNTL
-#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
-#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
-//PA_UTCL1_CNTL1
-#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
-#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
-#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
-#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
-#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
-#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//PA_UTCL1_CNTL2
-#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
-#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
-#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
-#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
-#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
-#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
-#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
-#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
-#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
-#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
-#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
-#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
-//PA_SIDEBAND_REQUEST_DELAYS
-#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
-#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
-#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
-#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
-//PA_SC_ENHANCE
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
-#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
-#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
-#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
-#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
-//PA_SC_ENHANCE_1
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
-#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
-#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
-#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
-#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
-#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
-#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
-#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
-#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
-#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
-#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
-#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
-#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
-#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
-#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
-#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
-#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
-#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
-#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
-#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
-#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
-#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
-#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
-#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
-#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
-#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
-#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
-#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
-#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
-#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
-#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L
-//PA_SC_DSM_CNTL
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
-//PA_SC_TILE_STEERING_CREST_OVERRIDE
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
-
-
-// addressBlock: gc_sqdec
-//SQ_CONFIG
-#define SQ_CONFIG__UNUSED__SHIFT 0x0
-#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
-#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
-#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
-#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
-#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
-#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
-#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
-#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
-#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
-#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
-#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
-#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
-#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
-#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
-#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
-//SQC_CONFIG
-#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
-#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
-#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
-#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
-#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
-#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
-#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
-#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
-#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
-#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
-#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
-#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
-#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
-#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
-#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
-#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
-#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
-#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
-#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
-#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
-#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
-#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
-#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
-#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
-#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
-#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
-#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
-#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
-#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
-#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
-//LDS_CONFIG
-#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
-#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
-//SQ_RANDOM_WAVE_PRI
-#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
-#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
-#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
-#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
-#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
-#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
-//SQ_REG_CREDITS
-#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
-#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
-#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
-#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
-#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
-#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
-#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
-#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
-#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
-#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
-#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
-#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
-//SQ_FIFO_SIZES
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
-//SQ_DSM_CNTL
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQ_DSM_CNTL2
-#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
-#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
-#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
-#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
-#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
-#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
-//SQ_RUNTIME_CONFIG
-#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
-#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
-//SH_MEM_BASES
-#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
-#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
-#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
-#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
-//SH_MEM_CONFIG
-#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
-#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
-#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
-#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
-#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
-#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
-#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
-#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
-//CC_GC_SHADER_RATE_CONFIG
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
-//GC_USER_SHADER_RATE_CONFIG
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
-//SQ_INTERRUPT_AUTO_MASK
-#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
-#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
-//SQ_INTERRUPT_MSG_CTRL
-#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
-#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
-//SQ_UTCL1_CNTL1
-#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
-#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
-#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
-#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
-#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQ_UTCL1_CNTL2
-#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
-#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
-#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
-#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
-//SQ_UTCL1_STATUS
-#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
-#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
-#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
-#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
-//SQ_SHADER_TBA_LO
-#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_SHADER_TBA_HI
-#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
-//SQ_SHADER_TMA_LO
-#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_SHADER_TMA_HI
-#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
-//SQC_DSM_CNTL
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//SQC_DSM_CNTLA
-#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQC_DSM_CNTLB
-#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQC_DSM_CNTL2
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//SQC_DSM_CNTL2A
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-//SQC_DSM_CNTL2B
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-//SQC_EDC_FUE_CNTL
-#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
-#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
-#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
-#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
-//SQC_EDC_CNT2
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L
-//SQC_EDC_CNT3
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
-//SQ_REG_TIMESTAMP
-#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
-//SQ_CMD_TIMESTAMP
-#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
-//SQ_IND_INDEX
-#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
-#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
-#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
-#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
-#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
-#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
-#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
-#define SQ_IND_INDEX__INDEX__SHIFT 0x10
-#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
-#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
-#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
-#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
-#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
-#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
-#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
-#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
-//SQ_IND_DATA
-#define SQ_IND_DATA__DATA__SHIFT 0x0
-#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
-//SQ_CMD
-#define SQ_CMD__CMD__SHIFT 0x0
-#define SQ_CMD__MODE__SHIFT 0x4
-#define SQ_CMD__CHECK_VMID__SHIFT 0x7
-#define SQ_CMD__DATA__SHIFT 0x8
-#define SQ_CMD__WAVE_ID__SHIFT 0x10
-#define SQ_CMD__SIMD_ID__SHIFT 0x14
-#define SQ_CMD__QUEUE_ID__SHIFT 0x18
-#define SQ_CMD__VM_ID__SHIFT 0x1c
-#define SQ_CMD__CMD_MASK 0x00000007L
-#define SQ_CMD__MODE_MASK 0x00000070L
-#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
-#define SQ_CMD__DATA_MASK 0x00000F00L
-#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
-#define SQ_CMD__SIMD_ID_MASK 0x00300000L
-#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
-#define SQ_CMD__VM_ID_MASK 0xF0000000L
-//SQ_TIME_HI
-#define SQ_TIME_HI__TIME__SHIFT 0x0
-#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
-//SQ_TIME_LO
-#define SQ_TIME_LO__TIME__SHIFT 0x0
-#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
-//SQ_DS_0
-#define SQ_DS_0__OFFSET0__SHIFT 0x0
-#define SQ_DS_0__OFFSET1__SHIFT 0x8
-#define SQ_DS_0__GDS__SHIFT 0x10
-#define SQ_DS_0__OP__SHIFT 0x11
-#define SQ_DS_0__ENCODING__SHIFT 0x1a
-#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
-#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
-#define SQ_DS_0__GDS_MASK 0x00010000L
-#define SQ_DS_0__OP_MASK 0x01FE0000L
-#define SQ_DS_0__ENCODING_MASK 0xFC000000L
-//SQ_DS_1
-#define SQ_DS_1__ADDR__SHIFT 0x0
-#define SQ_DS_1__DATA0__SHIFT 0x8
-#define SQ_DS_1__DATA1__SHIFT 0x10
-#define SQ_DS_1__VDST__SHIFT 0x18
-#define SQ_DS_1__ADDR_MASK 0x000000FFL
-#define SQ_DS_1__DATA0_MASK 0x0000FF00L
-#define SQ_DS_1__DATA1_MASK 0x00FF0000L
-#define SQ_DS_1__VDST_MASK 0xFF000000L
-//SQ_EXP_0
-#define SQ_EXP_0__EN__SHIFT 0x0
-#define SQ_EXP_0__TGT__SHIFT 0x4
-#define SQ_EXP_0__COMPR__SHIFT 0xa
-#define SQ_EXP_0__DONE__SHIFT 0xb
-#define SQ_EXP_0__VM__SHIFT 0xc
-#define SQ_EXP_0__ENCODING__SHIFT 0x1a
-#define SQ_EXP_0__EN_MASK 0x0000000FL
-#define SQ_EXP_0__TGT_MASK 0x000003F0L
-#define SQ_EXP_0__COMPR_MASK 0x00000400L
-#define SQ_EXP_0__DONE_MASK 0x00000800L
-#define SQ_EXP_0__VM_MASK 0x00001000L
-#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
-//SQ_EXP_1
-#define SQ_EXP_1__VSRC0__SHIFT 0x0
-#define SQ_EXP_1__VSRC1__SHIFT 0x8
-#define SQ_EXP_1__VSRC2__SHIFT 0x10
-#define SQ_EXP_1__VSRC3__SHIFT 0x18
-#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
-#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
-#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
-#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
-//SQ_FLAT_0
-#define SQ_FLAT_0__OFFSET__SHIFT 0x0
-#define SQ_FLAT_0__LDS__SHIFT 0xd
-#define SQ_FLAT_0__SEG__SHIFT 0xe
-#define SQ_FLAT_0__GLC__SHIFT 0x10
-#define SQ_FLAT_0__SLC__SHIFT 0x11
-#define SQ_FLAT_0__OP__SHIFT 0x12
-#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
-#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
-#define SQ_FLAT_0__LDS_MASK 0x00002000L
-#define SQ_FLAT_0__SEG_MASK 0x0000C000L
-#define SQ_FLAT_0__GLC_MASK 0x00010000L
-#define SQ_FLAT_0__SLC_MASK 0x00020000L
-#define SQ_FLAT_0__OP_MASK 0x01FC0000L
-#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
-//SQ_FLAT_1
-#define SQ_FLAT_1__ADDR__SHIFT 0x0
-#define SQ_FLAT_1__DATA__SHIFT 0x8
-#define SQ_FLAT_1__SADDR__SHIFT 0x10
-#define SQ_FLAT_1__NV__SHIFT 0x17
-#define SQ_FLAT_1__VDST__SHIFT 0x18
-#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
-#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
-#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
-#define SQ_FLAT_1__NV_MASK 0x00800000L
-#define SQ_FLAT_1__VDST_MASK 0xFF000000L
-//SQ_GLBL_0
-#define SQ_GLBL_0__OFFSET__SHIFT 0x0
-#define SQ_GLBL_0__LDS__SHIFT 0xd
-#define SQ_GLBL_0__SEG__SHIFT 0xe
-#define SQ_GLBL_0__GLC__SHIFT 0x10
-#define SQ_GLBL_0__SLC__SHIFT 0x11
-#define SQ_GLBL_0__OP__SHIFT 0x12
-#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
-#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
-#define SQ_GLBL_0__LDS_MASK 0x00002000L
-#define SQ_GLBL_0__SEG_MASK 0x0000C000L
-#define SQ_GLBL_0__GLC_MASK 0x00010000L
-#define SQ_GLBL_0__SLC_MASK 0x00020000L
-#define SQ_GLBL_0__OP_MASK 0x01FC0000L
-#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
-//SQ_GLBL_1
-#define SQ_GLBL_1__ADDR__SHIFT 0x0
-#define SQ_GLBL_1__DATA__SHIFT 0x8
-#define SQ_GLBL_1__SADDR__SHIFT 0x10
-#define SQ_GLBL_1__NV__SHIFT 0x17
-#define SQ_GLBL_1__VDST__SHIFT 0x18
-#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
-#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
-#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
-#define SQ_GLBL_1__NV_MASK 0x00800000L
-#define SQ_GLBL_1__VDST_MASK 0xFF000000L
-//SQ_INST
-#define SQ_INST__ENCODING__SHIFT 0x0
-#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
-//SQ_MIMG_0
-#define SQ_MIMG_0__OPM__SHIFT 0x0
-#define SQ_MIMG_0__DMASK__SHIFT 0x8
-#define SQ_MIMG_0__UNORM__SHIFT 0xc
-#define SQ_MIMG_0__GLC__SHIFT 0xd
-#define SQ_MIMG_0__DA__SHIFT 0xe
-#define SQ_MIMG_0__A16__SHIFT 0xf
-#define SQ_MIMG_0__TFE__SHIFT 0x10
-#define SQ_MIMG_0__LWE__SHIFT 0x11
-#define SQ_MIMG_0__OP__SHIFT 0x12
-#define SQ_MIMG_0__SLC__SHIFT 0x19
-#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
-#define SQ_MIMG_0__OPM_MASK 0x00000001L
-#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
-#define SQ_MIMG_0__UNORM_MASK 0x00001000L
-#define SQ_MIMG_0__GLC_MASK 0x00002000L
-#define SQ_MIMG_0__DA_MASK 0x00004000L
-#define SQ_MIMG_0__A16_MASK 0x00008000L
-#define SQ_MIMG_0__TFE_MASK 0x00010000L
-#define SQ_MIMG_0__LWE_MASK 0x00020000L
-#define SQ_MIMG_0__OP_MASK 0x01FC0000L
-#define SQ_MIMG_0__SLC_MASK 0x02000000L
-#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
-//SQ_MIMG_1
-#define SQ_MIMG_1__VADDR__SHIFT 0x0
-#define SQ_MIMG_1__VDATA__SHIFT 0x8
-#define SQ_MIMG_1__SRSRC__SHIFT 0x10
-#define SQ_MIMG_1__SSAMP__SHIFT 0x15
-#define SQ_MIMG_1__D16__SHIFT 0x1f
-#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
-#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
-#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
-#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
-#define SQ_MIMG_1__D16_MASK 0x80000000L
-//SQ_MTBUF_0
-#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MTBUF_0__GLC__SHIFT 0xe
-#define SQ_MTBUF_0__OP__SHIFT 0xf
-#define SQ_MTBUF_0__DFMT__SHIFT 0x13
-#define SQ_MTBUF_0__NFMT__SHIFT 0x17
-#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
-#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
-#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
-#define SQ_MTBUF_0__GLC_MASK 0x00004000L
-#define SQ_MTBUF_0__OP_MASK 0x00078000L
-#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
-#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
-#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
-//SQ_MTBUF_1
-#define SQ_MTBUF_1__VADDR__SHIFT 0x0
-#define SQ_MTBUF_1__VDATA__SHIFT 0x8
-#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MTBUF_1__SLC__SHIFT 0x16
-#define SQ_MTBUF_1__TFE__SHIFT 0x17
-#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
-#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
-#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
-#define SQ_MTBUF_1__SLC_MASK 0x00400000L
-#define SQ_MTBUF_1__TFE_MASK 0x00800000L
-#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
-//SQ_MUBUF_0
-#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MUBUF_0__GLC__SHIFT 0xe
-#define SQ_MUBUF_0__LDS__SHIFT 0x10
-#define SQ_MUBUF_0__SLC__SHIFT 0x11
-#define SQ_MUBUF_0__OP__SHIFT 0x12
-#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
-#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
-#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
-#define SQ_MUBUF_0__GLC_MASK 0x00004000L
-#define SQ_MUBUF_0__LDS_MASK 0x00010000L
-#define SQ_MUBUF_0__SLC_MASK 0x00020000L
-#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
-#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
-//SQ_MUBUF_1
-#define SQ_MUBUF_1__VADDR__SHIFT 0x0
-#define SQ_MUBUF_1__VDATA__SHIFT 0x8
-#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MUBUF_1__TFE__SHIFT 0x17
-#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
-#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
-#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
-#define SQ_MUBUF_1__TFE_MASK 0x00800000L
-#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
-//SQ_SCRATCH_0
-#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
-#define SQ_SCRATCH_0__LDS__SHIFT 0xd
-#define SQ_SCRATCH_0__SEG__SHIFT 0xe
-#define SQ_SCRATCH_0__GLC__SHIFT 0x10
-#define SQ_SCRATCH_0__SLC__SHIFT 0x11
-#define SQ_SCRATCH_0__OP__SHIFT 0x12
-#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
-#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
-#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
-#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
-#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
-#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
-#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
-#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
-//SQ_SCRATCH_1
-#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
-#define SQ_SCRATCH_1__DATA__SHIFT 0x8
-#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
-#define SQ_SCRATCH_1__NV__SHIFT 0x17
-#define SQ_SCRATCH_1__VDST__SHIFT 0x18
-#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
-#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
-#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
-#define SQ_SCRATCH_1__NV_MASK 0x00800000L
-#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
-//SQ_SMEM_0
-#define SQ_SMEM_0__SBASE__SHIFT 0x0
-#define SQ_SMEM_0__SDATA__SHIFT 0x6
-#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
-#define SQ_SMEM_0__NV__SHIFT 0xf
-#define SQ_SMEM_0__GLC__SHIFT 0x10
-#define SQ_SMEM_0__IMM__SHIFT 0x11
-#define SQ_SMEM_0__OP__SHIFT 0x12
-#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
-#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
-#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
-#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
-#define SQ_SMEM_0__NV_MASK 0x00008000L
-#define SQ_SMEM_0__GLC_MASK 0x00010000L
-#define SQ_SMEM_0__IMM_MASK 0x00020000L
-#define SQ_SMEM_0__OP_MASK 0x03FC0000L
-#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
-//SQ_SMEM_1
-#define SQ_SMEM_1__OFFSET__SHIFT 0x0
-#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
-#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
-#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
-//SQ_SOP1
-#define SQ_SOP1__SSRC0__SHIFT 0x0
-#define SQ_SOP1__OP__SHIFT 0x8
-#define SQ_SOP1__SDST__SHIFT 0x10
-#define SQ_SOP1__ENCODING__SHIFT 0x17
-#define SQ_SOP1__SSRC0_MASK 0x000000FFL
-#define SQ_SOP1__OP_MASK 0x0000FF00L
-#define SQ_SOP1__SDST_MASK 0x007F0000L
-#define SQ_SOP1__ENCODING_MASK 0xFF800000L
-//SQ_SOP2
-#define SQ_SOP2__SSRC0__SHIFT 0x0
-#define SQ_SOP2__SSRC1__SHIFT 0x8
-#define SQ_SOP2__SDST__SHIFT 0x10
-#define SQ_SOP2__OP__SHIFT 0x17
-#define SQ_SOP2__ENCODING__SHIFT 0x1e
-#define SQ_SOP2__SSRC0_MASK 0x000000FFL
-#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
-#define SQ_SOP2__SDST_MASK 0x007F0000L
-#define SQ_SOP2__OP_MASK 0x3F800000L
-#define SQ_SOP2__ENCODING_MASK 0xC0000000L
-//SQ_SOPC
-#define SQ_SOPC__SSRC0__SHIFT 0x0
-#define SQ_SOPC__SSRC1__SHIFT 0x8
-#define SQ_SOPC__OP__SHIFT 0x10
-#define SQ_SOPC__ENCODING__SHIFT 0x17
-#define SQ_SOPC__SSRC0_MASK 0x000000FFL
-#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
-#define SQ_SOPC__OP_MASK 0x007F0000L
-#define SQ_SOPC__ENCODING_MASK 0xFF800000L
-//SQ_SOPK
-#define SQ_SOPK__SIMM16__SHIFT 0x0
-#define SQ_SOPK__SDST__SHIFT 0x10
-#define SQ_SOPK__OP__SHIFT 0x17
-#define SQ_SOPK__ENCODING__SHIFT 0x1c
-#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
-#define SQ_SOPK__SDST_MASK 0x007F0000L
-#define SQ_SOPK__OP_MASK 0x0F800000L
-#define SQ_SOPK__ENCODING_MASK 0xF0000000L
-//SQ_SOPP
-#define SQ_SOPP__SIMM16__SHIFT 0x0
-#define SQ_SOPP__OP__SHIFT 0x10
-#define SQ_SOPP__ENCODING__SHIFT 0x17
-#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
-#define SQ_SOPP__OP_MASK 0x007F0000L
-#define SQ_SOPP__ENCODING_MASK 0xFF800000L
-//SQ_VINTRP
-#define SQ_VINTRP__VSRC__SHIFT 0x0
-#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
-#define SQ_VINTRP__ATTR__SHIFT 0xa
-#define SQ_VINTRP__OP__SHIFT 0x10
-#define SQ_VINTRP__VDST__SHIFT 0x12
-#define SQ_VINTRP__ENCODING__SHIFT 0x1a
-#define SQ_VINTRP__VSRC_MASK 0x000000FFL
-#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
-#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
-#define SQ_VINTRP__OP_MASK 0x00030000L
-#define SQ_VINTRP__VDST_MASK 0x03FC0000L
-#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
-//SQ_VOP1
-#define SQ_VOP1__SRC0__SHIFT 0x0
-#define SQ_VOP1__OP__SHIFT 0x9
-#define SQ_VOP1__VDST__SHIFT 0x11
-#define SQ_VOP1__ENCODING__SHIFT 0x19
-#define SQ_VOP1__SRC0_MASK 0x000001FFL
-#define SQ_VOP1__OP_MASK 0x0001FE00L
-#define SQ_VOP1__VDST_MASK 0x01FE0000L
-#define SQ_VOP1__ENCODING_MASK 0xFE000000L
-//SQ_VOP2
-#define SQ_VOP2__SRC0__SHIFT 0x0
-#define SQ_VOP2__VSRC1__SHIFT 0x9
-#define SQ_VOP2__VDST__SHIFT 0x11
-#define SQ_VOP2__OP__SHIFT 0x19
-#define SQ_VOP2__ENCODING__SHIFT 0x1f
-#define SQ_VOP2__SRC0_MASK 0x000001FFL
-#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
-#define SQ_VOP2__VDST_MASK 0x01FE0000L
-#define SQ_VOP2__OP_MASK 0x7E000000L
-#define SQ_VOP2__ENCODING_MASK 0x80000000L
-//SQ_VOP3P_0
-#define SQ_VOP3P_0__VDST__SHIFT 0x0
-#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
-#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
-#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
-#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3P_0__OP__SHIFT 0x10
-#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
-#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
-#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
-#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
-#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
-#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
-#define SQ_VOP3P_0__OP_MASK 0x007F0000L
-#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
-//SQ_VOP3P_1
-#define SQ_VOP3P_1__SRC0__SHIFT 0x0
-#define SQ_VOP3P_1__SRC1__SHIFT 0x9
-#define SQ_VOP3P_1__SRC2__SHIFT 0x12
-#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
-#define SQ_VOP3P_1__NEG__SHIFT 0x1d
-#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
-#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
-#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
-#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
-#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
-//SQ_VOP3_0
-#define SQ_VOP3_0__VDST__SHIFT 0x0
-#define SQ_VOP3_0__ABS__SHIFT 0x8
-#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
-#define SQ_VOP3_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0__OP__SHIFT 0x10
-#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0__VDST_MASK 0x000000FFL
-#define SQ_VOP3_0__ABS_MASK 0x00000700L
-#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
-#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
-#define SQ_VOP3_0__OP_MASK 0x03FF0000L
-#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
-//SQ_VOP3_0_SDST_ENC
-#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
-#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
-#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
-#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
-#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
-#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
-#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
-//SQ_VOP3_1
-#define SQ_VOP3_1__SRC0__SHIFT 0x0
-#define SQ_VOP3_1__SRC1__SHIFT 0x9
-#define SQ_VOP3_1__SRC2__SHIFT 0x12
-#define SQ_VOP3_1__OMOD__SHIFT 0x1b
-#define SQ_VOP3_1__NEG__SHIFT 0x1d
-#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
-#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
-#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
-#define SQ_VOP3_1__OMOD_MASK 0x18000000L
-#define SQ_VOP3_1__NEG_MASK 0xE0000000L
-//SQ_VOPC
-#define SQ_VOPC__SRC0__SHIFT 0x0
-#define SQ_VOPC__VSRC1__SHIFT 0x9
-#define SQ_VOPC__OP__SHIFT 0x11
-#define SQ_VOPC__ENCODING__SHIFT 0x19
-#define SQ_VOPC__SRC0_MASK 0x000001FFL
-#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
-#define SQ_VOPC__OP_MASK 0x01FE0000L
-#define SQ_VOPC__ENCODING_MASK 0xFE000000L
-//SQ_VOP_DPP
-#define SQ_VOP_DPP__SRC0__SHIFT 0x0
-#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
-#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
-#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
-#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
-#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
-#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
-#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
-#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
-#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
-#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
-#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
-#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
-#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
-//SQ_VOP_SDWA
-#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
-#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
-#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
-#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
-#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA__S0__SHIFT 0x17
-#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP_SDWA__S1__SHIFT 0x1f
-#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
-#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
-#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
-#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
-#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
-#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
-#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
-#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_SDWA__S0_MASK 0x00800000L
-#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
-#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
-#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
-#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
-#define SQ_VOP_SDWA__S1_MASK 0x80000000L
-//SQ_VOP_SDWA_SDST_ENC
-#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
-#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
-#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
-#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
-//SQ_LB_CTR_CTRL
-#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
-#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
-#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
-#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
-#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
-#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
-//SQ_LB_DATA0
-#define SQ_LB_DATA0__DATA__SHIFT 0x0
-#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA1
-#define SQ_LB_DATA1__DATA__SHIFT 0x0
-#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA2
-#define SQ_LB_DATA2__DATA__SHIFT 0x0
-#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA3
-#define SQ_LB_DATA3__DATA__SHIFT 0x0
-#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_CTR_SEL
-#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
-#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
-#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
-#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
-#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
-#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
-#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
-#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
-//SQ_LB_CTR0_CU
-#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR1_CU
-#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR2_CU
-#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR3_CU
-#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQC_EDC_CNT
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
-//SQ_EDC_SEC_CNT
-#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
-#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
-#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
-#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
-#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
-#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
-//SQ_EDC_DED_CNT
-#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
-#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
-#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
-#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
-#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
-#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
-//SQ_EDC_INFO
-#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
-#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
-#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
-#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
-#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
-#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
-#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
-#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
-//SQ_EDC_CNT
-#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
-#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
-#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
-#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
-#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
-#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
-#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
-#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
-#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
-#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
-#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
-#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
-#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
-#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
-#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
-#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
-#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
-#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
-#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
-#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
-#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
-#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
-#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
-#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
-#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
-#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
-#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
-#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
-//SQ_EDC_FUE_CNTL
-#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
-#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
-#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
-#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_CMN
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
-//SQ_THREAD_TRACE_WORD_EVENT
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
-//SQ_THREAD_TRACE_WORD_INST
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
-//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_ISSUE
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
-//SQ_THREAD_TRACE_WORD_MISC
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
-//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
-//SQ_THREAD_TRACE_WORD_REG_1_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_REG_2_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
-//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_WAVE
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
-//SQ_THREAD_TRACE_WORD_WAVE_START
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
-//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
-//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
-//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
-//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
-//SQ_WREXEC_EXEC_HI
-#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
-#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
-#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
-#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
-#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
-#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
-#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
-#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
-//SQ_WREXEC_EXEC_LO
-#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
-#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD0
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD1
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
-#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
-//SQ_BUF_RSRC_WORD2
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
-#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
-#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
-#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
-#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
-#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
-#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
-#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
-#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
-//SQ_IMG_RSRC_WORD0
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_IMG_RSRC_WORD1
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
-#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
-#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
-#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
-#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
-//SQ_IMG_RSRC_WORD2
-#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
-#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
-#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
-#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
-//SQ_IMG_RSRC_WORD3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
-#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
-#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
-#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD4
-#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
-#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
-#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
-#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
-//SQ_IMG_RSRC_WORD5
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
-#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
-#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
-#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
-#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
-#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
-#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
-#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
-#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
-#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD6
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD7
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_IMG_SAMP_WORD0
-#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
-//SQ_IMG_SAMP_WORD1
-#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
-#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
-#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
-#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
-//SQ_IMG_SAMP_WORD2
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
-#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
-#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
-#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
-//SQ_IMG_SAMP_WORD3
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
-#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
-//SQ_FLAT_SCRATCH_WORD0
-#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
-//SQ_FLAT_SCRATCH_WORD1
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
-//SQ_M0_GPR_IDX_WORD
-#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
-#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
-#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
-#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
-//SQC_ICACHE_UTCL1_CNTL1
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQC_ICACHE_UTCL1_CNTL2
-#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//SQC_DCACHE_UTCL1_CNTL1
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQC_DCACHE_UTCL1_CNTL2
-#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//SQC_ICACHE_UTCL1_STATUS
-#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//SQC_DCACHE_UTCL1_STATUS
-#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-
-
-// addressBlock: gc_shsdec
-//SX_DEBUG_1
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
-#define SX_DEBUG_1__PC_CFG__SHIFT 0xd
-#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
-#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L
-#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
-//SPI_PS_MAX_WAVE_ID
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
-//SPI_START_PHASE
-#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
-#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
-#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
-#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
-#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
-#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
-//SPI_GFX_CNTL
-#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
-#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
-//SPI_DSM_CNTL
-#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
-#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
-//SPI_DSM_CNTL2
-#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
-#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
-#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
-#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
-//SPI_EDC_CNT
-#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
-#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
-//SPI_CONFIG_PS_CU_EN
-#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
-#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
-#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
-#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
-#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
-#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
-//SPI_WF_LIFETIME_CNTL
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
-#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
-#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
-//SPI_WF_LIFETIME_LIMIT_0
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_1
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_2
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_3
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_4
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_5
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_6
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_7
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_8
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_9
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_0
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_1
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_2
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_3
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_4
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_5
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_6
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_7
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_8
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_9
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_10
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_11
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_12
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_13
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_14
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_15
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_16
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_17
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_18
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_19
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_20
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
-//SPI_LB_CTR_CTRL
-#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
-#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
-#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
-#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
-#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
-#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
-#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
-#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
-//SPI_LB_CU_MASK
-#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
-//SPI_LB_DATA_REG
-#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
-#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
-//SPI_PG_ENABLE_STATIC_CU_MASK
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
-//SPI_GDS_CREDITS
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
-#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
-#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
-//SPI_SX_EXPORT_BUFFER_SIZES
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
-//SPI_SX_SCOREBOARD_BUFFER_SIZES
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
-//SPI_CSQ_WF_ACTIVE_STATUS
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
-//SPI_CSQ_WF_ACTIVE_COUNT_0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_1
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_2
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_3
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_4
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_5
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_6
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_7
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
-//SPI_LB_DATA_WAVES
-#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
-#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
-#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
-#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_HSGS
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_VSPS
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_CS
-#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
-//SPI_P0_TRAP_SCREEN_PSBA_LO
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P0_TRAP_SCREEN_PSBA_HI
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P0_TRAP_SCREEN_PSMA_LO
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P0_TRAP_SCREEN_PSMA_HI
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P0_TRAP_SCREEN_GPR_MIN
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
-//SPI_P1_TRAP_SCREEN_PSBA_LO
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P1_TRAP_SCREEN_PSBA_HI
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P1_TRAP_SCREEN_PSMA_LO
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P1_TRAP_SCREEN_PSMA_HI
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P1_TRAP_SCREEN_GPR_MIN
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
-
-
-// addressBlock: gc_tpdec
-//TD_CNTL
-#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
-#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
-#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
-#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
-#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
-#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
-#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
-#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
-#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
-#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
-#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
-#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
-#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
-#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
-#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
-#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
-#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
-#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
-#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
-#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
-//TD_STATUS
-#define TD_STATUS__BUSY__SHIFT 0x1f
-#define TD_STATUS__BUSY_MASK 0x80000000L
-//TD_DSM_CNTL
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-//TD_DSM_CNTL2
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
-//TD_SCRATCH
-#define TD_SCRATCH__SCRATCH__SHIFT 0x0
-#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
-//TA_CNTL
-#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
-#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
-#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
-#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
-#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
-#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
-#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
-#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
-#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
-#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
-//TA_CNTL_AUX
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
-#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
-#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
-#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
-#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
-#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
-#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
-#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
-#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
-#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
-#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
-#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
-#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
-#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
-#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
-#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
-#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
-#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
-#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
-#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
-#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
-#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
-#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
-#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
-#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
-#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
-#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
-#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
-#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
-#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
-#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
-#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
-#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
-#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
-#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
-#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
-#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
-#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
-#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
-#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
-#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
-#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
-#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
-#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
-#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
-#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
-#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
-//TA_RESERVED_010C
-#define TA_RESERVED_010C__Unused__SHIFT 0x0
-#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
-//TA_GRAD_ADJ
-#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0
-#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8
-#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10
-#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18
-#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL
-#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L
-#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L
-#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L
-//TA_STATUS
-#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
-#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
-#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
-#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
-#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
-#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
-#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
-#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
-#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
-#define TA_STATUS__IN_BUSY__SHIFT 0x18
-#define TA_STATUS__FG_BUSY__SHIFT 0x19
-#define TA_STATUS__LA_BUSY__SHIFT 0x1a
-#define TA_STATUS__FL_BUSY__SHIFT 0x1b
-#define TA_STATUS__TA_BUSY__SHIFT 0x1c
-#define TA_STATUS__FA_BUSY__SHIFT 0x1d
-#define TA_STATUS__AL_BUSY__SHIFT 0x1e
-#define TA_STATUS__BUSY__SHIFT 0x1f
-#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
-#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
-#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
-#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
-#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
-#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
-#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
-#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
-#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
-#define TA_STATUS__IN_BUSY_MASK 0x01000000L
-#define TA_STATUS__FG_BUSY_MASK 0x02000000L
-#define TA_STATUS__LA_BUSY_MASK 0x04000000L
-#define TA_STATUS__FL_BUSY_MASK 0x08000000L
-#define TA_STATUS__TA_BUSY_MASK 0x10000000L
-#define TA_STATUS__FA_BUSY_MASK 0x20000000L
-#define TA_STATUS__AL_BUSY_MASK 0x40000000L
-#define TA_STATUS__BUSY_MASK 0x80000000L
-//TA_SCRATCH
-#define TA_SCRATCH__SCRATCH__SHIFT 0x0
-#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gdsdec
-//GDS_CONFIG
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
-//GDS_CNTL_STATUS
-#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
-#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
-#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
-#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
-#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
-#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
-#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
-#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
-#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
-#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
-#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
-#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
-#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
-#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
-#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
-#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
-#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
-#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
-#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
-#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
-//GDS_ENHANCE2
-#define GDS_ENHANCE2__MISC__SHIFT 0x0
-#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
-#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
-#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
-//GDS_PROTECTION_FAULT
-#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
-#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
-#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
-#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
-#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
-#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
-#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
-#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
-#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
-#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
-#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
-#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
-//GDS_VM_PROTECTION_FAULT
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
-#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
-#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
-#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
-#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
-#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
-#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
-#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
-#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
-#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
-#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
-#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
-//GDS_EDC_CNT
-#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
-#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
-#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
-#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
-#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
-#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
-//GDS_EDC_GRBM_CNT
-#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
-#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
-#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
-#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
-#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
-#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
-//GDS_EDC_OA_DED
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
-#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
-#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
-#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
-#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
-//GDS_DSM_CNTL
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
-#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
-#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
-#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
-#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
-#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
-#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
-#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
-#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
-#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
-#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
-//GDS_EDC_OA_PHY_CNT
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
-#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
-#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
-#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
-#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
-//GDS_EDC_OA_PIPE_CNT
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
-#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
-#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
-//GDS_DSM_CNTL2
-#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
-#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
-#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
-#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
-//GDS_WD_GDS_CSB
-#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
-#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
-#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
-#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
-
-
-// addressBlock: gc_rbdec
-//DB_DEBUG
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
-#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
-#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
-#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
-#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
-#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
-#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
-#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
-#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
-//DB_DEBUG2
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
-#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
-#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
-#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
-#define DB_DEBUG2__RESERVED__SHIFT 0x10
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
-#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
-#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
-#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
-#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
-#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
-#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
-#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
-#define DB_DEBUG2__RESERVED_MASK 0x00010000L
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
-#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
-#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
-#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
-#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
-//DB_DEBUG3
-#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
-#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
-#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
-#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
-#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
-#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
-#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
-#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
-#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
-#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
-#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
-#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
-#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
-#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
-#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
-#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
-#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
-#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
-#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
-#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
-#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
-#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
-#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
-#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
-#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
-#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
-#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
-#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
-#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
-#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
-#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
-#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
-#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
-#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
-#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
-#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
-#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
-#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
-#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
-#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
-#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
-#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
-#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
-#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
-#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
-#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
-#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
-#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
-#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
-#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
-#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
-#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
-#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
-#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
-#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
-#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
-#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
-#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
-#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
-#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
-#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
-#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
-#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
-//DB_DEBUG4
-#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
-#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
-#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
-#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
-#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
-#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
-#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
-#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
-#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
-#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
-#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
-#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
-#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
-#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
-#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
-#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
-#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
-#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
-#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
-#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
-#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
-#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
-#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
-#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
-#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
-#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
-#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
-#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
-#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
-#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
-#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
-#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
-#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
-#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
-#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
-#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
-#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
-#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
-#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
-#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L
-//DB_CREDIT_LIMIT
-#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
-#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
-#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
-#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
-#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
-#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
-#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
-#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
-//DB_WATERMARKS
-#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
-#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
-#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
-#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
-#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
-#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
-#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
-#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
-#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
-#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
-#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
-#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
-#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
-#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
-//DB_SUBTILE_CONTROL
-#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
-#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
-#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
-#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
-#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
-#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
-#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
-#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
-#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
-#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
-#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
-#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
-#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
-#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
-#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
-#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
-#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
-#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
-#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
-#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
-//DB_FREE_CACHELINES
-#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
-#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
-#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
-#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
-#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
-#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
-#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
-#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
-#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
-#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
-//DB_FIFO_DEPTH1
-#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
-#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
-#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
-#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
-#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
-#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
-#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
-#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
-#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
-#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
-//DB_FIFO_DEPTH2
-#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
-#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
-#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
-#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
-#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
-#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
-#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
-#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
-//DB_EXCEPTION_CONTROL
-#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
-#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
-#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
-#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
-#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
-#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
-//DB_RING_CONTROL
-#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
-#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
-//DB_MEM_ARB_WATERMARKS
-#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
-#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
-#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
-#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
-#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
-#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
-#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
-#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
-//DB_RMI_CACHE_POLICY
-#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
-#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
-#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
-#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
-#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
-#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
-#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
-#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
-#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
-#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
-#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
-#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
-#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
-#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
-#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
-#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
-#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
-#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
-#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
-#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
-#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
-#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
-#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
-#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
-#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
-#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
-#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
-#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
-#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
-#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
-//DB_DFSM_CONFIG
-#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
-#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
-#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
-#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
-#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
-#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
-#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
-#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
-#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
-#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
-//DB_DFSM_WATERMARK
-#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
-#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
-#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
-#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
-//DB_DFSM_TILES_IN_FLIGHT
-#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
-#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
-#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
-#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
-//DB_DFSM_PRIMS_IN_FLIGHT
-#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
-#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
-#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
-#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
-//DB_DFSM_WATCHDOG
-#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
-#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
-//DB_DFSM_FLUSH_ENABLE
-#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
-#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
-#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
-#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
-#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
-#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
-//DB_DFSM_FLUSH_AUX_EVENT
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
-//CC_RB_REDUNDANCY
-#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
-#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
-#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
-#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
-//CC_RB_BACKEND_DISABLE
-#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
-#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
-//GB_ADDR_CONFIG
-#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
-#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
-#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
-#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
-#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
-#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
-#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
-#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
-#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
-#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
-#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
-#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
-//GB_BACKEND_MAP
-#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
-#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
-//GB_GPU_ID
-#define GB_GPU_ID__GPU_ID__SHIFT 0x0
-#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
-//CC_RB_DAISY_CHAIN
-#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
-#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
-#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
-#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
-#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
-#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
-#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
-#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
-#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
-#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
-#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
-#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
-#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
-#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
-#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
-#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
-//GB_ADDR_CONFIG_READ
-#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
-#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
-#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
-#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
-#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
-#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
-#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
-#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
-#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
-#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
-#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
-#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
-#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
-#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
-#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
-#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
-#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
-#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
-#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
-#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
-//GB_TILE_MODE0
-#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE1
-#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE2
-#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE3
-#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE4
-#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE5
-#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE6
-#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE7
-#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE8
-#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE9
-#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE10
-#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE11
-#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE12
-#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE13
-#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE14
-#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE15
-#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE16
-#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE17
-#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE18
-#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE19
-#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE20
-#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE21
-#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE22
-#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE23
-#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE24
-#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE25
-#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE26
-#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE27
-#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE28
-#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE29
-#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE30
-#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE31
-#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_MACROTILE_MODE0
-#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE1
-#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE2
-#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE3
-#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE4
-#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE5
-#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE6
-#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE7
-#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE8
-#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE9
-#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE10
-#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE11
-#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE12
-#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE13
-#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE14
-#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE15
-#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
-//CB_HW_CONTROL
-#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
-#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
-#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
-#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
-#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
-#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
-#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
-#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
-#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
-#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
-#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
-#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
-#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
-#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
-#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
-#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
-#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
-#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
-#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
-#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
-#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
-#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
-#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
-#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
-#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
-#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
-//CB_HW_CONTROL_1
-#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
-#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
-#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
-#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
-#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
-#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
-#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
-#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
-#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
-#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
-//CB_HW_CONTROL_2
-#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
-#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
-#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
-#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
-#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
-#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
-#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
-#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
-#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
-#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
-//CB_HW_CONTROL_3
-#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
-#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
-#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
-#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
-#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
-#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
-#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
-#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
-#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
-#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
-#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
-#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
-#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
-#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
-#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
-#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
-#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
-#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
-#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
-#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
-#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
-#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
-#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
-#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
-#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
-#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
-#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
-//CB_HW_MEM_ARBITER_RD
-#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
-#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
-#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
-#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
-#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
-#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
-#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
-#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
-#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
-#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
-#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
-#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
-//CB_HW_MEM_ARBITER_WR
-#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
-#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
-#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
-#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
-#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
-#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
-#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
-#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
-#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
-#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
-#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
-#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
-//CB_DCC_CONFIG
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
-#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
-#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
-#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
-#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
-#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
-#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
-#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
-#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
-//GC_USER_RB_REDUNDANCY
-#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
-#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
-#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
-#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
-//GC_USER_RB_BACKEND_DISABLE
-#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
-#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
-
-
-// addressBlock: gc_ea_gceadec2
-//GCEA_EDC_CNT
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
-#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
-#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
-#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
-#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
-#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
-#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
-#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
-#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
-#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
-#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
-#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
-#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
-#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
-#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
-#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
-#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
-//GCEA_EDC_CNT2
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
-#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
-#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
-//GCEA_DSM_CNTL
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-//GCEA_DSM_CNTLA
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//GCEA_DSM_CNTLB
-//GCEA_DSM_CNTL2
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//GCEA_DSM_CNTL2A
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-//GCEA_DSM_CNTL2B
-//GCEA_TCC_XBR_CREDITS
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6
-#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8
-#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16
-#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18
-#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L
-#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L
-#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L
-#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L
-#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L
-//GCEA_TCC_XBR_MAXBURST
-#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0
-#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4
-#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8
-#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc
-#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL
-#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L
-#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L
-#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L
-//GCEA_PROBE_CNTL
-#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0
-#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5
-#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL
-#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L
-//GCEA_PROBE_MAP
-#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0
-#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1
-#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2
-#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3
-#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4
-#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5
-#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6
-#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7
-#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8
-#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9
-#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa
-#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb
-#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc
-#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd
-#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe
-#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf
-#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10
-#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L
-#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L
-#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L
-#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L
-#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L
-#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L
-#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L
-#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L
-#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L
-#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L
-#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L
-#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L
-#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L
-#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L
-#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L
-#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L
-#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L
-//GCEA_ERR_STATUS
-#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
-#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
-#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8
-#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9
-#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa
-#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
-#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
-#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L
-#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L
-#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L
-//GCEA_MISC2
-#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
-#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
-#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
-#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
-//GCEA_SDP_BACKDOOR_CMDCREDITS0
-#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL
-//GCEA_SDP_BACKDOOR_CMDCREDITS1
-#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL
-//GCEA_SDP_BACKDOOR_DATACREDITS0
-#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL
-//GCEA_SDP_BACKDOOR_DATACREDITS1
-#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL
-//GCEA_SDP_BACKDOOR_MISCCREDITS
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L
-//GCEA_SDP_ENABLE
-#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0
-#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L
-
-
-// addressBlock: gc_rmi_rmidec
-//RMI_GENERAL_CNTL
-#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
-#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
-#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
-#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
-#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
-#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
-#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
-#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
-#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
-#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
-#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
-//RMI_GENERAL_CNTL1
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
-#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
-#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
-#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
-#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
-//RMI_GENERAL_STATUS
-#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
-#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
-#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
-#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
-#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
-#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
-#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
-#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
-#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
-#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
-#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
-#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
-#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
-#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
-#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
-#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
-#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
-#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
-#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
-#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
-#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
-#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
-#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
-#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
-#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
-#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
-#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
-#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
-#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
-#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
-//RMI_SUBBLOCK_STATUS0
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
-#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
-#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
-//RMI_SUBBLOCK_STATUS1
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
-#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
-#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
-//RMI_SUBBLOCK_STATUS2
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
-//RMI_SUBBLOCK_STATUS3
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
-//RMI_XBAR_CONFIG
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
-#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
-#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
-//RMI_PROBE_POP_LOGIC_CNTL
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
-#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
-#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
-//RMI_UTC_XNACK_N_MISC_CNTL
-#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
-#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
-#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
-#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
-#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
-#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
-#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
-#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
-//RMI_DEMUX_CNTL
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
-//RMI_UTCL1_CNTL1
-#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
-#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
-#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//RMI_UTCL1_CNTL2
-#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
-#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
-#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
-#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
-#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
-#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
-#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//RMI_UTC_UNIT_CONFIG
-//RMI_TCIW_FORMATTER0_CNTL
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
-#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
-#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
-#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
-#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
-//RMI_TCIW_FORMATTER1_CNTL
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
-#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
-#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
-#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
-#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
-//RMI_SCOREBOARD_CNTL
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
-//RMI_SCOREBOARD_STATUS0
-#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
-#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
-#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
-#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
-//RMI_SCOREBOARD_STATUS1
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
-#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
-#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
-//RMI_SCOREBOARD_STATUS2
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
-//RMI_XBAR_ARBITER_CONFIG
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
-//RMI_XBAR_ARBITER_CONFIG_1
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
-//RMI_CLOCK_CNTRL
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
-//RMI_UTCL1_STATUS
-#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//RMI_SPARE
-#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
-#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
-#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
-#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
-#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
-#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
-#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
-#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
-#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
-#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
-#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
-#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
-#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
-#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
-#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
-#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
-#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
-#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
-#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
-#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
-//RMI_SPARE_1
-#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
-#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
-#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
-#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
-#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
-#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
-#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
-#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
-#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
-#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
-#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
-#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
-#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
-#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
-#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
-#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
-#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
-#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
-#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
-#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
-//RMI_SPARE_2
-#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
-#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
-#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
-#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
-#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
-#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
-#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
-#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
-#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
-#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
-#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
-#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
-#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
-#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
-#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
-#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
-#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
-#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
-#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
-#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
-#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
-#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
-#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
-#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
-
-
-// addressBlock: gc_dbgu_gfx_dbgudec
-//port_a_addr
-#define port_a_addr__Index__SHIFT 0x0
-#define port_a_addr__Reserved__SHIFT 0x8
-#define port_a_addr__ReadEnable__SHIFT 0x1f
-#define port_a_addr__Index_MASK 0x000000FFL
-#define port_a_addr__Reserved_MASK 0x7FFFFF00L
-#define port_a_addr__ReadEnable_MASK 0x80000000L
-//port_a_data_lo
-#define port_a_data_lo__Data__SHIFT 0x0
-#define port_a_data_lo__Data_MASK 0xFFFFFFFFL
-//port_a_data_hi
-#define port_a_data_hi__Data__SHIFT 0x0
-#define port_a_data_hi__Data_MASK 0xFFFFFFFFL
-//port_b_addr
-#define port_b_addr__Index__SHIFT 0x0
-#define port_b_addr__Reserved__SHIFT 0x8
-#define port_b_addr__ReadEnable__SHIFT 0x1f
-#define port_b_addr__Index_MASK 0x000000FFL
-#define port_b_addr__Reserved_MASK 0x7FFFFF00L
-#define port_b_addr__ReadEnable_MASK 0x80000000L
-//port_b_data_lo
-#define port_b_data_lo__Data__SHIFT 0x0
-#define port_b_data_lo__Data_MASK 0xFFFFFFFFL
-//port_b_data_hi
-#define port_b_data_hi__Data__SHIFT 0x0
-#define port_b_data_hi__Data_MASK 0xFFFFFFFFL
-//port_c_addr
-#define port_c_addr__Index__SHIFT 0x0
-#define port_c_addr__Reserved__SHIFT 0x8
-#define port_c_addr__ReadEnable__SHIFT 0x1f
-#define port_c_addr__Index_MASK 0x000000FFL
-#define port_c_addr__Reserved_MASK 0x7FFFFF00L
-#define port_c_addr__ReadEnable_MASK 0x80000000L
-//port_c_data_lo
-#define port_c_data_lo__Data__SHIFT 0x0
-#define port_c_data_lo__Data_MASK 0xFFFFFFFFL
-//port_c_data_hi
-#define port_c_data_hi__Data__SHIFT 0x0
-#define port_c_data_hi__Data_MASK 0xFFFFFFFFL
-//port_d_addr
-#define port_d_addr__Index__SHIFT 0x0
-#define port_d_addr__Reserved__SHIFT 0x8
-#define port_d_addr__ReadEnable__SHIFT 0x1f
-#define port_d_addr__Index_MASK 0x000000FFL
-#define port_d_addr__Reserved_MASK 0x7FFFFF00L
-#define port_d_addr__ReadEnable_MASK 0x80000000L
-//port_d_data_lo
-#define port_d_data_lo__Data__SHIFT 0x0
-#define port_d_data_lo__Data_MASK 0xFFFFFFFFL
-//port_d_data_hi
-#define port_d_data_hi__Data__SHIFT 0x0
-#define port_d_data_hi__Data_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_utcl2_atcl2dec
-//ATC_L2_CNTL
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
-#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
-#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
-#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
-#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
-//ATC_L2_CNTL2
-#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
-#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
-#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
-#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
-#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
-#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
-#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
-#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
-//ATC_L2_CACHE_DATA0
-#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
-#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
-#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
-#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
-#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
-#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
-#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
-#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
-//ATC_L2_CACHE_DATA1
-#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
-#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
-//ATC_L2_CACHE_DATA2
-#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
-#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
-//ATC_L2_CNTL3
-#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
-#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
-#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
-#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
-//ATC_L2_STATUS
-#define ATC_L2_STATUS__BUSY__SHIFT 0x0
-#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
-#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
-#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
-//ATC_L2_STATUS2
-#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
-#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
-#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
-#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
-//ATC_L2_MISC_CG
-#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
-#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
-#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
-#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
-#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
-#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
-//ATC_L2_MEM_POWER_LS
-#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//ATC_L2_CGTT_CLK_CTRL
-#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: gc_utcl2_vml2pfdec
-//VM_L2_CNTL
-#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
-#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
-#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
-#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
-#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
-#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
-#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
-#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
-#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
-#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
-#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
-#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
-#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
-#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
-#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
-#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
-#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
-#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
-#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
-#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
-#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
-#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
-#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
-#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
-#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
-#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
-#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
-#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
-//VM_L2_CNTL2
-#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
-#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
-#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
-#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
-#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
-#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
-#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
-#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
-#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
-#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
-#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
-#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
-#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
-#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
-//VM_L2_CNTL3
-#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
-#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
-#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
-#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
-#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
-#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
-#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
-#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
-#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
-#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
-#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
-#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
-//VM_L2_STATUS
-#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
-#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
-#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
-#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
-#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
-#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
-#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
-#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
-#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
-#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
-#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
-#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
-#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
-#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
-//VM_DUMMY_PAGE_FAULT_CNTL
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
-//VM_DUMMY_PAGE_FAULT_ADDR_LO32
-#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_DUMMY_PAGE_FAULT_ADDR_HI32
-#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_PROTECTION_FAULT_CNTL
-#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
-#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
-#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
-#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
-#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
-#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
-#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
-#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
-#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
-#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
-#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
-#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
-#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
-#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
-#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
-#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
-#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
-#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
-#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
-//VM_L2_PROTECTION_FAULT_CNTL2
-#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
-#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
-#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
-#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
-//VM_L2_PROTECTION_FAULT_MM_CNTL3
-#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_MM_CNTL4
-#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_STATUS
-#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
-#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
-#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
-#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
-#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
-#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
-#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
-#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
-#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
-#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
-#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
-#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
-#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
-#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
-#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
-#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
-//VM_L2_PROTECTION_FAULT_ADDR_LO32
-#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_ADDR_HI32
-#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
-//VM_L2_CNTL4
-#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
-#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
-#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
-#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
-#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
-#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
-#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
-#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
-#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
-#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
-#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
-#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
-//VM_L2_MM_GROUP_RT_CLASSES
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
-//VM_L2_BANK_SELECT_RESERVED_CID
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
-#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
-#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
-//VM_L2_BANK_SELECT_RESERVED_CID2
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
-#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
-//VM_L2_CACHE_PARITY_CNTL
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
-//VM_L2_CGTT_CLK_CTRL
-#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: gc_utcl2_vml2vcdec
-//VM_CONTEXT0_CNTL
-#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT1_CNTL
-#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT2_CNTL
-#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT3_CNTL
-#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT4_CNTL
-#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT5_CNTL
-#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT6_CNTL
-#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT7_CNTL
-#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT8_CNTL
-#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT9_CNTL
-#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT10_CNTL
-#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT11_CNTL
-#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT12_CNTL
-#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT13_CNTL
-#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT14_CNTL
-#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT15_CNTL
-#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXTS_DISABLE
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
-//VM_INVALIDATE_ENG0_SEM
-#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG1_SEM
-#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG2_SEM
-#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG3_SEM
-#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG4_SEM
-#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG5_SEM
-#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG6_SEM
-#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG7_SEM
-#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG8_SEM
-#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG9_SEM
-#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG10_SEM
-#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG11_SEM
-#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG12_SEM
-#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG13_SEM
-#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG14_SEM
-#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG15_SEM
-#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG16_SEM
-#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG17_SEM
-#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG0_REQ
-#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG1_REQ
-#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG2_REQ
-#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG3_REQ
-#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG4_REQ
-#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG5_REQ
-#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG6_REQ
-#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG7_REQ
-#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG8_REQ
-#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG9_REQ
-#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG10_REQ
-#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG11_REQ
-#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG12_REQ
-#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG13_REQ
-#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG14_REQ
-#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG15_REQ
-#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG16_REQ
-#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG17_REQ
-#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG0_ACK
-#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG1_ACK
-#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG2_ACK
-#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG3_ACK
-#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG4_ACK
-#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG5_ACK
-#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG6_ACK
-#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG7_ACK
-#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG8_ACK
-#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG9_ACK
-#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG10_ACK
-#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG11_ACK
-#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG12_ACK
-#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG13_ACK
-#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG14_ACK
-#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG15_ACK
-#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG16_ACK
-#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG17_ACK
-#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-
-
-// addressBlock: gc_utcl2_vmsharedpfdec
-//MC_VM_NB_MMIOBASE
-#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
-#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
-//MC_VM_NB_MMIOLIMIT
-#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
-#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
-//MC_VM_NB_PCI_CTRL
-#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
-#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
-//MC_VM_NB_PCI_ARB
-#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
-#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
-//MC_VM_NB_TOP_OF_DRAM_SLOT1
-#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
-#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
-//MC_VM_NB_LOWER_TOP_OF_DRAM2
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
-//MC_VM_NB_UPPER_TOP_OF_DRAM2
-#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
-#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
-//MC_VM_FB_OFFSET
-#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
-#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
-//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
-//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
-//MC_VM_STEERING
-#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
-#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
-//MC_SHARED_VIRT_RESET_REQ
-#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//MC_MEM_POWER_LS
-#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//MC_VM_CACHEABLE_DRAM_ADDRESS_START
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_CACHEABLE_DRAM_ADDRESS_END
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_APT_CNTL
-#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
-#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
-#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
-#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
-//MC_VM_LOCAL_HBM_ADDRESS_START
-#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_LOCAL_HBM_ADDRESS_END
-#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
-#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
-
-
-// addressBlock: gc_utcl2_vmsharedvcdec
-//MC_VM_FB_LOCATION_BASE
-#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
-#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
-//MC_VM_FB_LOCATION_TOP
-#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
-#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
-//MC_VM_AGP_TOP
-#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
-#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
-//MC_VM_AGP_BOT
-#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
-#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
-//MC_VM_AGP_BASE
-#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
-#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
-//MC_VM_SYSTEM_APERTURE_LOW_ADDR
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
-//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
-//MC_VM_MX_L1_TLB_CNTL
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
-#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
-#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
-#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
-#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
-#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
-#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
-
-
-// addressBlock: gc_ea_gceadec
-//GCEA_DRAM_RD_CLI2GRP_MAP0
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_RD_CLI2GRP_MAP1
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_WR_CLI2GRP_MAP0
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_WR_CLI2GRP_MAP1
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_RD_GRP2VC_MAP
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//GCEA_DRAM_WR_GRP2VC_MAP
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//GCEA_DRAM_RD_LAZY
-#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-//GCEA_DRAM_WR_LAZY
-#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-//GCEA_DRAM_RD_CAM_CNTL
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//GCEA_DRAM_WR_CAM_CNTL
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//GCEA_DRAM_PAGE_BURST
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//GCEA_DRAM_RD_PRI_AGE
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_DRAM_WR_PRI_AGE
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_DRAM_RD_PRI_QUEUING
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_WR_PRI_QUEUING
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_RD_PRI_FIXED
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_WR_PRI_FIXED
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_RD_PRI_URGENCY
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_DRAM_WR_PRI_URGENCY
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_DRAM_RD_PRI_QUANT_PRI1
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_RD_PRI_QUANT_PRI2
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_RD_PRI_QUANT_PRI3
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_WR_PRI_QUANT_PRI1
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_WR_PRI_QUANT_PRI2
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_WR_PRI_QUANT_PRI3
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_ADDRNORM_BASE_ADDR0
-#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
-#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
-#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
-#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
-#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_LIMIT_ADDR0
-#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
-#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
-#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_BASE_ADDR1
-#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
-#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
-#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
-#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
-#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_LIMIT_ADDR1
-#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
-#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
-#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_OFFSET_ADDR1
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
-//GCEA_ADDRNORM_HOLE_CNTL
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
-//GCEA_ADDRDEC_BANK_CFG
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
-//GCEA_ADDRDEC_MISC_CFG
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_PC
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_PC2
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
-//GCEA_ADDRDECDRAM_ADDR_HASH_CS0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDECDRAM_ADDR_HASH_CS1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDECDRAM_HARVEST_ENABLE
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
-//GCEA_ADDRDEC0_BASE_ADDR_CS0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_CS1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_CS2
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_CS3
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS2
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS3
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_CS01
-#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_CS23
-#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_SECCS01
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_SECCS23
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_CFG_CS01
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC0_ADDR_CFG_CS23
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC0_ADDR_SEL_CS01
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC0_ADDR_SEL_CS23
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_LO_CS01
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_LO_CS23
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_HI_CS01
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_HI_CS23
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC0_RM_SEL_CS01
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC0_RM_SEL_CS23
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC0_RM_SEL_SECCS01
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC0_RM_SEL_SECCS23
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_BASE_ADDR_CS0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_CS1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_CS2
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_CS3
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS2
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS3
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_CS01
-#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_CS23
-#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_SECCS01
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_SECCS23
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_CFG_CS01
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC1_ADDR_CFG_CS23
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC1_ADDR_SEL_CS01
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC1_ADDR_SEL_CS23
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_LO_CS01
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_LO_CS23
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_HI_CS01
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_HI_CS23
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC1_RM_SEL_CS01
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_RM_SEL_CS23
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_RM_SEL_SECCS01
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_RM_SEL_SECCS23
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_IO_RD_CLI2GRP_MAP0
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_IO_RD_CLI2GRP_MAP1
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_IO_WR_CLI2GRP_MAP0
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_IO_WR_CLI2GRP_MAP1
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_IO_RD_COMBINE_FLUSH
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//GCEA_IO_WR_COMBINE_FLUSH
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//GCEA_IO_GROUP_BURST
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//GCEA_IO_RD_PRI_AGE
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_IO_WR_PRI_AGE
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_IO_RD_PRI_QUEUING
-#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_WR_PRI_QUEUING
-#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_RD_PRI_FIXED
-#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_WR_PRI_FIXED
-#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_RD_PRI_URGENCY
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_IO_WR_PRI_URGENCY
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_IO_RD_PRI_URGENCY_MASK
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//GCEA_IO_WR_PRI_URGENCY_MASK
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//GCEA_IO_RD_PRI_QUANT_PRI1
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_RD_PRI_QUANT_PRI2
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_RD_PRI_QUANT_PRI3
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_WR_PRI_QUANT_PRI1
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_WR_PRI_QUANT_PRI2
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_WR_PRI_QUANT_PRI3
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_SDP_ARB_DRAM
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
-#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
-#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
-//GCEA_SDP_ARB_FINAL
-#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
-#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
-#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
-#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
-#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
-#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
-#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
-#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
-#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
-#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
-#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
-#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
-//GCEA_SDP_DRAM_PRIORITY
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//GCEA_SDP_IO_PRIORITY
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//GCEA_SDP_CREDITS
-#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
-#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
-#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
-#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18
-#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
-#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
-#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
-#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L
-//GCEA_SDP_TAG_RESERVE0
-#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
-#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
-#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
-#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
-#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
-#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
-#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
-#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
-//GCEA_SDP_TAG_RESERVE1
-#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
-#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
-#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
-#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
-#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
-#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
-#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
-#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
-//GCEA_SDP_VCC_RESERVE0
-#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//GCEA_SDP_VCC_RESERVE1
-#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//GCEA_SDP_VCD_RESERVE0
-#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//GCEA_SDP_VCD_RESERVE1
-#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//GCEA_SDP_REQ_CNTL
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
-#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
-#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
-#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
-#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
-//GCEA_MISC
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
-#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
-#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
-#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
-#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
-#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
-#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
-#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
-#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
-#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
-#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
-//GCEA_LATENCY_SAMPLING
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
-//GCEA_PERFCOUNTER_LO
-#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//GCEA_PERFCOUNTER_HI
-#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//GCEA_PERFCOUNTER0_CFG
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//GCEA_PERFCOUNTER1_CFG
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//GCEA_PERFCOUNTER_RSLT_CNTL
-#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: gc_tcdec
-//TCP_INVALIDATE
-#define TCP_INVALIDATE__START__SHIFT 0x0
-#define TCP_INVALIDATE__START_MASK 0x00000001L
-//TCP_STATUS
-#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
-#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
-#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
-#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
-#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
-#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
-#define TCP_STATUS__READ_BUSY__SHIFT 0x6
-#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
-#define TCP_STATUS__VM_BUSY__SHIFT 0x8
-#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
-#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
-#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
-#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
-#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
-#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
-#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
-#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
-#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
-//TCP_CNTL
-#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
-#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
-#define TCP_CNTL__L1_SIZE__SHIFT 0x2
-#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
-#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
-#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
-#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
-#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
-#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
-#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e
-#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
-#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
-#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL
-#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L
-#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
-#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L
-#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L
-#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
-#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L
-#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L
-//TCP_CHAN_STEER_LO
-#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
-#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
-#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
-#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
-#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
-#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
-#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
-#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
-#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL
-#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L
-#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L
-#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L
-#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L
-#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L
-#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L
-#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L
-//TCP_CHAN_STEER_HI
-#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
-#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
-#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
-#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
-#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
-#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
-#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
-#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
-#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL
-#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L
-#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L
-#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L
-#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L
-#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L
-#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L
-#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L
-//TCP_ADDR_CONFIG
-#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
-#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
-#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
-#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
-#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
-#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
-#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
-#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
-//TCP_CREDIT
-#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
-#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
-#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
-#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL
-#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L
-#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L
-//TCP_BUFFER_ADDR_HASH_CNTL
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
-//TCP_EDC_CNT
-#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
-#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
-#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
-#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL
-#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L
-#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L
-//TC_CFG_L1_LOAD_POLICY0
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L1_LOAD_POLICY1
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
-//TC_CFG_L1_STORE_POLICY
-#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
-#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
-#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
-#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
-#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
-#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
-#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
-#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
-#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
-#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
-#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
-#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
-#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
-#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
-#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
-#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
-#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
-#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
-#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
-#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
-#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
-#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
-#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
-#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
-#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
-#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
-#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
-#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
-#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
-#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
-#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
-#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
-#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L
-#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L
-#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L
-#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L
-#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L
-#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L
-#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L
-#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L
-#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L
-#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L
-#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L
-#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L
-#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L
-//TC_CFG_L2_LOAD_POLICY0
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L2_LOAD_POLICY1
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
-//TC_CFG_L2_STORE_POLICY0
-#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L2_STORE_POLICY1
-#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL
-#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L
-//TC_CFG_L2_ATOMIC_POLICY
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L1_VOLATILE
-#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
-#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL
-//TC_CFG_L2_VOLATILE
-#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
-#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
-//TCI_STATUS
-#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
-#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
-//TCI_CNTL_1
-#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
-#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
-#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
-#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
-#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
-#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
-//TCI_CNTL_2
-#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
-#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
-#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
-#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
-//TCC_CTRL
-#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
-#define TCC_CTRL__RATE__SHIFT 0x2
-#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
-#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
-#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
-#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
-#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15
-#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
-#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
-#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
-#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
-#define TCC_CTRL__RATE_MASK 0x0000000CL
-#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
-#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L
-#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
-#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
-#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L
-#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L
-#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L
-#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L
-//TCC_CTRL2
-#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
-#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
-//TCC_EDC_CNT
-#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0
-#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2
-#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4
-#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6
-#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8
-#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa
-#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc
-#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe
-#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10
-#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12
-#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14
-#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16
-#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18
-#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a
-#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c
-#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e
-#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L
-#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL
-#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L
-#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L
-#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L
-#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L
-#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L
-#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L
-#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L
-#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L
-#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L
-#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L
-#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L
-#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L
-#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L
-#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L
-//TCC_EDC_CNT2
-#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0
-#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2
-#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4
-#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6
-#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8
-#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L
-#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL
-#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L
-#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L
-#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L
-//TCC_REDUNDANCY
-#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
-#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
-#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L
-#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L
-//TCC_EXE_DISABLE
-#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
-#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L
-//TCC_DSM_CNTL
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
-//TCC_DSM_CNTLA
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
-//TCC_DSM_CNTL2
-#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17
-#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//TCC_DSM_CNTL2A
-#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe
-#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14
-#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d
-#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L
-//TCC_DSM_CNTL2B
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
-//TCC_WBINVL2
-#define TCC_WBINVL2__DONE__SHIFT 0x4
-#define TCC_WBINVL2__DONE_MASK 0x00000010L
-//TCC_SOFT_RESET
-#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
-#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
-//TCA_CTRL
-#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
-#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4
-#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5
-#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6
-#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7
-#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL
-#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L
-#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L
-#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L
-#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L
-//TCA_BURST_MASK
-#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0
-#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
-//TCA_BURST_CTRL
-#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0
-#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3
-#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4
-#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5
-#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6
-#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7
-#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8
-#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9
-#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
-#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb
-#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc
-#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd
-#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe
-#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L
-#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L
-#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L
-#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L
-#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L
-#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L
-#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L
-#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L
-#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L
-#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L
-#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L
-#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L
-#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L
-//TCA_DSM_CNTL
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
-//TCA_DSM_CNTL2
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//TCA_EDC_CNT
-#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0
-#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2
-#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L
-#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL
-
-
-// addressBlock: gc_shdec
-//SPI_SHADER_PGM_RSRC3_PS
-#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
-#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
-#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
-#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L
-//SPI_SHADER_PGM_LO_PS
-#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_PS
-#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_PS
-#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
-#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
-#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
-//SPI_SHADER_PGM_RSRC2_PS
-#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
-#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
-#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
-#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_PS_0
-#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_1
-#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_2
-#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_3
-#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_4
-#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_5
-#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_6
-#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_7
-#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_8
-#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_9
-#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_10
-#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_11
-#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_12
-#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_13
-#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_14
-#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_15
-#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_16
-#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_17
-#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_18
-#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_19
-#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_20
-#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_21
-#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_22
-#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_23
-#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_24
-#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_25
-#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_26
-#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_27
-#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_28
-#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_29
-#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_30
-#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_31
-#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_RSRC3_VS
-#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
-#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
-#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
-#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L
-//SPI_SHADER_LATE_ALLOC_VS
-#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
-#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
-//SPI_SHADER_PGM_LO_VS
-#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_VS
-#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_VS
-#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
-#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
-#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
-#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
-//SPI_SHADER_PGM_RSRC2_VS
-#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
-#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
-#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
-#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
-#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
-#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
-#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_VS_0
-#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_1
-#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_2
-#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_3
-#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_4
-#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_5
-#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_6
-#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_7
-#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_8
-#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_9
-#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_10
-#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_11
-#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_12
-#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_13
-#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_14
-#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_15
-#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_16
-#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_17
-#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_18
-#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_19
-#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_20
-#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_21
-#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_22
-#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_23
-#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_24
-#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_25
-#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_26
-#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_27
-#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_28
-#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_29
-#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_30
-#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_31
-#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_RSRC2_GS_VS
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
-#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_PGM_RSRC4_GS
-#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
-#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L
-//SPI_SHADER_USER_DATA_ADDR_LO_GS
-#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ADDR_HI_GS
-#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_LO_ES
-#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_ES
-#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC3_GS
-#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
-#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
-#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
-#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L
-//SPI_SHADER_PGM_LO_GS
-#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_GS
-#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_GS
-#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
-#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
-#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
-#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
-#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
-//SPI_SHADER_PGM_RSRC2_GS
-#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
-#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
-#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
-#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
-#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
-#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
-#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_ES_0
-#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_1
-#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_2
-#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_3
-#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_4
-#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_5
-#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_6
-#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_7
-#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_8
-#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_9
-#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_10
-#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_11
-#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_12
-#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_13
-#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_14
-#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_15
-#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_16
-#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_17
-#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_18
-#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_19
-#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_20
-#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_21
-#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_22
-#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_23
-#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_24
-#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_25
-#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_26
-#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_27
-#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_28
-#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_29
-#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_30
-#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_31
-#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_RSRC4_HS
-#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
-//SPI_SHADER_USER_DATA_ADDR_LO_HS
-#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ADDR_HI_HS
-#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_LO_LS
-#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_LS
-#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC3_HS
-#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L
-#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
-//SPI_SHADER_PGM_LO_HS
-#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_HS
-#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_HS
-#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
-#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
-#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
-//SPI_SHADER_PGM_RSRC2_HS
-#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L
-#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L
-#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_LS_0
-#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_1
-#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_2
-#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_3
-#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_4
-#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_5
-#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_6
-#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_7
-#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_8
-#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_9
-#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_10
-#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_11
-#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_12
-#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_13
-#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_14
-#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_15
-#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_16
-#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_17
-#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_18
-#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_19
-#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_20
-#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_21
-#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_22
-#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_23
-#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_24
-#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_25
-#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_26
-#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_27
-#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_28
-#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_29
-#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_30
-#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_31
-#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_0
-#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_1
-#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_2
-#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_3
-#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_4
-#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_5
-#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_6
-#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_7
-#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_8
-#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_9
-#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_10
-#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_11
-#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_12
-#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_13
-#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_14
-#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_15
-#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_16
-#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_17
-#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_18
-#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_19
-#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_20
-#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_21
-#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_22
-#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_23
-#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_24
-#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_25
-#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_26
-#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_27
-#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_28
-#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_29
-#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_30
-#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_31
-#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_DISPATCH_INITIATOR
-#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
-#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
-#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
-#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
-#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
-#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
-#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
-#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
-#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
-#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
-#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
-#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
-#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
-#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
-#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
-#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
-#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
-#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
-//COMPUTE_DIM_X
-#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
-//COMPUTE_DIM_Y
-#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
-//COMPUTE_DIM_Z
-#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
-//COMPUTE_START_X
-#define COMPUTE_START_X__START__SHIFT 0x0
-#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
-//COMPUTE_START_Y
-#define COMPUTE_START_Y__START__SHIFT 0x0
-#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
-//COMPUTE_START_Z
-#define COMPUTE_START_Z__START__SHIFT 0x0
-#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
-//COMPUTE_NUM_THREAD_X
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
-//COMPUTE_NUM_THREAD_Y
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
-//COMPUTE_NUM_THREAD_Z
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
-//COMPUTE_PIPELINESTAT_ENABLE
-#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
-#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
-//COMPUTE_PERFCOUNT_ENABLE
-#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
-#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
-//COMPUTE_PGM_LO
-#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
-#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_PGM_HI
-#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
-#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
-//COMPUTE_DISPATCH_PKT_ADDR_LO
-#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_DISPATCH_PKT_ADDR_HI
-#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
-//COMPUTE_DISPATCH_SCRATCH_BASE_LO
-#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_DISPATCH_SCRATCH_BASE_HI
-#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
-//COMPUTE_PGM_RSRC1
-#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
-#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
-#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
-#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
-#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
-#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
-#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
-#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
-#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
-#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
-#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
-#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
-#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
-#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
-#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
-#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
-#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
-#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
-//COMPUTE_PGM_RSRC2
-#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
-#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
-#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
-#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
-#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
-#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
-#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
-#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
-#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
-#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
-#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f
-#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
-#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
-#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
-#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
-#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
-#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
-#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
-#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
-#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
-#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L
-//COMPUTE_VMID
-#define COMPUTE_VMID__DATA__SHIFT 0x0
-#define COMPUTE_VMID__DATA_MASK 0x0000000FL
-//COMPUTE_RESOURCE_LIMITS
-#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
-#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
-#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
-#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
-#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b
-#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
-#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
-#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
-#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
-#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L
-//COMPUTE_STATIC_THREAD_MGMT_SE0
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_STATIC_THREAD_MGMT_SE1
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_TMPRING_SIZE
-#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
-#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
-#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
-#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
-//COMPUTE_STATIC_THREAD_MGMT_SE2
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_STATIC_THREAD_MGMT_SE3
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_RESTART_X
-#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
-//COMPUTE_RESTART_Y
-#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
-//COMPUTE_RESTART_Z
-#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
-//COMPUTE_THREAD_TRACE_ENABLE
-#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
-#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
-//COMPUTE_MISC_RESERVED
-#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
-#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
-#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
-#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
-#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
-#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
-#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L
-#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L
-#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L
-#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
-//COMPUTE_DISPATCH_ID
-#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
-#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
-//COMPUTE_THREADGROUP_ID
-#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
-#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
-//COMPUTE_RELAUNCH
-#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
-#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
-#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
-#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
-#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
-#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
-//COMPUTE_WAVE_RESTORE_ADDR_LO
-#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
-//COMPUTE_WAVE_RESTORE_ADDR_HI
-#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
-//COMPUTE_USER_DATA_0
-#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_1
-#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_2
-#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_3
-#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_4
-#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_5
-#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_6
-#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_7
-#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_8
-#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_9
-#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_10
-#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_11
-#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_12
-#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_13
-#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_14
-#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_15
-#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_NOWHERE
-#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
-#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_cppdec
-//CP_DFY_CNTL
-#define CP_DFY_CNTL__POLICY__SHIFT 0x0
-#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
-#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a
-#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
-#define CP_DFY_CNTL__MODE__SHIFT 0x1d
-#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
-#define CP_DFY_CNTL__POLICY_MASK 0x00000001L
-#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL
-#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L
-#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L
-#define CP_DFY_CNTL__MODE_MASK 0x60000000L
-#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L
-//CP_DFY_STAT
-#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
-#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
-#define CP_DFY_STAT__BUSY__SHIFT 0x1f
-#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL
-#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L
-#define CP_DFY_STAT__BUSY_MASK 0x80000000L
-//CP_DFY_ADDR_HI
-#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
-//CP_DFY_ADDR_LO
-#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
-#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L
-//CP_DFY_DATA_0
-#define CP_DFY_DATA_0__DATA__SHIFT 0x0
-#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_1
-#define CP_DFY_DATA_1__DATA__SHIFT 0x0
-#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_2
-#define CP_DFY_DATA_2__DATA__SHIFT 0x0
-#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_3
-#define CP_DFY_DATA_3__DATA__SHIFT 0x0
-#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_4
-#define CP_DFY_DATA_4__DATA__SHIFT 0x0
-#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_5
-#define CP_DFY_DATA_5__DATA__SHIFT 0x0
-#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_6
-#define CP_DFY_DATA_6__DATA__SHIFT 0x0
-#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_7
-#define CP_DFY_DATA_7__DATA__SHIFT 0x0
-#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_8
-#define CP_DFY_DATA_8__DATA__SHIFT 0x0
-#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_9
-#define CP_DFY_DATA_9__DATA__SHIFT 0x0
-#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_10
-#define CP_DFY_DATA_10__DATA__SHIFT 0x0
-#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_11
-#define CP_DFY_DATA_11__DATA__SHIFT 0x0
-#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_12
-#define CP_DFY_DATA_12__DATA__SHIFT 0x0
-#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_13
-#define CP_DFY_DATA_13__DATA__SHIFT 0x0
-#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_14
-#define CP_DFY_DATA_14__DATA__SHIFT 0x0
-#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_15
-#define CP_DFY_DATA_15__DATA__SHIFT 0x0
-#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_CMD
-#define CP_DFY_CMD__OFFSET__SHIFT 0x0
-#define CP_DFY_CMD__SIZE__SHIFT 0x10
-#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL
-#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L
-//CP_EOPQ_WAIT_TIME
-#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
-#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
-#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
-#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
-//CP_CPC_MGCG_SYNC_CNTL
-#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
-#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
-#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
-#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
-//CPC_INT_INFO
-#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
-#define CPC_INT_INFO__TYPE__SHIFT 0x10
-#define CPC_INT_INFO__VMID__SHIFT 0x14
-#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
-#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
-#define CPC_INT_INFO__TYPE_MASK 0x00010000L
-#define CPC_INT_INFO__VMID_MASK 0x00F00000L
-#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
-//CP_VIRT_STATUS
-#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
-#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
-//CPC_INT_ADDR
-#define CPC_INT_ADDR__ADDR__SHIFT 0x0
-#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
-//CPC_INT_PASID
-#define CPC_INT_PASID__PASID__SHIFT 0x0
-#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
-//CP_GFX_ERROR
-#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0
-#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
-#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5
-#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6
-#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
-#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
-#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
-#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
-#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
-#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
-#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
-#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
-#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
-#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
-#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
-#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
-#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
-#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
-#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
-#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
-#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
-#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
-#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
-#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
-#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
-#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
-#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
-#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
-#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
-#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
-#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
-#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L
-#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L
-#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
-#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
-#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
-#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
-#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
-#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
-#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
-#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
-#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
-#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
-#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
-#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
-#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
-#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
-#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
-#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
-#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
-#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
-#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
-#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
-#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
-#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
-#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
-#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
-#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
-//CPG_UTCL1_CNTL
-#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
-#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
-//CPC_UTCL1_CNTL
-#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
-#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
-//CPF_UTCL1_CNTL
-#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
-#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
-#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
-#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
-//CP_AQL_SMM_STATUS
-#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
-#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
-//CP_RB0_BASE
-#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB_BASE
-#define CP_RB_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB0_CNTL
-#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
-#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L
-#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB_CNTL
-#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB_RPTR_WR
-#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
-#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
-//CP_RB0_RPTR_ADDR
-#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB_RPTR_ADDR
-#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB0_RPTR_ADDR_HI
-#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB_RPTR_ADDR_HI
-#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB0_BUFSZ_MASK
-#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
-#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
-//CP_RB_BUFSZ_MASK
-#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
-#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
-//CP_RB_WPTR_POLL_ADDR_LO
-#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
-#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_RB_WPTR_POLL_ADDR_HI
-#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
-#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
-//GC_PRIV_MODE
-//CP_INT_CNTL
-#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_STATUS
-#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
-//CP_DEVICE_ID
-#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
-#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
-//CP_ME0_PIPE_PRIORITY_CNTS
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_RING_PRIORITY_CNTS
-#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_ME0_PIPE0_PRIORITY
-#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_RING0_PRIORITY
-#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME0_PIPE1_PRIORITY
-#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_RING1_PRIORITY
-#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME0_PIPE2_PRIORITY
-#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_RING2_PRIORITY
-#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_FATAL_ERROR
-#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
-#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
-#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
-#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
-#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
-#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
-#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
-#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
-#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
-#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
-//CP_RB_VMID
-#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
-#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
-#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
-#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
-#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
-#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
-//CP_ME0_PIPE0_VMID
-#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
-#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
-//CP_ME0_PIPE1_VMID
-#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
-#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
-//CP_RB0_WPTR
-#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB_WPTR
-#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB0_WPTR_HI
-#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
-#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB_WPTR_HI
-#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
-#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB1_WPTR
-#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB1_WPTR_HI
-#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
-#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB2_WPTR
-#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
-//CP_RB_DOORBELL_CONTROL
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_RANGE_LOWER
-#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
-#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
-//CP_RB_DOORBELL_RANGE_UPPER
-#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
-#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
-//CP_MEC_DOORBELL_RANGE_LOWER
-#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
-#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
-//CP_MEC_DOORBELL_RANGE_UPPER
-#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
-#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
-//CPG_UTCL1_ERROR
-#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
-#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
-//CPC_UTCL1_ERROR
-#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
-#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
-//CP_RB1_BASE
-#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB1_CNTL
-#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB1_RPTR_ADDR
-#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB1_RPTR_ADDR_HI
-#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB2_BASE
-#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB2_CNTL
-#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB2_RPTR_ADDR
-#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB2_RPTR_ADDR_HI
-#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB0_ACTIVE
-#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
-//CP_RB_ACTIVE
-#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
-//CP_INT_CNTL_RING0
-#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_CNTL_RING1
-#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_CNTL_RING2
-#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_STATUS_RING0
-#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
-//CP_INT_STATUS_RING1
-#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
-//CP_INT_STATUS_RING2
-#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
-#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
-//CP_PWR_CNTL
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
-//CP_MEM_SLP_CNTL
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
-#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
-#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
-#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
-#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
-#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
-#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
-#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
-#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
-//CP_ECC_FIRSTOCCURRENCE
-#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
-#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
-#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
-#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
-#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
-#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
-#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
-#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
-#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
-#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
-#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
-//CP_ECC_FIRSTOCCURRENCE_RING0
-#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_ECC_FIRSTOCCURRENCE_RING1
-#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_ECC_FIRSTOCCURRENCE_RING2
-#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
-//GB_EDC_MODE
-#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
-#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
-#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11
-#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
-#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
-#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
-#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
-#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
-#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L
-#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
-#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
-#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
-//CP_PQ_WPTR_POLL_CNTL
-#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
-#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
-#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
-#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
-#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
-#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
-#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
-#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
-//CP_PQ_WPTR_POLL_CNTL1
-#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
-#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
-//CP_ME1_PIPE0_INT_CNTL
-#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE1_INT_CNTL
-#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE2_INT_CNTL
-#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE3_INT_CNTL
-#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE0_INT_CNTL
-#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE1_INT_CNTL
-#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE2_INT_CNTL
-#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE3_INT_CNTL
-#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE0_INT_STATUS
-#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME1_PIPE1_INT_STATUS
-#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME1_PIPE2_INT_STATUS
-#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME1_PIPE3_INT_STATUS
-#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE0_INT_STATUS
-#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE1_INT_STATUS
-#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE2_INT_STATUS
-#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE3_INT_STATUS
-#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-//CC_GC_EDC_CONFIG
-#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-//CP_ME1_PIPE_PRIORITY_CNTS
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_ME1_PIPE0_PRIORITY
-#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME1_PIPE1_PRIORITY
-#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME1_PIPE2_PRIORITY
-#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME1_PIPE3_PRIORITY
-#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE_PRIORITY_CNTS
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_ME2_PIPE0_PRIORITY
-#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE1_PRIORITY
-#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE2_PRIORITY
-#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE3_PRIORITY
-#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_CE_PRGRM_CNTR_START
-#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL
-//CP_PFP_PRGRM_CNTR_START
-#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL
-//CP_ME_PRGRM_CNTR_START
-#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL
-//CP_MEC1_PRGRM_CNTR_START
-#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
-//CP_MEC2_PRGRM_CNTR_START
-#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
-//CP_CE_INTR_ROUTINE_START
-#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL
-//CP_PFP_INTR_ROUTINE_START
-#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL
-//CP_ME_INTR_ROUTINE_START
-#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL
-//CP_MEC1_INTR_ROUTINE_START
-#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
-//CP_MEC2_INTR_ROUTINE_START
-#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
-//CP_CONTEXT_CNTL
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
-//CP_MAX_CONTEXT
-#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
-#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
-//CP_IQ_WAIT_TIME1
-#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
-#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
-#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
-#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
-#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
-#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
-#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
-#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
-//CP_IQ_WAIT_TIME2
-#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
-#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
-#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
-#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
-#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
-#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
-#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
-#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
-//CP_RB0_BASE_HI
-#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
-//CP_RB1_BASE_HI
-#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
-//CP_VMID_RESET
-#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
-#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
-//CPC_INT_CNTL
-#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CPC_INT_STATUS
-#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_VMID_PREEMPT
-#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
-#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
-#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
-#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
-//CPC_INT_CNTX_ID
-#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
-#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
-//CP_PQ_STATUS
-#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
-#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
-#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
-#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
-//CP_CPC_IC_BASE_LO
-#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
-#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
-//CP_CPC_IC_BASE_HI
-#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
-#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
-//CP_CPC_IC_BASE_CNTL
-#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
-#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
-#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L
-//CP_CPC_IC_OP_CNTL
-#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
-#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
-#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
-#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
-#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
-#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
-//CP_MEC1_F32_INT_DIS
-#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
-#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
-#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
-#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
-#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
-#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
-#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
-#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
-#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
-#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
-#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
-#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
-#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
-#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
-#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
-#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
-#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
-#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
-#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
-#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
-#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
-#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
-#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
-#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
-#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
-#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
-//CP_MEC2_F32_INT_DIS
-#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
-#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
-#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
-#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
-#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
-#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
-#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
-#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
-#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
-#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
-#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
-#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
-#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
-#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
-#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
-#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
-#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
-#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
-#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
-#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
-#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
-#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
-#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
-#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
-#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
-#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
-//CP_VMID_STATUS
-#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
-#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
-#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
-#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_cppdec2
-//CP_RB_DOORBELL_CONTROL_SCH_0
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_1
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_2
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_3
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_4
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_5
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_6
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_7
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CLEAR
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
-//CP_GFX_MQD_CONTROL
-#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
-#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
-#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
-//CP_GFX_MQD_BASE_ADDR
-#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
-#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
-//CP_GFX_MQD_BASE_ADDR_HI
-#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB_STATUS
-#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
-#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
-#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
-#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
-//CPG_UTCL1_STATUS
-#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//CPC_UTCL1_STATUS
-#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//CPF_UTCL1_STATUS
-#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//CP_SD_CNTL
-#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
-#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
-#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
-#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
-#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
-#define CP_SD_CNTL__WD_EN__SHIFT 0x5
-#define CP_SD_CNTL__IA_EN__SHIFT 0x6
-#define CP_SD_CNTL__PA_EN__SHIFT 0x7
-#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
-#define CP_SD_CNTL__EA_EN__SHIFT 0x9
-#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
-#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
-#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
-#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
-#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
-#define CP_SD_CNTL__WD_EN_MASK 0x00000020L
-#define CP_SD_CNTL__IA_EN_MASK 0x00000040L
-#define CP_SD_CNTL__PA_EN_MASK 0x00000080L
-#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
-#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
-//CP_SOFT_RESET_CNTL
-#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
-#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
-#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
-#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
-#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
-#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
-#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
-#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
-#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
-#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
-#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
-#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
-#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
-#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
-//CP_CPC_GFX_CNTL
-#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
-#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
-#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
-#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
-#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
-#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
-#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
-#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
-
-
-// addressBlock: gc_spipdec
-//SPI_ARB_PRIORITY
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
-#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
-#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
-#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
-#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
-#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
-#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
-#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
-#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
-//SPI_ARB_CYCLES_0
-#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
-#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
-#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
-#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
-//SPI_ARB_CYCLES_1
-#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
-#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
-#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
-#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
-//SPI_WCL_PIPE_PERCENT_GFX
-#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
-#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
-#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
-#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
-#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
-#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
-#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
-#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
-#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
-//SPI_WCL_PIPE_PERCENT_HP3D
-#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
-#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
-#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
-#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
-#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
-//SPI_WCL_PIPE_PERCENT_CS0
-#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS1
-#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS2
-#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS3
-#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS4
-#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS5
-#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS6
-#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS7
-#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
-//SPI_COMPUTE_QUEUE_RESET
-#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
-#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
-//SPI_RESOURCE_RESERVE_CU_0
-#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_1
-#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_2
-#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_3
-#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_4
-#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_5
-#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_6
-#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_7
-#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_8
-#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_9
-#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_EN_CU_0
-#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_1
-#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_2
-#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_3
-#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_4
-#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_5
-#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_6
-#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_7
-#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_8
-#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_9
-#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_CU_10
-#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_11
-#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_EN_CU_10
-#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_11
-#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_CU_12
-#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_13
-#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_14
-#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_15
-#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_EN_CU_12
-#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_13
-#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_14
-#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_15
-#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_COMPUTE_WF_CTX_SAVE
-#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
-#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
-#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
-#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
-#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
-#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
-//SPI_ARB_CNTL_0
-#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
-#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
-#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
-#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
-#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
-#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
-
-
-// addressBlock: gc_cpphqddec
-//CP_HQD_GFX_CONTROL
-#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
-#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
-#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
-#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
-#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
-#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
-//CP_HQD_GFX_STATUS
-#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
-#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
-//CP_HPD_ROQ_OFFSETS
-#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
-#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
-#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
-#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
-#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
-#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L
-//CP_HPD_STATUS0
-#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
-#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
-#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
-#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
-#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
-#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
-#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
-#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
-#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
-#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
-#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
-#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
-//CP_HPD_UTCL1_CNTL
-#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
-#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
-//CP_HPD_UTCL1_ERROR
-#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
-#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
-#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
-#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
-#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
-#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
-//CP_HPD_UTCL1_ERROR_ADDR
-#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
-#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
-//CP_MQD_BASE_ADDR
-#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
-#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
-//CP_MQD_BASE_ADDR_HI
-#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_ACTIVE
-#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
-#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
-#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
-//CP_HQD_VMID
-#define CP_HQD_VMID__VMID__SHIFT 0x0
-#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
-#define CP_HQD_VMID__VQID__SHIFT 0x10
-#define CP_HQD_VMID__VMID_MASK 0x0000000FL
-#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
-#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
-//CP_HQD_PERSISTENT_STATE
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
-#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
-#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
-#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
-#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
-#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
-#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
-#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
-#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
-#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
-#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
-#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
-#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
-#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
-#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
-#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
-#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
-#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
-#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
-#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
-#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
-#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
-#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
-//CP_HQD_PIPE_PRIORITY
-#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
-#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
-//CP_HQD_QUEUE_PRIORITY
-#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
-#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
-//CP_HQD_QUANTUM
-#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
-#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
-#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
-#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
-#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
-#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
-#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
-#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
-//CP_HQD_PQ_BASE
-#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
-#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
-//CP_HQD_PQ_BASE_HI
-#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
-//CP_HQD_PQ_RPTR
-#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
-#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
-//CP_HQD_PQ_RPTR_REPORT_ADDR
-#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
-#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
-//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_PQ_WPTR_POLL_ADDR
-#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
-#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
-//CP_HQD_PQ_WPTR_POLL_ADDR_HI
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_PQ_DOORBELL_CONTROL
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
-//CP_HQD_PQ_CONTROL
-#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
-#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
-#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
-#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
-#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
-#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
-#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10
-#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
-#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
-#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
-#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
-#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
-#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
-#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
-#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
-#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
-#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
-#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
-#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
-#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
-#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
-#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L
-#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L
-#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
-#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L
-#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
-#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
-#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L
-#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
-#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
-//CP_HQD_IB_BASE_ADDR
-#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
-#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
-//CP_HQD_IB_BASE_ADDR_HI
-#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_IB_RPTR
-#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
-#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
-//CP_HQD_IB_CONTROL
-#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
-#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
-#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
-#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
-#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
-#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
-//CP_HQD_IQ_TIMER
-#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
-#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
-#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
-#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
-#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
-#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
-#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
-#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19
-#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
-#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
-#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
-#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
-#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
-#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
-#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
-#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
-#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
-#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
-#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
-#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L
-#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
-#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
-#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
-#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
-//CP_HQD_IQ_RPTR
-#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
-#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
-//CP_HQD_DEQUEUE_REQUEST
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
-//CP_HQD_DMA_OFFLOAD
-#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
-#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
-//CP_HQD_OFFLOAD
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
-//CP_HQD_SEMA_CMD
-#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
-#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
-#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
-#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
-//CP_HQD_MSG_TYPE
-#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
-#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
-#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
-#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
-//CP_HQD_ATOMIC0_PREOP_LO
-#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_HQD_ATOMIC0_PREOP_HI
-#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_HQD_ATOMIC1_PREOP_LO
-#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_HQD_ATOMIC1_PREOP_HI
-#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_SCHEDULER0
-#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
-#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_STATUS0
-#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
-#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
-#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
-#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
-#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
-#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
-#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
-#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
-#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
-#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
-#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
-#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
-#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
-#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
-#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
-#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
-#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
-#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
-//CP_HQD_HQ_CONTROL0
-#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
-#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_SCHEDULER1
-#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
-#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
-//CP_MQD_CONTROL
-#define CP_MQD_CONTROL__VMID__SHIFT 0x0
-#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
-#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
-#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
-#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
-#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
-#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
-#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
-#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
-//CP_HQD_HQ_STATUS1
-#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
-#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_CONTROL1
-#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
-#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
-//CP_HQD_EOP_BASE_ADDR
-#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
-#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
-//CP_HQD_EOP_BASE_ADDR_HI
-#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
-//CP_HQD_EOP_CONTROL
-#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
-#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
-#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
-#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
-#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
-#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
-#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
-#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
-#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
-#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
-//CP_HQD_EOP_RPTR
-#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
-#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
-#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
-#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
-#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
-#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
-#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
-#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
-#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
-#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
-//CP_HQD_EOP_WPTR
-#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
-#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
-#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
-#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
-#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
-#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
-//CP_HQD_EOP_EVENTS
-#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
-#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
-#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
-#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
-//CP_HQD_CTX_SAVE_BASE_ADDR_LO
-#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
-#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
-//CP_HQD_CTX_SAVE_BASE_ADDR_HI
-#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_CTX_SAVE_CONTROL
-#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
-#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L
-#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
-//CP_HQD_CNTL_STACK_OFFSET
-#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
-#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
-//CP_HQD_CNTL_STACK_SIZE
-#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
-#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
-//CP_HQD_WG_STATE_OFFSET
-#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
-#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
-//CP_HQD_CTX_SAVE_SIZE
-#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
-#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
-//CP_HQD_GDS_RESOURCE_STATE
-#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
-#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
-#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
-#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
-//CP_HQD_ERROR
-#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
-#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
-#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
-#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
-#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
-#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
-#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
-#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
-#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
-#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
-#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
-#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
-#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
-#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
-#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
-#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
-#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
-#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
-#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
-#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
-#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
-#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
-#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
-#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
-#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
-#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
-#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
-#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
-#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
-#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
-//CP_HQD_EOP_WPTR_MEM
-#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
-#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
-//CP_HQD_AQL_CONTROL
-#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
-#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
-#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
-#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
-#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
-#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
-#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
-#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
-//CP_HQD_PQ_WPTR_LO
-#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
-//CP_HQD_PQ_WPTR_HI
-#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_didtdec
-//DIDT_IND_INDEX
-#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
-#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
-//DIDT_IND_DATA
-#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
-#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gccacdec
-//GC_CAC_CTRL_1
-#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
-#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
-#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
-#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
-//GC_CAC_CTRL_2
-#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
-#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
-#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2
-#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
-#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
-#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL
-//GC_CAC_CGTT_CLK_CTRL
-#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//GC_CAC_AGGR_LOWER
-#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
-#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_AGGR_UPPER
-#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
-#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
-//GC_CAC_PG_AGGR_LOWER
-#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0
-#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_PG_AGGR_UPPER
-#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0
-#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xFFFFFFFFL
-//GC_CAC_SOFT_CTRL
-#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
-#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1
-#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
-#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL
-//GC_DIDT_CTRL0
-#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
-#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
-#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
-#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
-//GC_DIDT_CTRL1
-#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
-#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
-#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//GC_DIDT_CTRL2
-#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe
-#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a
-#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f
-#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L
-#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L
-//GC_DIDT_WEIGHT
-#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
-#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
-#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
-#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
-#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
-#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
-#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
-#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
-//GC_EDC_CTRL
-#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
-#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa
-#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
-#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L
-//GC_EDC_THRESHOLD
-#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//GC_EDC_STATUS
-#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0
-#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3
-#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L
-#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L
-//GC_EDC_OVERFLOW
-#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11
-#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12
-#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L
-#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L
-//GC_EDC_ROLLING_POWER_DELTA
-#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//GC_DIDT_DROOP_CTRL
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf
-#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L
-#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L
-//GC_EDC_DROOP_CTRL
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf
-#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14
-#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L
-#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L
-#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L
-//GC_CAC_IND_INDEX
-#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
-#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
-//GC_CAC_IND_DATA
-#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
-#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
-//SE_CAC_CGTT_CLK_CTRL
-#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//SE_CAC_IND_INDEX
-#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
-#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
-//SE_CAC_IND_DATA
-#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
-#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_tcpdec
-//TCP_WATCH0_ADDR_H
-#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH0_ADDR_L
-#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH0_CNTL
-#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
-//TCP_WATCH1_ADDR_H
-#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH1_ADDR_L
-#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH1_CNTL
-#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
-//TCP_WATCH2_ADDR_H
-#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH2_ADDR_L
-#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH2_CNTL
-#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
-//TCP_WATCH3_ADDR_H
-#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH3_ADDR_L
-#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH3_CNTL
-#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
-//TCP_GATCL1_CNTL
-#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
-#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
-#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
-#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L
-#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L
-#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//TCP_ATC_EDC_GATCL1_CNT
-#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
-#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL
-//TCP_GATCL1_DSM_CNTL
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
-#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L
-#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L
-//TCP_CNTL2
-#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
-#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL
-//TCP_UTCL1_CNTL1
-#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
-#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
-#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//TCP_UTCL1_CNTL2
-#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
-#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
-#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//TCP_UTCL1_STATUS
-#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//TCP_PERFCOUNTER_FILTER
-#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
-#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
-#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
-#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
-#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb
-#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf
-#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14
-#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16
-#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19
-#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a
-#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b
-#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
-#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
-#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
-#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L
-#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L
-#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L
-#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L
-#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L
-#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L
-#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L
-#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L
-#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L
-//TCP_PERFCOUNTER_FILTER_EN
-#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
-#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
-#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
-#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
-#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
-#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
-#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8
-#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9
-#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
-#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb
-#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
-#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
-#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
-#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
-#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
-#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
-#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L
-#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L
-#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L
-#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L
-
-
-// addressBlock: gc_gdspdec
-//GDS_VMID0_BASE
-#define GDS_VMID0_BASE__BASE__SHIFT 0x0
-#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID0_SIZE
-#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID1_BASE
-#define GDS_VMID1_BASE__BASE__SHIFT 0x0
-#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID1_SIZE
-#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID2_BASE
-#define GDS_VMID2_BASE__BASE__SHIFT 0x0
-#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID2_SIZE
-#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID3_BASE
-#define GDS_VMID3_BASE__BASE__SHIFT 0x0
-#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID3_SIZE
-#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID4_BASE
-#define GDS_VMID4_BASE__BASE__SHIFT 0x0
-#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID4_SIZE
-#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID5_BASE
-#define GDS_VMID5_BASE__BASE__SHIFT 0x0
-#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID5_SIZE
-#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID6_BASE
-#define GDS_VMID6_BASE__BASE__SHIFT 0x0
-#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID6_SIZE
-#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID7_BASE
-#define GDS_VMID7_BASE__BASE__SHIFT 0x0
-#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID7_SIZE
-#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID8_BASE
-#define GDS_VMID8_BASE__BASE__SHIFT 0x0
-#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID8_SIZE
-#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID9_BASE
-#define GDS_VMID9_BASE__BASE__SHIFT 0x0
-#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID9_SIZE
-#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID10_BASE
-#define GDS_VMID10_BASE__BASE__SHIFT 0x0
-#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID10_SIZE
-#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID11_BASE
-#define GDS_VMID11_BASE__BASE__SHIFT 0x0
-#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID11_SIZE
-#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID12_BASE
-#define GDS_VMID12_BASE__BASE__SHIFT 0x0
-#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID12_SIZE
-#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID13_BASE
-#define GDS_VMID13_BASE__BASE__SHIFT 0x0
-#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID13_SIZE
-#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID14_BASE
-#define GDS_VMID14_BASE__BASE__SHIFT 0x0
-#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID14_SIZE
-#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID15_BASE
-#define GDS_VMID15_BASE__BASE__SHIFT 0x0
-#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID15_SIZE
-#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_GWS_VMID0
-#define GDS_GWS_VMID0__BASE__SHIFT 0x0
-#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID1
-#define GDS_GWS_VMID1__BASE__SHIFT 0x0
-#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID2
-#define GDS_GWS_VMID2__BASE__SHIFT 0x0
-#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID3
-#define GDS_GWS_VMID3__BASE__SHIFT 0x0
-#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID4
-#define GDS_GWS_VMID4__BASE__SHIFT 0x0
-#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID5
-#define GDS_GWS_VMID5__BASE__SHIFT 0x0
-#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID6
-#define GDS_GWS_VMID6__BASE__SHIFT 0x0
-#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID7
-#define GDS_GWS_VMID7__BASE__SHIFT 0x0
-#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID8
-#define GDS_GWS_VMID8__BASE__SHIFT 0x0
-#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID9
-#define GDS_GWS_VMID9__BASE__SHIFT 0x0
-#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID10
-#define GDS_GWS_VMID10__BASE__SHIFT 0x0
-#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID11
-#define GDS_GWS_VMID11__BASE__SHIFT 0x0
-#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID12
-#define GDS_GWS_VMID12__BASE__SHIFT 0x0
-#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID13
-#define GDS_GWS_VMID13__BASE__SHIFT 0x0
-#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID14
-#define GDS_GWS_VMID14__BASE__SHIFT 0x0
-#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID15
-#define GDS_GWS_VMID15__BASE__SHIFT 0x0
-#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
-//GDS_OA_VMID0
-#define GDS_OA_VMID0__MASK__SHIFT 0x0
-#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID1
-#define GDS_OA_VMID1__MASK__SHIFT 0x0
-#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID2
-#define GDS_OA_VMID2__MASK__SHIFT 0x0
-#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID3
-#define GDS_OA_VMID3__MASK__SHIFT 0x0
-#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID4
-#define GDS_OA_VMID4__MASK__SHIFT 0x0
-#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID5
-#define GDS_OA_VMID5__MASK__SHIFT 0x0
-#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID6
-#define GDS_OA_VMID6__MASK__SHIFT 0x0
-#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID7
-#define GDS_OA_VMID7__MASK__SHIFT 0x0
-#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID8
-#define GDS_OA_VMID8__MASK__SHIFT 0x0
-#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID9
-#define GDS_OA_VMID9__MASK__SHIFT 0x0
-#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID10
-#define GDS_OA_VMID10__MASK__SHIFT 0x0
-#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID11
-#define GDS_OA_VMID11__MASK__SHIFT 0x0
-#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID12
-#define GDS_OA_VMID12__MASK__SHIFT 0x0
-#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID13
-#define GDS_OA_VMID13__MASK__SHIFT 0x0
-#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID14
-#define GDS_OA_VMID14__MASK__SHIFT 0x0
-#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID15
-#define GDS_OA_VMID15__MASK__SHIFT 0x0
-#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
-//GDS_GWS_RESET0
-#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
-#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
-#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
-#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
-#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
-#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
-#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
-#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
-#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
-#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
-#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
-#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
-#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
-#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
-#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
-#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
-#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
-#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
-#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
-#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
-#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
-#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
-#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
-#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
-#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
-#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
-#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
-#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
-#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
-#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
-#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
-#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
-#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
-#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
-#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
-#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
-#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
-#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
-#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
-#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
-#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
-#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
-#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
-#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
-#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
-#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
-#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
-#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
-#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
-#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
-#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
-#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
-#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
-#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
-#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
-#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
-#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
-#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
-#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
-#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
-#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
-#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
-#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
-#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
-//GDS_GWS_RESET1
-#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
-#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
-#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
-#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
-#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
-#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
-#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
-#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
-#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
-#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
-#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
-#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
-#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
-#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
-#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
-#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
-#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
-#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
-#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
-#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
-#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
-#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
-#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
-#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
-#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
-#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
-#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
-#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
-#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
-#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
-#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
-#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
-#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
-#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
-#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
-#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
-#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
-#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
-#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
-#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
-#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
-#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
-#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
-#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
-#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
-#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
-#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
-#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
-#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
-#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
-#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
-#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
-#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
-#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
-#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
-#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
-#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
-#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
-#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
-#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
-#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
-#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
-#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
-#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
-//GDS_GWS_RESOURCE_RESET
-#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
-#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
-#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
-#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
-//GDS_COMPUTE_MAX_WAVE_ID
-#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//GDS_OA_RESET_MASK
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
-#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
-#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
-#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
-#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
-#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
-#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
-#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
-#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
-#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
-#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
-#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
-#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
-#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
-#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
-#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
-#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
-#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
-#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
-#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
-#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
-//GDS_OA_RESET
-#define GDS_OA_RESET__RESET__SHIFT 0x0
-#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
-#define GDS_OA_RESET__RESET_MASK 0x00000001L
-#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
-//GDS_ENHANCE
-#define GDS_ENHANCE__MISC__SHIFT 0x0
-#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
-#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
-#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12
-#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13
-#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14
-#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
-#define GDS_ENHANCE__UNUSED__SHIFT 0x16
-#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
-#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
-#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
-#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L
-#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L
-#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L
-#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
-#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L
-//GDS_OA_CGPG_RESTORE
-#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
-#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
-#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
-#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
-#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
-#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
-#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
-#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
-#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
-#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
-//GDS_CS_CTXSW_STATUS
-#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
-#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
-#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
-#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
-#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
-#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
-//GDS_CS_CTXSW_CNT0
-#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_CS_CTXSW_CNT1
-#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_CS_CTXSW_CNT2
-#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_CS_CTXSW_CNT3
-#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_GFX_CTXSW_STATUS
-#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
-#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
-#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
-#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
-#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
-#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
-//GDS_VS_CTXSW_CNT0
-#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_VS_CTXSW_CNT1
-#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_VS_CTXSW_CNT2
-#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_VS_CTXSW_CNT3
-#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT0
-#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT1
-#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT2
-#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT3
-#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT0
-#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT1
-#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT2
-#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT3
-#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT0
-#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT1
-#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT2
-#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT3
-#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT0
-#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT1
-#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT2
-#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT3
-#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT0
-#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT1
-#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT2
-#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT3
-#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT0
-#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT1
-#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT2
-#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT3
-#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT0
-#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT1
-#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT2
-#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT3
-#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT0
-#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT1
-#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT2
-#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT3
-#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT0
-#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT1
-#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT2
-#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT3
-#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_rasdec
-//RAS_SIGNATURE_CONTROL
-#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
-#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L
-//RAS_SIGNATURE_MASK
-#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
-#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE0
-#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE1
-#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE2
-#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE3
-#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_DB_SIGNATURE0
-#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_PA_SIGNATURE0
-#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_VGT_SIGNATURE0
-#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SQ_SIGNATURE0
-#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE0
-#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE1
-#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE2
-#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE3
-#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE4
-#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE5
-#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE6
-#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE7
-#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_IA_SIGNATURE0
-#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_IA_SIGNATURE1
-#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SPI_SIGNATURE0
-#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SPI_SIGNATURE1
-#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_TA_SIGNATURE0
-#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_TD_SIGNATURE0
-#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_CB_SIGNATURE0
-#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_BCI_SIGNATURE0
-#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_BCI_SIGNATURE1
-#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_TA_SIGNATURE1
-#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gfxdec0
-//DB_RENDER_CONTROL
-#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
-#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
-#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
-#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
-#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
-#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
-#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
-#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
-#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
-#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
-#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
-#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
-#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
-#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
-#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
-#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
-#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
-#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
-#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
-#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
-//DB_COUNT_CONTROL
-#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
-#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
-#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
-#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
-#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
-#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
-#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
-#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
-#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
-#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
-#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
-#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
-#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
-#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
-#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
-#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
-#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
-#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
-//DB_DEPTH_VIEW
-#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
-#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
-#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
-#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
-#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
-#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
-#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
-#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
-#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
-//DB_RENDER_OVERRIDE
-#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
-#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
-#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
-#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
-#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
-#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
-#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
-#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
-#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
-#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
-#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
-#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
-#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
-#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
-#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
-#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
-#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
-#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
-#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
-#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
-#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
-#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
-#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
-#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
-#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
-#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
-#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
-#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
-#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
-#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
-#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
-#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
-#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
-#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
-#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
-#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
-//DB_RENDER_OVERRIDE2
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
-#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
-#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
-#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
-#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
-#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
-#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
-#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
-#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
-#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
-#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
-#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
-#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
-#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
-#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
-#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
-#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
-#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
-#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
-#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
-#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
-#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
-#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
-#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
-#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
-//DB_HTILE_DATA_BASE
-#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
-#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_HTILE_DATA_BASE_HI
-#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_DEPTH_SIZE
-#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0
-#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10
-#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL
-#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L
-//DB_DEPTH_BOUNDS_MIN
-#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
-#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
-//DB_DEPTH_BOUNDS_MAX
-#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
-#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
-//DB_STENCIL_CLEAR
-#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
-#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
-//DB_DEPTH_CLEAR
-#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
-#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
-//PA_SC_SCREEN_SCISSOR_TL
-#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_SCISSOR_BR
-#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
-//DB_Z_INFO
-#define DB_Z_INFO__FORMAT__SHIFT 0x0
-#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
-#define DB_Z_INFO__SW_MODE__SHIFT 0x4
-#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
-#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd
-#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf
-#define DB_Z_INFO__MAXMIP__SHIFT 0x10
-#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
-#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
-#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
-#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
-#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
-#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
-#define DB_Z_INFO__FORMAT_MASK 0x00000003L
-#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
-#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
-#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
-#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
-#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L
-#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
-#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
-#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
-#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
-#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
-#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
-#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
-//DB_STENCIL_INFO
-#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
-#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
-#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
-#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd
-#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf
-#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
-#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
-#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
-#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
-#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
-#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
-#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
-#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L
-#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
-#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
-#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
-//DB_Z_READ_BASE
-#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
-#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_Z_READ_BASE_HI
-#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_STENCIL_READ_BASE
-#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
-#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_STENCIL_READ_BASE_HI
-#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_Z_WRITE_BASE
-#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
-#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_Z_WRITE_BASE_HI
-#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_STENCIL_WRITE_BASE
-#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
-#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_STENCIL_WRITE_BASE_HI
-#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_DFSM_CONTROL
-#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
-#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
-#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
-#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
-#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
-#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
-//DB_RENDER_FILTER
-#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0
-#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL
-//DB_Z_INFO2
-#define DB_Z_INFO2__EPITCH__SHIFT 0x0
-#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
-//DB_STENCIL_INFO2
-#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0
-#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL
-//TA_BC_BASE_ADDR
-#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
-#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
-//TA_BC_BASE_ADDR_HI
-#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
-#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_0
-#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_1
-#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_2
-#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_3
-#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_2
-#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//COHER_DEST_BASE_3
-#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//PA_SC_WINDOW_OFFSET
-#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
-#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
-#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
-#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
-//PA_SC_WINDOW_SCISSOR_TL
-#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_WINDOW_SCISSOR_BR
-#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_RULE
-#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
-#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
-//PA_SC_CLIPRECT_0_TL
-#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_0_BR
-#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_1_TL
-#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_1_BR
-#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_2_TL
-#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_2_BR
-#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_3_TL
-#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_3_BR
-#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_EDGERULE
-#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
-#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
-#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
-#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
-#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
-#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
-#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
-#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
-#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
-#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
-#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
-#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
-#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
-#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
-//PA_SU_HARDWARE_SCREEN_OFFSET
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
-//CB_TARGET_MASK
-#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
-#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
-#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
-#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
-#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
-#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
-#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
-#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
-#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
-#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
-#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
-#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
-#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
-#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
-#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
-#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
-//CB_SHADER_MASK
-#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
-#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
-#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
-#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
-#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
-#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
-#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
-#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
-#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
-#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
-#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
-#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
-#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
-#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
-#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
-#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
-//PA_SC_GENERIC_SCISSOR_TL
-#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_GENERIC_SCISSOR_BR
-#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
-//COHER_DEST_BASE_0
-#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//COHER_DEST_BASE_1
-#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_SCISSOR_0_TL
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_0_BR
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_1_TL
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_1_BR
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_2_TL
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_2_BR
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_3_TL
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_3_BR
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_4_TL
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_4_BR
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_5_TL
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_5_BR
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_6_TL
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_6_BR
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_7_TL
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_7_BR
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_8_TL
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_8_BR
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_9_TL
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_9_BR
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_10_TL
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_10_BR
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_11_TL
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_11_BR
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_12_TL
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_12_BR
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_13_TL
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_13_BR
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_14_TL
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_14_BR
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_15_TL
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_15_BR
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_ZMIN_0
-#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_0
-#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_1
-#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_1
-#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_2
-#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_2
-#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_3
-#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_3
-#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_4
-#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_4
-#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_5
-#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_5
-#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_6
-#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_6
-#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_7
-#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_7
-#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_8
-#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_8
-#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_9
-#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_9
-#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_10
-#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_10
-#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_11
-#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_11
-#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_12
-#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_12
-#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_13
-#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_13
-#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_14
-#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_14
-#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_15
-#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_15
-#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_RASTER_CONFIG
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
-#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
-#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
-#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
-#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
-#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
-#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
-#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
-#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
-#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
-#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
-#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
-#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
-#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
-#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
-#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
-#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
-#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
-#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
-#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
-#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
-#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
-#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
-#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
-#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
-#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L
-#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L
-//PA_SC_RASTER_CONFIG_1
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L
-//PA_SC_SCREEN_EXTENT_CONTROL
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
-//PA_SC_TILE_STEERING_OVERRIDE
-#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
-#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8
-#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
-#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L
-//CP_PERFMON_CNTX_CNTL
-#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
-#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
-//CP_PIPEID
-#define CP_PIPEID__PIPE_ID__SHIFT 0x0
-#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
-//CP_RINGID
-#define CP_RINGID__RINGID__SHIFT 0x0
-#define CP_RINGID__RINGID_MASK 0x00000003L
-//CP_VMID
-#define CP_VMID__VMID__SHIFT 0x0
-#define CP_VMID__VMID_MASK 0x0000000FL
-//PA_SC_RIGHT_VERT_GRID
-#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
-#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
-#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
-#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
-//PA_SC_LEFT_VERT_GRID
-#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
-#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
-#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
-#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
-#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
-#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
-#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
-#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
-//PA_SC_HORIZ_GRID
-#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
-#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
-#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
-#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
-#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
-#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
-#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
-#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
-//PA_SC_FOV_WINDOW_LR
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL
-#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L
-#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L
-//PA_SC_FOV_WINDOW_TB
-#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0
-#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8
-#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL
-#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L
-//VGT_MULTI_PRIM_IB_RESET_INDX
-#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
-#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
-//CB_BLEND_RED
-#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
-#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
-//CB_BLEND_GREEN
-#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
-#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
-//CB_BLEND_BLUE
-#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
-#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
-//CB_BLEND_ALPHA
-#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
-#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
-//CB_DCC_CONTROL
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
-//DB_STENCIL_CONTROL
-#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
-#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
-#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
-#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
-#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
-#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
-#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
-#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
-#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
-#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
-#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
-#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
-//DB_STENCILREFMASK
-#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
-#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
-#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
-#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
-#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
-#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
-#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
-#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
-//DB_STENCILREFMASK_BF
-#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
-#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
-#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
-#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
-#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
-#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
-#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
-#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
-//PA_CL_VPORT_XSCALE
-#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET
-#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE
-#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET
-#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE
-#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET
-#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_1
-#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_1
-#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_1
-#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_1
-#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_1
-#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_1
-#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_2
-#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_2
-#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_2
-#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_2
-#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_2
-#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_2
-#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_3
-#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_3
-#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_3
-#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_3
-#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_3
-#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_3
-#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_4
-#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_4
-#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_4
-#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_4
-#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_4
-#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_4
-#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_5
-#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_5
-#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_5
-#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_5
-#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_5
-#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_5
-#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_6
-#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_6
-#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_6
-#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_6
-#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_6
-#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_6
-#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_7
-#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_7
-#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_7
-#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_7
-#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_7
-#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_7
-#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_8
-#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_8
-#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_8
-#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_8
-#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_8
-#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_8
-#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_9
-#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_9
-#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_9
-#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_9
-#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_9
-#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_9
-#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_10
-#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_10
-#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_10
-#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_10
-#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_10
-#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_10
-#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_11
-#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_11
-#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_11
-#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_11
-#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_11
-#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_11
-#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_12
-#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_12
-#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_12
-#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_12
-#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_12
-#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_12
-#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_13
-#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_13
-#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_13
-#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_13
-#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_13
-#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_13
-#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_14
-#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_14
-#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_14
-#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_14
-#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_14
-#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_14
-#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_15
-#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_15
-#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_15
-#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_15
-#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_15
-#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_15
-#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_X
-#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_Y
-#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_Z
-#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_W
-#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_X
-#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_Y
-#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_Z
-#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_W
-#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_X
-#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_Y
-#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_Z
-#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_W
-#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_X
-#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_Y
-#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_Z
-#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_W
-#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_X
-#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_Y
-#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_Z
-#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_W
-#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_X
-#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_Y
-#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_Z
-#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_W
-#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//SPI_PS_INPUT_CNTL_0
-#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_1
-#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_2
-#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_3
-#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_4
-#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_5
-#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_6
-#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_7
-#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_8
-#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_9
-#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_10
-#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_11
-#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_12
-#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_13
-#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_14
-#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_15
-#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_16
-#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_17
-#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_18
-#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_19
-#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_20
-#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_21
-#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_22
-#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_23
-#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_24
-#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_25
-#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_26
-#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_27
-#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_28
-#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_29
-#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_30
-#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_31
-#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
-//SPI_VS_OUT_CONFIG
-#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
-#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
-#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
-#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
-//SPI_PS_INPUT_ENA
-#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
-#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
-#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
-#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
-#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
-#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
-#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
-#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
-#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
-#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
-#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
-#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
-#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
-#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
-#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
-#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
-#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
-#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
-#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
-#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
-#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
-#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
-#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
-#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
-#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
-#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
-#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
-#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
-#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
-#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
-#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
-#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
-//SPI_PS_INPUT_ADDR
-#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
-#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
-#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
-#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
-#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
-#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
-#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
-#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
-#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
-#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
-#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
-#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
-#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
-#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
-#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
-#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
-#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
-#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
-#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
-#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
-#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
-#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
-#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
-#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
-#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
-#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
-#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
-#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
-//SPI_INTERP_CONTROL_0
-#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
-#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
-//SPI_PS_IN_CONTROL
-#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
-#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
-#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
-#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
-#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
-#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
-#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
-#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
-#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
-#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
-//SPI_BARYC_CNTL
-#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
-#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
-#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
-#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
-#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
-#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
-#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
-#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
-#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
-#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
-#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
-#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
-#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
-#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
-//SPI_TMPRING_SIZE
-#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
-#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
-#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
-#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
-//SPI_SHADER_POS_FORMAT
-#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
-#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
-#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
-#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
-#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
-#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
-#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
-//SPI_SHADER_Z_FORMAT
-#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
-//SPI_SHADER_COL_FORMAT
-#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
-#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
-#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
-#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
-#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
-#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
-#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
-#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
-#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
-#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
-#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
-#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
-#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
-#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
-#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
-//SX_PS_DOWNCONVERT
-#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
-#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
-#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
-#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
-#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
-#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
-#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
-#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
-#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
-#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
-#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
-#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
-#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
-#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
-#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
-#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
-//SX_BLEND_OPT_EPSILON
-#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
-#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
-#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
-#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
-#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
-#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
-#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
-#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
-#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
-#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
-#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
-#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
-#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
-#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
-#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
-#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
-//SX_BLEND_OPT_CONTROL
-#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
-#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
-#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
-#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
-#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
-#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
-#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
-#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
-#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
-#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
-#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
-#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
-#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
-#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
-#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
-#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
-#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
-#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
-#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
-#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
-#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
-#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
-#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
-#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
-#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
-#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
-#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
-#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
-#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
-#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
-#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
-#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
-#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
-#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
-//SX_MRT0_BLEND_OPT
-#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT1_BLEND_OPT
-#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT2_BLEND_OPT
-#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT3_BLEND_OPT
-#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT4_BLEND_OPT
-#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT5_BLEND_OPT
-#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT6_BLEND_OPT
-#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT7_BLEND_OPT
-#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//CB_BLEND0_CONTROL
-#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND1_CONTROL
-#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND2_CONTROL
-#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND3_CONTROL
-#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND4_CONTROL
-#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND5_CONTROL
-#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND6_CONTROL
-#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND7_CONTROL
-#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_MRT0_EPITCH
-#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT1_EPITCH
-#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT2_EPITCH
-#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT3_EPITCH
-#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT4_EPITCH
-#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT5_EPITCH
-#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT6_EPITCH
-#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT7_EPITCH
-#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CS_COPY_STATE
-#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-//GFX_COPY_STATE
-#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-//PA_CL_POINT_X_RAD
-#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_POINT_Y_RAD
-#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_POINT_SIZE
-#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_POINT_CULL_RAD
-#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
-//VGT_DMA_BASE_HI
-#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
-#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
-//VGT_DMA_BASE
-#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
-#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
-//VGT_DRAW_INITIATOR
-#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
-#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
-#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
-#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
-#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
-#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
-#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
-#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
-#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
-#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
-#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
-#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
-#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
-#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
-#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
-#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
-//VGT_IMMED_DATA
-#define VGT_IMMED_DATA__DATA__SHIFT 0x0
-#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
-//VGT_EVENT_ADDRESS_REG
-#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
-#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
-//DB_DEPTH_CONTROL
-#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
-#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
-#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
-#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
-#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
-#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
-#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
-#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
-#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
-#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
-#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
-#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
-#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
-#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
-#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
-#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
-#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
-#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
-#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
-#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
-//DB_EQAA
-#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
-#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
-#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
-#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
-#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
-#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
-#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
-#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
-#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
-#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
-#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
-#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
-#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
-#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
-#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
-#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
-#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
-#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
-#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
-#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
-#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
-#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
-#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
-#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
-//CB_COLOR_CONTROL
-#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
-#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
-#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
-#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
-#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
-#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
-#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
-#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
-//DB_SHADER_CONTROL
-#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
-#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
-#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
-#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
-#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
-#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
-#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
-#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
-#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
-#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
-#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
-#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
-#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
-#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
-#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
-#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
-#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
-#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
-#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
-#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
-#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
-#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
-#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
-#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
-#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
-#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
-#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
-#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
-#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
-#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
-#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
-#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
-//PA_CL_CLIP_CNTL
-#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
-#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
-#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
-#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
-#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
-#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
-#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
-#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
-#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
-#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
-#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
-#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
-#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
-#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
-#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
-#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
-#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
-#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
-#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
-#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
-#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
-#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
-#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
-#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
-#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
-#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
-#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
-#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
-#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
-#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
-#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
-#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
-#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
-#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
-#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
-#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
-#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
-#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
-//PA_SU_SC_MODE_CNTL
-#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
-#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
-#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
-#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
-#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
-#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
-#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
-#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
-#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
-#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
-#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
-#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
-#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
-#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
-#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
-#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
-#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
-#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
-#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
-#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
-#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
-#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
-#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
-#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
-//PA_CL_VTE_CNTL
-#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
-#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
-#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
-#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
-#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
-#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
-#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
-#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
-#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
-#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
-#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
-#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
-#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
-#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
-#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
-#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
-#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
-#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
-#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
-#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
-//PA_CL_VS_OUT_CNTL
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
-#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
-#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
-#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
-#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
-#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
-#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
-#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
-#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L
-//PA_CL_NANINF_CNTL
-#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
-#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
-#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
-#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
-#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
-#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
-#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
-#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
-#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
-#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
-#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
-#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
-#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
-#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
-#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
-#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
-#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
-#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
-#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
-#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
-#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
-#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
-#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
-#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
-#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
-#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
-#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
-#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
-#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
-#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
-#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
-#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
-//PA_SU_LINE_STIPPLE_CNTL
-#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
-#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
-#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
-#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
-#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
-#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
-#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
-//PA_SU_LINE_STIPPLE_SCALE
-#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
-//PA_SU_PRIM_FILTER_CNTL
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
-#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
-#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
-#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
-#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
-#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
-#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
-#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
-#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
-#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
-#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
-#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
-#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
-#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
-#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
-//PA_SU_SMALL_PRIM_FILTER_CNTL
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L
-//PA_CL_OBJPRIM_ID_CNTL
-#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
-#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
-#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2
-#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
-#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
-#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L
-//PA_CL_NGG_CNTL
-#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
-#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
-#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
-#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
-//PA_SU_OVER_RASTERIZATION_CNTL
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
-#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
-#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
-//PA_SU_POINT_SIZE
-#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
-#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
-#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
-#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
-//PA_SU_POINT_MINMAX
-#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
-#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
-#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
-#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
-//PA_SU_LINE_CNTL
-#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
-#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
-//PA_SC_LINE_STIPPLE
-#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
-#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
-#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
-#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
-#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
-#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
-#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
-#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
-//VGT_OUTPUT_PATH_CNTL
-#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
-#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
-//VGT_HOS_CNTL
-#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
-#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
-//VGT_HOS_MAX_TESS_LEVEL
-#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
-#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
-//VGT_HOS_MIN_TESS_LEVEL
-#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
-#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
-//VGT_HOS_REUSE_DEPTH
-#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
-#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
-//VGT_GROUP_PRIM_TYPE
-#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
-#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
-#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
-#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
-#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
-#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
-#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
-//VGT_GROUP_FIRST_DECR
-#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
-#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
-//VGT_GROUP_DECR
-#define VGT_GROUP_DECR__DECR__SHIFT 0x0
-#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
-//VGT_GROUP_VECT_0_CNTL
-#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
-#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
-#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
-#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
-#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
-#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
-#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
-#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
-#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
-#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
-#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
-#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
-//VGT_GROUP_VECT_1_CNTL
-#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
-#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
-#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
-#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
-#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
-#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
-#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
-#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
-#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
-#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
-#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
-#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
-//VGT_GROUP_VECT_0_FMT_CNTL
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
-//VGT_GROUP_VECT_1_FMT_CNTL
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
-//VGT_GS_MODE
-#define VGT_GS_MODE__MODE__SHIFT 0x0
-#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
-#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
-#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
-#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
-#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
-#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
-#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
-#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
-#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
-#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
-#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
-#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
-#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
-#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
-#define VGT_GS_MODE__MODE_MASK 0x00000007L
-#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
-#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
-#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
-#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
-#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
-#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
-#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L
-#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L
-#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L
-#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
-#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
-#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
-#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
-#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
-//VGT_GS_ONCHIP_CNTL
-#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
-#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
-#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
-#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
-#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
-#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
-//PA_SC_MODE_CNTL_0
-#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
-#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
-#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
-#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
-#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
-#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
-#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
-#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
-#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
-#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
-#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
-#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
-#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
-#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
-//PA_SC_MODE_CNTL_1
-#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
-#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
-#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
-#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
-#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
-#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
-#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
-#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
-#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
-#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
-#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
-#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
-#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
-#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
-#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
-#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
-#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
-#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
-#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
-#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
-//VGT_ENHANCE
-#define VGT_ENHANCE__MISC__SHIFT 0x0
-#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
-//VGT_GS_PER_ES
-#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
-#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
-//VGT_ES_PER_GS
-#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
-#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
-//VGT_GS_PER_VS
-#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
-#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
-//VGT_GSVS_RING_OFFSET_1
-#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
-//VGT_GSVS_RING_OFFSET_2
-#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
-//VGT_GSVS_RING_OFFSET_3
-#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
-//VGT_GS_OUT_PRIM_TYPE
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
-#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
-#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
-//IA_ENHANCE
-#define IA_ENHANCE__MISC__SHIFT 0x0
-#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
-//VGT_DMA_SIZE
-#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
-#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
-//VGT_DMA_MAX_SIZE
-#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
-#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
-//VGT_DMA_INDEX_TYPE
-#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
-#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
-#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
-#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
-#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
-#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
-#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
-#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
-#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
-#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L
-#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
-#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
-#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
-//WD_ENHANCE
-#define WD_ENHANCE__MISC__SHIFT 0x0
-#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
-//VGT_PRIMITIVEID_EN
-#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
-#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
-#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
-#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
-#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
-#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
-//VGT_DMA_NUM_INSTANCES
-#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
-#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
-//VGT_PRIMITIVEID_RESET
-#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
-#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
-//VGT_EVENT_INITIATOR
-#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
-#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
-#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
-#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
-#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
-#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
-//VGT_GS_MAX_PRIMS_PER_SUBGROUP
-#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0
-#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL
-//VGT_DRAW_PAYLOAD_CNTL
-#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
-#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
-#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2
-#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3
-#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
-#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
-#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
-#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
-//VGT_INDEX_PAYLOAD_CNTL
-#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0
-#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L
-//VGT_INSTANCE_STEP_RATE_0
-#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
-#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
-//VGT_INSTANCE_STEP_RATE_1
-#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
-#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
-//VGT_ESGS_RING_ITEMSIZE
-#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GSVS_RING_ITEMSIZE
-#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
-//VGT_REUSE_OFF
-#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
-#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
-//VGT_VTX_CNT_EN
-#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
-#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
-//DB_HTILE_SURFACE
-#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
-#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
-#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
-#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
-#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
-#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
-#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
-#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13
-#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
-#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
-#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
-#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L
-#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L
-#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
-#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
-#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L
-//DB_SRESULTS_COMPARE_STATE0
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
-#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
-#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
-//DB_SRESULTS_COMPARE_STATE1
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
-#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
-#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
-//DB_PRELOAD_CONTROL
-#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
-#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
-#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
-#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
-#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
-#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
-#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
-#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
-//VGT_STRMOUT_BUFFER_SIZE_0
-#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_0
-#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_0
-#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_SIZE_1
-#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_1
-#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_1
-#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_SIZE_2
-#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_2
-#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_2
-#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_SIZE_3
-#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_3
-#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_3
-#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
-#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
-#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
-#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
-//VGT_GS_MAX_VERT_OUT
-#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
-#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
-//VGT_TESS_DISTRIBUTION
-#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
-#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
-#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
-#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
-#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
-#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
-#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
-#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
-#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
-#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
-//VGT_SHADER_STAGES_EN
-#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
-#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
-#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
-#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
-#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
-#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
-#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
-#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
-#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
-#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
-#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
-#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
-#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
-#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
-#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
-#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
-#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
-#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
-#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
-#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
-#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
-#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L
-//VGT_LS_HS_CONFIG
-#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
-#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
-#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
-#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
-#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
-//VGT_GS_VERT_ITEMSIZE
-#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GS_VERT_ITEMSIZE_1
-#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GS_VERT_ITEMSIZE_2
-#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GS_VERT_ITEMSIZE_3
-#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
-//VGT_TF_PARAM
-#define VGT_TF_PARAM__TYPE__SHIFT 0x0
-#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
-#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
-#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
-#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
-#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
-#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
-#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
-#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
-#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
-#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
-#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
-#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
-#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
-#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L
-#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
-//DB_ALPHA_TO_MASK
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
-#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
-#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
-//VGT_DISPATCH_DRAW_INDEX
-#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
-#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_DB_FMT_CNTL
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
-//PA_SU_POLY_OFFSET_CLAMP
-#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_FRONT_SCALE
-#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_FRONT_OFFSET
-#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_BACK_SCALE
-#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_BACK_OFFSET
-#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
-//VGT_GS_INSTANCE_CNT
-#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
-#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
-#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
-#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
-//VGT_STRMOUT_CONFIG
-#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
-#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
-#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
-#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
-#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
-#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
-#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
-#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
-#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
-#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
-#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
-#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
-#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
-//VGT_STRMOUT_BUFFER_CONFIG
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
-//VGT_DMA_EVENT_INITIATOR
-#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
-#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
-#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
-#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
-#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
-#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
-//PA_SC_CENTROID_PRIORITY_0
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
-//PA_SC_CENTROID_PRIORITY_1
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
-//PA_SC_LINE_CNTL
-#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
-#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
-#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
-#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
-#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
-#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
-#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
-#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
-//PA_SC_AA_CONFIG
-#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
-#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
-#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
-#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
-#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
-#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
-#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
-#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
-#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
-#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
-#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
-#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
-//PA_SU_VTX_CNTL
-#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
-#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
-#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
-#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
-#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
-#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
-//PA_CL_GB_VERT_CLIP_ADJ
-#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_GB_VERT_DISC_ADJ
-#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_GB_HORZ_CLIP_ADJ
-#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_GB_HORZ_DISC_ADJ
-#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_MASK_X0Y0_X1Y0
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
-//PA_SC_AA_MASK_X0Y1_X1Y1
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
-//PA_SC_SHADER_CONTROL
-#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
-#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
-#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
-#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
-#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
-#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
-//PA_SC_BINNER_CNTL_0
-#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
-#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
-#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
-#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
-#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
-#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
-#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
-#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
-#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
-#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
-#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
-#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
-//PA_SC_BINNER_CNTL_1
-#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
-#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
-#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
-#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
-//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
-//PA_SC_NGG_MODE_CNTL
-#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
-#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
-//VGT_VERTEX_REUSE_BLOCK_CNTL
-#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
-#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
-//VGT_OUT_DEALLOC_CNTL
-#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
-#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
-//CB_COLOR0_BASE
-#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_BASE_EXT
-#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR0_ATTRIB2
-#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR0_VIEW
-#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR0_INFO
-#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR0_ATTRIB
-#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR0_DCC_CONTROL
-#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR0_CMASK
-#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_CMASK_BASE_EXT
-#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR0_FMASK
-#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_FMASK_BASE_EXT
-#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR0_CLEAR_WORD0
-#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR0_CLEAR_WORD1
-#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR0_DCC_BASE
-#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_DCC_BASE_EXT
-#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_BASE
-#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_BASE_EXT
-#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_ATTRIB2
-#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR1_VIEW
-#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR1_INFO
-#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR1_ATTRIB
-#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR1_DCC_CONTROL
-#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR1_CMASK
-#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_CMASK_BASE_EXT
-#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_FMASK
-#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_FMASK_BASE_EXT
-#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_CLEAR_WORD0
-#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR1_CLEAR_WORD1
-#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR1_DCC_BASE
-#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_DCC_BASE_EXT
-#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_BASE
-#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_BASE_EXT
-#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_ATTRIB2
-#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR2_VIEW
-#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR2_INFO
-#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR2_ATTRIB
-#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR2_DCC_CONTROL
-#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR2_CMASK
-#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_CMASK_BASE_EXT
-#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_FMASK
-#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_FMASK_BASE_EXT
-#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_CLEAR_WORD0
-#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR2_CLEAR_WORD1
-#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR2_DCC_BASE
-#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_DCC_BASE_EXT
-#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_BASE
-#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_BASE_EXT
-#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_ATTRIB2
-#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR3_VIEW
-#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR3_INFO
-#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR3_ATTRIB
-#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR3_DCC_CONTROL
-#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR3_CMASK
-#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_CMASK_BASE_EXT
-#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_FMASK
-#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_FMASK_BASE_EXT
-#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_CLEAR_WORD0
-#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR3_CLEAR_WORD1
-#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR3_DCC_BASE
-#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_DCC_BASE_EXT
-#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_BASE
-#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_BASE_EXT
-#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_ATTRIB2
-#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR4_VIEW
-#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR4_INFO
-#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR4_ATTRIB
-#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR4_DCC_CONTROL
-#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR4_CMASK
-#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_CMASK_BASE_EXT
-#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_FMASK
-#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_FMASK_BASE_EXT
-#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_CLEAR_WORD0
-#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR4_CLEAR_WORD1
-#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR4_DCC_BASE
-#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_DCC_BASE_EXT
-#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_BASE
-#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_BASE_EXT
-#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_ATTRIB2
-#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR5_VIEW
-#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR5_INFO
-#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR5_ATTRIB
-#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR5_DCC_CONTROL
-#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR5_CMASK
-#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_CMASK_BASE_EXT
-#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_FMASK
-#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_FMASK_BASE_EXT
-#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_CLEAR_WORD0
-#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR5_CLEAR_WORD1
-#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR5_DCC_BASE
-#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_DCC_BASE_EXT
-#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_BASE
-#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_BASE_EXT
-#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_ATTRIB2
-#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR6_VIEW
-#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR6_INFO
-#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR6_ATTRIB
-#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR6_DCC_CONTROL
-#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR6_CMASK
-#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_CMASK_BASE_EXT
-#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_FMASK
-#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_FMASK_BASE_EXT
-#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_CLEAR_WORD0
-#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR6_CLEAR_WORD1
-#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR6_DCC_BASE
-#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_DCC_BASE_EXT
-#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_BASE
-#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_BASE_EXT
-#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_ATTRIB2
-#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR7_VIEW
-#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR7_INFO
-#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR7_ATTRIB
-#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR7_DCC_CONTROL
-#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR7_CMASK
-#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_CMASK_BASE_EXT
-#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_FMASK
-#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_FMASK_BASE_EXT
-#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_CLEAR_WORD0
-#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR7_CLEAR_WORD1
-#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR7_DCC_BASE
-#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_DCC_BASE_EXT
-#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-
-
-// addressBlock: gc_gfxudec
-//CP_EOP_DONE_ADDR_LO
-#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
-#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
-//CP_EOP_DONE_ADDR_HI
-#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_EOP_DONE_DATA_LO
-#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
-#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
-//CP_EOP_DONE_DATA_HI
-#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
-#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
-//CP_EOP_LAST_FENCE_LO
-#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
-#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
-//CP_EOP_LAST_FENCE_HI
-#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
-#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
-//CP_STREAM_OUT_ADDR_LO
-#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
-#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_STREAM_OUT_ADDR_HI
-#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
-#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT0_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT0_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT0_LO
-#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT0_HI
-#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT1_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT1_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT1_LO
-#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT1_HI
-#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT2_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT2_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT2_LO
-#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT2_HI
-#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT3_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT3_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT3_LO
-#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT3_HI
-#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
-//CP_PIPE_STATS_ADDR_LO
-#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
-#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_PIPE_STATS_ADDR_HI
-#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
-#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
-//CP_VGT_IAVERT_COUNT_LO
-#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
-#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_IAVERT_COUNT_HI
-#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
-#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_IAPRIM_COUNT_LO
-#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
-#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_IAPRIM_COUNT_HI
-#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
-#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_GSPRIM_COUNT_LO
-#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
-#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_GSPRIM_COUNT_HI
-#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
-#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_VSINVOC_COUNT_LO
-#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_VSINVOC_COUNT_HI
-#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_GSINVOC_COUNT_LO
-#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_GSINVOC_COUNT_HI
-#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_HSINVOC_COUNT_LO
-#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_HSINVOC_COUNT_HI
-#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_DSINVOC_COUNT_LO
-#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_DSINVOC_COUNT_HI
-#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_PA_CINVOC_COUNT_LO
-#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
-#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_PA_CINVOC_COUNT_HI
-#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
-#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_PA_CPRIM_COUNT_LO
-#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
-#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_PA_CPRIM_COUNT_HI
-#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
-#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT0_LO
-#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT0_HI
-#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT1_LO
-#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT1_HI
-#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_VGT_CSINVOC_COUNT_LO
-#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_CSINVOC_COUNT_HI
-#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_PIPE_STATS_CONTROL
-#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
-#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L
-//CP_STREAM_OUT_CONTROL
-#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
-#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L
-//CP_STRMOUT_CNTL
-#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
-#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
-//SCRATCH_REG0
-#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
-//SCRATCH_REG1
-#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
-//SCRATCH_REG2
-#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
-//SCRATCH_REG3
-#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
-//SCRATCH_REG4
-#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
-//SCRATCH_REG5
-#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
-//SCRATCH_REG6
-#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
-//SCRATCH_REG7
-#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
-//CP_APPEND_DATA_HI
-#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
-#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_CS_FENCE_HI
-#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_PS_FENCE_HI
-#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
-//SCRATCH_UMSK
-#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
-#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
-#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
-#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
-//SCRATCH_ADDR
-#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
-#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
-//CP_PFP_ATOMIC_PREOP_LO
-#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_PFP_ATOMIC_PREOP_HI
-#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC0_PREOP_LO
-#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC0_PREOP_HI
-#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC1_PREOP_LO
-#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC1_PREOP_HI
-#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_APPEND_ADDR_LO
-#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
-#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_APPEND_ADDR_HI
-#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
-#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
-#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
-#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
-#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
-#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
-#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L
-#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
-//CP_APPEND_DATA_LO
-#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
-#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_CS_FENCE_LO
-#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_PS_FENCE_LO
-#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
-//CP_ATOMIC_PREOP_LO
-#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ME_ATOMIC_PREOP_LO
-#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ATOMIC_PREOP_HI
-#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_ATOMIC_PREOP_HI
-#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC0_PREOP_LO
-#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC0_PREOP_LO
-#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC0_PREOP_HI
-#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC0_PREOP_HI
-#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC1_PREOP_LO
-#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC1_PREOP_LO
-#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC1_PREOP_HI
-#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC1_PREOP_HI
-#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_MC_WADDR_LO
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
-//CP_ME_MC_WADDR_HI
-#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
-#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
-#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
-#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L
-//CP_ME_MC_WDATA_LO
-#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
-#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
-//CP_ME_MC_WDATA_HI
-#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
-#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
-//CP_ME_MC_RADDR_LO
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
-//CP_ME_MC_RADDR_HI
-#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
-#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
-#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
-#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L
-//CP_SEM_WAIT_TIMER
-#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
-#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
-//CP_SIG_SEM_ADDR_LO
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
-//CP_SIG_SEM_ADDR_HI
-#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
-#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
-#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
-#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
-#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
-#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
-#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
-#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
-#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
-//CP_WAIT_REG_MEM_TIMEOUT
-#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
-#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
-//CP_WAIT_SEM_ADDR_LO
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
-//CP_WAIT_SEM_ADDR_HI
-#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
-#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
-#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
-#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
-#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
-#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
-#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
-#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
-#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
-#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
-//CP_DMA_PFP_CONTROL
-#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
-#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
-#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
-#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
-#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
-#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
-#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
-#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
-#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
-#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
-//CP_DMA_ME_CONTROL
-#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
-#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
-#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
-#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
-#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
-#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
-#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
-#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
-#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
-#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
-//CP_COHER_BASE_HI
-#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
-#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
-//CP_COHER_START_DELAY
-#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
-#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
-//CP_COHER_CNTL
-#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
-#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
-#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
-#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
-#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
-#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
-#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
-#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
-#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
-#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
-#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
-#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
-#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
-#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
-#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
-#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
-#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
-#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
-#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
-#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
-#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
-#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
-#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
-#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
-#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
-#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
-//CP_COHER_SIZE
-#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
-#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
-//CP_COHER_BASE
-#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
-#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
-//CP_COHER_STATUS
-#define CP_COHER_STATUS__MEID__SHIFT 0x18
-#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
-#define CP_COHER_STATUS__MEID_MASK 0x03000000L
-#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
-//CP_DMA_ME_SRC_ADDR
-#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
-#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_ME_SRC_ADDR_HI
-#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
-#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_ME_DST_ADDR
-#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
-#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_ME_DST_ADDR_HI
-#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
-#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_ME_COMMAND
-#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
-#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
-#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
-#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
-#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
-#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
-#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
-#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
-#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
-#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
-#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
-#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
-#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
-#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
-//CP_DMA_PFP_SRC_ADDR
-#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
-#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_PFP_SRC_ADDR_HI
-#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
-#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_PFP_DST_ADDR
-#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
-#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_PFP_DST_ADDR_HI
-#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
-#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_PFP_COMMAND
-#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
-#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
-#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
-#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
-#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
-#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
-#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
-#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
-#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
-#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
-#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
-#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
-#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
-#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
-//CP_DMA_CNTL
-#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
-#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
-#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
-#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
-#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
-#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
-#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
-#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
-#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L
-#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
-#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
-#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
-//CP_DMA_READ_TAGS
-#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
-//CP_COHER_SIZE_HI
-#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
-#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
-//CP_PFP_IB_CONTROL
-#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
-#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
-//CP_PFP_LOAD_CONTROL
-#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
-#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
-#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
-#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
-#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
-#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
-#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
-#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
-//CP_SCRATCH_INDEX
-#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
-//CP_SCRATCH_DATA
-#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
-//CP_RB_OFFSET
-#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
-#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
-//CP_IB1_OFFSET
-#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
-#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
-//CP_IB2_OFFSET
-#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
-#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
-//CP_IB1_PREAMBLE_BEGIN
-#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
-#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL
-//CP_IB1_PREAMBLE_END
-#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
-#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL
-//CP_IB2_PREAMBLE_BEGIN
-#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
-#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
-//CP_IB2_PREAMBLE_END
-#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
-#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
-//CP_CE_IB1_OFFSET
-#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
-#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
-//CP_CE_IB2_OFFSET
-#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
-#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
-//CP_CE_COUNTER
-#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_CE_RB_OFFSET
-#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
-#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
-//CP_CE_INIT_CMD_BUFSZ
-#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
-#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
-//CP_CE_IB1_CMD_BUFSZ
-#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
-#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_CE_IB2_CMD_BUFSZ
-#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
-#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_IB1_CMD_BUFSZ
-#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
-#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_IB2_CMD_BUFSZ
-#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
-#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_ST_CMD_BUFSZ
-#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
-#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_CE_INIT_BASE_LO
-#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
-#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
-//CP_CE_INIT_BASE_HI
-#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
-#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
-//CP_CE_INIT_BUFSZ
-#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
-#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
-//CP_CE_IB1_BASE_LO
-#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
-#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
-//CP_CE_IB1_BASE_HI
-#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
-#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
-//CP_CE_IB1_BUFSZ
-#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
-#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
-//CP_CE_IB2_BASE_LO
-#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
-#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
-//CP_CE_IB2_BASE_HI
-#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
-#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
-//CP_CE_IB2_BUFSZ
-#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
-#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
-//CP_IB1_BASE_LO
-#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
-#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
-//CP_IB1_BASE_HI
-#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
-#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
-//CP_IB1_BUFSZ
-#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
-#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
-//CP_IB2_BASE_LO
-#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
-#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
-//CP_IB2_BASE_HI
-#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
-#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
-//CP_IB2_BUFSZ
-#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
-#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
-//CP_ST_BASE_LO
-#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
-#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
-//CP_ST_BASE_HI
-#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
-#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
-//CP_ST_BUFSZ
-#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
-#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
-//CP_EOP_DONE_EVENT_CNTL
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
-#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
-#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L
-#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L
-#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
-//CP_EOP_DONE_DATA_CNTL
-#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
-#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
-#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
-#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
-#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
-#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
-//CP_EOP_DONE_CNTX_ID
-#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
-#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
-//CP_PFP_COMPLETION_STATUS
-#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
-#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
-//CP_CE_COMPLETION_STATUS
-#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
-#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
-//CP_PRED_NOT_VISIBLE
-#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
-#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
-//CP_PFP_METADATA_BASE_ADDR
-#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_PFP_METADATA_BASE_ADDR_HI
-#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_CE_METADATA_BASE_ADDR
-#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_CE_METADATA_BASE_ADDR_HI
-#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_DRAW_INDX_INDR_ADDR
-#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_DRAW_INDX_INDR_ADDR_HI
-#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_DISPATCH_INDR_ADDR
-#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_DISPATCH_INDR_ADDR_HI
-#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_INDEX_BASE_ADDR
-#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_INDEX_BASE_ADDR_HI
-#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_INDEX_TYPE
-#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
-//CP_GDS_BKUP_ADDR
-#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_GDS_BKUP_ADDR_HI
-#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_SAMPLE_STATUS
-#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
-#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
-#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
-#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
-#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
-#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
-#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
-#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
-#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
-#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
-#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
-#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
-#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
-#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
-#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
-#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
-//CP_ME_COHER_CNTL
-#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
-#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
-#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
-#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
-#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
-#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
-#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
-#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
-#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
-#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
-#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
-#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
-#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
-#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
-#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
-#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
-#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
-#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
-#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
-#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
-#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
-#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
-#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
-#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
-#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
-#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
-//CP_ME_COHER_SIZE
-#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
-#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
-//CP_ME_COHER_SIZE_HI
-#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
-#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
-//CP_ME_COHER_BASE
-#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
-#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
-//CP_ME_COHER_BASE_HI
-#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
-#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
-//CP_ME_COHER_STATUS
-#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
-#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
-#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
-#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
-//RLC_GPM_PERF_COUNT_0
-#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
-#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
-#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
-#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
-#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
-#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
-#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
-#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
-#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
-#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L
-#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L
-#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
-#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
-#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
-#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
-//RLC_GPM_PERF_COUNT_1
-#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
-#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
-#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
-#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
-#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
-#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
-#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
-#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
-#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
-#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L
-#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L
-#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
-#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
-#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
-#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
-//GRBM_GFX_INDEX
-#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
-#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
-#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
-#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
-#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
-#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
-#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L
-#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
-#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
-#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
-#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
-//VGT_GSVS_RING_SIZE
-#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
-#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
-//VGT_PRIMITIVE_TYPE
-#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
-//VGT_INDEX_TYPE
-#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
-#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
-#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
-//VGT_MAX_VTX_INDX
-#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
-#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
-//VGT_MIN_VTX_INDX
-#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
-#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
-//VGT_INDX_OFFSET
-#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
-#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
-//VGT_MULTI_PRIM_IB_RESET_EN
-#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
-#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
-#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
-#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
-//VGT_NUM_INDICES
-#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
-#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
-//VGT_NUM_INSTANCES
-#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
-#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
-//VGT_TF_RING_SIZE
-#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
-#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
-//VGT_HS_OFFCHIP_PARAM
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
-//VGT_TF_MEMORY_BASE
-#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
-#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
-//VGT_TF_MEMORY_BASE_HI
-#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
-#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
-//WD_POS_BUF_BASE
-#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
-#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//WD_POS_BUF_BASE_HI
-#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
-#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
-//WD_CNTL_SB_BUF_BASE
-#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
-#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//WD_CNTL_SB_BUF_BASE_HI
-#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
-#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
-//WD_INDEX_BUF_BASE
-#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
-#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//WD_INDEX_BUF_BASE_HI
-#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
-#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
-//IA_MULTI_VGT_PARAM
-#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
-#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
-#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
-#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16
-#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17
-#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
-#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
-#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
-#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
-#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
-//VGT_OBJECT_ID
-#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0
-#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL
-//VGT_INSTANCE_BASE_ID
-#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
-#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
-//PA_SU_LINE_STIPPLE_VALUE
-#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
-//PA_SC_LINE_STIPPLE_STATE
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
-//PA_SC_SCREEN_EXTENT_MIN_0
-#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_EXTENT_MAX_0
-#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_EXTENT_MIN_1
-#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_EXTENT_MAX_1
-#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
-//PA_SC_P3D_TRAP_SCREEN_HV_EN
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
-//PA_SC_P3D_TRAP_SCREEN_H
-#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
-//PA_SC_P3D_TRAP_SCREEN_V
-#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
-//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
-#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
-//PA_SC_P3D_TRAP_SCREEN_COUNT
-#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
-//PA_SC_HP3D_TRAP_SCREEN_HV_EN
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
-//PA_SC_HP3D_TRAP_SCREEN_H
-#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
-//PA_SC_HP3D_TRAP_SCREEN_V
-#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
-//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
-#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
-//PA_SC_HP3D_TRAP_SCREEN_COUNT
-#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
-//PA_SC_TRAP_SCREEN_HV_EN
-#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
-#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
-//PA_SC_TRAP_SCREEN_H
-#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
-//PA_SC_TRAP_SCREEN_V
-#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
-//PA_SC_TRAP_SCREEN_OCCURRENCE
-#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
-//PA_SC_TRAP_SCREEN_COUNT
-#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
-//SQ_THREAD_TRACE_BASE
-#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
-#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_SIZE
-#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
-#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL
-//SQ_THREAD_TRACE_MASK
-#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
-#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
-#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
-#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
-#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
-#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
-#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
-#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL
-#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
-#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
-#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L
-#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
-#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
-#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
-//SQ_THREAD_TRACE_TOKEN_MASK
-#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
-#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
-//SQ_THREAD_TRACE_PERF_MASK
-#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
-#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_CTRL
-#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
-#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
-//SQ_THREAD_TRACE_MODE
-#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
-#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
-#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
-#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
-#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
-#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
-#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
-#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
-#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
-#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
-#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a
-#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
-#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
-#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
-#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
-#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
-#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
-#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L
-#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L
-#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
-#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
-#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L
-#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
-#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
-#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
-#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L
-#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
-#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
-#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
-#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
-//SQ_THREAD_TRACE_BASE2
-#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL
-//SQ_THREAD_TRACE_TOKEN_MASK2
-#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_WPTR
-#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
-#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
-#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL
-#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L
-//SQ_THREAD_TRACE_STATUS
-#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
-#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
-#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c
-#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
-#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
-#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
-#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL
-#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L
-#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L
-#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
-#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
-#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
-//SQ_THREAD_TRACE_HIWATER
-#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
-#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
-//SQ_THREAD_TRACE_CNTR
-#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
-#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_0
-#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_1
-#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_2
-#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_3
-#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
-//SQC_CACHES
-#define SQC_CACHES__TARGET_INST__SHIFT 0x0
-#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
-#define SQC_CACHES__INVALIDATE__SHIFT 0x2
-#define SQC_CACHES__WRITEBACK__SHIFT 0x3
-#define SQC_CACHES__VOL__SHIFT 0x4
-#define SQC_CACHES__COMPLETE__SHIFT 0x10
-#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
-#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
-#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
-#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
-#define SQC_CACHES__VOL_MASK 0x00000010L
-#define SQC_CACHES__COMPLETE_MASK 0x00010000L
-//SQC_WRITEBACK
-#define SQC_WRITEBACK__DWB__SHIFT 0x0
-#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
-#define SQC_WRITEBACK__DWB_MASK 0x00000001L
-#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
-//TA_CS_BC_BASE_ADDR
-#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
-#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
-//TA_CS_BC_BASE_ADDR_HI
-#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
-#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
-//TA_GRAD_ADJ_UCONFIG
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L
-#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L
-//DB_OCCLUSION_COUNT0_LOW
-#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT0_HI
-#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_OCCLUSION_COUNT1_LOW
-#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT1_HI
-#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_OCCLUSION_COUNT2_LOW
-#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT2_HI
-#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_OCCLUSION_COUNT3_LOW
-#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT3_HI
-#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_ZPASS_COUNT_LOW
-#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_ZPASS_COUNT_HI
-#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
-#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//GDS_RD_ADDR
-#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
-#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
-//GDS_RD_DATA
-#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
-#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
-//GDS_RD_BURST_ADDR
-#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
-#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
-//GDS_RD_BURST_COUNT
-#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
-#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
-//GDS_RD_BURST_DATA
-#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
-#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
-//GDS_WR_ADDR
-#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
-#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
-//GDS_WR_DATA
-#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
-#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
-//GDS_WR_BURST_ADDR
-#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
-#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
-//GDS_WR_BURST_DATA
-#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
-#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
-//GDS_WRITE_COMPLETE
-#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
-#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
-//GDS_ATOM_CNTL
-#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
-#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
-#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
-#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
-#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
-#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
-#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
-#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
-//GDS_ATOM_COMPLETE
-#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
-#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
-#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
-#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
-//GDS_ATOM_BASE
-#define GDS_ATOM_BASE__BASE__SHIFT 0x0
-#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
-#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
-#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
-//GDS_ATOM_SIZE
-#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
-#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
-#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
-#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
-//GDS_ATOM_OFFSET0
-#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
-#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
-#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
-//GDS_ATOM_OFFSET1
-#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
-#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
-#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
-//GDS_ATOM_DST
-#define GDS_ATOM_DST__DST__SHIFT 0x0
-#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
-//GDS_ATOM_OP
-#define GDS_ATOM_OP__OP__SHIFT 0x0
-#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OP__OP_MASK 0x000000FFL
-#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
-//GDS_ATOM_SRC0
-#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_SRC0_U
-#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_SRC1
-#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_SRC1_U
-#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ0
-#define GDS_ATOM_READ0__DATA__SHIFT 0x0
-#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ0_U
-#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
-#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ1
-#define GDS_ATOM_READ1__DATA__SHIFT 0x0
-#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ1_U
-#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
-#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
-//GDS_GWS_RESOURCE_CNTL
-#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
-#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
-#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
-//GDS_GWS_RESOURCE
-#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
-#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
-#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
-#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
-#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
-#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
-#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c
-#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d
-#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e
-#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f
-#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
-#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL
-#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
-#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
-#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
-#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L
-#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L
-#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L
-#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L
-#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L
-//GDS_GWS_RESOURCE_CNT
-#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
-#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
-#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_CNTL
-#define GDS_OA_CNTL__INDEX__SHIFT 0x0
-#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
-#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
-#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
-//GDS_OA_COUNTER
-#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
-#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
-//GDS_OA_ADDRESS
-#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
-#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
-#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
-#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
-#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
-#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
-#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
-#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L
-#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L
-#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L
-#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
-#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
-//GDS_OA_INCDEC
-#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
-#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
-#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
-#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
-//GDS_OA_RING_SIZE
-#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
-#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
-//SPI_CONFIG_CNTL
-#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
-#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
-#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
-#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
-#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
-#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
-#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
-#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
-#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
-#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
-#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
-#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
-#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
-#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
-#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
-#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
-#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
-#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
-//SPI_CONFIG_CNTL_1
-#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
-#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
-#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
-#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
-#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
-#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
-#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
-#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
-#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
-#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
-#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
-#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L
-//SPI_CONFIG_CNTL_2
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
-
-
-// addressBlock: gc_perfddec
-//CPG_PERFCOUNTER1_LO
-#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPG_PERFCOUNTER1_HI
-#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPG_PERFCOUNTER0_LO
-#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPG_PERFCOUNTER0_HI
-#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER1_LO
-#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER1_HI
-#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER0_LO
-#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER0_HI
-#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER1_LO
-#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER1_HI
-#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER0_LO
-#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER0_HI
-#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPF_LATENCY_STATS_DATA
-#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
-#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
-//CPG_LATENCY_STATS_DATA
-#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
-#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
-//CPC_LATENCY_STATS_DATA
-#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
-#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER0_LO
-#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER0_HI
-#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER1_LO
-#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER1_HI
-#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE0_PERFCOUNTER_LO
-#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE0_PERFCOUNTER_HI
-#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE1_PERFCOUNTER_LO
-#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE1_PERFCOUNTER_HI
-#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE2_PERFCOUNTER_LO
-#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE2_PERFCOUNTER_HI
-#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE3_PERFCOUNTER_LO
-#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE3_PERFCOUNTER_HI
-#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER0_LO
-#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER0_HI
-#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER1_LO
-#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER1_HI
-#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER2_LO
-#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER2_HI
-#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER3_LO
-#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER3_HI
-#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER0_LO
-#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER0_HI
-#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER1_LO
-#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER1_HI
-#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER2_LO
-#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER2_HI
-#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER3_LO
-#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER3_HI
-#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER0_LO
-#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER0_HI
-#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER1_LO
-#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER1_HI
-#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER2_LO
-#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER2_HI
-#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER3_LO
-#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER3_HI
-#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER0_LO
-#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER0_HI
-#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SU_PERFCOUNTER1_LO
-#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER1_HI
-#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SU_PERFCOUNTER2_LO
-#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER2_HI
-#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SU_PERFCOUNTER3_LO
-#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER3_HI
-#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SC_PERFCOUNTER0_LO
-#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER0_HI
-#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER1_LO
-#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER1_HI
-#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER2_LO
-#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER2_HI
-#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER3_LO
-#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER3_HI
-#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER4_LO
-#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER4_HI
-#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER5_LO
-#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER5_HI
-#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER6_LO
-#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER6_HI
-#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER7_LO
-#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER7_HI
-#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER0_HI
-#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER0_LO
-#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER1_HI
-#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER1_LO
-#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER2_HI
-#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER2_LO
-#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER3_HI
-#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER3_LO
-#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER4_HI
-#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER4_LO
-#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER5_HI
-#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER5_LO
-#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER0_LO
-#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER0_HI
-#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER1_LO
-#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER1_HI
-#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER2_LO
-#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER2_HI
-#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER3_LO
-#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER3_HI
-#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER4_LO
-#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER4_HI
-#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER5_LO
-#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER5_HI
-#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER6_LO
-#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER6_HI
-#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER7_LO
-#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER7_HI
-#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER8_LO
-#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER8_HI
-#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER9_LO
-#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER9_HI
-#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER10_LO
-#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER10_HI
-#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER11_LO
-#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER11_HI
-#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER12_LO
-#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER12_HI
-#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER13_LO
-#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER13_HI
-#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER14_LO
-#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER14_HI
-#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER15_LO
-#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER15_HI
-#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER0_LO
-#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER0_HI
-#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER1_LO
-#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER1_HI
-#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER2_LO
-#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER2_HI
-#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER3_LO
-#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER3_HI
-#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER0_LO
-#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER0_HI
-#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER1_LO
-#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER1_HI
-#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER2_LO
-#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER2_HI
-#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER3_LO
-#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER3_HI
-#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER0_LO
-#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER0_HI
-#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER1_LO
-#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER1_HI
-#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER0_LO
-#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER0_HI
-#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER1_LO
-#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER1_HI
-#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER0_LO
-#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER0_HI
-#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER1_LO
-#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER1_HI
-#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER2_LO
-#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER2_HI
-#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER3_LO
-#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER3_HI
-#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER0_LO
-#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER0_HI
-#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER1_LO
-#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER1_HI
-#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER2_LO
-#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER2_HI
-#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER3_LO
-#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER3_HI
-#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER0_LO
-#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER0_HI
-#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER1_LO
-#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER1_HI
-#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER2_LO
-#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER2_HI
-#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER3_LO
-#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER3_HI
-#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER0_LO
-#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER0_HI
-#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER1_LO
-#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER1_HI
-#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER2_LO
-#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER2_HI
-#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER3_LO
-#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER3_HI
-#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER0_LO
-#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER0_HI
-#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER1_LO
-#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER1_HI
-#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER2_LO
-#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER2_HI
-#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER3_LO
-#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER3_HI
-#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER0_LO
-#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER0_HI
-#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER1_LO
-#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER1_HI
-#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER0_LO
-#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER0_HI
-#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER1_LO
-#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER1_HI
-#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER2_LO
-#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER2_HI
-#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER3_LO
-#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER3_HI
-#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_utcl2_atcl2pfcntrdec
-//ATC_L2_PERFCOUNTER_LO
-#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//ATC_L2_PERFCOUNTER_HI
-#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_utcl2_vml2prdec
-//MC_VM_L2_PERFCOUNTER_LO
-#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//MC_VM_L2_PERFCOUNTER_HI
-#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_perfsdec
-//CPG_PERFCOUNTER1_SELECT
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPG_PERFCOUNTER0_SELECT1
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
-//CPG_PERFCOUNTER0_SELECT
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPC_PERFCOUNTER1_SELECT
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPC_PERFCOUNTER0_SELECT1
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
-//CPF_PERFCOUNTER1_SELECT
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPF_PERFCOUNTER0_SELECT1
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
-//CPF_PERFCOUNTER0_SELECT
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CP_PERFMON_CNTL
-#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
-#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
-#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
-#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
-#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
-#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
-//CPC_PERFCOUNTER0_SELECT
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPF_TC_PERF_COUNTER_WINDOW_SELECT
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
-//CPG_TC_PERF_COUNTER_WINDOW_SELECT
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
-//CPF_LATENCY_STATS_SELECT
-#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
-#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
-#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
-#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
-#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
-#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
-//CPG_LATENCY_STATS_SELECT
-#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
-#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
-#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
-#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
-#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
-#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
-//CPC_LATENCY_STATS_SELECT
-#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
-#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
-#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
-#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L
-#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
-#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
-//CP_DRAW_OBJECT
-#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
-#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
-//CP_DRAW_OBJECT_COUNTER
-#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
-#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
-//CP_DRAW_WINDOW_MASK_HI
-#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
-#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
-//CP_DRAW_WINDOW_HI
-#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
-#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
-//CP_DRAW_WINDOW_LO
-#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
-#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
-#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
-#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
-//CP_DRAW_WINDOW_CNTL
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
-#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
-#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
-//GRBM_PERFCOUNTER0_SELECT
-#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
-#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
-#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
-#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
-#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
-#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
-#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
-#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
-#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
-#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
-#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
-#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
-#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
-//GRBM_PERFCOUNTER1_SELECT
-#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
-#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
-#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
-#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
-#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
-#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
-#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
-#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
-#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
-#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
-#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
-#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
-#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
-//GRBM_SE0_PERFCOUNTER_SELECT
-#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//GRBM_SE1_PERFCOUNTER_SELECT
-#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//GRBM_SE2_PERFCOUNTER_SELECT
-#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//GRBM_SE3_PERFCOUNTER_SELECT
-#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//WD_PERFCOUNTER0_SELECT
-#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//WD_PERFCOUNTER1_SELECT
-#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//WD_PERFCOUNTER2_SELECT
-#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//WD_PERFCOUNTER3_SELECT
-#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER0_SELECT
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER1_SELECT
-#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER2_SELECT
-#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
-#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER3_SELECT
-#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
-#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER0_SELECT1
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//VGT_PERFCOUNTER0_SELECT
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER1_SELECT
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER2_SELECT
-#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
-#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER3_SELECT
-#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
-#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER0_SELECT1
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//VGT_PERFCOUNTER1_SELECT1
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//VGT_PERFCOUNTER_SEID_MASK
-#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
-#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL
-//PA_SU_PERFCOUNTER0_SELECT
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SU_PERFCOUNTER0_SELECT1
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-//PA_SU_PERFCOUNTER1_SELECT
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SU_PERFCOUNTER1_SELECT1
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-//PA_SU_PERFCOUNTER2_SELECT
-#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SU_PERFCOUNTER3_SELECT
-#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SC_PERFCOUNTER0_SELECT
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SC_PERFCOUNTER0_SELECT1
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-//PA_SC_PERFCOUNTER1_SELECT
-#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER2_SELECT
-#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER3_SELECT
-#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER4_SELECT
-#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER5_SELECT
-#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER6_SELECT
-#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER7_SELECT
-#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
-//SPI_PERFCOUNTER0_SELECT
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER1_SELECT
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER2_SELECT
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER3_SELECT
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER0_SELECT1
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER1_SELECT1
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER2_SELECT1
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER3_SELECT1
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER4_SELECT
-#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL
-//SPI_PERFCOUNTER5_SELECT
-#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL
-//SPI_PERFCOUNTER_BINS
-#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
-#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
-#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
-#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
-#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
-#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
-#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
-#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
-#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
-#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
-#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
-#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
-#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
-#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
-#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
-#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
-//SQ_PERFCOUNTER0_SELECT
-#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER1_SELECT
-#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER2_SELECT
-#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER3_SELECT
-#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER4_SELECT
-#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER5_SELECT
-#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER6_SELECT
-#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER7_SELECT
-#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER8_SELECT
-#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER9_SELECT
-#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER10_SELECT
-#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER11_SELECT
-#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER12_SELECT
-#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER13_SELECT
-#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER14_SELECT
-#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER15_SELECT
-#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER_CTRL
-#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
-#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
-#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
-#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
-#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
-#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
-#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
-#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
-#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
-#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
-#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
-#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
-#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
-#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
-#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
-#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
-#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L
-#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
-//SQ_PERFCOUNTER_MASK
-#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
-#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L
-//SQ_PERFCOUNTER_CTRL2
-#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
-#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
-//SX_PERFCOUNTER0_SELECT
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER1_SELECT
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER2_SELECT
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER3_SELECT
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER0_SELECT1
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
-//SX_PERFCOUNTER1_SELECT1
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
-//GDS_PERFCOUNTER0_SELECT
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER1_SELECT
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER2_SELECT
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER3_SELECT
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER0_SELECT1
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
-//TA_PERFCOUNTER0_SELECT
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TA_PERFCOUNTER0_SELECT1
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TA_PERFCOUNTER1_SELECT
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TD_PERFCOUNTER0_SELECT
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TD_PERFCOUNTER0_SELECT1
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TD_PERFCOUNTER1_SELECT
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER0_SELECT
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER0_SELECT1
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TCP_PERFCOUNTER1_SELECT
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER1_SELECT1
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TCP_PERFCOUNTER2_SELECT
-#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER3_SELECT
-#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER0_SELECT
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER0_SELECT1
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCC_PERFCOUNTER1_SELECT
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER1_SELECT1
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCC_PERFCOUNTER2_SELECT
-#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER3_SELECT
-#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER0_SELECT
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER0_SELECT1
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCA_PERFCOUNTER1_SELECT
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER1_SELECT1
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCA_PERFCOUNTER2_SELECT
-#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER3_SELECT
-#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER_FILTER
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
-//CB_PERFCOUNTER0_SELECT
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
-#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER0_SELECT1
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//CB_PERFCOUNTER1_SELECT
-#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER2_SELECT
-#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER3_SELECT
-#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER0_SELECT
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER0_SELECT1
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//DB_PERFCOUNTER1_SELECT
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER1_SELECT1
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//DB_PERFCOUNTER2_SELECT
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER3_SELECT
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//RLC_SPM_PERFMON_CNTL
-#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x2
-#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
-#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
-#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
-#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFCL
-#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
-#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
-#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
-//RLC_SPM_PERFMON_RING_BASE_LO
-#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
-//RLC_SPM_PERFMON_RING_BASE_HI
-#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
-#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
-#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
-//RLC_SPM_PERFMON_RING_SIZE
-#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
-//RLC_SPM_PERFMON_SEGMENT_SIZE
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
-//RLC_SPM_SE_MUXSEL_ADDR
-#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
-#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
-//RLC_SPM_SE_MUXSEL_DATA
-#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
-#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
-//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_CB_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_DB_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_PA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_IA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SC_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TD_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SX_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_GLOBAL_MUXSEL_ADDR
-#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
-#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
-//RLC_SPM_GLOBAL_MUXSEL_DATA
-#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
-#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
-//RLC_SPM_RING_RDPTR
-#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
-#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
-//RLC_SPM_SEGMENT_THRESHOLD
-#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
-#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL
-//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_PERFMON_CLK_CNTL
-#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
-#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
-//RLC_PERFMON_CNTL
-#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
-#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
-//RLC_PERFCOUNTER0_SELECT
-#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
-//RLC_PERFCOUNTER1_SELECT
-#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
-//RLC_GPU_IOV_PERF_CNT_CNTL
-#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
-#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
-#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
-//RLC_GPU_IOV_PERF_CNT_WR_ADDR
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
-//RLC_GPU_IOV_PERF_CNT_WR_DATA
-#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL
-//RLC_GPU_IOV_PERF_CNT_RD_ADDR
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
-//RLC_GPU_IOV_PERF_CNT_RD_DATA
-#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL
-//RMI_PERFCOUNTER0_SELECT
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERFCOUNTER0_SELECT1
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//RMI_PERFCOUNTER1_SELECT
-#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERFCOUNTER2_SELECT
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERFCOUNTER2_SELECT1
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//RMI_PERFCOUNTER3_SELECT
-#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERF_COUNTER_CNTL
-#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
-#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
-#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
-#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
-#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
-#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
-#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
-#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
-#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
-#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
-
-
-// addressBlock: gc_utcl2_atcl2pfcntldec
-//ATC_L2_PERFCOUNTER0_CFG
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//ATC_L2_PERFCOUNTER1_CFG
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//ATC_L2_PERFCOUNTER_RSLT_CNTL
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: gc_utcl2_vml2pldec
-//MC_VM_L2_PERFCOUNTER0_CFG
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER1_CFG
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER2_CFG
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER3_CFG
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER4_CFG
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER5_CFG
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER6_CFG
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER7_CFG
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: gc_rlcpdec
-//RLC_CNTL
-#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
-#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
-#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
-#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
-#define RLC_CNTL__RESERVED__SHIFT 0x4
-#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
-#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
-#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
-#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
-#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
-//RLC_STAT
-#define RLC_STAT__RLC_BUSY__SHIFT 0x0
-#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
-#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
-#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3
-#define RLC_STAT__MC_BUSY__SHIFT 0x4
-#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
-#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
-#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
-#define RLC_STAT__RESERVED__SHIFT 0x8
-#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
-#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L
-#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L
-#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L
-#define RLC_STAT__MC_BUSY_MASK 0x00000010L
-#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
-#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
-#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
-#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
-//RLC_SAFE_MODE
-#define RLC_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
-#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
-#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
-#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
-#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
-//RLC_MEM_SLP_CNTL
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
-#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
-#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
-#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
-#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
-#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
-#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
-#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
-#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
-//SMU_RLC_RESPONSE
-#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
-#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
-//RLC_RLCV_SAFE_MODE
-#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
-#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
-#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
-#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
-#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
-//RLC_SMU_SAFE_MODE
-#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L
-#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL
-#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L
-#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L
-#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
-//RLC_RLCV_COMMAND
-#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
-#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
-#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
-#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
-//RLC_REFCLOCK_TIMESTAMP_LSB
-#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
-#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
-//RLC_REFCLOCK_TIMESTAMP_MSB
-#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
-#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_INT_0
-#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_INT_1
-#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_INT_2
-#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_CTRL
-#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
-#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
-#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
-#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
-#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4
-#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
-#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
-#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
-#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
-#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L
-//RLC_LB_CNTR_MAX
-#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
-#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_STAT
-#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
-#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
-#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
-#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
-#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4
-#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
-#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
-#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
-#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
-#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L
-//RLC_GPM_TIMER_INT_3
-#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
-//RLC_SERDES_WR_NONCU_MASTER_MASK_1
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L
-//RLC_SERDES_NONCU_MASTER_BUSY_1
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L
-//RLC_INT_STAT
-#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
-#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
-#define RLC_INT_STAT__RESERVED__SHIFT 0x9
-#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
-#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
-#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
-//RLC_LB_CNTL
-#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
-#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
-#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
-#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
-#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
-#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
-#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
-#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
-#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
-#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
-#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L
-#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L
-//RLC_MGCG_CTRL
-#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
-#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
-#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
-#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
-#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
-#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
-#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
-#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
-#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
-#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
-#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
-#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
-#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
-#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
-#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
-#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
-//RLC_LB_CNTR_INIT
-#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
-#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL
-//RLC_LOAD_BALANCE_CNTR
-#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
-#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
-//RLC_JUMP_TABLE_RESTORE
-#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
-#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
-//RLC_PG_DELAY_2
-#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
-#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
-#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
-#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
-#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
-#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L
-//RLC_GPU_CLOCK_COUNT_LSB
-#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
-#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
-//RLC_GPU_CLOCK_COUNT_MSB
-#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
-#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
-//RLC_CAPTURE_GPU_CLOCK_COUNT
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_UCODE_CNTL
-#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
-#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
-//RLC_GPM_THREAD_RESET
-#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
-#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
-#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
-#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
-#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
-#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
-#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
-#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
-#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
-#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
-//RLC_GPM_CP_DMA_COMPLETE_T0
-#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
-#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
-#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
-#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPM_CP_DMA_COMPLETE_T1
-#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
-#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
-#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
-#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
-//RLC_FIREWALL_VIOLATION
-#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0
-#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL
-//RLC_GPM_STAT
-#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
-#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
-#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
-#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
-#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
-#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
-#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
-#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
-#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
-#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
-#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
-#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
-#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
-#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
-#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
-#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
-#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
-#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
-#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
-#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
-#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
-#define RLC_GPM_STAT__RESERVED__SHIFT 0x17
-#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
-#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
-#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
-#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
-#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
-#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
-#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
-#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
-#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
-#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
-#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
-#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
-#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
-#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L
-#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L
-#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L
-#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L
-#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
-#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
-#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
-#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
-#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
-#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L
-#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
-//RLC_GPU_CLOCK_32_RES_SEL
-#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
-#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
-#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
-#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
-//RLC_GPU_CLOCK_32
-#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
-#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
-//RLC_PG_CNTL
-#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
-#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
-#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
-#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
-#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
-#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
-#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
-#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
-#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
-#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
-#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
-#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
-#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
-#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
-#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
-#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
-#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
-#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
-#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
-#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
-#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L
-#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L
-//RLC_GPM_THREAD_PRIORITY
-#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
-#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
-#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
-#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
-#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
-#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
-#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
-#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
-//RLC_GPM_THREAD_ENABLE
-#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
-#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
-#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
-#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
-#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
-#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
-#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
-#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
-#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
-#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
-//RLC_CGTT_MGCG_OVERRIDE
-#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0
-#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
-#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
-#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8
-#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L
-#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
-#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
-#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L
-//RLC_CGCG_CGLS_CTRL
-#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
-#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
-#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
-#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
-#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
-#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
-#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
-#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
-#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
-#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
-#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
-#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
-#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
-#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
-#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
-#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
-//RLC_CGCG_RAMP_CTRL
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
-//RLC_DYN_PG_STATUS
-#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
-#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_DYN_PG_REQUEST
-#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
-#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_PG_DELAY
-#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
-#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
-#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
-#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
-#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
-#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
-#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
-#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
-//RLC_CU_STATUS
-#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
-#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
-//RLC_LB_INIT_CU_MASK
-#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
-#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_LB_ALWAYS_ACTIVE_CU_MASK
-#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
-#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_LB_PARAMS
-#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
-#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
-#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
-#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
-//RLC_THREAD1_DELAY
-#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
-#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
-#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
-#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
-#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL
-#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
-#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
-#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L
-//RLC_PG_ALWAYS_ON_CU_MASK
-#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
-#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_MAX_PG_CU
-#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
-#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
-#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL
-#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L
-//RLC_AUTO_PG_CTRL
-#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
-#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
-#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
-#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
-#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
-#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
-#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
-#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
-#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
-#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
-//RLC_SMU_GRBM_REG_SAVE_CTRL
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL
-//RLC_SERDES_RD_MASTER_INDEX
-#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
-#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
-#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc
-#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd
-#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11
-#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13
-#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL
-#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
-#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L
-#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L
-#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L
-#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L
-//RLC_SERDES_RD_DATA_0
-#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_RD_DATA_1
-#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_RD_DATA_2
-#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_WR_CU_MASTER_MASK
-#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
-#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL
-//RLC_SERDES_WR_NONCU_MASTER_MASK
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L
-//RLC_SERDES_WR_CTRL
-#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
-#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
-#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
-#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
-#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
-#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
-#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
-#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
-#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
-#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
-#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
-#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
-#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
-#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL
-#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
-#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
-#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
-#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
-#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
-#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
-#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L
-#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L
-#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L
-#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L
-#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L
-#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L
-//RLC_SERDES_WR_DATA
-#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
-#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_CU_MASTER_BUSY
-#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
-#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL
-//RLC_SERDES_NONCU_MASTER_BUSY
-#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
-#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19
-#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a
-#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L
-//RLC_GPM_GENERAL_0
-#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_1
-#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_2
-#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_3
-#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_4
-#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_5
-#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_6
-#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_7
-#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_SCRATCH_ADDR
-#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
-#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
-#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
-#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
-//RLC_GPM_SCRATCH_DATA
-#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
-#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_STATIC_PG_STATUS
-#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
-#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_SPM_MC_CNTL
-#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
-#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
-#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5
-#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8
-#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
-#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
-#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L
-#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L
-#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L
-#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L
-//RLC_SPM_INT_CNTL
-#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
-#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
-#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
-#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_SPM_INT_STATUS
-#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
-#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
-#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
-#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
-//RLC_SMU_MESSAGE
-#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
-#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL
-//RLC_GPM_LOG_SIZE
-#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
-#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
-//RLC_PG_DELAY_3
-#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
-#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
-#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
-#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
-//RLC_GPR_REG1
-#define RLC_GPR_REG1__DATA__SHIFT 0x0
-#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPR_REG2
-#define RLC_GPR_REG2__DATA__SHIFT 0x0
-#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_LOG_CONT
-#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
-#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_DISABLE_TH0
-#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
-#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_DISABLE_TH1
-#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
-#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_FORCE_TH0
-#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
-#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_FORCE_TH1
-#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
-#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL
-//RLC_SRM_CNTL
-#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
-#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
-#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
-#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
-#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
-#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_ARAM_ADDR
-#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
-#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
-#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
-#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
-//RLC_SRM_ARAM_DATA
-#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
-#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_DRAM_ADDR
-#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
-#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
-#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
-#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
-//RLC_SRM_DRAM_DATA
-#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
-#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_GPM_COMMAND
-#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
-#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
-#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
-#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
-#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
-#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
-#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L
-#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
-#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L
-#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
-//RLC_SRM_GPM_COMMAND_STATUS
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
-#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
-#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_RLCV_COMMAND
-#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
-#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
-#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
-#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
-#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
-#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
-#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
-#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
-#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
-#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
-#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
-#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
-//RLC_SRM_RLCV_COMMAND_STATUS
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
-#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
-#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_INDEX_CNTL_ADDR_0
-#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_1
-#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_2
-#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_3
-#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_4
-#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_5
-#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_6
-#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_7
-#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_DATA_0
-#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_1
-#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_2
-#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_3
-#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_4
-#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_5
-#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_6
-#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_7
-#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_STAT
-#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
-#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
-#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
-#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
-#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
-#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_GPM_ABORT
-#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
-#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
-#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
-#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_CSIB_ADDR_LO
-#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
-#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
-//RLC_CSIB_ADDR_HI
-#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
-#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
-//RLC_CSIB_LENGTH
-#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
-#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
-//RLC_SMU_COMMAND
-#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
-#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL
-//RLC_CP_SCHEDULERS
-#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
-#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
-#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
-#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
-#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
-#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
-#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
-#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
-//RLC_SMU_ARGUMENT_1
-#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
-#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL
-//RLC_SMU_ARGUMENT_2
-#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
-#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_8
-#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_9
-#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_10
-#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_11
-#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_12
-#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_CNTL_0
-#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
-#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
-#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
-#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
-#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
-#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
-#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
-#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
-//RLC_GPM_UTCL1_CNTL_1
-#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
-#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
-#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
-#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
-#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
-#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
-#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
-#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
-//RLC_GPM_UTCL1_CNTL_2
-#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
-#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
-#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
-#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
-#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
-#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
-#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
-#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
-//RLC_SPM_UTCL1_CNTL
-#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
-#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
-//RLC_UTCL1_STATUS_2
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
-#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
-#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
-//RLC_LB_THR_CONFIG_2
-#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL
-//RLC_LB_THR_CONFIG_3
-#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL
-//RLC_LB_THR_CONFIG_4
-#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL
-//RLC_SPM_UTCL1_ERROR_1
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_SPM_UTCL1_ERROR_2
-#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH0_ERROR_1
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_LB_THR_CONFIG_1
-#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH0_ERROR_2
-#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH1_ERROR_1
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_GPM_UTCL1_TH1_ERROR_2
-#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH2_ERROR_1
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_GPM_UTCL1_TH2_ERROR_2
-#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_CGCG_CGLS_CTRL_3D
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c
-#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d
-#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L
-#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L
-#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L
-//RLC_CGCG_RAMP_CTRL_3D
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L
-//RLC_SEMAPHORE_0
-#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
-#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
-#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
-#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
-//RLC_SEMAPHORE_1
-#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
-#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
-#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
-#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
-//RLC_CP_EOF_INT
-#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
-#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
-#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
-#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_CP_EOF_INT_CNT
-#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
-#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
-//RLC_SPARE_INT
-#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
-#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
-#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
-#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_PREWALKER_UTCL1_CNTL
-#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
-#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
-//RLC_PREWALKER_UTCL1_TRIG
-#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
-#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
-#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
-#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
-#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
-#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
-#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
-#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
-#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
-#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
-#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
-#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
-#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
-#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
-#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
-//RLC_PREWALKER_UTCL1_ADDR_LSB
-#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
-//RLC_PREWALKER_UTCL1_ADDR_MSB
-#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
-//RLC_PREWALKER_UTCL1_SIZE_LSB
-#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
-//RLC_PREWALKER_UTCL1_SIZE_MSB
-#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
-//RLC_DSM_TRIG
-//RLC_UTCL1_STATUS
-#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
-#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
-#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
-#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
-#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
-#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
-#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
-#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
-//RLC_R2I_CNTL_0
-#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
-//RLC_R2I_CNTL_1
-#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
-//RLC_R2I_CNTL_2
-#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
-//RLC_R2I_CNTL_3
-#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
-//RLC_UTCL2_CNTL
-#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
-#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1
-#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
-#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_LBPW_CU_STAT
-#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0
-#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10
-#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL
-#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L
-//RLC_DS_CNTL
-#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0
-#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1
-#define RLC_DS_CNTL__RESRVED__SHIFT 0x2
-#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10
-#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11
-#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12
-#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L
-#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L
-#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL
-#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L
-#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L
-#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L
-//RLC_RLCV_SPARE_INT
-#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
-#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
-#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
-#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
-
-
-// addressBlock: gc_pwrdec
-//CGTS_SM_CTRL_REG
-#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
-#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
-#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
-#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
-#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
-#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
-#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
-#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
-#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
-#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
-#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
-#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
-#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
-#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
-#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
-#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L
-//CGTS_RD_CTRL_REG
-#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
-#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
-#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL
-#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L
-//CGTS_RD_REG
-#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
-#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL
-//CGTS_TCC_DISABLE
-#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
-#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
-//CGTS_USER_TCC_DISABLE
-#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
-#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
-//CGTS_CU0_SP0_CTRL_REG
-#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_LDS_SQ_CTRL_REG
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_TA_SQC_CTRL_REG
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_SP1_CTRL_REG
-#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_TD_TCP_CTRL_REG
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_SP0_CTRL_REG
-#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_LDS_SQ_CTRL_REG
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_TA_SQC_CTRL_REG
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU1_SP1_CTRL_REG
-#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_TD_TCP_CTRL_REG
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_SP0_CTRL_REG
-#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_LDS_SQ_CTRL_REG
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_TA_SQC_CTRL_REG
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU2_SP1_CTRL_REG
-#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_TD_TCP_CTRL_REG
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_SP0_CTRL_REG
-#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_LDS_SQ_CTRL_REG
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_TA_SQC_CTRL_REG
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_SP1_CTRL_REG
-#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_TD_TCP_CTRL_REG
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_SP0_CTRL_REG
-#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_LDS_SQ_CTRL_REG
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_TA_SQC_CTRL_REG
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU4_SP1_CTRL_REG
-#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_TD_TCP_CTRL_REG
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_SP0_CTRL_REG
-#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_LDS_SQ_CTRL_REG
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_TA_SQC_CTRL_REG
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU5_SP1_CTRL_REG
-#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_TD_TCP_CTRL_REG
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_SP0_CTRL_REG
-#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_LDS_SQ_CTRL_REG
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_TA_SQC_CTRL_REG
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_SP1_CTRL_REG
-#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_TD_TCP_CTRL_REG
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_SP0_CTRL_REG
-#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_LDS_SQ_CTRL_REG
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_TA_SQC_CTRL_REG
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU7_SP1_CTRL_REG
-#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_TD_TCP_CTRL_REG
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_SP0_CTRL_REG
-#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_LDS_SQ_CTRL_REG
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_TA_SQC_CTRL_REG
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU8_SP1_CTRL_REG
-#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_TD_TCP_CTRL_REG
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_SP0_CTRL_REG
-#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_LDS_SQ_CTRL_REG
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_TA_SQC_CTRL_REG
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_SP1_CTRL_REG
-#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_TD_TCP_CTRL_REG
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_SP0_CTRL_REG
-#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_LDS_SQ_CTRL_REG
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_TA_SQC_CTRL_REG
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU10_SP1_CTRL_REG
-#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_TD_TCP_CTRL_REG
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_SP0_CTRL_REG
-#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_LDS_SQ_CTRL_REG
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_TA_SQC_CTRL_REG
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU11_SP1_CTRL_REG
-#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_TD_TCP_CTRL_REG
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_SP0_CTRL_REG
-#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_LDS_SQ_CTRL_REG
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_TA_SQC_CTRL_REG
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_SP1_CTRL_REG
-#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_TD_TCP_CTRL_REG
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_SP0_CTRL_REG
-#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_LDS_SQ_CTRL_REG
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_TA_SQC_CTRL_REG
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU13_SP1_CTRL_REG
-#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_TD_TCP_CTRL_REG
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_SP0_CTRL_REG
-#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_LDS_SQ_CTRL_REG
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_TA_SQC_CTRL_REG
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU14_SP1_CTRL_REG
-#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_TD_TCP_CTRL_REG
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_SP0_CTRL_REG
-#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_LDS_SQ_CTRL_REG
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_TA_SQC_CTRL_REG
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_SP1_CTRL_REG
-#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_TD_TCP_CTRL_REG
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_TCPI_CTRL_REG
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU1_TCPI_CTRL_REG
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU2_TCPI_CTRL_REG
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU3_TCPI_CTRL_REG
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU4_TCPI_CTRL_REG
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU5_TCPI_CTRL_REG
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU6_TCPI_CTRL_REG
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU7_TCPI_CTRL_REG
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU8_TCPI_CTRL_REG
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU9_TCPI_CTRL_REG
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU10_TCPI_CTRL_REG
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU11_TCPI_CTRL_REG
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU12_TCPI_CTRL_REG
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU13_TCPI_CTRL_REG
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU14_TCPI_CTRL_REG
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU15_TCPI_CTRL_REG
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTT_SPI_CLK_CTRL
-#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
-#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
-#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
-#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
-#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
-#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
-#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
-#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
-#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
-#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
-#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
-#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
-#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_PC_CLK_CTRL
-#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
-#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
-#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
-#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
-#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
-#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
-#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
-#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
-#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
-#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
-#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
-#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
-#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
-#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
-#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_BCI_CLK_CTRL
-#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
-#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
-#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
-#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
-#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
-#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
-#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
-#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
-#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
-#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
-#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
-#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
-#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
-#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
-#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_VGT_CLK_CTRL
-#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
-#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
-#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
-#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
-#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
-#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
-#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
-#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
-#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_IA_CLK_CTRL
-#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_WD_CLK_CTRL
-#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
-#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
-#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
-#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
-#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
-#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
-#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
-#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
-#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
-#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
-#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_PA_CLK_CTRL
-#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
-#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
-#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
-#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
-#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
-#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
-//CGTT_SC_CLK_CTRL0
-#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
-#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
-#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
-#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
-#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
-#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
-//CGTT_SC_CLK_CTRL1
-#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
-#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
-#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
-//CGTT_SQ_CLK_CTRL
-#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
-#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
-#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_SQG_CLK_CTRL
-#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
-#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
-#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
-#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
-#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//SQ_ALU_CLK_CTRL
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
-//SQ_TEX_CLK_CTRL
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
-//SQ_LDS_CLK_CTRL
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
-//SQ_POWER_THROTTLE
-#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
-#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
-#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
-#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL
-#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L
-#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L
-//SQ_POWER_THROTTLE2
-#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
-#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
-#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL0
-#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL1
-#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL2
-#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL3
-#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL4
-#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
-//TD_CGTT_CTRL
-#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
-#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//TA_CGTT_CTRL
-#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
-#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_TCPI_CLK_CTRL
-#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_TCI_CLK_CTRL
-#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_GDS_CLK_CTRL
-#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//DB_CGTT_CLK_CTRL_0
-#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
-#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
-#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
-#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
-//CB_CGTT_SCLK_CTRL
-#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//TCC_CGTT_SCLK_CTRL
-#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//TCA_CGTT_SCLK_CTRL
-#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_CP_CLK_CTRL
-#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//CGTT_CPF_CLK_CTRL
-#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//CGTT_CPC_CLK_CTRL
-#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//RLC_PWR_CTRL
-#define RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT 0x0
-#define RLC_PWR_CTRL__RESERVED__SHIFT 0x1
-#define RLC_PWR_CTRL__DLDO_STATUS__SHIFT 0x8
-#define RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK 0x00000001L
-#define RLC_PWR_CTRL__RESERVED_MASK 0x000000FEL
-#define RLC_PWR_CTRL__DLDO_STATUS_MASK 0x00000100L
-//CGTT_RLC_CLK_CTRL
-#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//RLC_GFX_RM_CNTL
-#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
-#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
-#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
-#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RMI_CGTT_SCLK_CTRL
-#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_TCPF_CLK_CTRL
-#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-
-
-// addressBlock: gc_ea_pwrdec
-//GCEA_CGTT_CLK_CTRL
-#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
-#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
-
-
-// addressBlock: gc_utcl2_vmsharedhvdec
-//MC_VM_FB_SIZE_OFFSET_VF0
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF1
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF2
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF3
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF4
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF5
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF6
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF7
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF8
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF9
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF10
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF11
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF12
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF13
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF14
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF15
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
-//VM_IOMMU_MMIO_CNTRL_1
-#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
-#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
-//MC_VM_MARC_BASE_LO_0
-#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_1
-#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_2
-#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_3
-#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_HI_0
-#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_1
-#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_2
-#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_3
-#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_LO_0
-#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_1
-#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_2
-#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_3
-#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_HI_0
-#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_1
-#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_2
-#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_3
-#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_LO_0
-#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_1
-#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_2
-#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_3
-#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_HI_0
-#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_1
-#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_2
-#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_3
-#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
-//VM_IOMMU_CONTROL_REGISTER
-#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
-#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
-//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
-#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
-#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
-//VM_PCIE_ATS_CNTL
-#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
-#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
-#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_0
-#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_1
-#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_2
-#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_3
-#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_4
-#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_5
-#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_6
-#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_7
-#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_8
-#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_9
-#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_10
-#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_11
-#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_12
-#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_13
-#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_14
-#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_15
-#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
-//UTCL2_CGTT_CLK_CTRL
-#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
-#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
-#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: gc_hypdec
-//CP_HYP_PFP_UCODE_ADDR
-#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
-//CP_PFP_UCODE_ADDR
-#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
-//CP_HYP_PFP_UCODE_DATA
-#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_PFP_UCODE_DATA
-#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_ME_UCODE_ADDR
-#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL
-//CP_ME_RAM_RADDR
-#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
-#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL
-//CP_ME_RAM_WADDR
-#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
-#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL
-//CP_HYP_ME_UCODE_DATA
-#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_ME_RAM_DATA
-#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
-#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
-//CP_CE_UCODE_ADDR
-#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
-//CP_HYP_CE_UCODE_ADDR
-#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
-//CP_CE_UCODE_DATA
-#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_CE_UCODE_DATA
-#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_MEC1_UCODE_ADDR
-#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_MEC_ME1_UCODE_ADDR
-#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_HYP_MEC1_UCODE_DATA
-#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_MEC_ME1_UCODE_DATA
-#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_MEC2_UCODE_ADDR
-#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_MEC_ME2_UCODE_ADDR
-#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_HYP_MEC2_UCODE_DATA
-#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_MEC_ME2_UCODE_DATA
-#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_UCODE_ADDR
-#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
-#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
-#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
-//RLC_GPM_UCODE_DATA
-#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//GRBM_GFX_INDEX_SR_SELECT
-#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
-//GRBM_GFX_INDEX_SR_DATA
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8
-#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
-#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
-#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
-#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L
-#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
-#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
-#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
-//GRBM_GFX_CNTL_SR_SELECT
-#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
-#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
-//GRBM_GFX_CNTL_SR_DATA
-#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
-#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
-#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
-#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
-#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
-#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
-#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
-#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
-//GRBM_CAM_INDEX
-#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
-#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
-//GRBM_HYP_CAM_INDEX
-#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
-#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
-//GRBM_CAM_DATA
-#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
-#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
-#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
-#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
-//GRBM_HYP_CAM_DATA
-#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
-#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
-#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
-#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
-//RLC_GPU_IOV_VF_ENABLE
-#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
-#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
-#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
-#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
-//RLC_GFX_RM_CNTL_ADJ
-#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT 0x0
-#define RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT 0x1
-#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK 0x00000001L
-#define RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_CFG_REG6
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
-#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
-#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
-//RLC_GPU_IOV_CFG_REG8
-#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-//RLC_RLCV_TIMER_INT_0
-#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
-#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
-//RLC_RLCV_TIMER_CTRL
-#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
-#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1
-#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
-#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_RLCV_TIMER_STAT
-#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
-#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1
-#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
-#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_VF_DOORBELL_STATUS
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
-//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
-//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
-//RLC_GPU_IOV_VF_MASK
-#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
-#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L
-//RLC_HYP_SEMAPHORE_2
-#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
-#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
-#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
-#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
-//RLC_HYP_SEMAPHORE_3
-#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
-#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
-#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
-#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
-//RLC_CLK_CNTL
-#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
-#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1
-#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2
-#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L
-#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L
-#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL
-//RLC_GPU_IOV_SCH_BLOCK
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
-#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
-#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
-//RLC_GPU_IOV_CFG_REG1
-#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
-#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
-#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
-#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
-#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
-#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
-#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
-#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
-#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
-#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
-//RLC_GPU_IOV_CFG_REG2
-#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
-#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
-#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
-//RLC_GPU_IOV_VM_BUSY_STATUS
-#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCH_0
-#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_ACTIVE_FCN_ID
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
-//RLC_GPU_IOV_SCH_3
-#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCH_1
-#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCH_2
-#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_UCODE_ADDR
-#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
-#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
-#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
-//RLC_GPU_IOV_UCODE_DATA
-#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCRATCH_ADDR
-#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
-#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
-#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
-#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
-//RLC_GPU_IOV_SCRATCH_DATA
-#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_F32_CNTL
-#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
-#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_F32_RESET
-#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
-#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
-#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_SDMA0_STATUS
-#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
-#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
-#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL
-#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L
-//RLC_GPU_IOV_SDMA1_STATUS
-#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
-#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
-#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL
-#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L
-//RLC_GPU_IOV_SMU_RESPONSE
-#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
-#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_VIRT_RESET_REQ
-#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
-#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
-#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
-//RLC_GPU_IOV_RLC_RESPONSE
-#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
-#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_INT_DISABLE
-#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
-#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_INT_FORCE
-#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
-#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SDMA0_BUSY_STATUS
-#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SDMA1_BUSY_STATUS
-#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gccacind
-//GC_CAC_CNTL
-#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
-#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
-#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
-#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
-#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f
-#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
-#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
-#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
-#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
-#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L
-//GC_CAC_OVR_SEL
-#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
-#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
-//GC_CAC_OVR_VAL
-#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
-#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_BCI_0
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CB_0
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CB_1
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CP_0
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CP_1
-#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_DB_0
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_DB_1
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_GDS_0
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_GDS_1
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_IA_0
-#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_LDS_0
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_LDS_1
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_PA_0
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_PC_0
-#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SC_0
-#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SPI_0
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SPI_1
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SPI_2
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_0
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_1
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_2
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_3
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_4
-#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SX_0
-#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SXRB_0
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TA_0
-#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCC_0
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCC_1
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCC_2
-#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCP_0
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCP_1
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCP_2
-#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TD_0
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TD_1
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TD_2
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_VGT_0
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_VGT_1
-#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_WD_0
-#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_0
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_1
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_2
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_3
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_4
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_5
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L
-//GC_CAC_ACC_BCI0
-#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB0
-#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB1
-#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB2
-#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB3
-#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CP0
-#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CP1
-#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CP2
-#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB0
-#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB1
-#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB2
-#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB3
-#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS0
-#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS1
-#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS2
-#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS3
-#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_IA0
-#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS0
-#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS1
-#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS2
-#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS3
-#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_PA0
-#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_PA1
-#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_PC0
-#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SC0
-#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI0
-#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI1
-#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI2
-#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI3
-#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI4
-#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI5
-#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_PG_0
-#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_PG_0__unused__SHIFT 0x10
-#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_PG_0__unused_MASK 0xFFFF0000L
-//GC_CAC_ACC_PG0
-#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_PG
-#define GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT 0x10
-#define GC_CAC_OVRD_PG__OVRRD_SELECT_MASK 0x0000FFFFL
-#define GC_CAC_OVRD_PG__OVRRD_VALUE_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ATCL2_0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
-//GC_CAC_ACC_EA0
-#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA1
-#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA2
-#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA3
-#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ATCL20
-#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_EA
-#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
-#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
-#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
-//GC_CAC_OVRD_UTCL2_ATCL2
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_WEIGHT_EA_0
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_EA_1
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_RMI_0
-#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10
-#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L
-//GC_CAC_ACC_RMI0
-#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_RMI
-#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_WEIGHT_UTCL2_ATCL2_1
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
-//GC_CAC_ACC_UTCL2_ATCL21
-#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ATCL22
-#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ATCL23
-#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA4
-#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA5
-#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_EA_2
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
-//GC_CAC_ACC_SQ0_LOWER
-#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ0_UPPER
-#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ1_LOWER
-#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ1_UPPER
-#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ2_LOWER
-#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ2_UPPER
-#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ3_LOWER
-#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ3_UPPER
-#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ4_LOWER
-#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ4_UPPER
-#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ5_LOWER
-#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ5_UPPER
-#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ6_LOWER
-#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ6_UPPER
-#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ7_LOWER
-#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ7_UPPER
-#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ8_LOWER
-#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ8_UPPER
-#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SX0
-#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SXRB0
-#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SXRB1
-#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TA0
-#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC0
-#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC1
-#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC2
-#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC3
-#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC4
-#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP0
-#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP1
-#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP2
-#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP3
-#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP4
-#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD0
-#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD1
-#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD2
-#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD3
-#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD4
-#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD5
-#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_VGT0
-#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_VGT1
-#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_VGT2
-#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_WD0
-#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU0
-#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU1
-#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU2
-#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU3
-#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU4
-#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU5
-#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU6
-#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU7
-#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU8
-#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU9
-#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU10
-#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_BCI
-#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
-#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
-#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
-//GC_CAC_OVRD_CB
-#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_CP
-#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
-#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
-#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
-//GC_CAC_OVRD_DB
-#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_GDS
-#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_IA
-#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_LDS
-#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_PA
-#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
-#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
-#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
-//GC_CAC_OVRD_PC
-#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SC
-#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SPI
-#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
-#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
-#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
-//GC_CAC_OVRD_CU
-#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SQ
-#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9
-#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL
-#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L
-//GC_CAC_OVRD_SX
-#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SXRB
-#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_TA
-#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_TCC
-#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_OVRD_TCP
-#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_OVRD_TD
-#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6
-#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL
-#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L
-//GC_CAC_OVRD_VGT
-#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3
-#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L
-#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L
-//GC_CAC_OVRD_WD
-#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_ACC_BCI1
-#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_UTCL2_ATCL2_2
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_1
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_2
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_3
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_4
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_VML2_0
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_VML2_1
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_VML2_2
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L
-//GC_CAC_ACC_UTCL2_ATCL24
-#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER0
-#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER1
-#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER2
-#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER3
-#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER4
-#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER5
-#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER6
-#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER7
-#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER8
-#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER9
-#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML20
-#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML21
-#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML22
-#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML23
-#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML24
-#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_UTCL2_ROUTER
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
-//GC_CAC_OVRD_UTCL2_VML2
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_WEIGHT_UTCL2_WALKER_0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_WALKER_1
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_WALKER_2
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L
-//GC_CAC_ACC_UTCL2_WALKER0
-#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER1
-#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER2
-#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER3
-#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER4
-#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_UTCL2_WALKER
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
-
-
-// addressBlock: secacind
-//SE_CAC_CNTL
-#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
-#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
-#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
-#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
-#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f
-#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
-#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
-#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
-#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
-#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L
-//SE_CAC_OVR_SEL
-#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
-#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
-//SE_CAC_OVR_VAL
-#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
-#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
-
-
-// addressBlock: sqind
-//SQ_WAVE_MODE
-#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
-#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
-#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
-#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
-#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
-#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
-#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
-#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18
-#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19
-#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a
-#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
-#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
-#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
-#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
-#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
-#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
-#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
-#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
-#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
-#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
-#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L
-#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L
-#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L
-#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L
-#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
-#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
-//SQ_WAVE_STATUS
-#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
-#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
-#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
-#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
-#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
-#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
-#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
-#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
-#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
-#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
-#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
-#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
-#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
-#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
-#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
-#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
-#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
-#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
-#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
-#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
-#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
-#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
-#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
-#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
-#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
-#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
-#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
-#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
-#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
-#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
-#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
-#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
-#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
-#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
-#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
-#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
-#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
-#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
-#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
-#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L
-#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
-#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
-//SQ_WAVE_TRAPSTS
-#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
-#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
-#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
-#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
-#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
-#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
-#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
-#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
-#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
-#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
-#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
-#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L
-#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
-#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
-//SQ_WAVE_HW_ID
-#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
-#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
-#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
-#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
-#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
-#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
-#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
-#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
-#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
-#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
-#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
-#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL
-#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
-#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L
-#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L
-#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
-#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L
-#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L
-#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L
-#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
-#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
-#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L
-//SQ_WAVE_GPR_ALLOC
-#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
-#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
-#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
-#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
-#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL
-#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L
-#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L
-#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
-//SQ_WAVE_LDS_ALLOC
-#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
-#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
-#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL
-#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
-//SQ_WAVE_IB_STS
-#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
-#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
-#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
-#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
-#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
-#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
-#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
-#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
-#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
-#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
-#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
-#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
-#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L
-#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
-//SQ_WAVE_PC_LO
-#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
-#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
-//SQ_WAVE_PC_HI
-#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
-#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
-//SQ_WAVE_INST_DW0
-#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
-#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
-//SQ_WAVE_INST_DW1
-#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
-#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL
-//SQ_WAVE_IB_DBG0
-#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
-#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
-#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
-#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
-#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
-#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
-#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
-#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
-#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
-#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
-#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f
-#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
-#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
-#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L
-#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
-#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L
-#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L
-#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L
-#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L
-#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L
-#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L
-#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L
-//SQ_WAVE_IB_DBG1
-#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
-#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
-#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
-#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
-#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
-#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
-#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
-#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L
-#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
-#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
-#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L
-#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L
-#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L
-#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
-//SQ_WAVE_FLUSH_IB
-#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
-#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP0
-#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP1
-#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP2
-#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP3
-#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP4
-#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP5
-#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP6
-#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP7
-#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP8
-#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP9
-#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP10
-#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP11
-#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP12
-#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP13
-#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP14
-#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP15
-#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_M0
-#define SQ_WAVE_M0__M0__SHIFT 0x0
-#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
-//SQ_WAVE_EXEC_LO
-#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
-#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
-//SQ_WAVE_EXEC_HI
-#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
-#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
-//SQ_INTERRUPT_WORD_AUTO_CTXID
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L
-//SQ_INTERRUPT_WORD_AUTO_HI
-#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L
-#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L
-//SQ_INTERRUPT_WORD_AUTO_LO
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
-#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3
-#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6
-#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L
-#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L
-#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L
-#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L
-#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L
-//SQ_INTERRUPT_WORD_CMN_CTXID
-#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L
-#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L
-//SQ_INTERRUPT_WORD_CMN_HI
-#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L
-#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L
-//SQ_INTERRUPT_WORD_WAVE_CTXID
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L
-//SQ_INTERRUPT_WORD_WAVE_HI
-#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL
-#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L
-#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L
-#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L
-//SQ_INTERRUPT_WORD_WAVE_LO
-#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19
-#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e
-#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL
-#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L
-#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L
-#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L
-#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L
-
-
-
-
-
-
-
-
-// addressBlock: didtind
-//DIDT_SQ_CTRL0
-#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_SQ_CTRL1
-#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_SQ_CTRL2
-#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_SQ_STALL_CTRL
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_SQ_TUNING_CTRL
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
-#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_SQ_CTRL3
-#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_SQ_STALL_PATTERN_1_2
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_STALL_PATTERN_3_4
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_STALL_PATTERN_5_6
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_STALL_PATTERN_7
-#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_SQ_WEIGHT0_3
-#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_SQ_WEIGHT4_7
-#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_SQ_WEIGHT8_11
-#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_SQ_EDC_CTRL
-#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_SQ_EDC_THRESHOLD
-#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_SQ_EDC_STALL_PATTERN_1_2
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_EDC_STALL_PATTERN_3_4
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_EDC_STALL_PATTERN_5_6
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_EDC_STALL_PATTERN_7
-#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_SQ_EDC_STATUS
-#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_SQ_EDC_STALL_DELAY_1
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12
-#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L
-#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
-//DIDT_SQ_EDC_STALL_DELAY_2
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12
-#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L
-#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
-//DIDT_SQ_EDC_STALL_DELAY_3
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0xc
-#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x0003F000L
-#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L
-//DIDT_SQ_EDC_OVERFLOW
-#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_SQ_EDC_ROLLING_POWER_DELTA
-#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_DB_CTRL0
-#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_DB_CTRL1
-#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_DB_CTRL2
-#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_DB_STALL_CTRL
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_DB_TUNING_CTRL
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_DB_STALL_AUTO_RELEASE_CTRL
-#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_DB_CTRL3
-#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_DB_STALL_PATTERN_1_2
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_STALL_PATTERN_3_4
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_STALL_PATTERN_5_6
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_STALL_PATTERN_7
-#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DB_WEIGHT0_3
-#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_DB_WEIGHT4_7
-#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_DB_WEIGHT8_11
-#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_DB_EDC_CTRL
-#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_DB_EDC_THRESHOLD
-#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_DB_EDC_STALL_PATTERN_1_2
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_EDC_STALL_PATTERN_3_4
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_EDC_STALL_PATTERN_5_6
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_EDC_STALL_PATTERN_7
-#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DB_EDC_STATUS
-#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_DB_EDC_STALL_DELAY_1
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x3
-#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x00000007L
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000038L
-#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L
-//DIDT_DB_EDC_OVERFLOW
-#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_DB_EDC_ROLLING_POWER_DELTA
-#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_TD_CTRL0
-#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_TD_CTRL1
-#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_TD_CTRL2
-#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_TD_STALL_CTRL
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_TD_TUNING_CTRL
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_TD_STALL_AUTO_RELEASE_CTRL
-#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_TD_CTRL3
-#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_TD_STALL_PATTERN_1_2
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_STALL_PATTERN_3_4
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_STALL_PATTERN_5_6
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_STALL_PATTERN_7
-#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TD_WEIGHT0_3
-#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_TD_WEIGHT4_7
-#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_TD_WEIGHT8_11
-#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_TD_EDC_CTRL
-#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_TD_EDC_THRESHOLD
-#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_TD_EDC_STALL_PATTERN_1_2
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_EDC_STALL_PATTERN_3_4
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_EDC_STALL_PATTERN_5_6
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_EDC_STALL_PATTERN_7
-#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TD_EDC_STATUS
-#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_TD_EDC_STALL_DELAY_1
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12
-#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L
-#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
-//DIDT_TD_EDC_STALL_DELAY_2
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12
-#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L
-#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
-//DIDT_TD_EDC_STALL_DELAY_3
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0xc
-#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x0003F000L
-#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L
-//DIDT_TD_EDC_OVERFLOW
-#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_TD_EDC_ROLLING_POWER_DELTA
-#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_TCP_CTRL0
-#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_TCP_CTRL1
-#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_TCP_CTRL2
-#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_TCP_STALL_CTRL
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_TCP_TUNING_CTRL
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
-#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_TCP_CTRL3
-#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_TCP_STALL_PATTERN_1_2
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_STALL_PATTERN_3_4
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_STALL_PATTERN_5_6
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_STALL_PATTERN_7
-#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TCP_WEIGHT0_3
-#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_TCP_WEIGHT4_7
-#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_TCP_WEIGHT8_11
-#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_TCP_EDC_CTRL
-#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_TCP_EDC_THRESHOLD
-#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_TCP_EDC_STALL_PATTERN_1_2
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_EDC_STALL_PATTERN_3_4
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_EDC_STALL_PATTERN_5_6
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_EDC_STALL_PATTERN_7
-#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TCP_EDC_STATUS
-#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_TCP_EDC_STALL_DELAY_1
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12
-#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L
-#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
-//DIDT_TCP_EDC_STALL_DELAY_2
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12
-#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L
-#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
-//DIDT_TCP_EDC_STALL_DELAY_3
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0xc
-#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x0003F000L
-#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L
-//DIDT_TCP_EDC_OVERFLOW
-#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_TCP_EDC_ROLLING_POWER_DELTA
-#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_DBR_CTRL0
-#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_DBR_CTRL1
-#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_DBR_CTRL2
-#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_DBR_STALL_CTRL
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_DBR_TUNING_CTRL
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_DBR_STALL_AUTO_RELEASE_CTRL
-#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_DBR_CTRL3
-#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_DBR_STALL_PATTERN_1_2
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_STALL_PATTERN_3_4
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_STALL_PATTERN_5_6
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_STALL_PATTERN_7
-#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DBR_WEIGHT0_3
-#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_DBR_WEIGHT4_7
-#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_DBR_WEIGHT8_11
-#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_DBR_EDC_CTRL
-#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_DBR_EDC_THRESHOLD
-#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_DBR_EDC_STALL_PATTERN_1_2
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_EDC_STALL_PATTERN_3_4
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_EDC_STALL_PATTERN_5_6
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_EDC_STALL_PATTERN_7
-#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DBR_EDC_STATUS
-#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4
-#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L
-//DIDT_DBR_EDC_STALL_DELAY_1
-#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x1
-#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000001L
-#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFFEL
-//DIDT_DBR_EDC_OVERFLOW
-#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_DBR_EDC_ROLLING_POWER_DELTA
-#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_SQ_STALL_EVENT_COUNTER
-#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_DB_STALL_EVENT_COUNTER
-#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_TD_STALL_EVENT_COUNTER
-#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_TCP_STALL_EVENT_COUNTER
-#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_DBR_STALL_EVENT_COUNTER
-#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-
-
-
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h
deleted file mode 100644
index 392ef77..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h
+++ /dev/null
@@ -1,1028 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mmhub_9_1_DEFAULT_HEADER
-#define _mmhub_9_1_DEFAULT_HEADER
-
-
-// addressBlock: mmhub_dagbdec
-#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI19_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI20_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI21_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI22_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI23_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI24_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI25_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI26_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI27_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI28_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI29_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI30_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RDCLI31_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8
-#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f
-#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039
-#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
-#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
-#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111
-#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408
-#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7
-#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI19_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI20_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI21_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI22_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI23_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI24_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI25_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI26_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI27_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI28_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI29_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI30_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WRCLI31_DEFAULT 0xfe5fe0f9
-#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8
-#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f
-#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039
-#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
-#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
-#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111
-#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_DEFAULT 0x11111111
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_DEFAULT 0x00000000
-#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082
-#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408
-#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7
-#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870
-#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88
-#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000
-#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000
-#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa
-#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000
-#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff
-#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000
-#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff
-#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff
-#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-#define mmDAGB0_RESERVE0_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE1_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE2_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE3_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE4_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE5_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE6_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE7_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE8_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE9_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE10_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE11_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE12_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE13_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE14_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE15_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE16_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE17_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE18_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE19_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE20_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE21_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE22_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE23_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE24_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE25_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE26_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE27_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE28_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE29_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE30_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE31_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE32_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE33_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE34_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE35_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE36_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE37_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE38_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE39_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE40_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE41_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE42_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE43_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE44_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE45_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE46_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE47_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE48_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE49_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE50_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE51_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE52_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE53_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE54_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE55_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE56_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE57_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE58_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE59_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE60_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE61_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE62_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE63_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE64_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE65_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE66_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE67_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE68_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE69_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE70_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE71_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE72_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE73_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE74_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE75_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE76_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE77_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE78_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE79_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE80_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE81_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE82_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE83_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE84_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE85_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE86_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE87_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE88_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE89_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE90_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE91_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE92_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE93_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE94_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE95_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE96_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE97_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE98_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE99_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE100_DEFAULT 0x00000000
-#define mmDAGB0_RESERVE101_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_ea_mmeadec
-#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555
-#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555
-#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555
-#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555
-#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25
-#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25
-#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924
-#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924
-#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333
-#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333
-#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000
-#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
-#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
-#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
-#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
-#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
-#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03
-#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
-#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
-#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040
-#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff
-#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
-#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000
-#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf
-#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000
-#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000
-#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000
-#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000
-#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000
-#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000
-#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f
-#define mmMMEA0_MISC_DEFAULT 0x00180130
-#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000
-#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000
-#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000
-#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000
-#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000
-#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000
-#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000
-#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000
-#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000
-#define mmMMEA0_MISC2_DEFAULT 0x00000000
-#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555
-#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555
-#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555
-#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555
-#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25
-#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25
-#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924
-#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924
-#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333
-#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333
-#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000
-#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
-#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
-#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
-#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
-#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
-#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03
-#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
-#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
-#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040
-#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff
-#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
-#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000
-#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf
-#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000
-#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000
-#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000
-#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000
-#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000
-#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000
-#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f
-#define mmMMEA1_MISC_DEFAULT 0x00180130
-#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000
-#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000
-#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000
-#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000
-#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000
-#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000
-#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000
-#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000
-#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000
-#define mmMMEA1_MISC2_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_pctldec
-#define mmPCTL_MISC_DEFAULT 0x00000889
-#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000
-#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000
-#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000
-#define mmPCTL_PG_DAGB_DEFAULT 0x00000000
-#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000
-#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000
-#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000
-#define mmPCTL0_MISC_DEFAULT 0x00001000
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
-#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
-#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
-#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000
-#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000
-#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000
-#define mmPCTL1_MISC_DEFAULT 0x00000800
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
-#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
-#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
-#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000
-#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000
-#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000
-#define mmPCTL2_MISC_DEFAULT 0x00000800
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
-#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
-#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
-
-
-// addressBlock: mmhub_l1tlb_vml1dec
-#define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_l1tlb_vml1pldec
-#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: mmhub_l1tlb_vml1prdec
-#define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_l1tlb_vmtlspfdec
-#define mmVM_L2_SAW_CNTL_DEFAULT 0x0c0b8602
-#define mmVM_L2_SAW_CNTL2_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CNTL3_DEFAULT 0x80100004
-#define mmVM_L2_SAW_CNTL4_DEFAULT 0x00000001
-#define mmVM_L2_SAW_CONTEXT0_CNTL_DEFAULT 0x00fffed8
-#define mmVM_L2_SAW_CONTEXT0_CNTL2_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_SAW_CONTEXTS_DISABLE_DEFAULT 0x00000000
-#define mmVM_L2_SAW_PIPES_BUSY_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_utcl2_atcl2dec
-#define mmATC_L2_CNTL_DEFAULT 0x000001c9
-#define mmATC_L2_CNTL2_DEFAULT 0x00000100
-#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000
-#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000
-#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000
-#define mmATC_L2_CNTL3_DEFAULT 0x000001f8
-#define mmATC_L2_STATUS_DEFAULT 0x00000000
-#define mmATC_L2_STATUS2_DEFAULT 0x00000000
-#define mmATC_L2_MISC_CG_DEFAULT 0x00000200
-#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: mmhub_utcl2_vml2pfdec
-#define mmVM_L2_CNTL_DEFAULT 0x00080602
-#define mmVM_L2_CNTL2_DEFAULT 0x00000000
-#define mmVM_L2_CNTL3_DEFAULT 0x80100007
-#define mmVM_L2_STATUS_DEFAULT 0x00000000
-#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
-#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
-#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CNTL4_DEFAULT 0x000000c1
-#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
-#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
-#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
-#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
-#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: mmhub_utcl2_vml2vcdec
-#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_utcl2_vml2pldec
-#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: mmhub_utcl2_vml2prdec
-#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_utcl2_vmsharedhvdec
-#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
-#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
-#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
-#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
-#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
-#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: mmhub_utcl2_vmsharedpfdec
-#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
-#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
-#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
-#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
-#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
-#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
-#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
-#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmMC_VM_STEERING_DEFAULT 0x00000001
-#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
-#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000
-#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
-#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
-#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_utcl2_vmsharedvcdec
-#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
-#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
-#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000
-#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000
-#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501
-
-
-// addressBlock: mmhub_utcl2_atcl2pfcntrdec
-#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: mmhub_utcl2_atcl2pfcntldec
-#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h
deleted file mode 100644
index 1445bba..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h
+++ /dev/null
@@ -1,1658 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma0_4_1_SH_MASK_HEADER
-#define _sdma0_4_1_SH_MASK_HEADER
-
-
-// addressBlock: sdma0_sdma0dec
-//SDMA0_UCODE_ADDR
-#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
-#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
-//SDMA0_UCODE_DATA
-#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
-#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_VM_CNTL
-#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
-#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
-//SDMA0_VM_CTX_LO
-#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
-#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_VM_CTX_HI
-#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
-#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_ACTIVE_FCN_ID
-#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//SDMA0_VM_CTX_CNTL
-#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
-#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
-#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L
-#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L
-//SDMA0_VIRT_RESET_REQ
-#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//SDMA0_CONTEXT_REG_TYPE0
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L
-//SDMA0_CONTEXT_REG_TYPE1
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
-#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
-#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L
-#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
-#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
-//SDMA0_CONTEXT_REG_TYPE2
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
-//SDMA0_CONTEXT_REG_TYPE3
-#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
-//SDMA0_PUB_REG_TYPE0
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE1
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE2
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE3
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
-//SDMA0_MMHUB_CNTL
-#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
-#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
-//SDMA0_CONTEXT_GROUP_BOUNDARY
-#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
-#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
-//SDMA0_POWER_CNTL
-#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
-#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
-#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
-#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
-#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
-#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
-#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
-#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
-#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
-#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
-#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
-#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
-#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
-#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
-#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
-#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
-//SDMA0_CLK_CTRL
-#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//SDMA0_CNTL
-#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
-#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
-#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
-#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
-#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
-#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
-#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
-#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
-#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
-#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
-#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
-#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
-#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
-#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
-#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
-#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
-#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
-#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
-#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
-#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
-//SDMA0_CHICKEN_BITS
-#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
-#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
-#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
-#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
-#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
-#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
-#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
-#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
-#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
-#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
-#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
-#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
-#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
-#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
-#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
-#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
-#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
-#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
-#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
-#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
-#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
-#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
-//SDMA0_GB_ADDR_CONFIG
-#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA0_GB_ADDR_CONFIG_READ
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
-#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
-#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA0_RB_RPTR_FETCH_HI
-#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
-//SDMA0_RB_RPTR_FETCH
-#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
-#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
-//SDMA0_IB_OFFSET_FETCH
-#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
-#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
-//SDMA0_PROGRAM
-#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
-#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
-//SDMA0_STATUS_REG
-#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
-#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
-#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
-#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
-#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
-#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
-#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
-#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
-#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
-#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
-#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
-#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
-#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
-#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
-#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
-#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
-#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
-#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
-#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
-#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
-#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
-#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
-#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
-#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
-#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
-#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
-#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
-#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
-#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
-#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
-#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
-#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
-#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
-#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
-#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
-#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
-#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
-#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
-#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
-#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
-#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
-#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
-#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
-#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
-#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
-#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
-#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
-#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
-#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
-#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
-#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
-#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
-#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
-#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
-#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
-#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
-#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
-#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
-//SDMA0_STATUS1_REG
-#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
-#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
-#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
-#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
-#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
-#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
-#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
-#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
-#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
-#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
-#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
-#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
-#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
-#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
-#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
-#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
-#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
-#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
-#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
-#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
-#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
-#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
-#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
-#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
-#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
-#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
-#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
-#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
-//SDMA0_RD_BURST_CNTL
-#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
-#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
-//SDMA0_HBM_PAGE_CONFIG
-#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
-#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
-//SDMA0_UCODE_CHECKSUM
-#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
-#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
-//SDMA0_F32_CNTL
-#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
-#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
-#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
-#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
-//SDMA0_FREEZE
-#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
-#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
-#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
-#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
-#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
-#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
-#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
-#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
-//SDMA0_PHASE0_QUANTUM
-#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA0_PHASE1_QUANTUM
-#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA_POWER_GATING
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
-#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
-#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
-//SDMA_PGFSM_CONFIG
-#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
-#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
-#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
-#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
-#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
-#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
-#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
-#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
-#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
-#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
-#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
-#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
-#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
-#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
-#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
-#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
-#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
-#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
-//SDMA_PGFSM_WRITE
-#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
-#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
-//SDMA_PGFSM_READ
-#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
-#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
-//SDMA0_EDC_CONFIG
-#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
-#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
-//SDMA0_BA_THRESHOLD
-#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
-#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
-#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
-#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
-//SDMA0_ID
-#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
-#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
-//SDMA0_VERSION
-#define SDMA0_VERSION__MINVER__SHIFT 0x0
-#define SDMA0_VERSION__MAJVER__SHIFT 0x8
-#define SDMA0_VERSION__REV__SHIFT 0x10
-#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
-#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
-#define SDMA0_VERSION__REV_MASK 0x003F0000L
-//SDMA0_EDC_COUNTER
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
-#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
-#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
-#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
-#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
-#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
-#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
-#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
-#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
-#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
-#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
-//SDMA0_EDC_COUNTER_CLEAR
-#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
-#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
-//SDMA0_STATUS2_REG
-#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
-#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
-#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
-#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
-#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
-#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
-//SDMA0_ATOMIC_CNTL
-#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
-#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
-#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
-#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
-//SDMA0_ATOMIC_PREOP_LO
-#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
-#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
-//SDMA0_ATOMIC_PREOP_HI
-#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
-#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_CNTL
-#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
-#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
-#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
-#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
-#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
-#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
-#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
-#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
-#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
-#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
-#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
-#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
-//SDMA0_UTCL1_WATERMK
-#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
-#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
-#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
-#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
-#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
-#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
-#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
-#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
-//SDMA0_UTCL1_RD_STATUS
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
-#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
-#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
-#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
-#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
-#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
-#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
-#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
-#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
-#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
-#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
-//SDMA0_UTCL1_WR_STATUS
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
-#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
-#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
-#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
-#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
-//SDMA0_UTCL1_INV0
-#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
-#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
-#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
-#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
-#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
-#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
-#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
-#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
-#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
-#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
-#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
-#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
-#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
-#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
-#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
-#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
-#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
-#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
-#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
-#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
-#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
-#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
-#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
-#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
-#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
-#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
-#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
-#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
-//SDMA0_UTCL1_INV1
-#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_INV2
-#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
-#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_RD_XNACK0
-#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_RD_XNACK1
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA0_UTCL1_WR_XNACK0
-#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_WR_XNACK1
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA0_UTCL1_TIMEOUT
-#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
-#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
-#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
-#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
-//SDMA0_UTCL1_PAGE
-#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
-#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
-#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
-#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
-#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
-#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
-#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
-#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
-//SDMA0_POWER_CNTL_IDLE
-#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
-#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
-#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
-#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
-#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
-#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
-//SDMA0_RELAX_ORDERING_LUT
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
-#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
-#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
-#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
-#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
-#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
-#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
-#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
-#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
-#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
-#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
-#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
-#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
-#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
-#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
-#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
-#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
-#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
-#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
-#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
-#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
-#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
-#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
-#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
-#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
-#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
-#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
-#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
-#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
-//SDMA0_CHICKEN_BITS_2
-#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
-#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
-//SDMA0_STATUS3_REG
-#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
-#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
-#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
-#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
-#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
-#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
-//SDMA0_PHYSICAL_ADDR_LO
-#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
-#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
-#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
-#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
-#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
-#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
-#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
-#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
-//SDMA0_PHYSICAL_ADDR_HI
-#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
-//SDMA0_ERROR_LOG
-#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0
-#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10
-#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
-#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L
-//SDMA0_PUB_DUMMY_REG0
-#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG1
-#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG2
-#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG3
-#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_F32_COUNTER
-#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
-#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_UNBREAKABLE
-#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0
-#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L
-//SDMA0_PERFMON_CNTL
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
-#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
-#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
-#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
-#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
-//SDMA0_PERFCOUNTER0_RESULT
-#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA0_PERFCOUNTER1_RESULT
-#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
-//SDMA0_CRD_CNTL
-#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
-#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
-#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
-#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
-//SDMA0_MMHUB_TRUSTLVL
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
-//SDMA0_GPU_IOV_VIOLATION_LOG
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
-#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//SDMA0_ULV_CNTL
-#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0
-#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
-#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
-#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
-#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
-#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
-#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
-#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
-//SDMA0_EA_DBIT_ADDR_DATA
-#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
-#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_EA_DBIT_ADDR_INDEX
-#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
-#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
-//SDMA0_GFX_RB_CNTL
-#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_GFX_RB_BASE
-#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_BASE_HI
-#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_GFX_RB_RPTR
-#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_RPTR_HI
-#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR
-#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_HI
-#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_CNTL
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_GFX_RB_RPTR_ADDR_HI
-#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_RPTR_ADDR_LO
-#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_IB_CNTL
-#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_GFX_IB_RPTR
-#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_GFX_IB_OFFSET
-#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_GFX_IB_BASE_LO
-#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_GFX_IB_BASE_HI
-#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_IB_SIZE
-#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_GFX_SKIP_CNTL
-#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_GFX_CONTEXT_STATUS
-#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_GFX_DOORBELL
-#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_GFX_CONTEXT_CNTL
-#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
-#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
-//SDMA0_GFX_STATUS
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_GFX_DOORBELL_LOG
-#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_GFX_WATERMARK
-#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_GFX_DOORBELL_OFFSET
-#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_GFX_CSA_ADDR_LO
-#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_CSA_ADDR_HI
-#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_IB_SUB_REMAIN
-#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_GFX_PREEMPT
-#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_GFX_DUMMY_REG
-#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_RB_AQL_CNTL
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_GFX_MINOR_PTR_UPDATE
-#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_GFX_MIDCMD_DATA0
-#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA1
-#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA2
-#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA3
-#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA4
-#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA5
-#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA6
-#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA7
-#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA8
-#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_CNTL
-#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_RLC0_RB_CNTL
-#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_RLC0_RB_BASE
-#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_BASE_HI
-#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_RLC0_RB_RPTR
-#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_RPTR_HI
-#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR
-#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_HI
-#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_CNTL
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_RLC0_RB_RPTR_ADDR_HI
-#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_RPTR_ADDR_LO
-#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_IB_CNTL
-#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_RLC0_IB_RPTR
-#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC0_IB_OFFSET
-#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC0_IB_BASE_LO
-#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_RLC0_IB_BASE_HI
-#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_IB_SIZE
-#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_RLC0_SKIP_CNTL
-#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_RLC0_CONTEXT_STATUS
-#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_RLC0_DOORBELL
-#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_RLC0_STATUS
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_RLC0_DOORBELL_LOG
-#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_WATERMARK
-#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_RLC0_DOORBELL_OFFSET
-#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_RLC0_CSA_ADDR_LO
-#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_CSA_ADDR_HI
-#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_IB_SUB_REMAIN
-#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_RLC0_PREEMPT
-#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_RLC0_DUMMY_REG
-#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_RB_AQL_CNTL
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_RLC0_MINOR_PTR_UPDATE
-#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_RLC0_MIDCMD_DATA0
-#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA1
-#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA2
-#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA3
-#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA4
-#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA5
-#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA6
-#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA7
-#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA8
-#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_CNTL
-#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_RLC1_RB_CNTL
-#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_RLC1_RB_BASE
-#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_BASE_HI
-#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_RLC1_RB_RPTR
-#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_RPTR_HI
-#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR
-#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_HI
-#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_CNTL
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_RLC1_RB_RPTR_ADDR_HI
-#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_RPTR_ADDR_LO
-#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_IB_CNTL
-#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_RLC1_IB_RPTR
-#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC1_IB_OFFSET
-#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC1_IB_BASE_LO
-#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_RLC1_IB_BASE_HI
-#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_IB_SIZE
-#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_RLC1_SKIP_CNTL
-#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_RLC1_CONTEXT_STATUS
-#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_RLC1_DOORBELL
-#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_RLC1_STATUS
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_RLC1_DOORBELL_LOG
-#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_WATERMARK
-#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_RLC1_DOORBELL_OFFSET
-#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_RLC1_CSA_ADDR_LO
-#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_CSA_ADDR_HI
-#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_IB_SUB_REMAIN
-#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_RLC1_PREEMPT
-#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_RLC1_DUMMY_REG
-#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_RB_AQL_CNTL
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_RLC1_MINOR_PTR_UPDATE
-#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_RLC1_MIDCMD_DATA0
-#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA1
-#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA2
-#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA3
-#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA4
-#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA5
-#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA6
-#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA7
-#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA8
-#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_CNTL
-#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
deleted file mode 100644
index 5793a10..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _vcn_1_0_DEFAULT_HEADER
-#define _vcn_1_0_DEFAULT_HEADER
-
-
-// addressBlock: uvd_uvd_pg_dec
-#define mmUVD_PGFSM_CONFIG_DEFAULT 0x00000000
-#define mmUVD_PGFSM_STATUS_DEFAULT 0x002aaaaa
-#define mmUVD_POWER_STATUS_DEFAULT 0x00000801
-#define mmCC_UVD_HARVESTING_DEFAULT 0x00000000
-#define mmUVD_SCRATCH1_DEFAULT 0x00000000
-#define mmUVD_SCRATCH2_DEFAULT 0x00000000
-#define mmUVD_SCRATCH3_DEFAULT 0x00000000
-#define mmUVD_SCRATCH4_DEFAULT 0x00000000
-#define mmUVD_SCRATCH5_DEFAULT 0x00000000
-#define mmUVD_SCRATCH6_DEFAULT 0x00000000
-#define mmUVD_SCRATCH7_DEFAULT 0x00000000
-#define mmUVD_SCRATCH8_DEFAULT 0x00000000
-#define mmUVD_SCRATCH9_DEFAULT 0x00000000
-#define mmUVD_SCRATCH10_DEFAULT 0x00000000
-#define mmUVD_SCRATCH11_DEFAULT 0x00000000
-#define mmUVD_SCRATCH12_DEFAULT 0x00000000
-#define mmUVD_SCRATCH13_DEFAULT 0x00000000
-#define mmUVD_SCRATCH14_DEFAULT 0x00000000
-#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
-
-
-// addressBlock: uvd_uvdgendec
-#define mmUVD_LCM_CGC_CNTRL_DEFAULT 0xa0f00000
-
-
-// addressBlock: uvd_uvdnpdec
-#define mmUVD_JPEG_CNTL_DEFAULT 0x00000004
-#define mmUVD_JPEG_RB_BASE_DEFAULT 0x00000000
-#define mmUVD_JPEG_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_JPEG_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_JPEG_RB_SIZE_DEFAULT 0x00000000
-#define mmUVD_JPEG_UV_TILING_CTRL_DEFAULT 0x02104800
-#define mmUVD_JPEG_TILING_CTRL_DEFAULT 0x02104800
-#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_JPEG_GPCOM_CMD_DEFAULT 0x00000000
-#define mmUVD_JPEG_GPCOM_DATA0_DEFAULT 0x00000000
-#define mmUVD_JPEG_GPCOM_DATA1_DEFAULT 0x00000000
-#define mmUVD_JPEG_JRB_BASE_LO_DEFAULT 0x00000000
-#define mmUVD_JPEG_JRB_BASE_HI_DEFAULT 0x00000000
-#define mmUVD_JPEG_JRB_SIZE_DEFAULT 0x00000000
-#define mmUVD_JPEG_JRB_RPTR_DEFAULT 0x00000000
-#define mmUVD_JPEG_JRB_WPTR_DEFAULT 0x00000000
-#define mmUVD_JPEG_UV_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_SEMA_ADDR_LOW_DEFAULT 0x00000000
-#define mmUVD_SEMA_ADDR_HIGH_DEFAULT 0x00000000
-#define mmUVD_SEMA_CMD_DEFAULT 0x00000080
-#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000
-#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000
-#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000
-#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000
-#define mmUVD_SUVD_CGC_STATUS_DEFAULT 0x00000000
-#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_NO_OP_DEFAULT 0x00000000
-#define mmUVD_JPEG_CNTL2_DEFAULT 0x00000000
-#define mmUVD_VERSION_DEFAULT 0x00010000
-#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH9_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH10_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH11_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH12_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH13_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH14_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH15_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH16_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH17_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH18_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH19_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH20_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH21_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH22_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH23_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE2_DEFAULT 0x00000000
-#define mmUVD_RB_RPTR2_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR2_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE_DEFAULT 0x00000000
-#define mmUVD_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR4_DEFAULT 0x00000000
-#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: uvd_uvddec
-#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003
-#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_JRBC_IB_VMID_DEFAULT 0x00000000
-#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_JRBC_RB_CNTL_DEFAULT 0x00000100
-#define mmUVD_JRBC_IB_SIZE_DEFAULT 0x00000000
-#define mmUVD_JRBC_LMI_SWAP_CNTL_DEFAULT 0x00000000
-#define mmUVD_JRBC_SOFT_RESET_DEFAULT 0x00000000
-#define mmUVD_JRBC_STATUS_DEFAULT 0x00000003
-#define mmUVD_RB_RPTR3_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR3_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE3_DEFAULT 0x00000000
-#define mmJPEG_CGC_GATE_DEFAULT 0x00300000
-#define mmUVD_CTX_INDEX_DEFAULT 0x00000000
-#define mmUVD_CTX_DATA_DEFAULT 0x00000000
-#define mmUVD_CGC_GATE_DEFAULT 0x000fffff
-#define mmUVD_CGC_STATUS_DEFAULT 0x00000000
-#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d
-#define mmUVD_GP_SCRATCH0_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH1_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH2_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH3_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH5_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH6_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH7_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE_VMID_DEFAULT 0x00000000
-#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000
-#define mmUVD_MASTINT_EN_DEFAULT 0x00000000
-#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d
-#define mmUVD_LMI_CTRL_DEFAULT 0x00104340
-#define mmUVD_LMI_STATUS_DEFAULT 0x003fff7f
-#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000
-#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000
-#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040
-#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000
-#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040
-#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000
-#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088
-#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000
-#define mmUVD_GPCOM_SYS_CMD_DEFAULT 0x00000000
-#define mmUVD_GPCOM_SYS_DATA0_DEFAULT 0x00000000
-#define mmUVD_GPCOM_SYS_DATA1_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
-#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000
-#define mmUVD_SOFT_RESET_DEFAULT 0x00000008
-#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000
-#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101
-#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000
-#define mmUVD_STATUS_DEFAULT 0x00000000
-#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000
-#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000
-#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000
-#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000
-#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000
-#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000
-#define mmUVD_RBC_WPTR_POLL_CNTL_DEFAULT 0x00400100
-#define mmUVD_RBC_WPTR_POLL_ADDR_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO4_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI4_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE4_DEFAULT 0x00000000
-#define mmUVD_RB_RPTR4_DEFAULT 0x00000000
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
new file mode 100644
index 0000000..4be3cb5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma0_4_0_DEFAULT_HEADER
+#define _sdma0_4_0_DEFAULT_HEADER
+
+
+// addressBlock: sdma0_sdma0dec
+#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
+#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
+#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
+#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
+#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
+#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
+#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000
+#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882
+#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
+#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
+#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000
+#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100
+#define mmSDMA0_CNTL_DEFAULT 0x00000002
+#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07
+#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012
+#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
+#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
+#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
+#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
+#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
+#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
+#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003
+#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
+#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
+#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
+#define mmSDMA0_FREEZE_DEFAULT 0x00000000
+#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA_POWER_GATING_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000
+#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
+#define mmSDMA0_ID_DEFAULT 0x00000001
+#define mmSDMA0_VERSION_DEFAULT 0x00000400
+#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
+#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
+#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
+#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
+#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019
+#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
+#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff
+#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff
+#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600
+#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001
+#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0
+#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200
+#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
+#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005
+#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000
+#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f
+#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
+#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
+#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
+#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
+#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
+#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000
+#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd
+#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
+#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0
+#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
+#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
+#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
new file mode 100644
index 0000000..9975869
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
@@ -0,0 +1,547 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma0_4_0_OFFSET_HEADER
+#define _sdma0_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: sdma0_sdma0dec
+// base address: 0x4980
+#define mmSDMA0_UCODE_ADDR 0x0000
+#define mmSDMA0_UCODE_ADDR_BASE_IDX 0
+#define mmSDMA0_UCODE_DATA 0x0001
+#define mmSDMA0_UCODE_DATA_BASE_IDX 0
+#define mmSDMA0_VM_CNTL 0x0004
+#define mmSDMA0_VM_CNTL_BASE_IDX 0
+#define mmSDMA0_VM_CTX_LO 0x0005
+#define mmSDMA0_VM_CTX_LO_BASE_IDX 0
+#define mmSDMA0_VM_CTX_HI 0x0006
+#define mmSDMA0_VM_CTX_HI_BASE_IDX 0
+#define mmSDMA0_ACTIVE_FCN_ID 0x0007
+#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmSDMA0_VM_CTX_CNTL 0x0008
+#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0
+#define mmSDMA0_VIRT_RESET_REQ 0x0009
+#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0
+#define mmSDMA0_VF_ENABLE 0x000a
+#define mmSDMA0_VF_ENABLE_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b
+#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c
+#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d
+#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e
+#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE0 0x000f
+#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE1 0x0010
+#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE2 0x0011
+#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE3 0x0012
+#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0
+#define mmSDMA0_MMHUB_CNTL 0x0013
+#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0
+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019
+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define mmSDMA0_POWER_CNTL 0x001a
+#define mmSDMA0_POWER_CNTL_BASE_IDX 0
+#define mmSDMA0_CLK_CTRL 0x001b
+#define mmSDMA0_CLK_CTRL_BASE_IDX 0
+#define mmSDMA0_CNTL 0x001c
+#define mmSDMA0_CNTL_BASE_IDX 0
+#define mmSDMA0_CHICKEN_BITS 0x001d
+#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0
+#define mmSDMA0_GB_ADDR_CONFIG 0x001e
+#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
+#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f
+#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020
+#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define mmSDMA0_RB_RPTR_FETCH 0x0022
+#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0
+#define mmSDMA0_IB_OFFSET_FETCH 0x0023
+#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0
+#define mmSDMA0_PROGRAM 0x0024
+#define mmSDMA0_PROGRAM_BASE_IDX 0
+#define mmSDMA0_STATUS_REG 0x0025
+#define mmSDMA0_STATUS_REG_BASE_IDX 0
+#define mmSDMA0_STATUS1_REG 0x0026
+#define mmSDMA0_STATUS1_REG_BASE_IDX 0
+#define mmSDMA0_RD_BURST_CNTL 0x0027
+#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0
+#define mmSDMA0_HBM_PAGE_CONFIG 0x0028
+#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0
+#define mmSDMA0_UCODE_CHECKSUM 0x0029
+#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0
+#define mmSDMA0_F32_CNTL 0x002a
+#define mmSDMA0_F32_CNTL_BASE_IDX 0
+#define mmSDMA0_FREEZE 0x002b
+#define mmSDMA0_FREEZE_BASE_IDX 0
+#define mmSDMA0_PHASE0_QUANTUM 0x002c
+#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0
+#define mmSDMA0_PHASE1_QUANTUM 0x002d
+#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0
+#define mmSDMA_POWER_GATING 0x002e
+#define mmSDMA_POWER_GATING_BASE_IDX 0
+#define mmSDMA_PGFSM_CONFIG 0x002f
+#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0
+#define mmSDMA_PGFSM_WRITE 0x0030
+#define mmSDMA_PGFSM_WRITE_BASE_IDX 0
+#define mmSDMA_PGFSM_READ 0x0031
+#define mmSDMA_PGFSM_READ_BASE_IDX 0
+#define mmSDMA0_EDC_CONFIG 0x0032
+#define mmSDMA0_EDC_CONFIG_BASE_IDX 0
+#define mmSDMA0_BA_THRESHOLD 0x0033
+#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0
+#define mmSDMA0_ID 0x0034
+#define mmSDMA0_ID_BASE_IDX 0
+#define mmSDMA0_VERSION 0x0035
+#define mmSDMA0_VERSION_BASE_IDX 0
+#define mmSDMA0_EDC_COUNTER 0x0036
+#define mmSDMA0_EDC_COUNTER_BASE_IDX 0
+#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037
+#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0
+#define mmSDMA0_STATUS2_REG 0x0038
+#define mmSDMA0_STATUS2_REG_BASE_IDX 0
+#define mmSDMA0_ATOMIC_CNTL 0x0039
+#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0
+#define mmSDMA0_ATOMIC_PREOP_LO 0x003a
+#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0
+#define mmSDMA0_ATOMIC_PREOP_HI 0x003b
+#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0
+#define mmSDMA0_UTCL1_CNTL 0x003c
+#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0
+#define mmSDMA0_UTCL1_WATERMK 0x003d
+#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_STATUS 0x003e
+#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_STATUS 0x003f
+#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV0 0x0040
+#define mmSDMA0_UTCL1_INV0_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV1 0x0041
+#define mmSDMA0_UTCL1_INV1_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV2 0x0042
+#define mmSDMA0_UTCL1_INV2_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_XNACK0 0x0043
+#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_XNACK1 0x0044
+#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_XNACK0 0x0045
+#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_XNACK1 0x0046
+#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0
+#define mmSDMA0_UTCL1_TIMEOUT 0x0047
+#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0
+#define mmSDMA0_UTCL1_PAGE 0x0048
+#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0
+#define mmSDMA0_POWER_CNTL_IDLE 0x0049
+#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0
+#define mmSDMA0_RELAX_ORDERING_LUT 0x004a
+#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0
+#define mmSDMA0_CHICKEN_BITS_2 0x004b
+#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0
+#define mmSDMA0_STATUS3_REG 0x004c
+#define mmSDMA0_STATUS3_REG_BASE_IDX 0
+#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d
+#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e
+#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PHASE2_QUANTUM 0x004f
+#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0
+#define mmSDMA0_ERROR_LOG 0x0050
+#define mmSDMA0_ERROR_LOG_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG0 0x0051
+#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG1 0x0052
+#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG2 0x0053
+#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG3 0x0054
+#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0
+#define mmSDMA0_F32_COUNTER 0x0055
+#define mmSDMA0_F32_COUNTER_BASE_IDX 0
+#define mmSDMA0_UNBREAKABLE 0x0056
+#define mmSDMA0_UNBREAKABLE_BASE_IDX 0
+#define mmSDMA0_PERFMON_CNTL 0x0057
+#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058
+#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059
+#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
+#define mmSDMA0_CRD_CNTL 0x005b
+#define mmSDMA0_CRD_CNTL_BASE_IDX 0
+#define mmSDMA0_MMHUB_TRUSTLVL 0x005c
+#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmSDMA0_ULV_CNTL 0x005e
+#define mmSDMA0_ULV_CNTL_BASE_IDX 0
+#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060
+#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061
+#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define mmSDMA0_GFX_RB_CNTL 0x0080
+#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_RB_BASE 0x0081
+#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0
+#define mmSDMA0_GFX_RB_BASE_HI 0x0082
+#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR 0x0083
+#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_HI 0x0084
+#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR 0x0085
+#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_HI 0x0086
+#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_IB_CNTL 0x008a
+#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_IB_RPTR 0x008b
+#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_GFX_IB_OFFSET 0x008c
+#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_GFX_IB_BASE_LO 0x008d
+#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_GFX_IB_BASE_HI 0x008e
+#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_GFX_IB_SIZE 0x008f
+#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_GFX_SKIP_CNTL 0x0090
+#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091
+#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL 0x0092
+#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093
+#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_STATUS 0x00a8
+#define mmSDMA0_GFX_STATUS_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9
+#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_GFX_WATERMARK 0x00aa
+#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab
+#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac
+#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad
+#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af
+#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_GFX_PREEMPT 0x00b0
+#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0
+#define mmSDMA0_GFX_DUMMY_REG 0x00b1
+#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4
+#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0
+#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1
+#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2
+#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3
+#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4
+#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5
+#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6
+#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7
+#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8
+#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9
+#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_CNTL 0x00e0
+#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_BASE 0x00e1
+#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2
+#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR 0x00e3
+#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4
+#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR 0x00e5
+#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6
+#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_CNTL 0x00ea
+#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_RPTR 0x00eb
+#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_OFFSET 0x00ec
+#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed
+#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee
+#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_SIZE 0x00ef
+#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0
+#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1
+#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL 0x00f2
+#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0
+#define mmSDMA0_PAGE_STATUS 0x0108
+#define mmSDMA0_PAGE_STATUS_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109
+#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_PAGE_WATERMARK 0x010a
+#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b
+#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c
+#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d
+#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f
+#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_PAGE_PREEMPT 0x0110
+#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0
+#define mmSDMA0_PAGE_DUMMY_REG 0x0111
+#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114
+#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120
+#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121
+#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122
+#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123
+#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124
+#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125
+#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126
+#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127
+#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128
+#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129
+#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_CNTL 0x0140
+#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_BASE 0x0141
+#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_BASE_HI 0x0142
+#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR 0x0143
+#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144
+#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR 0x0145
+#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146
+#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_CNTL 0x014a
+#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_RPTR 0x014b
+#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_OFFSET 0x014c
+#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_BASE_LO 0x014d
+#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_BASE_HI 0x014e
+#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_SIZE 0x014f
+#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC0_SKIP_CNTL 0x0150
+#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151
+#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL 0x0152
+#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC0_STATUS 0x0168
+#define mmSDMA0_RLC0_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169
+#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_RLC0_WATERMARK 0x016a
+#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b
+#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c
+#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d
+#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f
+#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC0_PREEMPT 0x0170
+#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC0_DUMMY_REG 0x0171
+#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174
+#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180
+#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181
+#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182
+#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183
+#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184
+#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185
+#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186
+#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187
+#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188
+#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189
+#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_CNTL 0x01a0
+#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_BASE 0x01a1
+#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2
+#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR 0x01a3
+#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4
+#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR 0x01a5
+#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6
+#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_CNTL 0x01aa
+#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_RPTR 0x01ab
+#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_OFFSET 0x01ac
+#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad
+#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae
+#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_SIZE 0x01af
+#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0
+#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1
+#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL 0x01b2
+#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC1_STATUS 0x01c8
+#define mmSDMA0_RLC1_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9
+#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_RLC1_WATERMARK 0x01ca
+#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb
+#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc
+#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd
+#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf
+#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC1_PREEMPT 0x01d0
+#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC1_DUMMY_REG 0x01d1
+#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4
+#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0
+#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1
+#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2
+#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3
+#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4
+#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5
+#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6
+#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7
+#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8
+#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9
+#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h
new file mode 100644
index 0000000..f846cc8
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h
@@ -0,0 +1,1852 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma0_4_0_SH_MASK_HEADER
+#define _sdma0_4_0_SH_MASK_HEADER
+
+
+// addressBlock: sdma0_sdma0dec
+//SDMA0_UCODE_ADDR
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
+//SDMA0_UCODE_DATA
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_VM_CNTL
+#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
+//SDMA0_VM_CTX_LO
+#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_VM_CTX_HI
+#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_ACTIVE_FCN_ID
+#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SDMA0_VM_CTX_CNTL
+#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L
+#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA0_VIRT_RESET_REQ
+#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SDMA0_VF_ENABLE
+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+//SDMA0_CONTEXT_REG_TYPE0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L
+//SDMA0_CONTEXT_REG_TYPE1
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
+//SDMA0_CONTEXT_REG_TYPE2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
+//SDMA0_CONTEXT_REG_TYPE3
+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
+//SDMA0_PUB_REG_TYPE0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L
+#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L
+#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L
+//SDMA0_PUB_REG_TYPE1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L
+//SDMA0_PUB_REG_TYPE2
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L
+#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
+//SDMA0_PUB_REG_TYPE3
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
+//SDMA0_MMHUB_CNTL
+#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
+#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
+//SDMA0_CONTEXT_GROUP_BOUNDARY
+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA0_POWER_CNTL
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+//SDMA0_CLK_CTRL
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA0_CNTL
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA0_CHICKEN_BITS
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
+//SDMA0_GB_ADDR_CONFIG
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_GB_ADDR_CONFIG_READ
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_RB_RPTR_FETCH_HI
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA0_RB_RPTR_FETCH
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA0_IB_OFFSET_FETCH
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PROGRAM
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA0_STATUS_REG
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA0_STATUS1_REG
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA0_RD_BURST_CNTL
+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+//SDMA0_HBM_PAGE_CONFIG
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA0_UCODE_CHECKSUM
+#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA0_F32_CNTL
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
+//SDMA0_FREEZE
+#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA0_PHASE0_QUANTUM
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_PHASE1_QUANTUM
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA_POWER_GATING
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
+//SDMA_PGFSM_CONFIG
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
+//SDMA_PGFSM_WRITE
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
+//SDMA_PGFSM_READ
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
+//SDMA0_EDC_CONFIG
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
+//SDMA0_BA_THRESHOLD
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA0_ID
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA0_VERSION
+#define SDMA0_VERSION__MINVER__SHIFT 0x0
+#define SDMA0_VERSION__MAJVER__SHIFT 0x8
+#define SDMA0_VERSION__REV__SHIFT 0x10
+#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA0_VERSION__REV_MASK 0x003F0000L
+//SDMA0_EDC_COUNTER
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
+//SDMA0_EDC_COUNTER_CLEAR
+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
+//SDMA0_STATUS2_REG
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA0_ATOMIC_CNTL
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA0_ATOMIC_PREOP_LO
+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA0_ATOMIC_PREOP_HI
+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_CNTL
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA0_UTCL1_WATERMK
+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
+//SDMA0_UTCL1_RD_STATUS
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA0_UTCL1_WR_STATUS
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA0_UTCL1_INV0
+#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA0_UTCL1_INV1
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_INV2
+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK1
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_WR_XNACK0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_WR_XNACK1
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_TIMEOUT
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA0_UTCL1_PAGE
+#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA0_POWER_CNTL_IDLE
+#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA0_RELAX_ORDERING_LUT
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA0_CHICKEN_BITS_2
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+//SDMA0_STATUS3_REG
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+//SDMA0_PHYSICAL_ADDR_LO
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA0_PHYSICAL_ADDR_HI
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA0_PHASE2_QUANTUM
+#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_ERROR_LOG
+#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA0_PUB_DUMMY_REG0
+#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG1
+#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG2
+#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG3
+#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_F32_COUNTER
+#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_UNBREAKABLE
+#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0
+#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L
+//SDMA0_PERFMON_CNTL
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SDMA0_PERFCOUNTER0_RESULT
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER1_RESULT
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
+//SDMA0_CRD_CNTL
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA0_MMHUB_TRUSTLVL
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
+//SDMA0_GPU_IOV_VIOLATION_LOG
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//SDMA0_ULV_CNTL
+#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA0_EA_DBIT_ADDR_DATA
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_EA_DBIT_ADDR_INDEX
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA0_GFX_RB_CNTL
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_GFX_RB_BASE
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_BASE_HI
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_GFX_RB_RPTR
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_HI
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_HI
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_CNTL
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_GFX_RB_RPTR_ADDR_HI
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_ADDR_LO
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_IB_CNTL
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_GFX_IB_RPTR
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_OFFSET
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_BASE_LO
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_GFX_IB_BASE_HI
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SIZE
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_GFX_SKIP_CNTL
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_GFX_CONTEXT_STATUS
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_GFX_DOORBELL
+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_GFX_CONTEXT_CNTL
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+//SDMA0_GFX_STATUS
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_GFX_DOORBELL_LOG
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_GFX_WATERMARK
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_GFX_DOORBELL_OFFSET
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_GFX_CSA_ADDR_LO
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_CSA_ADDR_HI
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SUB_REMAIN
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_GFX_PREEMPT
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_GFX_DUMMY_REG
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_RB_AQL_CNTL
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_GFX_MINOR_PTR_UPDATE
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_GFX_MIDCMD_DATA0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA1
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA2
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA3
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA4
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA5
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA6
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA7
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA8
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_CNTL
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_PAGE_RB_CNTL
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_PAGE_RB_BASE
+#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_BASE_HI
+#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_PAGE_RB_RPTR
+#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_HI
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR
+#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_HI
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_PAGE_RB_RPTR_ADDR_HI
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_ADDR_LO
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_IB_CNTL
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_PAGE_IB_RPTR
+#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_OFFSET
+#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_BASE_LO
+#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_PAGE_IB_BASE_HI
+#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SIZE
+#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_PAGE_SKIP_CNTL
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_PAGE_CONTEXT_STATUS
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_PAGE_DOORBELL
+#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_PAGE_STATUS
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_PAGE_DOORBELL_LOG
+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_WATERMARK
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_PAGE_DOORBELL_OFFSET
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_LO
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_HI
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SUB_REMAIN
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_PAGE_PREEMPT
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_PAGE_DUMMY_REG
+#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_RB_AQL_CNTL
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_PAGE_MINOR_PTR_UPDATE
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_PAGE_MIDCMD_DATA0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA1
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA2
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA3
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA4
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA5
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA6
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA7
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA8
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_CNTL
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC0_RB_CNTL
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC0_RB_BASE
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_BASE_HI
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC0_RB_RPTR
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_HI
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_HI
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC0_RB_RPTR_ADDR_HI
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_ADDR_LO
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_IB_CNTL
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC0_IB_RPTR
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_OFFSET
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_BASE_LO
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC0_IB_BASE_HI
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SIZE
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC0_SKIP_CNTL
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_RLC0_CONTEXT_STATUS
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC0_DOORBELL
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC0_STATUS
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC0_DOORBELL_LOG
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_WATERMARK
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC0_DOORBELL_OFFSET
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_LO
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_HI
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SUB_REMAIN
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC0_PREEMPT
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC0_DUMMY_REG
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_RB_AQL_CNTL
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC0_MINOR_PTR_UPDATE
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC0_MIDCMD_DATA0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA1
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA2
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA3
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA4
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA5
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA6
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA7
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA8
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_CNTL
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC1_RB_CNTL
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC1_RB_BASE
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_BASE_HI
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC1_RB_RPTR
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_HI
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_HI
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC1_RB_RPTR_ADDR_HI
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_ADDR_LO
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_IB_CNTL
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC1_IB_RPTR
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_OFFSET
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_BASE_LO
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC1_IB_BASE_HI
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SIZE
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC1_SKIP_CNTL
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_RLC1_CONTEXT_STATUS
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC1_DOORBELL
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC1_STATUS
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC1_DOORBELL_LOG
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_WATERMARK
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC1_DOORBELL_OFFSET
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_LO
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_HI
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SUB_REMAIN
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC1_PREEMPT
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC1_DUMMY_REG
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_RB_AQL_CNTL
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC1_MINOR_PTR_UPDATE
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC1_MIDCMD_DATA0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA1
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA2
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA3
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA4
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA5
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA6
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA7
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA8
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_CNTL
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
new file mode 100644
index 0000000..9347337
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma1_4_0_DEFAULT_HEADER
+#define _sdma1_4_0_DEFAULT_HEADER
+
+
+// addressBlock: sdma1_sdma1dec
+#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
+#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
+#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
+#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
+#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
+#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
+#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000
+#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882
+#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
+#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
+#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000
+#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100
+#define mmSDMA1_CNTL_DEFAULT 0x00000002
+#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07
+#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012
+#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
+#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000
+#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000
+#define mmSDMA1_PROGRAM_DEFAULT 0x00000000
+#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557
+#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff
+#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003
+#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000
+#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000
+#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001
+#define mmSDMA1_FREEZE_DEFAULT 0x00000000
+#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff
+#define mmSDMA1_ID_DEFAULT 0x00000001
+#define mmSDMA1_VERSION_DEFAULT 0x00000400
+#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000
+#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
+#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001
+#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200
+#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019
+#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
+#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff
+#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff
+#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600
+#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001
+#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0
+#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200
+#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
+#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005
+#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000
+#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f
+#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000
+#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000
+#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000
+#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000
+#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000
+#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000
+#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd
+#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
+#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0
+#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
+#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
+#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h
new file mode 100644
index 0000000..f2c151a7
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h
@@ -0,0 +1,539 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma1_4_0_OFFSET_HEADER
+#define _sdma1_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: sdma1_sdma1dec
+// base address: 0x5180
+#define mmSDMA1_UCODE_ADDR 0x0000
+#define mmSDMA1_UCODE_ADDR_BASE_IDX 0
+#define mmSDMA1_UCODE_DATA 0x0001
+#define mmSDMA1_UCODE_DATA_BASE_IDX 0
+#define mmSDMA1_VM_CNTL 0x0004
+#define mmSDMA1_VM_CNTL_BASE_IDX 0
+#define mmSDMA1_VM_CTX_LO 0x0005
+#define mmSDMA1_VM_CTX_LO_BASE_IDX 0
+#define mmSDMA1_VM_CTX_HI 0x0006
+#define mmSDMA1_VM_CTX_HI_BASE_IDX 0
+#define mmSDMA1_ACTIVE_FCN_ID 0x0007
+#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmSDMA1_VM_CTX_CNTL 0x0008
+#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0
+#define mmSDMA1_VIRT_RESET_REQ 0x0009
+#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0
+#define mmSDMA1_VF_ENABLE 0x000a
+#define mmSDMA1_VF_ENABLE_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b
+#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c
+#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d
+#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e
+#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE0 0x000f
+#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE1 0x0010
+#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE2 0x0011
+#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE3 0x0012
+#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0
+#define mmSDMA1_MMHUB_CNTL 0x0013
+#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0
+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019
+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define mmSDMA1_POWER_CNTL 0x001a
+#define mmSDMA1_POWER_CNTL_BASE_IDX 0
+#define mmSDMA1_CLK_CTRL 0x001b
+#define mmSDMA1_CLK_CTRL_BASE_IDX 0
+#define mmSDMA1_CNTL 0x001c
+#define mmSDMA1_CNTL_BASE_IDX 0
+#define mmSDMA1_CHICKEN_BITS 0x001d
+#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0
+#define mmSDMA1_GB_ADDR_CONFIG 0x001e
+#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0
+#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f
+#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020
+#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define mmSDMA1_RB_RPTR_FETCH 0x0022
+#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0
+#define mmSDMA1_IB_OFFSET_FETCH 0x0023
+#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0
+#define mmSDMA1_PROGRAM 0x0024
+#define mmSDMA1_PROGRAM_BASE_IDX 0
+#define mmSDMA1_STATUS_REG 0x0025
+#define mmSDMA1_STATUS_REG_BASE_IDX 0
+#define mmSDMA1_STATUS1_REG 0x0026
+#define mmSDMA1_STATUS1_REG_BASE_IDX 0
+#define mmSDMA1_RD_BURST_CNTL 0x0027
+#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0
+#define mmSDMA1_HBM_PAGE_CONFIG 0x0028
+#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0
+#define mmSDMA1_UCODE_CHECKSUM 0x0029
+#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0
+#define mmSDMA1_F32_CNTL 0x002a
+#define mmSDMA1_F32_CNTL_BASE_IDX 0
+#define mmSDMA1_FREEZE 0x002b
+#define mmSDMA1_FREEZE_BASE_IDX 0
+#define mmSDMA1_PHASE0_QUANTUM 0x002c
+#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0
+#define mmSDMA1_PHASE1_QUANTUM 0x002d
+#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0
+#define mmSDMA1_EDC_CONFIG 0x0032
+#define mmSDMA1_EDC_CONFIG_BASE_IDX 0
+#define mmSDMA1_BA_THRESHOLD 0x0033
+#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0
+#define mmSDMA1_ID 0x0034
+#define mmSDMA1_ID_BASE_IDX 0
+#define mmSDMA1_VERSION 0x0035
+#define mmSDMA1_VERSION_BASE_IDX 0
+#define mmSDMA1_EDC_COUNTER 0x0036
+#define mmSDMA1_EDC_COUNTER_BASE_IDX 0
+#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037
+#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0
+#define mmSDMA1_STATUS2_REG 0x0038
+#define mmSDMA1_STATUS2_REG_BASE_IDX 0
+#define mmSDMA1_ATOMIC_CNTL 0x0039
+#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0
+#define mmSDMA1_ATOMIC_PREOP_LO 0x003a
+#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0
+#define mmSDMA1_ATOMIC_PREOP_HI 0x003b
+#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0
+#define mmSDMA1_UTCL1_CNTL 0x003c
+#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0
+#define mmSDMA1_UTCL1_WATERMK 0x003d
+#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_STATUS 0x003e
+#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_STATUS 0x003f
+#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV0 0x0040
+#define mmSDMA1_UTCL1_INV0_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV1 0x0041
+#define mmSDMA1_UTCL1_INV1_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV2 0x0042
+#define mmSDMA1_UTCL1_INV2_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_XNACK0 0x0043
+#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_XNACK1 0x0044
+#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_XNACK0 0x0045
+#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_XNACK1 0x0046
+#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0
+#define mmSDMA1_UTCL1_TIMEOUT 0x0047
+#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0
+#define mmSDMA1_UTCL1_PAGE 0x0048
+#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0
+#define mmSDMA1_POWER_CNTL_IDLE 0x0049
+#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0
+#define mmSDMA1_RELAX_ORDERING_LUT 0x004a
+#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0
+#define mmSDMA1_CHICKEN_BITS_2 0x004b
+#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0
+#define mmSDMA1_STATUS3_REG 0x004c
+#define mmSDMA1_STATUS3_REG_BASE_IDX 0
+#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d
+#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e
+#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PHASE2_QUANTUM 0x004f
+#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0
+#define mmSDMA1_ERROR_LOG 0x0050
+#define mmSDMA1_ERROR_LOG_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG0 0x0051
+#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG1 0x0052
+#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG2 0x0053
+#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG3 0x0054
+#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0
+#define mmSDMA1_F32_COUNTER 0x0055
+#define mmSDMA1_F32_COUNTER_BASE_IDX 0
+#define mmSDMA1_UNBREAKABLE 0x0056
+#define mmSDMA1_UNBREAKABLE_BASE_IDX 0
+#define mmSDMA1_PERFMON_CNTL 0x0057
+#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058
+#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059
+#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
+#define mmSDMA1_CRD_CNTL 0x005b
+#define mmSDMA1_CRD_CNTL_BASE_IDX 0
+#define mmSDMA1_MMHUB_TRUSTLVL 0x005c
+#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmSDMA1_ULV_CNTL 0x005e
+#define mmSDMA1_ULV_CNTL_BASE_IDX 0
+#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060
+#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061
+#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define mmSDMA1_GFX_RB_CNTL 0x0080
+#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_RB_BASE 0x0081
+#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0
+#define mmSDMA1_GFX_RB_BASE_HI 0x0082
+#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR 0x0083
+#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_HI 0x0084
+#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR 0x0085
+#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_HI 0x0086
+#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_IB_CNTL 0x008a
+#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_IB_RPTR 0x008b
+#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_GFX_IB_OFFSET 0x008c
+#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_GFX_IB_BASE_LO 0x008d
+#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_GFX_IB_BASE_HI 0x008e
+#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_GFX_IB_SIZE 0x008f
+#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_GFX_SKIP_CNTL 0x0090
+#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091
+#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL 0x0092
+#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093
+#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_STATUS 0x00a8
+#define mmSDMA1_GFX_STATUS_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9
+#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_GFX_WATERMARK 0x00aa
+#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab
+#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac
+#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad
+#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af
+#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_GFX_PREEMPT 0x00b0
+#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0
+#define mmSDMA1_GFX_DUMMY_REG 0x00b1
+#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4
+#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0
+#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1
+#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2
+#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3
+#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4
+#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5
+#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6
+#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7
+#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8
+#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9
+#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_CNTL 0x00e0
+#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_BASE 0x00e1
+#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2
+#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR 0x00e3
+#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4
+#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR 0x00e5
+#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6
+#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_CNTL 0x00ea
+#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_RPTR 0x00eb
+#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_OFFSET 0x00ec
+#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed
+#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee
+#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_SIZE 0x00ef
+#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0
+#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1
+#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL 0x00f2
+#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0
+#define mmSDMA1_PAGE_STATUS 0x0108
+#define mmSDMA1_PAGE_STATUS_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109
+#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_PAGE_WATERMARK 0x010a
+#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b
+#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c
+#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d
+#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f
+#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_PAGE_PREEMPT 0x0110
+#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0
+#define mmSDMA1_PAGE_DUMMY_REG 0x0111
+#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114
+#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120
+#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121
+#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122
+#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123
+#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124
+#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125
+#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126
+#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127
+#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128
+#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129
+#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_CNTL 0x0140
+#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_BASE 0x0141
+#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_BASE_HI 0x0142
+#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR 0x0143
+#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144
+#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR 0x0145
+#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146
+#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_CNTL 0x014a
+#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_RPTR 0x014b
+#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_OFFSET 0x014c
+#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_BASE_LO 0x014d
+#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_BASE_HI 0x014e
+#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_SIZE 0x014f
+#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC0_SKIP_CNTL 0x0150
+#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151
+#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL 0x0152
+#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC0_STATUS 0x0168
+#define mmSDMA1_RLC0_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169
+#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_RLC0_WATERMARK 0x016a
+#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b
+#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c
+#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d
+#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f
+#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC0_PREEMPT 0x0170
+#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC0_DUMMY_REG 0x0171
+#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174
+#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180
+#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181
+#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182
+#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183
+#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184
+#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185
+#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186
+#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187
+#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188
+#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189
+#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_CNTL 0x01a0
+#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_BASE 0x01a1
+#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2
+#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR 0x01a3
+#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4
+#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR 0x01a5
+#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6
+#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_CNTL 0x01aa
+#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_RPTR 0x01ab
+#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_OFFSET 0x01ac
+#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad
+#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae
+#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_SIZE 0x01af
+#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0
+#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1
+#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL 0x01b2
+#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC1_STATUS 0x01c8
+#define mmSDMA1_RLC1_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9
+#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_RLC1_WATERMARK 0x01ca
+#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb
+#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc
+#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd
+#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf
+#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC1_PREEMPT 0x01d0
+#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC1_DUMMY_REG 0x01d1
+#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4
+#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0
+#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1
+#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2
+#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3
+#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4
+#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5
+#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6
+#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7
+#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8
+#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9
+#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h
new file mode 100644
index 0000000..99849e0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h
@@ -0,0 +1,1810 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma1_4_0_SH_MASK_HEADER
+#define _sdma1_4_0_SH_MASK_HEADER
+
+
+// addressBlock: sdma1_sdma1dec
+//SDMA1_UCODE_ADDR
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL
+//SDMA1_UCODE_DATA
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_VM_CNTL
+#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL
+//SDMA1_VM_CTX_LO
+#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_VM_CTX_HI
+#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_ACTIVE_FCN_ID
+#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SDMA1_VM_CTX_CNTL
+#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L
+#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA1_VIRT_RESET_REQ
+#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SDMA1_VF_ENABLE
+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+//SDMA1_CONTEXT_REG_TYPE0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L
+//SDMA1_CONTEXT_REG_TYPE1
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
+//SDMA1_CONTEXT_REG_TYPE2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
+//SDMA1_CONTEXT_REG_TYPE3
+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
+//SDMA1_PUB_REG_TYPE0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L
+#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L
+#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L
+//SDMA1_PUB_REG_TYPE1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L
+//SDMA1_PUB_REG_TYPE2
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L
+#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
+//SDMA1_PUB_REG_TYPE3
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
+//SDMA1_MMHUB_CNTL
+#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
+#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
+//SDMA1_CONTEXT_GROUP_BOUNDARY
+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA1_POWER_CNTL
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+//SDMA1_CLK_CTRL
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA1_CNTL
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA1_CHICKEN_BITS
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
+//SDMA1_GB_ADDR_CONFIG
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_GB_ADDR_CONFIG_READ
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_RB_RPTR_FETCH_HI
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA1_RB_RPTR_FETCH
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA1_IB_OFFSET_FETCH
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PROGRAM
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA1_STATUS_REG
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA1_STATUS1_REG
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA1_RD_BURST_CNTL
+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+//SDMA1_HBM_PAGE_CONFIG
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L
+//SDMA1_UCODE_CHECKSUM
+#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA1_F32_CNTL
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L
+//SDMA1_FREEZE
+#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA1_PHASE0_QUANTUM
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_PHASE1_QUANTUM
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_EDC_CONFIG
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
+//SDMA1_BA_THRESHOLD
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA1_ID
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA1_VERSION
+#define SDMA1_VERSION__MINVER__SHIFT 0x0
+#define SDMA1_VERSION__MAJVER__SHIFT 0x8
+#define SDMA1_VERSION__REV__SHIFT 0x10
+#define SDMA1_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA1_VERSION__REV_MASK 0x003F0000L
+//SDMA1_EDC_COUNTER
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
+//SDMA1_EDC_COUNTER_CLEAR
+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
+//SDMA1_STATUS2_REG
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA1_ATOMIC_CNTL
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA1_ATOMIC_PREOP_LO
+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA1_ATOMIC_PREOP_HI
+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_CNTL
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA1_UTCL1_WATERMK
+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
+//SDMA1_UTCL1_RD_STATUS
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA1_UTCL1_WR_STATUS
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA1_UTCL1_INV0
+#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA1_UTCL1_INV1
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_INV2
+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK1
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_WR_XNACK0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_WR_XNACK1
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_TIMEOUT
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA1_UTCL1_PAGE
+#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA1_POWER_CNTL_IDLE
+#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA1_RELAX_ORDERING_LUT
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA1_CHICKEN_BITS_2
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+//SDMA1_STATUS3_REG
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+//SDMA1_PHYSICAL_ADDR_LO
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA1_PHYSICAL_ADDR_HI
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA1_PHASE2_QUANTUM
+#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_ERROR_LOG
+#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA1_PUB_DUMMY_REG0
+#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG1
+#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG2
+#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG3
+#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_F32_COUNTER
+#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_UNBREAKABLE
+#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0
+#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L
+//SDMA1_PERFMON_CNTL
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SDMA1_PERFCOUNTER0_RESULT
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER1_RESULT
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
+//SDMA1_CRD_CNTL
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA1_MMHUB_TRUSTLVL
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
+//SDMA1_GPU_IOV_VIOLATION_LOG
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//SDMA1_ULV_CNTL
+#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA1_EA_DBIT_ADDR_DATA
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_EA_DBIT_ADDR_INDEX
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA1_GFX_RB_CNTL
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_GFX_RB_BASE
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_BASE_HI
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_GFX_RB_RPTR
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_HI
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_HI
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_CNTL
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_GFX_RB_RPTR_ADDR_HI
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_ADDR_LO
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_IB_CNTL
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_GFX_IB_RPTR
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_OFFSET
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_BASE_LO
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_GFX_IB_BASE_HI
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SIZE
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_GFX_SKIP_CNTL
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_GFX_CONTEXT_STATUS
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_GFX_DOORBELL
+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_GFX_CONTEXT_CNTL
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+//SDMA1_GFX_STATUS
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_GFX_DOORBELL_LOG
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_GFX_WATERMARK
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_GFX_DOORBELL_OFFSET
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_GFX_CSA_ADDR_LO
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_CSA_ADDR_HI
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SUB_REMAIN
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_GFX_PREEMPT
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_GFX_DUMMY_REG
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_RB_AQL_CNTL
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_GFX_MINOR_PTR_UPDATE
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_GFX_MIDCMD_DATA0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA1
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA2
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA3
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA4
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA5
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA6
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA7
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA8
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_CNTL
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_PAGE_RB_CNTL
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_PAGE_RB_BASE
+#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_BASE_HI
+#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_PAGE_RB_RPTR
+#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_HI
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR
+#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_HI
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_PAGE_RB_RPTR_ADDR_HI
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_ADDR_LO
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_IB_CNTL
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_PAGE_IB_RPTR
+#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_OFFSET
+#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_BASE_LO
+#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_PAGE_IB_BASE_HI
+#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SIZE
+#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_PAGE_SKIP_CNTL
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_PAGE_CONTEXT_STATUS
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_PAGE_DOORBELL
+#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_PAGE_STATUS
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_PAGE_DOORBELL_LOG
+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_WATERMARK
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_PAGE_DOORBELL_OFFSET
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_LO
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_HI
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SUB_REMAIN
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_PAGE_PREEMPT
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_PAGE_DUMMY_REG
+#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_RB_AQL_CNTL
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_PAGE_MINOR_PTR_UPDATE
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_PAGE_MIDCMD_DATA0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA1
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA2
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA3
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA4
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA5
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA6
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA7
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA8
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_CNTL
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC0_RB_CNTL
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC0_RB_BASE
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_BASE_HI
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC0_RB_RPTR
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_HI
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_HI
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC0_RB_RPTR_ADDR_HI
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_ADDR_LO
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_IB_CNTL
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC0_IB_RPTR
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_OFFSET
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_BASE_LO
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC0_IB_BASE_HI
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SIZE
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC0_SKIP_CNTL
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_RLC0_CONTEXT_STATUS
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC0_DOORBELL
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC0_STATUS
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC0_DOORBELL_LOG
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_WATERMARK
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC0_DOORBELL_OFFSET
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_LO
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_HI
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SUB_REMAIN
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC0_PREEMPT
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC0_DUMMY_REG
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_RB_AQL_CNTL
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC0_MINOR_PTR_UPDATE
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC0_MIDCMD_DATA0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA1
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA2
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA3
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA4
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA5
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA6
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA7
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA8
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_CNTL
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC1_RB_CNTL
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC1_RB_BASE
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_BASE_HI
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC1_RB_RPTR
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_HI
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_HI
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC1_RB_RPTR_ADDR_HI
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_ADDR_LO
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_IB_CNTL
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC1_IB_RPTR
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_OFFSET
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_BASE_LO
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC1_IB_BASE_HI
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SIZE
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC1_SKIP_CNTL
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_RLC1_CONTEXT_STATUS
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC1_DOORBELL
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC1_STATUS
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC1_DOORBELL_LOG
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_WATERMARK
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC1_DOORBELL_OFFSET
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_LO
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_HI
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SUB_REMAIN
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC1_PREEMPT
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC1_DUMMY_REG
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_RB_AQL_CNTL
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC1_MINOR_PTR_UPDATE
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC1_MIDCMD_DATA0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA1
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA2
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA3
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA4
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA5
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA6
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA7
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA8
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_CNTL
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h
new file mode 100644
index 0000000..128a18f
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_DEFAULT_HEADER
+#define _umc_6_0_DEFAULT_HEADER
+
+#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000
+
+#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203
+
+#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h
new file mode 100644
index 0000000..6985dbb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_OFFSET_H_
+#define _umc_6_0_OFFSET_H_
+
+#define mmUMCCH0_0_EccCtrl 0x0053
+#define mmUMCCH0_0_EccCtrl_BASE_IDX 0
+#define mmUMCCH1_0_EccCtrl 0x0853
+#define mmUMCCH1_0_EccCtrl_BASE_IDX 0
+#define mmUMCCH2_0_EccCtrl 0x1053
+#define mmUMCCH2_0_EccCtrl_BASE_IDX 0
+#define mmUMCCH3_0_EccCtrl 0x1853
+#define mmUMCCH3_0_EccCtrl_BASE_IDX 0
+
+#define mmUMCCH0_0_UMC_CONFIG 0x0040
+#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0
+#define mmUMCCH1_0_UMC_CONFIG 0x0840
+#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0
+#define mmUMCCH2_0_UMC_CONFIG 0x1040
+#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0
+#define mmUMCCH3_0_UMC_CONFIG 0x1840
+#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0
+
+#define mmUMCCH0_0_UmcLocalCap 0x0306
+#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0
+#define mmUMCCH1_0_UmcLocalCap 0x0b06
+#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0
+#define mmUMCCH2_0_UmcLocalCap 0x1306
+#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0
+#define mmUMCCH3_0_UmcLocalCap 0x1b06
+#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h
new file mode 100644
index 0000000..3e857d1
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_SH_MASK_HEADER
+#define _umc_6_0_SH_MASK_HEADER
+
+#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L
+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa
+#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L
+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0
+
+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L
+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f
+
+#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L
+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
rename to drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
deleted file mode 100644
index 1650dc3..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _athub_1_0_DEFAULT_HEADER
-#define _athub_1_0_DEFAULT_HEADER
-
-
-// addressBlock: athub_atsdec
-#define mmATC_ATS_CNTL_DEFAULT 0x009a0800
-#define mmATC_ATS_STATUS_DEFAULT 0x00000000
-#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
-#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
-#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
-#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
-#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
-#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
-#define mmATHUB_MISC_CNTL_DEFAULT 0x00040200
-#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
-#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000
-#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000
-#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000
-#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000
-#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000
-#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
-#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
-#define mmATHUB_COMMAND_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
-#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
-#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmATS_IH_CREDIT_DEFAULT 0x00150002
-#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002
-#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000
-#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000
-#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210
-#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000
-#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000
-
-
-// addressBlock: athub_xpbdec
-#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000
-#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000
-#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000
-#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG0_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG1_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG2_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG3_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG4_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG5_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG6_DEFAULT 0x00000000
-#define mmXPB_CLG_CFG7_DEFAULT 0x00000000
-#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000
-#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000
-#define mmXPB_LB_ADDR_DEFAULT 0x00000000
-#define mmXPB_WCB_STS_DEFAULT 0x00000000
-#define mmXPB_HST_CFG_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f
-#define mmXPB_P2P_BAR0_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR1_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR2_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR3_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR4_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR5_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR6_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR7_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000
-#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000
-#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000
-#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000
-#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000
-#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000
-#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000
-#define mmXPB_CLK_GAT_DEFAULT 0x00040400
-#define mmXPB_INTF_CFG_DEFAULT 0x000f1040
-#define mmXPB_INTF_STS_DEFAULT 0x00000000
-#define mmXPB_PIPE_STS_DEFAULT 0x00000000
-#define mmXPB_SUB_CTRL_DEFAULT 0x00000000
-#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000
-#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000
-#define mmXPB_STICKY_DEFAULT 0x00000000
-#define mmXPB_STICKY_W1C_DEFAULT 0x00000000
-#define mmXPB_MISC_CFG_DEFAULT 0x4d585042
-#define mmXPB_INTF_CFG2_DEFAULT 0x00000040
-#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000
-#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000
-#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000
-#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x00000000
-#define mmXPB_CLG_MM_MATCH_DEFAULT 0x03000000
-#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000
-#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000
-#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040
-#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080
-#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0
-#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100
-#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140
-#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000
-#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0
-#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000
-#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040
-#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080
-#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0
-
-
-// addressBlock: athub_rpbdec
-#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230
-#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0
-#define mmRPB_TAG_CONF_DEFAULT 0x00204020
-#define mmRPB_EFF_CNTL_DEFAULT 0x00001010
-#define mmRPB_ARB_CNTL_DEFAULT 0x00040404
-#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104
-#define mmRPB_BIF_CNTL_DEFAULT 0x01000404
-#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810
-#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810
-#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000
-#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000
-#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000
-#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000
-#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810
-#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000004
-#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00004040
-#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000
-#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000
-#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000
-#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000
-#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000
-#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000
-#define mmRPB_ATS_CNTL_DEFAULT 0x58088422
-#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13
-#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14814
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
deleted file mode 100644
index 80042e1..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _athub_1_0_OFFSET_HEADER
-#define _athub_1_0_OFFSET_HEADER
-
-
-
-// addressBlock: athub_atsdec
-// base address: 0x3080
-#define mmATC_ATS_CNTL 0x0000
-#define mmATC_ATS_CNTL_BASE_IDX 0
-#define mmATC_ATS_STATUS 0x0003
-#define mmATC_ATS_STATUS_BASE_IDX 0
-#define mmATC_ATS_FAULT_CNTL 0x0004
-#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
-#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
-#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
-#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
-#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
-#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
-#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
-#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
-#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
-#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
-#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
-#define mmATHUB_MISC_CNTL 0x000a
-#define mmATHUB_MISC_CNTL_BASE_IDX 0
-#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
-#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
-#define mmATC_VMID0_PASID_MAPPING 0x000c
-#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID1_PASID_MAPPING 0x000d
-#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID2_PASID_MAPPING 0x000e
-#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID3_PASID_MAPPING 0x000f
-#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID4_PASID_MAPPING 0x0010
-#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID5_PASID_MAPPING 0x0011
-#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID6_PASID_MAPPING 0x0012
-#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID7_PASID_MAPPING 0x0013
-#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID8_PASID_MAPPING 0x0014
-#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID9_PASID_MAPPING 0x0015
-#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID10_PASID_MAPPING 0x0016
-#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID11_PASID_MAPPING 0x0017
-#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID12_PASID_MAPPING 0x0018
-#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID13_PASID_MAPPING 0x0019
-#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID14_PASID_MAPPING 0x001a
-#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID15_PASID_MAPPING 0x001b
-#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
-#define mmATC_ATS_VMID_STATUS 0x001c
-#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
-#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
-#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
-#define mmATC_PERFCOUNTER0_CFG 0x001e
-#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmATC_PERFCOUNTER1_CFG 0x001f
-#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmATC_PERFCOUNTER2_CFG 0x0020
-#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
-#define mmATC_PERFCOUNTER3_CFG 0x0021
-#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
-#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
-#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-#define mmATC_PERFCOUNTER_LO 0x0023
-#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
-#define mmATC_PERFCOUNTER_HI 0x0024
-#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL 0x0025
-#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
-#define mmATHUB_PCIE_PASID_CNTL 0x0026
-#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
-#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
-#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
-#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
-#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
-#define mmATHUB_COMMAND 0x0029
-#define mmATHUB_COMMAND_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
-#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
-#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
-#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
-#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
-#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
-#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
-#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
-#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
-#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
-#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
-#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
-#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
-#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
-#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
-#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
-#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
-#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
-#define mmATHUB_MEM_POWER_LS 0x003a
-#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
-#define mmATS_IH_CREDIT 0x003b
-#define mmATS_IH_CREDIT_BASE_IDX 0
-#define mmATHUB_IH_CREDIT 0x003c
-#define mmATHUB_IH_CREDIT_BASE_IDX 0
-#define mmATC_VMID16_PASID_MAPPING 0x003d
-#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID17_PASID_MAPPING 0x003e
-#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID18_PASID_MAPPING 0x003f
-#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID19_PASID_MAPPING 0x0040
-#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID20_PASID_MAPPING 0x0041
-#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID21_PASID_MAPPING 0x0042
-#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID22_PASID_MAPPING 0x0043
-#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID23_PASID_MAPPING 0x0044
-#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID24_PASID_MAPPING 0x0045
-#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID25_PASID_MAPPING 0x0046
-#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID26_PASID_MAPPING 0x0047
-#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID27_PASID_MAPPING 0x0048
-#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID28_PASID_MAPPING 0x0049
-#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID29_PASID_MAPPING 0x004a
-#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID30_PASID_MAPPING 0x004b
-#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
-#define mmATC_VMID31_PASID_MAPPING 0x004c
-#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
-#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d
-#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
-#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e
-#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
-#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f
-#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmATC_ATS_SDPPORT_CNTL 0x0050
-#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
-#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052
-#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
-#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053
-#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
-
-
-// addressBlock: athub_xpbdec
-// base address: 0x31f0
-#define mmXPB_RTR_SRC_APRTR0 0x005c
-#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR1 0x005d
-#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR2 0x005e
-#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR3 0x005f
-#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR4 0x0060
-#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR5 0x0061
-#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR6 0x0062
-#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR7 0x0063
-#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR8 0x0064
-#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
-#define mmXPB_RTR_SRC_APRTR9 0x0065
-#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
-#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066
-#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
-#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067
-#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
-#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068
-#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
-#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069
-#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP0 0x006a
-#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP1 0x006b
-#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP2 0x006c
-#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP3 0x006d
-#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP4 0x006e
-#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP5 0x006f
-#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP6 0x0070
-#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP7 0x0071
-#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP8 0x0072
-#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
-#define mmXPB_RTR_DEST_MAP9 0x0073
-#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
-#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074
-#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
-#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075
-#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
-#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076
-#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
-#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077
-#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
-#define mmXPB_CLG_CFG0 0x0078
-#define mmXPB_CLG_CFG0_BASE_IDX 0
-#define mmXPB_CLG_CFG1 0x0079
-#define mmXPB_CLG_CFG1_BASE_IDX 0
-#define mmXPB_CLG_CFG2 0x007a
-#define mmXPB_CLG_CFG2_BASE_IDX 0
-#define mmXPB_CLG_CFG3 0x007b
-#define mmXPB_CLG_CFG3_BASE_IDX 0
-#define mmXPB_CLG_CFG4 0x007c
-#define mmXPB_CLG_CFG4_BASE_IDX 0
-#define mmXPB_CLG_CFG5 0x007d
-#define mmXPB_CLG_CFG5_BASE_IDX 0
-#define mmXPB_CLG_CFG6 0x007e
-#define mmXPB_CLG_CFG6_BASE_IDX 0
-#define mmXPB_CLG_CFG7 0x007f
-#define mmXPB_CLG_CFG7_BASE_IDX 0
-#define mmXPB_CLG_EXTRA 0x0080
-#define mmXPB_CLG_EXTRA_BASE_IDX 0
-#define mmXPB_CLG_EXTRA_MSK 0x0081
-#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
-#define mmXPB_LB_ADDR 0x0082
-#define mmXPB_LB_ADDR_BASE_IDX 0
-#define mmXPB_WCB_STS 0x0083
-#define mmXPB_WCB_STS_BASE_IDX 0
-#define mmXPB_HST_CFG 0x0084
-#define mmXPB_HST_CFG_BASE_IDX 0
-#define mmXPB_P2P_BAR_CFG 0x0085
-#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
-#define mmXPB_P2P_BAR0 0x0086
-#define mmXPB_P2P_BAR0_BASE_IDX 0
-#define mmXPB_P2P_BAR1 0x0087
-#define mmXPB_P2P_BAR1_BASE_IDX 0
-#define mmXPB_P2P_BAR2 0x0088
-#define mmXPB_P2P_BAR2_BASE_IDX 0
-#define mmXPB_P2P_BAR3 0x0089
-#define mmXPB_P2P_BAR3_BASE_IDX 0
-#define mmXPB_P2P_BAR4 0x008a
-#define mmXPB_P2P_BAR4_BASE_IDX 0
-#define mmXPB_P2P_BAR5 0x008b
-#define mmXPB_P2P_BAR5_BASE_IDX 0
-#define mmXPB_P2P_BAR6 0x008c
-#define mmXPB_P2P_BAR6_BASE_IDX 0
-#define mmXPB_P2P_BAR7 0x008d
-#define mmXPB_P2P_BAR7_BASE_IDX 0
-#define mmXPB_P2P_BAR_SETUP 0x008e
-#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
-#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090
-#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
-#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091
-#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR0 0x0092
-#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR1 0x0093
-#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR2 0x0094
-#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR3 0x0095
-#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR4 0x0096
-#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR5 0x0097
-#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR6 0x0098
-#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR7 0x0099
-#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR8 0x009a
-#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
-#define mmXPB_PEER_SYS_BAR9 0x009b
-#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
-#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c
-#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
-#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d
-#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
-#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e
-#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
-#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f
-#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
-#define mmXPB_CLK_GAT 0x00a0
-#define mmXPB_CLK_GAT_BASE_IDX 0
-#define mmXPB_INTF_CFG 0x00a1
-#define mmXPB_INTF_CFG_BASE_IDX 0
-#define mmXPB_INTF_STS 0x00a2
-#define mmXPB_INTF_STS_BASE_IDX 0
-#define mmXPB_PIPE_STS 0x00a3
-#define mmXPB_PIPE_STS_BASE_IDX 0
-#define mmXPB_SUB_CTRL 0x00a4
-#define mmXPB_SUB_CTRL_BASE_IDX 0
-#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5
-#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
-#define mmXPB_PERF_KNOBS 0x00a6
-#define mmXPB_PERF_KNOBS_BASE_IDX 0
-#define mmXPB_STICKY 0x00a7
-#define mmXPB_STICKY_BASE_IDX 0
-#define mmXPB_STICKY_W1C 0x00a8
-#define mmXPB_STICKY_W1C_BASE_IDX 0
-#define mmXPB_MISC_CFG 0x00a9
-#define mmXPB_MISC_CFG_BASE_IDX 0
-#define mmXPB_INTF_CFG2 0x00aa
-#define mmXPB_INTF_CFG2_BASE_IDX 0
-#define mmXPB_CLG_EXTRA_RD 0x00ab
-#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
-#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac
-#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
-#define mmXPB_CLG_GFX_MATCH 0x00ad
-#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
-#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae
-#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
-#define mmXPB_CLG_MM_MATCH 0x00af
-#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
-#define mmXPB_CLG_MM_MATCH_MSK 0x00b0
-#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1
-#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2
-#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3
-#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4
-#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5
-#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6
-#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7
-#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
-#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8
-#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
-#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9
-#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
-#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba
-#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
-#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb
-#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
-#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc
-#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
-
-
-// addressBlock: athub_rpbdec
-// base address: 0x33b0
-#define mmRPB_PASSPW_CONF 0x00cc
-#define mmRPB_PASSPW_CONF_BASE_IDX 0
-#define mmRPB_BLOCKLEVEL_CONF 0x00cd
-#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
-#define mmRPB_TAG_CONF 0x00cf
-#define mmRPB_TAG_CONF_BASE_IDX 0
-#define mmRPB_EFF_CNTL 0x00d1
-#define mmRPB_EFF_CNTL_BASE_IDX 0
-#define mmRPB_ARB_CNTL 0x00d2
-#define mmRPB_ARB_CNTL_BASE_IDX 0
-#define mmRPB_ARB_CNTL2 0x00d3
-#define mmRPB_ARB_CNTL2_BASE_IDX 0
-#define mmRPB_BIF_CNTL 0x00d4
-#define mmRPB_BIF_CNTL_BASE_IDX 0
-#define mmRPB_WR_SWITCH_CNTL 0x00d5
-#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
-#define mmRPB_RD_SWITCH_CNTL 0x00d7
-#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
-#define mmRPB_CID_QUEUE_WR 0x00d8
-#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
-#define mmRPB_CID_QUEUE_RD 0x00d9
-#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
-#define mmRPB_CID_QUEUE_EX 0x00dc
-#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
-#define mmRPB_CID_QUEUE_EX_DATA 0x00dd
-#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
-#define mmRPB_SWITCH_CNTL2 0x00de
-#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
-#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df
-#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
-#define mmRPB_VC_SWITCH_RDWR 0x00e0
-#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
-#define mmRPB_PERFCOUNTER_LO 0x00e1
-#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
-#define mmRPB_PERFCOUNTER_HI 0x00e2
-#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
-#define mmRPB_PERFCOUNTER0_CFG 0x00e3
-#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmRPB_PERFCOUNTER1_CFG 0x00e4
-#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmRPB_PERFCOUNTER2_CFG 0x00e5
-#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
-#define mmRPB_PERFCOUNTER3_CFG 0x00e6
-#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
-#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7
-#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-#define mmRPB_RD_QUEUE_CNTL 0x00e9
-#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
-#define mmRPB_RD_QUEUE_CNTL2 0x00ea
-#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
-#define mmRPB_WR_QUEUE_CNTL 0x00eb
-#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
-#define mmRPB_WR_QUEUE_CNTL2 0x00ec
-#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
-#define mmRPB_EA_QUEUE_WR 0x00ed
-#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
-#define mmRPB_ATS_CNTL 0x00ee
-#define mmRPB_ATS_CNTL_BASE_IDX 0
-#define mmRPB_ATS_CNTL2 0x00ef
-#define mmRPB_ATS_CNTL2_BASE_IDX 0
-#define mmRPB_SDPPORT_CNTL 0x00f0
-#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
deleted file mode 100644
index 777b05c..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
+++ /dev/null
@@ -1,2045 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _athub_1_0_SH_MASK_HEADER
-#define _athub_1_0_SH_MASK_HEADER
-
-
-// addressBlock: athub_atsdec
-//ATC_ATS_CNTL
-#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
-#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
-#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
-#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
-#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
-#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
-#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
-#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
-#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
-#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
-#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
-#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L
-#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L
-#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
-//ATC_ATS_STATUS
-#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
-#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
-#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
-#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3
-#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6
-#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
-#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
-#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
-#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L
-#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L
-//ATC_ATS_FAULT_CNTL
-#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
-#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
-#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
-#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL
-#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L
-#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L
-//ATC_ATS_FAULT_STATUS_INFO
-#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
-#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
-#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
-#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
-#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
-#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
-#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
-#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
-#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL
-#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L
-#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
-#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
-#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
-#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
-#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L
-#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L
-//ATC_ATS_FAULT_STATUS_ADDR
-#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
-#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL
-//ATC_ATS_DEFAULT_PAGE_LOW
-#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
-#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL
-//ATC_TRANS_FAULT_RSPCNTRL
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L
-#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L
-//ATC_ATS_FAULT_STATUS_INFO2
-#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
-#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
-#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9
-#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L
-#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL
-#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L
-//ATHUB_MISC_CNTL
-#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6
-#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12
-#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13
-#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14
-#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15
-#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b
-#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c
-#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L
-#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L
-#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L
-#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L
-#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L
-#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L
-#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L
-//ATC_VMID_PASID_MAPPING_UPDATE_STATUS
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L
-//ATC_VMID0_PASID_MAPPING
-#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID1_PASID_MAPPING
-#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID2_PASID_MAPPING
-#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID3_PASID_MAPPING
-#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID4_PASID_MAPPING
-#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID5_PASID_MAPPING
-#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID6_PASID_MAPPING
-#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID7_PASID_MAPPING
-#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID8_PASID_MAPPING
-#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID9_PASID_MAPPING
-#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID10_PASID_MAPPING
-#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID11_PASID_MAPPING
-#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID12_PASID_MAPPING
-#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID13_PASID_MAPPING
-#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID14_PASID_MAPPING
-#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID15_PASID_MAPPING
-#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_ATS_VMID_STATUS
-#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
-#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
-#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
-#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
-#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
-#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
-#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
-#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
-#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
-#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
-#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
-#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
-#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
-#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
-#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
-#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
-#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10
-#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11
-#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12
-#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13
-#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14
-#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15
-#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16
-#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17
-#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18
-#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19
-#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a
-#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b
-#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c
-#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d
-#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e
-#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f
-#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L
-#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L
-#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L
-#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L
-#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L
-#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L
-#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L
-#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L
-#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L
-#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L
-#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L
-#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L
-#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L
-#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L
-#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L
-#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L
-#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L
-#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L
-#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L
-#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L
-#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L
-#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L
-#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L
-#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L
-#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L
-#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L
-#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L
-#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L
-#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L
-#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L
-#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L
-#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L
-//ATC_ATS_GFX_ATCL2_STATUS
-#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
-#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
-//ATC_PERFCOUNTER0_CFG
-#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//ATC_PERFCOUNTER1_CFG
-#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//ATC_PERFCOUNTER2_CFG
-#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//ATC_PERFCOUNTER3_CFG
-#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
-#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
-#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
-#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
-//ATC_PERFCOUNTER_RSLT_CNTL
-#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-//ATC_PERFCOUNTER_LO
-#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//ATC_PERFCOUNTER_HI
-#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//ATHUB_PCIE_ATS_CNTL
-#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10
-#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
-#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_PASID_CNTL
-#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10
-#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11
-#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12
-#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L
-#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L
-#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L
-//ATHUB_PCIE_PAGE_REQ_CNTL
-#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
-#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
-#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L
-#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L
-//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC
-#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
-#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
-//ATHUB_COMMAND
-#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
-#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L
-//ATHUB_PCIE_ATS_CNTL_VF_0
-#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_1
-#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_2
-#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_3
-#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_4
-#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_5
-#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_6
-#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_7
-#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_8
-#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_9
-#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_10
-#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_11
-#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_12
-#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_13
-#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_14
-#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_PCIE_ATS_CNTL_VF_15
-#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
-#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
-//ATHUB_MEM_POWER_LS
-#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//ATS_IH_CREDIT
-#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
-#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
-//ATHUB_IH_CREDIT
-#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
-#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
-//ATC_VMID16_PASID_MAPPING
-#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID17_PASID_MAPPING
-#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID18_PASID_MAPPING
-#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID19_PASID_MAPPING
-#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID20_PASID_MAPPING
-#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID21_PASID_MAPPING
-#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID22_PASID_MAPPING
-#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID23_PASID_MAPPING
-#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID24_PASID_MAPPING
-#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID25_PASID_MAPPING
-#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID26_PASID_MAPPING
-#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID27_PASID_MAPPING
-#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID28_PASID_MAPPING
-#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID29_PASID_MAPPING
-#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID30_PASID_MAPPING
-#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_VMID31_PASID_MAPPING
-#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0
-#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
-#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f
-#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL
-#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
-#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L
-//ATC_ATS_MMHUB_ATCL2_STATUS
-#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
-#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
-//ATHUB_SHARED_VIRT_RESET_REQ
-#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//ATHUB_SHARED_ACTIVE_FCN_ID
-#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//ATC_ATS_SDPPORT_CNTL
-#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0
-#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1
-#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19
-#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L
-#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L
-#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L
-#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L
-//ATC_ATS_VMID_SNAPSHOT_GFX_STAT
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L
-#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L
-//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L
-#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L
-
-
-// addressBlock: athub_xpbdec
-//XPB_RTR_SRC_APRTR0
-#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR1
-#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR2
-#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR3
-#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR4
-#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR5
-#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR6
-#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR7
-#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR8
-#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_SRC_APRTR9
-#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
-#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_XDMA_RTR_SRC_APRTR0
-#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
-#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_XDMA_RTR_SRC_APRTR1
-#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
-#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_XDMA_RTR_SRC_APRTR2
-#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
-#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_XDMA_RTR_SRC_APRTR3
-#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
-#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
-//XPB_RTR_DEST_MAP0
-#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP1
-#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP2
-#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP3
-#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP4
-#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP5
-#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP6
-#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP7
-#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP8
-#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L
-//XPB_RTR_DEST_MAP9
-#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
-#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
-#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
-#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
-#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L
-#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L
-#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L
-//XPB_XDMA_RTR_DEST_MAP0
-#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
-#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
-#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
-#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
-#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L
-#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
-#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
-//XPB_XDMA_RTR_DEST_MAP1
-#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
-#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
-#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
-#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
-#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L
-#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
-#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
-//XPB_XDMA_RTR_DEST_MAP2
-#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
-#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
-#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
-#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
-#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L
-#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
-#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
-//XPB_XDMA_RTR_DEST_MAP3
-#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
-#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
-#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
-#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
-#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
-#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L
-#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
-#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
-#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
-#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
-//XPB_CLG_CFG0
-#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG1
-#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG2
-#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG3
-#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG4
-#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG5
-#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG6
-#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_CFG7
-#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
-#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
-#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
-#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL
-#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L
-#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L
-//XPB_CLG_EXTRA
-#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0
-#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6
-#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb
-#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc
-#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf
-#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15
-#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a
-#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b
-#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL
-#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L
-#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L
-#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L
-#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L
-#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L
-#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L
-#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L
-//XPB_CLG_EXTRA_MSK
-#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0
-#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6
-#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb
-#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11
-#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL
-#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L
-#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L
-#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L
-//XPB_LB_ADDR
-#define XPB_LB_ADDR__CMP0__SHIFT 0x0
-#define XPB_LB_ADDR__MASK0__SHIFT 0xa
-#define XPB_LB_ADDR__CMP1__SHIFT 0x14
-#define XPB_LB_ADDR__MASK1__SHIFT 0x1a
-#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL
-#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L
-#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L
-#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L
-//XPB_WCB_STS
-#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
-#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
-#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
-#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL
-#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L
-#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L
-//XPB_HST_CFG
-#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0
-#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L
-//XPB_P2P_BAR_CFG
-#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
-#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
-#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
-#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
-#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
-#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
-#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
-#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
-#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
-#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL
-#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L
-#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L
-#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L
-#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L
-#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L
-#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L
-#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L
-#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L
-//XPB_P2P_BAR0
-#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR0__VALID__SHIFT 0xc
-#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR0__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR1
-#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR1__VALID__SHIFT 0xc
-#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR1__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR2
-#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR2__VALID__SHIFT 0xc
-#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR2__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR3
-#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR3__VALID__SHIFT 0xc
-#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR3__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR4
-#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR4__VALID__SHIFT 0xc
-#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR4__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR5
-#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR5__VALID__SHIFT 0xc
-#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR5__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR6
-#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR6__VALID__SHIFT 0xc
-#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR6__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR7
-#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
-#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
-#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR7__VALID__SHIFT 0xc
-#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL
-#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L
-#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR7__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR_SETUP
-#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
-#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
-#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
-#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
-#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
-#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
-#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
-#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL
-#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L
-#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L
-#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L
-#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L
-#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L
-#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L
-//XPB_P2P_BAR_DELTA_ABOVE
-#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
-#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
-#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL
-#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L
-//XPB_P2P_BAR_DELTA_BELOW
-#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
-#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
-#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL
-#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L
-//XPB_PEER_SYS_BAR0
-#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR1
-#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR2
-#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR3
-#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR4
-#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR5
-#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR6
-#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR7
-#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR8
-#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL
-//XPB_PEER_SYS_BAR9
-#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
-#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1
-#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L
-#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL
-//XPB_XDMA_PEER_SYS_BAR0
-#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
-#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1
-#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L
-#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
-//XPB_XDMA_PEER_SYS_BAR1
-#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
-#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1
-#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L
-#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
-//XPB_XDMA_PEER_SYS_BAR2
-#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
-#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1
-#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L
-#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
-//XPB_XDMA_PEER_SYS_BAR3
-#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
-#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1
-#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L
-#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
-//XPB_CLK_GAT
-#define XPB_CLK_GAT__ONDLY__SHIFT 0x0
-#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6
-#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc
-#define XPB_CLK_GAT__ENABLE__SHIFT 0x12
-#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
-#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL
-#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L
-#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L
-#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L
-#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L
-//XPB_INTF_CFG
-#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
-#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
-#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
-#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
-#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
-#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
-#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
-#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
-#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
-#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
-#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
-#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL
-#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L
-#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L
-#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L
-#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L
-#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L
-#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L
-#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L
-#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L
-#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L
-#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L
-//XPB_INTF_STS
-#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
-#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
-#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
-#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
-#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
-#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
-#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
-#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL
-#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L
-#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L
-#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L
-#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L
-#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L
-#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L
-//XPB_PIPE_STS
-#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
-#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
-#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
-#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
-#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
-#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
-#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
-#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
-#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
-#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
-#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
-#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
-#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
-#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L
-#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL
-#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L
-#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L
-#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L
-#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L
-#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L
-#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L
-#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L
-#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L
-#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L
-#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L
-#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L
-//XPB_SUB_CTRL
-#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
-#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
-#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
-#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
-#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
-#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
-#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
-#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
-#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
-#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
-#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
-#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
-#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
-#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
-#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
-#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
-#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
-#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
-#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
-#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
-#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L
-#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L
-#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L
-#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L
-#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L
-#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L
-#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L
-#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L
-#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L
-#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L
-#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L
-#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L
-#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L
-#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L
-#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L
-#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L
-#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L
-#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L
-#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L
-#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L
-//XPB_MAP_INVERT_FLUSH_NUM_LSB
-#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
-#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL
-//XPB_PERF_KNOBS
-#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
-#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
-#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
-#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL
-#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L
-#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L
-//XPB_STICKY
-#define XPB_STICKY__BITS__SHIFT 0x0
-#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL
-//XPB_STICKY_W1C
-#define XPB_STICKY_W1C__BITS__SHIFT 0x0
-#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL
-//XPB_MISC_CFG
-#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
-#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
-#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
-#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
-#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
-#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL
-#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L
-#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L
-#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L
-#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L
-//XPB_INTF_CFG2
-#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
-#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL
-//XPB_CLG_EXTRA_RD
-#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0
-#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6
-#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb
-#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc
-#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf
-#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15
-#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a
-#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b
-#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL
-#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L
-#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L
-#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L
-#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L
-#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L
-#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L
-#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L
-//XPB_CLG_EXTRA_MSK_RD
-#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0
-#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6
-#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb
-#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11
-#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL
-#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L
-#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L
-#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L
-//XPB_CLG_GFX_MATCH
-#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0
-#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6
-#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc
-#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12
-#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18
-#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19
-#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a
-#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b
-#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL
-#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
-#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L
-#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
-#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L
-#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L
-#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L
-#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L
-//XPB_CLG_GFX_MATCH_MSK
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
-#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
-//XPB_CLG_MM_MATCH
-#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0
-#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6
-#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc
-#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12
-#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18
-#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19
-#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a
-#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b
-#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL
-#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
-#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L
-#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
-#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L
-#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L
-#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L
-#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L
-//XPB_CLG_MM_MATCH_MSK
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
-#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
-//XPB_CLG_GFX_UNITID_MAPPING0
-#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING1
-#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING2
-#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING3
-#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING4
-#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING5
-#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING6
-#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_GFX_UNITID_MAPPING7
-#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_MM_UNITID_MAPPING0
-#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_MM_UNITID_MAPPING1
-#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_MM_UNITID_MAPPING2
-#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
-//XPB_CLG_MM_UNITID_MAPPING3
-#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
-#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
-#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
-#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
-#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
-#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
-
-
-// addressBlock: athub_rpbdec
-//RPB_PASSPW_CONF
-#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0
-#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1
-#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2
-#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3
-#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4
-#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5
-#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6
-#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7
-#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8
-#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9
-#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa
-#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb
-#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc
-#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd
-#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe
-#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf
-#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10
-#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11
-#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L
-#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L
-#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L
-#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L
-#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L
-#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L
-#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L
-#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L
-#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L
-#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L
-#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L
-#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L
-#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L
-#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L
-#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L
-#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L
-#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L
-#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L
-//RPB_BLOCKLEVEL_CONF
-#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0
-#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2
-#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4
-#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6
-#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8
-#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa
-#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc
-#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe
-#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf
-#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10
-#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11
-#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L
-#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL
-#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L
-#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L
-#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L
-#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L
-#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L
-#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L
-#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L
-#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L
-#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L
-//RPB_TAG_CONF
-#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0
-#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8
-#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10
-#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL
-#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L
-#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L
-//RPB_EFF_CNTL
-#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
-#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
-#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL
-#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L
-//RPB_ARB_CNTL
-#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0
-#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8
-#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10
-#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18
-#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19
-#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL
-#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L
-#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L
-#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L
-#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L
-//RPB_ARB_CNTL2
-#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0
-#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8
-#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10
-#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL
-#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L
-#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L
-//RPB_BIF_CNTL
-#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0
-#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8
-#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10
-#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11
-#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12
-#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13
-#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b
-#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c
-#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d
-#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e
-#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL
-#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L
-#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L
-#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L
-#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L
-#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L
-#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L
-#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L
-#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L
-#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L
-//RPB_WR_SWITCH_CNTL
-#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
-#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
-#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
-#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
-#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
-#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
-#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
-#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
-#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
-#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
-//RPB_RD_SWITCH_CNTL
-#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
-#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
-#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
-#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
-#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
-#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
-#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
-#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
-#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
-#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
-//RPB_CID_QUEUE_WR
-#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0
-#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5
-#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb
-#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc
-#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf
-#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12
-#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL
-#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L
-#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L
-#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L
-#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L
-#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L
-//RPB_CID_QUEUE_RD
-#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0
-#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5
-#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb
-#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe
-#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL
-#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L
-#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L
-#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L
-//RPB_CID_QUEUE_EX
-#define RPB_CID_QUEUE_EX__START__SHIFT 0x0
-#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
-#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L
-#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL
-//RPB_CID_QUEUE_EX_DATA
-#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
-#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
-#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL
-#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L
-//RPB_SWITCH_CNTL2
-#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0
-#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7
-#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe
-#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15
-#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL
-#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L
-#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L
-#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L
-//RPB_DEINTRLV_COMBINE_CNTL
-#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0
-#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4
-#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5
-#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL
-#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L
-#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L
-//RPB_VC_SWITCH_RDWR
-#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0
-#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2
-#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa
-#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L
-#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL
-#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L
-//RPB_PERFCOUNTER_LO
-#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//RPB_PERFCOUNTER_HI
-#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//RPB_PERFCOUNTER0_CFG
-#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//RPB_PERFCOUNTER1_CFG
-#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//RPB_PERFCOUNTER2_CFG
-#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//RPB_PERFCOUNTER3_CFG
-#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
-#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
-#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
-#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
-#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
-#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
-#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
-#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
-#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
-//RPB_PERFCOUNTER_RSLT_CNTL
-#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-//RPB_RD_QUEUE_CNTL
-#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
-#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
-#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
-#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
-#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
-#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
-#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
-#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
-#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
-#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
-#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
-#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
-#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
-#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
-#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
-#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
-#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
-#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
-//RPB_RD_QUEUE_CNTL2
-#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
-#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
-#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
-#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
-#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
-#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
-#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
-#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
-//RPB_WR_QUEUE_CNTL
-#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
-#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
-#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
-#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
-#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
-#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
-#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
-#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
-#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
-#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
-#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
-#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
-#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
-#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
-#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
-#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
-#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
-#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
-//RPB_WR_QUEUE_CNTL2
-#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
-#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
-#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
-#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
-#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
-#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
-#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
-#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
-//RPB_EA_QUEUE_WR
-#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0
-#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5
-#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8
-#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb
-#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL
-#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L
-#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L
-#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L
-//RPB_ATS_CNTL
-#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0
-#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1
-#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2
-#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7
-#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf
-#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13
-#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17
-#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19
-#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L
-#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L
-#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL
-#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L
-#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L
-#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L
-#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L
-#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L
-//RPB_ATS_CNTL2
-#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0
-#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6
-#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc
-#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf
-#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12
-#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL
-#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L
-#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L
-#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L
-#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L
-//RPB_SDPPORT_CNTL
-#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0
-#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1
-#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3
-#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4
-#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5
-#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6
-#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa
-#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb
-#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd
-#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe
-#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf
-#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10
-#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14
-#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b
-#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L
-#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L
-#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L
-#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L
-#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L
-#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L
-#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L
-#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L
-#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L
-#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L
-#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L
-#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L
-#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L
-#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L
-#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
deleted file mode 100644
index 8a0007c..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
+++ /dev/null
@@ -1,9868 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _dce_12_0_DEFAULT_HEADER
-#define _dce_12_0_DEFAULT_HEADER
-
-
-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
-#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
-#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon0_dispdec
-#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon13_dispdec
-#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_displaypllregs_dispdec
-#define mmPPLL_VREG_CFG_DEFAULT 0x00000000
-#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100
-#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040
-#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002
-#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090
-#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004
-#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500
-#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004
-#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000
-#define mmPPLL_POSTDIV_DEFAULT 0x00000400
-#define mmPPLL_OBSERVE0_DEFAULT 0x00000000
-#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000
-#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000
-#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dccg_pll0_dispdec
-#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon1_dispdec
-#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_mcif_wb0_dispdec
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
-#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
-#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
-#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
-#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
-#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
-
-
-// addressBlock: dce_dc_mcif_wb1_dispdec
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
-#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
-#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
-#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
-#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
-#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
-
-
-// addressBlock: dce_dc_mcif_wb2_dispdec
-#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
-#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
-#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
-#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
-#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
-#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
-
-
-// addressBlock: dce_dc_cwb0_dispdec
-#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110
-#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
-#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff
-#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000
-#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
-#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
-#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_cwb1_dispdec
-#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110
-#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
-#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff
-#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000
-#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
-#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
-#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
-#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon9_dispdec
-#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dispdec
-#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
-#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
-#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f
-#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f
-#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000
-#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002
-#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000
-#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000
-#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000
-#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000
-#define mmD1VGA_CONTROL_DEFAULT 0x00000000
-#define mmD2VGA_CONTROL_DEFAULT 0x00000000
-#define mmVGA_STATUS_DEFAULT 0x00000000
-#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000
-#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018
-#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000
-#define mmVGA_QOS_CTRL_DEFAULT 0x00000000
-#define mmCRTC8_IDX_DEFAULT 0x00000000
-#define mmCRTC8_DATA_DEFAULT 0x00000000
-#define mmGENFC_WT_DEFAULT 0x00000000
-#define mmGENS1_DEFAULT 0x00000000
-#define mmATTRDW_DEFAULT 0x00000000
-#define mmATTRX_DEFAULT 0x00000000
-#define mmATTRDR_DEFAULT 0x00000000
-#define mmGENMO_WT_DEFAULT 0x00000000
-#define mmGENS0_DEFAULT 0x00000000
-#define mmGENENB_DEFAULT 0x00000000
-#define mmSEQ8_IDX_DEFAULT 0x00000000
-#define mmSEQ8_DATA_DEFAULT 0x00000000
-#define mmDAC_MASK_DEFAULT 0x00000000
-#define mmDAC_R_INDEX_DEFAULT 0x00000000
-#define mmDAC_W_INDEX_DEFAULT 0x00000000
-#define mmDAC_DATA_DEFAULT 0x00000000
-#define mmGENFC_RD_DEFAULT 0x00000000
-#define mmGENMO_RD_DEFAULT 0x00000000
-#define mmGRPH8_IDX_DEFAULT 0x00000000
-#define mmGRPH8_DATA_DEFAULT 0x00000000
-#define mmCRTC8_IDX_1_DEFAULT 0x00000000
-#define mmCRTC8_DATA_1_DEFAULT 0x00000000
-#define mmGENFC_WT_1_DEFAULT 0x00000000
-#define mmGENS1_1_DEFAULT 0x00000000
-#define mmD3VGA_CONTROL_DEFAULT 0x00000000
-#define mmD4VGA_CONTROL_DEFAULT 0x00000000
-#define mmD5VGA_CONTROL_DEFAULT 0x00000000
-#define mmD6VGA_CONTROL_DEFAULT 0x00000000
-#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100
-#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000
-#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100
-#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmREFCLK_CNTL_DEFAULT 0x00000000
-#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000
-#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003
-#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000
-#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000
-#define mmDCCG_DS_CNTL_DEFAULT 0x00000000
-#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680
-#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600
-#define mmDPREFCLK_CNTL_DEFAULT 0x00000000
-#define mmAOMCLK0_CNTL_DEFAULT 0x00000000
-#define mmAOMCLK1_CNTL_DEFAULT 0x00000000
-#define mmAOMCLK2_CNTL_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001
-#define mmDCE_VERSION_DEFAULT 0x00000000
-#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000
-#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000
-#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000
-#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064
-#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000
-#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000
-#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000
-#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000
-#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000
-#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000
-#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000
-#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmSMU_CONTROL_DEFAULT 0x00000000
-#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000
-#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0
-#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028
-#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001
-#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800
-#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd
-#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000
-#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464
-#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f
-#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
-#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
-#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000
-#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO0_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO0_MODULO_DEFAULT 0x00000000
-#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO1_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO1_MODULO_DEFAULT 0x00000000
-#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO2_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO2_MODULO_DEFAULT 0x00000000
-#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO3_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO3_MODULO_DEFAULT 0x00000000
-#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO4_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO4_MODULO_DEFAULT 0x00000000
-#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP_DTO5_PHASE_DEFAULT 0x00000000
-#define mmDP_DTO5_MODULO_DEFAULT 0x00000000
-#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000
-#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000
-#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100
-#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200
-#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300
-#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400
-#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500
-#define mmDVOACLKD_CNTL_DEFAULT 0x00070000
-#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000
-#define mmDVOACLKC_CNTL_DEFAULT 0x00030000
-#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030
-#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001
-#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000
-#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001
-#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff
-#define mmFBC_CNTL_DEFAULT 0x00000500
-#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000
-#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000
-#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f
-#define mmFBC_COMP_MODE_DEFAULT 0x00000000
-#define mmFBC_IND_LUT0_DEFAULT 0x00000000
-#define mmFBC_IND_LUT1_DEFAULT 0x00000000
-#define mmFBC_IND_LUT2_DEFAULT 0x00000000
-#define mmFBC_IND_LUT3_DEFAULT 0x00000000
-#define mmFBC_IND_LUT4_DEFAULT 0x00000000
-#define mmFBC_IND_LUT5_DEFAULT 0x00000000
-#define mmFBC_IND_LUT6_DEFAULT 0x00000000
-#define mmFBC_IND_LUT7_DEFAULT 0x00000000
-#define mmFBC_IND_LUT8_DEFAULT 0x00000000
-#define mmFBC_IND_LUT9_DEFAULT 0x00000000
-#define mmFBC_IND_LUT10_DEFAULT 0x00000000
-#define mmFBC_IND_LUT11_DEFAULT 0x00000000
-#define mmFBC_IND_LUT12_DEFAULT 0x00000000
-#define mmFBC_IND_LUT13_DEFAULT 0x00000000
-#define mmFBC_IND_LUT14_DEFAULT 0x00000000
-#define mmFBC_IND_LUT15_DEFAULT 0x00000000
-#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000
-#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000
-#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000
-#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000
-#define mmFBC_MISC_DEFAULT 0x0c306008
-#define mmFBC_STATUS_DEFAULT 0x00000000
-#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000
-#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000
-#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001
-#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000
-#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000
-#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001
-#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000
-#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000
-#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001
-#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000
-#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000
-#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001
-#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000
-#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000
-#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001
-#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000
-#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000
-#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001
-#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000
-#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000
-#define mmDSI_PG_CONFIG_DEFAULT 0x00000001
-#define mmDSI_PG_ENABLE_DEFAULT 0x00000000
-#define mmDSI_PG_STATUS_DEFAULT 0x00000000
-#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001
-#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000
-#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000
-#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000
-#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001
-#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000
-#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000
-#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000
-#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000
-#define mmDMIFV_STATUS_DEFAULT 0x00000000
-#define mmDMIF_CONTROL_DEFAULT 0x00000c04
-#define mmDMIF_STATUS_DEFAULT 0x0ff00000
-#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710
-#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmDMIF_P_VMID_DEFAULT 0x00000000
-#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000
-#define mmDMIF_STATUS2_DEFAULT 0x00000000
-#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmPIPE1_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmPIPE2_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmPIPE3_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmPIPE4_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmPIPE5_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmLOW_POWER_TILING_CONTROL_DEFAULT 0x00001000
-#define mmMCIF_CONTROL_DEFAULT 0x00000000
-#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080
-#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000
-#define mmSMU_WM_CONTROL_DEFAULT 0x00000000
-#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00
-#define mmRBBMIF_STATUS_DEFAULT 0x80000000
-#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000
-#define mmDCI_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCI_MEM_PWR_STATUS2_DEFAULT 0x00000000
-#define mmDCI_CLK_CNTL_DEFAULT 0x00000000
-#define mmDCI_CLK_CNTL2_DEFAULT 0x00020020
-#define mmDCI_MEM_PWR_CNTL_DEFAULT 0x00000000
-#define mmDCI_MEM_PWR_CNTL2_DEFAULT 0x00000000
-#define mmDCI_MEM_PWR_CNTL3_DEFAULT 0x00000000
-#define mmPIPE0_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmPIPE1_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmPIPE2_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmPIPE3_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmPIPE4_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmPIPE5_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000
-#define mmDCI_SOFT_RESET_DEFAULT 0x00000000
-#define mmDMIF_URG_OVERRIDE_DEFAULT 0x00000000
-#define mmPIPE6_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE7_ARBITRATION_CONTROL3_DEFAULT 0x00000000
-#define mmPIPE6_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmPIPE7_MAX_REQUESTS_DEFAULT 0x000003ff
-#define mmDVMM_REG_RD_STATUS_DEFAULT 0x00000000
-#define mmDVMM_REG_RD_DATA_DEFAULT 0x00000000
-#define mmDVMM_PTE_REQ_DEFAULT 0x000120ff
-#define mmDVMM_CNTL_DEFAULT 0x00000000
-#define mmDVMM_FAULT_STATUS_DEFAULT 0x00000000
-#define mmDVMM_FAULT_ADDR_DEFAULT 0x00000000
-#define mmFMON_CTRL_DEFAULT 0x0000f040
-#define mmDVMM_PTE_PGMEM_CONTROL_DEFAULT 0x00000000
-#define mmDVMM_PTE_PGMEM_STATE_DEFAULT 0x00000000
-#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
-#define mmDCI_MEM_PWR_CNTL4_DEFAULT 0x0000003f
-#define mmMCIF_WB_MISC_CTRL_DEFAULT 0x00010001
-#define mmDCI_MEM_PWR_STATUS3_DEFAULT 0x00000000
-#define mmDMIF_CURSOR_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_CURSOR_MEM_CONTROL_DEFAULT 0x00000000
-#define mmDCHUB_FB_LOCATION_DEFAULT 0x00000000
-#define mmDCHUB_FB_OFFSET_DEFAULT 0x00000000
-#define mmDCHUB_AGP_BASE_DEFAULT 0x00000000
-#define mmDCHUB_AGP_BOT_DEFAULT 0x00000000
-#define mmDCHUB_AGP_TOP_DEFAULT 0x00000000
-#define mmDCHUB_DRAM_APER_BASE_DEFAULT 0x00000000
-#define mmDCHUB_DRAM_APER_DEF_DEFAULT 0x00000000
-#define mmDCHUB_DRAM_APER_TOP_DEFAULT 0x00000000
-#define mmDCHUB_CONTROL_STATUS_DEFAULT 0x00c00000
-#define mmWB_ENABLE_DEFAULT 0x00000000
-#define mmWB_EC_CONFIG_DEFAULT 0x55000000
-#define mmCNV_MODE_DEFAULT 0x00000000
-#define mmCNV_WINDOW_START_DEFAULT 0x00000000
-#define mmCNV_WINDOW_SIZE_DEFAULT 0x00100010
-#define mmCNV_UPDATE_DEFAULT 0x00000000
-#define mmCNV_SOURCE_SIZE_DEFAULT 0x00100010
-#define mmCNV_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCNV_CSC_C11_C12_DEFAULT 0x00000000
-#define mmCNV_CSC_C13_C14_DEFAULT 0x00000000
-#define mmCNV_CSC_C21_C22_DEFAULT 0x00000000
-#define mmCNV_CSC_C23_C24_DEFAULT 0x00000000
-#define mmCNV_CSC_C31_C32_DEFAULT 0x00000000
-#define mmCNV_CSC_C33_C34_DEFAULT 0x00000000
-#define mmCNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000
-#define mmCNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000
-#define mmCNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000
-#define mmCNV_CSC_CLAMP_R_DEFAULT 0x00000fff
-#define mmCNV_CSC_CLAMP_G_DEFAULT 0x00000fff
-#define mmCNV_CSC_CLAMP_B_DEFAULT 0x00000fff
-#define mmCNV_TEST_CNTL_DEFAULT 0x00000000
-#define mmCNV_TEST_CRC_RED_DEFAULT 0x0000fff0
-#define mmCNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0
-#define mmCNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0
-#define mmCNV_INPUT_SELECT_DEFAULT 0x00000000
-#define mmWB_SOFT_RESET_DEFAULT 0x00000000
-#define mmWB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100
-#define mmWB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100
-#define mmWBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmWBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmWBSCL_MODE_DEFAULT 0x00000000
-#define mmWBSCL_TAP_CONTROL_DEFAULT 0x00001111
-#define mmWBSCL_DEST_SIZE_DEFAULT 0x00010001
-#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000
-#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
-#define mmWBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000
-#define mmWBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000
-#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
-#define mmWBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000
-#define mmWBSCL_ROUND_OFFSET_DEFAULT 0x00800010
-#define mmWBSCL_CLAMP_DEFAULT 0x01fe01fe
-#define mmWBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000
-#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmWBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000
-#define mmWBSCL_TEST_CNTL_DEFAULT 0x00000000
-#define mmWBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00
-#define mmWBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff
-#define mmWBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00
-#define mmWBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000
-#define mmWB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000
-#define mmWBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000
-#define mmDMCU_CTRL_DEFAULT 0xffff0101
-#define mmDMCU_STATUS_DEFAULT 0x00000001
-#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000
-#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000
-#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000
-#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004
-#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000
-#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000
-#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000
-#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000
-#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000
-#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000
-#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000
-#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000
-#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000
-#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000
-#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000
-#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000
-#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000
-#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000
-#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000
-#define mmDMCU_INT_CNT_DEFAULT 0x00000000
-#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000
-#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102
-#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000
-#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000
-#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000
-#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000
-#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000
-#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000
-#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000
-#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000
-#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000
-#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000
-#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000
-#define mmBL1_PWM_USER_LEVEL_DEFAULT 0x00000000
-#define mmBL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000
-#define mmBL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000
-#define mmBL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000
-#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000
-#define mmBL1_PWM_ABM_CNTL_DEFAULT 0x00000000
-#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmBL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000
-#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000
-#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000
-#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
-#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
-#define mmDC_ABM1_CNTL_DEFAULT 0x00000000
-#define mmDC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000
-#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400
-#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400
-#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400
-#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400
-#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400
-#define mmDC_ABM1_ACE_THRES_12_DEFAULT 0x00000000
-#define mmDC_ABM1_ACE_THRES_34_DEFAULT 0x00000000
-#define mmDC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000
-#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_OVR_SCAN_BIN_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmDC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_1_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_2_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_3_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_4_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_5_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_6_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_7_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_8_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_9_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_10_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_11_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_12_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_13_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_14_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_15_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_16_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_17_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_18_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_19_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_20_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_21_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_22_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_23_DEFAULT 0x00000000
-#define mmDC_ABM1_HG_RESULT_24_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000
-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000
-#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_DEFAULT 0x00000000
-#define mmDC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000
-#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000
-#define mmAZALIA_AUDIO_DTO_DEFAULT 0x001b0018
-#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001
-#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000
-#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a
-#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a
-#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000
-#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000
-#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000
-#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060
-#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008
-#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080
-#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000
-#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000
-#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01
-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700
-#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100
-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
-#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000
-#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000
-#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
-#define mmDAC_ENABLE_DEFAULT 0x00000004
-#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000
-#define mmDAC_CRC_EN_DEFAULT 0x00000000
-#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff
-#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f
-#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff
-#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f
-#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000
-#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000
-#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000
-#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b
-#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519
-#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000
-#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000
-#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000
-#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6
-#define mmDAC_POWERDOWN_DEFAULT 0x01010100
-#define mmDAC_CONTROL_DEFAULT 0x00000000
-#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000
-#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000
-#define mmDAC_PWR_CNTL_DEFAULT 0x00000000
-#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000
-#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_CONTROL_DEFAULT 0x00000000
-#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001
-#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000
-#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000
-#define mmDC_I2C_DATA_DEFAULT 0x00000000
-#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000
-#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002
-#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000
-#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4
-#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000
-#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000
-#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000
-#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002
-#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000
-#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000
-#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000
-#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000
-#define mmDCO_SCRATCH0_DEFAULT 0x00000000
-#define mmDCO_SCRATCH1_DEFAULT 0x00000000
-#define mmDCO_SCRATCH2_DEFAULT 0x00000000
-#define mmDCO_SCRATCH3_DEFAULT 0x00000000
-#define mmDCO_SCRATCH4_DEFAULT 0x00000000
-#define mmDCO_SCRATCH5_DEFAULT 0x00000000
-#define mmDCO_SCRATCH6_DEFAULT 0x00000000
-#define mmDCO_SCRATCH7_DEFAULT 0x00000000
-#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000
-#define mmDCO_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCO_MEM_PWR_CTRL_DEFAULT 0x6db6d800
-#define mmDCO_MEM_PWR_CTRL2_DEFAULT 0x001b0000
-#define mmDCO_CLK_CNTL_DEFAULT 0x00000000
-#define mmDCO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000
-#define mmDIG_SOFT_RESET_2_DEFAULT 0x00000000
-#define mmDCO_STEREOSYNC_SEL_DEFAULT 0x00000000
-#define mmDCO_SOFT_RESET_DEFAULT 0x00000000
-#define mmDIG_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCO_MEM_PWR_STATUS1_DEFAULT 0x00000000
-#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000
-#define mmDCO_CLK_CNTL2_DEFAULT 0x00000000
-#define mmDCO_CLK_CNTL3_DEFAULT 0x00000000
-#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000
-#define mmDCO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000
-#define mmDCO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000
-#define mmDCO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000
-#define mmFMT_MEMORY0_CONTROL_DEFAULT 0x00000030
-#define mmFMT_MEMORY1_CONTROL_DEFAULT 0x00000031
-#define mmFMT_MEMORY2_CONTROL_DEFAULT 0x00000032
-#define mmFMT_MEMORY3_CONTROL_DEFAULT 0x00000033
-#define mmFMT_MEMORY4_CONTROL_DEFAULT 0x00000034
-#define mmFMT_MEMORY5_CONTROL_DEFAULT 0x00000035
-#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000
-#define mmDC_GENERICA_DEFAULT 0x00000000
-#define mmDC_GENERICB_DEFAULT 0x00000000
-#define mmDC_PAD_EXTERN_SIG_DEFAULT 0x00000000
-#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000
-#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101
-#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333
-#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000
-#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000
-#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000
-#define mmBL_PWM_CNTL_DEFAULT 0x00000000
-#define mmBL_PWM_CNTL2_DEFAULT 0x00000000
-#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001
-#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000
-#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000
-#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000
-#define mmDCIO_GSL0_CNTL_DEFAULT 0x00000000
-#define mmDCIO_GSL1_CNTL_DEFAULT 0x00000000
-#define mmDCIO_GSL2_CNTL_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000
-#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000
-#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000
-#define mmDCO_DCFE_EXT_VSYNC_CNTL_DEFAULT 0x00000000
-#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4
-#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000
-#define mmAUXP_IMPCAL_DEFAULT 0x0a000000
-#define mmAUXN_IMPCAL_DEFAULT 0x04000000
-#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000
-#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000
-#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000
-#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000
-#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000
-#define mmUNIPHYLPA_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYLPB_LINK_CNTL_DEFAULT 0x01100100
-#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
-#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000
-#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000
-#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000
-#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444
-#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000
-#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000
-#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000
-#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040
-#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000
-#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10
-#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000
-#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440
-#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000
-#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202
-#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040
-#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000
-#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47ac470f
-#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147
-#define mmPHY_AUX_CNTL_DEFAULT 0x00010001
-#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c
-#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060
-#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000
-#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000
-#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000
-#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202
-#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000
-#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000
-#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000
-#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000
-#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f
-#define mmBPHYC_DAC_MACRO_CNTL_DEFAULT 0x00202002
-#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_DEFAULT 0x00700255
-#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDISP_DSI_DUAL_CTRL_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDPRX_AUX_REFERENCE_PULSE_DIV_DEFAULT 0x0a640064
-#define mmDPRX_AUX_CONTROL_DEFAULT 0x01012c00
-#define mmDPRX_AUX_HPD_CONTROL1_DEFAULT 0x00001407
-#define mmDPRX_AUX_HPD_CONTROL2_DEFAULT 0x00000000
-#define mmDPRX_AUX_RX_STATUS_DEFAULT 0x00000000
-#define mmDPRX_AUX_RX_ERROR_MASK_DEFAULT 0x00000000
-#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDPRX_AUX_DPHY_TX_CONTROL_DEFAULT 0x00001002
-#define mmDPRX_AUX_DPHY_RX_CONTROL0_DEFAULT 0x203d1210
-#define mmDPRX_AUX_DPHY_RX_CONTROL1_DEFAULT 0x0a00fa00
-#define mmDPRX_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDPRX_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDPRX_AUX_DMCU_HW_INT_STATUS_DEFAULT 0x00003f00
-#define mmDPRX_AUX_DMCU_HW_INT_ACK_DEFAULT 0x00000000
-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_DEFAULT 0x00000000
-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_DEFAULT 0x00000001
-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_DEFAULT 0x00000000
-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_DEFAULT 0x00000000
-#define mmDPRX_AUX_AUX_BUF_INDEX_DEFAULT 0x00000000
-#define mmDPRX_AUX_AUX_BUF_DATA_DEFAULT 0x00000000
-#define mmDPRX_AUX_EDID_INDEX_DEFAULT 0x00000000
-#define mmDPRX_AUX_EDID_DATA_DEFAULT 0x00000000
-#define mmDPRX_AUX_DPCD_INDEX1_DEFAULT 0x00000000
-#define mmDPRX_AUX_DPCD_DATA1_DEFAULT 0x00000000
-#define mmDPRX_AUX_DPCD_INDEX2_DEFAULT 0x00000000
-#define mmDPRX_AUX_DPCD_DATA2_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG_INDEX1_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG_DATA1_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG_INDEX2_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG_DATA2_DEFAULT 0x00000000
-#define mmDPRX_AUX_KSV_INDEX1_DEFAULT 0x00000000
-#define mmDPRX_AUX_KSV_DATA1_DEFAULT 0x00000000
-#define mmDPRX_AUX_KSV_INDEX2_DEFAULT 0x00000000
-#define mmDPRX_AUX_KSV_DATA2_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_DEFAULT 0x00000032
-#define mmDPRX_AUX_MSG_BUF_CONTROL1_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG_BUF_CONTROL2_DEFAULT 0x00000000
-#define mmDPRX_AUX_SCRATCH1_DEFAULT 0x00000000
-#define mmDPRX_AUX_SCRATCH2_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG1_PENDING_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG2_PENDING_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG3_PENDING_DEFAULT 0x00000000
-#define mmDPRX_AUX_MSG4_PENDING_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_DEFAULT 0x00000003
-#define mmDPRX_DPHY_DPCD_MSTM_CTRL_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_DEFAULT 0x20000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_DEFAULT 0x20000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_DEFAULT 0x20000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_DEFAULT 0x20000000
-#define mmDPRX_DPHY_READY_DEFAULT 0x00000000
-#define mmDPRX_DPHY_COMMA_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_DEFAULT 0x00000000
-#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_DEFAULT 0x00000000
-#define mmDPRX_DPHY_SR_ERROR_COUNT_A_DEFAULT 0x00000000
-#define mmDPRX_DPHY_BS_ERROR_COUNT_A_DEFAULT 0x00000000
-#define mmDPRX_DPHY_BS_ERROR_COUNT_B_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LANESETUP0_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LANESETUP1_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LFSRADV_DEFAULT 0x00000039
-#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_DEFAULT 0x00000000
-#define mmDPRX_DPHY_SET_ENABLE_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ECF_LSB_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ECF_MSB_DEFAULT 0x00000000
-#define mmDPRX_DPHY_ENHANCED_FRAME_EN_DEFAULT 0x00000001
-#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_DEFAULT 0x000a6800
-#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_DEFAULT 0xbcbcbcbc
-#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_DEFAULT 0x800071c5
-#define mmDPRX_DPHY_BYPASS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_INT_RESET_DEFAULT 0x00000000
-#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_DEFAULT 0x00000000
-#define mmDPRX_DPHY_SPARE_DEFAULT 0x00000000
-#define mmDCRX_GATE_DISABLE_CNTL_DEFAULT 0x00001f0f
-#define mmDCRX_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCRX_LIGHT_SLEEP_CNTL_DEFAULT 0x00000101
-#define mmDCRX_DISPCLK_GATE_CNTL_DEFAULT 0x00000200
-#define mmDCRX_CLK_CNTL_DEFAULT 0x00000000
-#define mmDCRX_TEST_CLK_CNTL_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_DEFAULT 0x00000000
-#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_DEFAULT 0x00000000
-#define mmI2S0_CNTL_DEFAULT 0x00010000
-#define mmSPDIF0_CNTL_DEFAULT 0x00000000
-#define mmI2S1_CNTL_DEFAULT 0x00010000
-#define mmSPDIF1_CNTL_DEFAULT 0x00000000
-#define mmI2S0_STATUS_DEFAULT 0x00000000
-#define mmI2S1_STATUS_DEFAULT 0x00000000
-#define mmI2S0_CRC_TEST_CNTL_DEFAULT 0x00000100
-#define mmI2S0_CRC_TEST_DATA_01_DEFAULT 0x00000000
-#define mmI2S0_CRC_TEST_DATA_23_DEFAULT 0x00000000
-#define mmI2S1_CRC_TEST_CNTL_DEFAULT 0x00000100
-#define mmI2S1_CRC_TEST_DATA_0_DEFAULT 0x00000000
-#define mmSPDIF0_CRC_TEST_CNTL_DEFAULT 0x00000100
-#define mmSPDIF0_CRC_TEST_DATA_0_DEFAULT 0x00000000
-#define mmSPDIF1_CRC_TEST_CNTL_DEFAULT 0x00000100
-#define mmSPDIF1_CRC_TEST_DATA_DEFAULT 0x00000000
-#define mmCRC_I2S_CONT_REPEAT_NUM_DEFAULT 0x00000000
-#define mmCRC_SPDIF_CONT_REPEAT_NUM_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream0_dispdec
-#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream1_dispdec
-#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream2_dispdec
-#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream3_dispdec
-#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream4_dispdec
-#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream5_dispdec
-#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream6_dispdec
-#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream7_dispdec
-#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint0_dispdec
-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint1_dispdec
-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint2_dispdec
-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint3_dispdec
-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint4_dispdec
-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint5_dispdec
-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint6_dispdec
-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0endpoint7_dispdec
-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream8_dispdec
-#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream9_dispdec
-#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream10_dispdec
-#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream11_dispdec
-#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream12_dispdec
-#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream13_dispdec
-#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream14_dispdec
-#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0stream15_dispdec
-#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
-#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint0_dispdec
-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint1_dispdec
-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint2_dispdec
-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint3_dispdec
-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint4_dispdec
-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint5_dispdec
-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint6_dispdec
-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azf0inputendpoint7_dispdec
-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcp0_dispdec
-#define mmDCP0_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmDCP0_GRPH_CONTROL_DEFAULT 0x20002040
-#define mmDCP0_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_PITCH_DEFAULT 0x00000000
-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
-#define mmDCP0_GRPH_X_START_DEFAULT 0x00000000
-#define mmDCP0_GRPH_Y_START_DEFAULT 0x00000000
-#define mmDCP0_GRPH_X_END_DEFAULT 0x00000000
-#define mmDCP0_GRPH_Y_END_DEFAULT 0x00000000
-#define mmDCP0_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmDCP0_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
-#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
-#define mmDCP0_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_GRPH_DFQ_STATUS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
-#define mmDCP0_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
-#define mmDCP0_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
-#define mmDCP0_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
-#define mmDCP0_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
-#define mmDCP0_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_INPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP0_INPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP0_INPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP0_INPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP0_INPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP0_INPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP0_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP0_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP0_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP0_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP0_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP0_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP0_DENORM_CONTROL_DEFAULT 0x00000003
-#define mmDCP0_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
-#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
-#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
-#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
-#define mmDCP0_KEY_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_KEY_RANGE_ALPHA_DEFAULT 0x00000000
-#define mmDCP0_KEY_RANGE_RED_DEFAULT 0x00000000
-#define mmDCP0_KEY_RANGE_GREEN_DEFAULT 0x00000000
-#define mmDCP0_KEY_RANGE_BLUE_DEFAULT 0x00000000
-#define mmDCP0_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmDCP0_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmDCP0_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmDCP0_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmDCP0_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmDCP0_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
-#define mmDCP0_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmDCP0_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmDCP0_CUR_CONTROL_DEFAULT 0x00000810
-#define mmDCP0_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP0_CUR_SIZE_DEFAULT 0x00000000
-#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP0_CUR_POSITION_DEFAULT 0x00000000
-#define mmDCP0_CUR_HOT_SPOT_DEFAULT 0x00000000
-#define mmDCP0_CUR_COLOR1_DEFAULT 0x00000000
-#define mmDCP0_CUR_COLOR2_DEFAULT 0x00000000
-#define mmDCP0_CUR_UPDATE_DEFAULT 0x00000000
-#define mmDCP0_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
-#define mmDCP0_CUR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_RW_MODE_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP0_DC_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
-#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
-#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
-#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
-#define mmDCP0_DCP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_DCP_CRC_MASK_DEFAULT 0x00000000
-#define mmDCP0_DCP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmDCP0_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmDCP0_DCP_CRC_LAST_DEFAULT 0x00000000
-#define mmDCP0_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmDCP0_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCP0_DCP_GSL_CONTROL_DEFAULT 0x60000020
-#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
-#define mmDCP0_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
-#define mmDCP0_HW_ROTATION_DEFAULT 0x00000000
-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
-#define mmDCP0_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP0_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP0_ALPHA_CONTROL_DEFAULT 0x00000002
-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
-#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
-#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
-#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
-#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_lb0_dispdec
-#define mmLB0_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLB0_LB_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLB0_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLB0_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLB0_LB_VLINE_START_END_DEFAULT 0x00000000
-#define mmLB0_LB_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLB0_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmLB0_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLB0_LB_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLB0_LB_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLB0_LB_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLB0_LB_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLB0_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLB0_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLB0_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLB0_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLB0_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLB0_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLB0_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLB0_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLB0_LB_BUFFER_STATUS_DEFAULT 0x00000002
-#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-#define mmLB0_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
-#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
-#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
-#define mmLB0_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dcfe0_dispdec
-#define mmDCFE0_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFE0_DCFE_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFE0_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFE0_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFE0_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFE0_DCFE_MISC_DEFAULT 0x00000001
-#define mmDCFE0_DCFE_FLUSH_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon3_dispdec
-#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmif_pg0_dispdec
-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
-#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIF_PG0_DPG_DVMM_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_scl0_dispdec
-#define mmSCL0_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCL0_SCL_MODE_DEFAULT 0x00000000
-#define mmSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL0_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCL0_SCL_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCL0_SCL_UPDATE_DEFAULT 0x00000000
-#define mmSCL0_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmSCL0_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCL0_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCL0_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCL0_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCL0_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCL0_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCL0_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blnd0_dispdec
-#define mmBLND0_BLND_CONTROL_DEFAULT 0xff0220ff
-#define mmBLND0_BLND_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLND0_BLND_CONTROL2_DEFAULT 0x00000010
-#define mmBLND0_BLND_UPDATE_DEFAULT 0x00000000
-#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLND0_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLND0_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtc0_dispdec
-#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTC0_CRTC_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VBI_END_DEFAULT 0x00000003
-#define mmCRTC0_CRTC_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CONTROL_DEFAULT 0x80400110
-#define mmCRTC0_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTC0_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTC0_CRTC_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTC0_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_GSL_CONTROL_DEFAULT 0x00020000
-#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC0_CRTC_DRR_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_fmt0_dispdec
-#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT0_FMT_CRC_CNTL_DEFAULT 0x01000040
-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
-#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT0_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcp1_dispdec
-#define mmDCP1_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmDCP1_GRPH_CONTROL_DEFAULT 0x20002040
-#define mmDCP1_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_PITCH_DEFAULT 0x00000000
-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
-#define mmDCP1_GRPH_X_START_DEFAULT 0x00000000
-#define mmDCP1_GRPH_Y_START_DEFAULT 0x00000000
-#define mmDCP1_GRPH_X_END_DEFAULT 0x00000000
-#define mmDCP1_GRPH_Y_END_DEFAULT 0x00000000
-#define mmDCP1_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmDCP1_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
-#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
-#define mmDCP1_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_GRPH_DFQ_STATUS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
-#define mmDCP1_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
-#define mmDCP1_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
-#define mmDCP1_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
-#define mmDCP1_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
-#define mmDCP1_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_INPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP1_INPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP1_INPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP1_INPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP1_INPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP1_INPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP1_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP1_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP1_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP1_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP1_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP1_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP1_DENORM_CONTROL_DEFAULT 0x00000003
-#define mmDCP1_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
-#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
-#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
-#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
-#define mmDCP1_KEY_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_KEY_RANGE_ALPHA_DEFAULT 0x00000000
-#define mmDCP1_KEY_RANGE_RED_DEFAULT 0x00000000
-#define mmDCP1_KEY_RANGE_GREEN_DEFAULT 0x00000000
-#define mmDCP1_KEY_RANGE_BLUE_DEFAULT 0x00000000
-#define mmDCP1_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmDCP1_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmDCP1_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmDCP1_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmDCP1_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmDCP1_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
-#define mmDCP1_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmDCP1_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmDCP1_CUR_CONTROL_DEFAULT 0x00000810
-#define mmDCP1_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP1_CUR_SIZE_DEFAULT 0x00000000
-#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP1_CUR_POSITION_DEFAULT 0x00000000
-#define mmDCP1_CUR_HOT_SPOT_DEFAULT 0x00000000
-#define mmDCP1_CUR_COLOR1_DEFAULT 0x00000000
-#define mmDCP1_CUR_COLOR2_DEFAULT 0x00000000
-#define mmDCP1_CUR_UPDATE_DEFAULT 0x00000000
-#define mmDCP1_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
-#define mmDCP1_CUR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_RW_MODE_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP1_DC_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
-#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
-#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
-#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
-#define mmDCP1_DCP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_DCP_CRC_MASK_DEFAULT 0x00000000
-#define mmDCP1_DCP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmDCP1_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmDCP1_DCP_CRC_LAST_DEFAULT 0x00000000
-#define mmDCP1_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmDCP1_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCP1_DCP_GSL_CONTROL_DEFAULT 0x60000020
-#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
-#define mmDCP1_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
-#define mmDCP1_HW_ROTATION_DEFAULT 0x00000000
-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
-#define mmDCP1_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP1_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP1_ALPHA_CONTROL_DEFAULT 0x00000002
-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
-#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
-#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
-#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
-#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_lb1_dispdec
-#define mmLB1_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLB1_LB_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLB1_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLB1_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLB1_LB_VLINE_START_END_DEFAULT 0x00000000
-#define mmLB1_LB_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLB1_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmLB1_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLB1_LB_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLB1_LB_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLB1_LB_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLB1_LB_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLB1_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLB1_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLB1_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLB1_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLB1_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLB1_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLB1_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLB1_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLB1_LB_BUFFER_STATUS_DEFAULT 0x00000002
-#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-#define mmLB1_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
-#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
-#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
-#define mmLB1_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dcfe1_dispdec
-#define mmDCFE1_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFE1_DCFE_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFE1_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFE1_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFE1_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFE1_DCFE_MISC_DEFAULT 0x00000001
-#define mmDCFE1_DCFE_FLUSH_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon4_dispdec
-#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmif_pg1_dispdec
-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
-#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIF_PG1_DPG_DVMM_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_scl1_dispdec
-#define mmSCL1_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCL1_SCL_MODE_DEFAULT 0x00000000
-#define mmSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL1_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCL1_SCL_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCL1_SCL_UPDATE_DEFAULT 0x00000000
-#define mmSCL1_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmSCL1_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCL1_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCL1_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCL1_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCL1_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCL1_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCL1_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blnd1_dispdec
-#define mmBLND1_BLND_CONTROL_DEFAULT 0xff0220ff
-#define mmBLND1_BLND_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLND1_BLND_CONTROL2_DEFAULT 0x00000010
-#define mmBLND1_BLND_UPDATE_DEFAULT 0x00000000
-#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLND1_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLND1_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtc1_dispdec
-#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTC1_CRTC_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VBI_END_DEFAULT 0x00000003
-#define mmCRTC1_CRTC_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CONTROL_DEFAULT 0x80400110
-#define mmCRTC1_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTC1_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTC1_CRTC_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTC1_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_GSL_CONTROL_DEFAULT 0x00020000
-#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC1_CRTC_DRR_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_fmt1_dispdec
-#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT1_FMT_CRC_CNTL_DEFAULT 0x01000040
-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
-#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT1_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcp2_dispdec
-#define mmDCP2_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmDCP2_GRPH_CONTROL_DEFAULT 0x20002040
-#define mmDCP2_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_PITCH_DEFAULT 0x00000000
-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
-#define mmDCP2_GRPH_X_START_DEFAULT 0x00000000
-#define mmDCP2_GRPH_Y_START_DEFAULT 0x00000000
-#define mmDCP2_GRPH_X_END_DEFAULT 0x00000000
-#define mmDCP2_GRPH_Y_END_DEFAULT 0x00000000
-#define mmDCP2_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmDCP2_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
-#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
-#define mmDCP2_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_GRPH_DFQ_STATUS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
-#define mmDCP2_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
-#define mmDCP2_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
-#define mmDCP2_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
-#define mmDCP2_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
-#define mmDCP2_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_INPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP2_INPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP2_INPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP2_INPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP2_INPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP2_INPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP2_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP2_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP2_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP2_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP2_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP2_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP2_DENORM_CONTROL_DEFAULT 0x00000003
-#define mmDCP2_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
-#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
-#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
-#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
-#define mmDCP2_KEY_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_KEY_RANGE_ALPHA_DEFAULT 0x00000000
-#define mmDCP2_KEY_RANGE_RED_DEFAULT 0x00000000
-#define mmDCP2_KEY_RANGE_GREEN_DEFAULT 0x00000000
-#define mmDCP2_KEY_RANGE_BLUE_DEFAULT 0x00000000
-#define mmDCP2_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmDCP2_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmDCP2_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmDCP2_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmDCP2_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmDCP2_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
-#define mmDCP2_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmDCP2_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmDCP2_CUR_CONTROL_DEFAULT 0x00000810
-#define mmDCP2_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP2_CUR_SIZE_DEFAULT 0x00000000
-#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP2_CUR_POSITION_DEFAULT 0x00000000
-#define mmDCP2_CUR_HOT_SPOT_DEFAULT 0x00000000
-#define mmDCP2_CUR_COLOR1_DEFAULT 0x00000000
-#define mmDCP2_CUR_COLOR2_DEFAULT 0x00000000
-#define mmDCP2_CUR_UPDATE_DEFAULT 0x00000000
-#define mmDCP2_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
-#define mmDCP2_CUR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_RW_MODE_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP2_DC_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
-#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
-#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
-#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
-#define mmDCP2_DCP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_DCP_CRC_MASK_DEFAULT 0x00000000
-#define mmDCP2_DCP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmDCP2_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmDCP2_DCP_CRC_LAST_DEFAULT 0x00000000
-#define mmDCP2_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmDCP2_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCP2_DCP_GSL_CONTROL_DEFAULT 0x60000020
-#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
-#define mmDCP2_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
-#define mmDCP2_HW_ROTATION_DEFAULT 0x00000000
-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
-#define mmDCP2_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP2_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP2_ALPHA_CONTROL_DEFAULT 0x00000002
-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
-#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
-#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
-#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
-#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_lb2_dispdec
-#define mmLB2_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLB2_LB_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLB2_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLB2_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLB2_LB_VLINE_START_END_DEFAULT 0x00000000
-#define mmLB2_LB_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLB2_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmLB2_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLB2_LB_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLB2_LB_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLB2_LB_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLB2_LB_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLB2_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLB2_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLB2_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLB2_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLB2_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLB2_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLB2_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLB2_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLB2_LB_BUFFER_STATUS_DEFAULT 0x00000002
-#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-#define mmLB2_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
-#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
-#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
-#define mmLB2_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dcfe2_dispdec
-#define mmDCFE2_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFE2_DCFE_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFE2_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFE2_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFE2_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFE2_DCFE_MISC_DEFAULT 0x00000001
-#define mmDCFE2_DCFE_FLUSH_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon5_dispdec
-#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmif_pg2_dispdec
-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
-#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIF_PG2_DPG_DVMM_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_scl2_dispdec
-#define mmSCL2_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCL2_SCL_MODE_DEFAULT 0x00000000
-#define mmSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL2_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCL2_SCL_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCL2_SCL_UPDATE_DEFAULT 0x00000000
-#define mmSCL2_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmSCL2_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCL2_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCL2_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCL2_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCL2_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCL2_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCL2_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blnd2_dispdec
-#define mmBLND2_BLND_CONTROL_DEFAULT 0xff0220ff
-#define mmBLND2_BLND_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLND2_BLND_CONTROL2_DEFAULT 0x00000010
-#define mmBLND2_BLND_UPDATE_DEFAULT 0x00000000
-#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLND2_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLND2_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtc2_dispdec
-#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTC2_CRTC_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VBI_END_DEFAULT 0x00000003
-#define mmCRTC2_CRTC_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CONTROL_DEFAULT 0x80400110
-#define mmCRTC2_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTC2_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTC2_CRTC_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTC2_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_GSL_CONTROL_DEFAULT 0x00020000
-#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC2_CRTC_DRR_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_fmt2_dispdec
-#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT2_FMT_CRC_CNTL_DEFAULT 0x01000040
-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
-#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT2_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcp3_dispdec
-#define mmDCP3_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmDCP3_GRPH_CONTROL_DEFAULT 0x20002040
-#define mmDCP3_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_PITCH_DEFAULT 0x00000000
-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
-#define mmDCP3_GRPH_X_START_DEFAULT 0x00000000
-#define mmDCP3_GRPH_Y_START_DEFAULT 0x00000000
-#define mmDCP3_GRPH_X_END_DEFAULT 0x00000000
-#define mmDCP3_GRPH_Y_END_DEFAULT 0x00000000
-#define mmDCP3_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmDCP3_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
-#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
-#define mmDCP3_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_GRPH_DFQ_STATUS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
-#define mmDCP3_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
-#define mmDCP3_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
-#define mmDCP3_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
-#define mmDCP3_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
-#define mmDCP3_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_INPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP3_INPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP3_INPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP3_INPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP3_INPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP3_INPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP3_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP3_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP3_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP3_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP3_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP3_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP3_DENORM_CONTROL_DEFAULT 0x00000003
-#define mmDCP3_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
-#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
-#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
-#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
-#define mmDCP3_KEY_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_KEY_RANGE_ALPHA_DEFAULT 0x00000000
-#define mmDCP3_KEY_RANGE_RED_DEFAULT 0x00000000
-#define mmDCP3_KEY_RANGE_GREEN_DEFAULT 0x00000000
-#define mmDCP3_KEY_RANGE_BLUE_DEFAULT 0x00000000
-#define mmDCP3_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmDCP3_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmDCP3_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmDCP3_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmDCP3_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmDCP3_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
-#define mmDCP3_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmDCP3_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmDCP3_CUR_CONTROL_DEFAULT 0x00000810
-#define mmDCP3_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP3_CUR_SIZE_DEFAULT 0x00000000
-#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP3_CUR_POSITION_DEFAULT 0x00000000
-#define mmDCP3_CUR_HOT_SPOT_DEFAULT 0x00000000
-#define mmDCP3_CUR_COLOR1_DEFAULT 0x00000000
-#define mmDCP3_CUR_COLOR2_DEFAULT 0x00000000
-#define mmDCP3_CUR_UPDATE_DEFAULT 0x00000000
-#define mmDCP3_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
-#define mmDCP3_CUR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_RW_MODE_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP3_DC_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
-#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
-#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
-#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
-#define mmDCP3_DCP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_DCP_CRC_MASK_DEFAULT 0x00000000
-#define mmDCP3_DCP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmDCP3_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmDCP3_DCP_CRC_LAST_DEFAULT 0x00000000
-#define mmDCP3_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmDCP3_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCP3_DCP_GSL_CONTROL_DEFAULT 0x60000020
-#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
-#define mmDCP3_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
-#define mmDCP3_HW_ROTATION_DEFAULT 0x00000000
-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
-#define mmDCP3_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP3_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP3_ALPHA_CONTROL_DEFAULT 0x00000002
-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
-#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
-#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
-#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
-#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_lb3_dispdec
-#define mmLB3_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLB3_LB_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLB3_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLB3_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLB3_LB_VLINE_START_END_DEFAULT 0x00000000
-#define mmLB3_LB_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLB3_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmLB3_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLB3_LB_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLB3_LB_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLB3_LB_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLB3_LB_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLB3_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLB3_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLB3_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLB3_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLB3_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLB3_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLB3_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLB3_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLB3_LB_BUFFER_STATUS_DEFAULT 0x00000002
-#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-#define mmLB3_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
-#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
-#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
-#define mmLB3_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dcfe3_dispdec
-#define mmDCFE3_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFE3_DCFE_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFE3_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFE3_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFE3_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFE3_DCFE_MISC_DEFAULT 0x00000001
-#define mmDCFE3_DCFE_FLUSH_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon6_dispdec
-#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmif_pg3_dispdec
-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
-#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIF_PG3_DPG_DVMM_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_scl3_dispdec
-#define mmSCL3_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCL3_SCL_MODE_DEFAULT 0x00000000
-#define mmSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL3_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCL3_SCL_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCL3_SCL_UPDATE_DEFAULT 0x00000000
-#define mmSCL3_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmSCL3_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCL3_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCL3_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCL3_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCL3_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCL3_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCL3_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blnd3_dispdec
-#define mmBLND3_BLND_CONTROL_DEFAULT 0xff0220ff
-#define mmBLND3_BLND_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLND3_BLND_CONTROL2_DEFAULT 0x00000010
-#define mmBLND3_BLND_UPDATE_DEFAULT 0x00000000
-#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLND3_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLND3_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtc3_dispdec
-#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTC3_CRTC_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VBI_END_DEFAULT 0x00000003
-#define mmCRTC3_CRTC_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CONTROL_DEFAULT 0x80400110
-#define mmCRTC3_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTC3_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTC3_CRTC_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTC3_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_GSL_CONTROL_DEFAULT 0x00020000
-#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC3_CRTC_DRR_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_fmt3_dispdec
-#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT3_FMT_CRC_CNTL_DEFAULT 0x01000040
-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
-#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT3_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcp4_dispdec
-#define mmDCP4_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmDCP4_GRPH_CONTROL_DEFAULT 0x20002040
-#define mmDCP4_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_PITCH_DEFAULT 0x00000000
-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
-#define mmDCP4_GRPH_X_START_DEFAULT 0x00000000
-#define mmDCP4_GRPH_Y_START_DEFAULT 0x00000000
-#define mmDCP4_GRPH_X_END_DEFAULT 0x00000000
-#define mmDCP4_GRPH_Y_END_DEFAULT 0x00000000
-#define mmDCP4_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmDCP4_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
-#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
-#define mmDCP4_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_GRPH_DFQ_STATUS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
-#define mmDCP4_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
-#define mmDCP4_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
-#define mmDCP4_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
-#define mmDCP4_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
-#define mmDCP4_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_INPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP4_INPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP4_INPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP4_INPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP4_INPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP4_INPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP4_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP4_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP4_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP4_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP4_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP4_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP4_DENORM_CONTROL_DEFAULT 0x00000003
-#define mmDCP4_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
-#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
-#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
-#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
-#define mmDCP4_KEY_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_KEY_RANGE_ALPHA_DEFAULT 0x00000000
-#define mmDCP4_KEY_RANGE_RED_DEFAULT 0x00000000
-#define mmDCP4_KEY_RANGE_GREEN_DEFAULT 0x00000000
-#define mmDCP4_KEY_RANGE_BLUE_DEFAULT 0x00000000
-#define mmDCP4_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmDCP4_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmDCP4_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmDCP4_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmDCP4_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmDCP4_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
-#define mmDCP4_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmDCP4_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmDCP4_CUR_CONTROL_DEFAULT 0x00000810
-#define mmDCP4_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP4_CUR_SIZE_DEFAULT 0x00000000
-#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP4_CUR_POSITION_DEFAULT 0x00000000
-#define mmDCP4_CUR_HOT_SPOT_DEFAULT 0x00000000
-#define mmDCP4_CUR_COLOR1_DEFAULT 0x00000000
-#define mmDCP4_CUR_COLOR2_DEFAULT 0x00000000
-#define mmDCP4_CUR_UPDATE_DEFAULT 0x00000000
-#define mmDCP4_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
-#define mmDCP4_CUR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_RW_MODE_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP4_DC_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
-#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
-#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
-#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
-#define mmDCP4_DCP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_DCP_CRC_MASK_DEFAULT 0x00000000
-#define mmDCP4_DCP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmDCP4_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmDCP4_DCP_CRC_LAST_DEFAULT 0x00000000
-#define mmDCP4_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmDCP4_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCP4_DCP_GSL_CONTROL_DEFAULT 0x60000020
-#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
-#define mmDCP4_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
-#define mmDCP4_HW_ROTATION_DEFAULT 0x00000000
-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
-#define mmDCP4_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP4_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP4_ALPHA_CONTROL_DEFAULT 0x00000002
-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
-#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
-#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
-#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
-#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_lb4_dispdec
-#define mmLB4_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLB4_LB_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLB4_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLB4_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLB4_LB_VLINE_START_END_DEFAULT 0x00000000
-#define mmLB4_LB_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLB4_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmLB4_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLB4_LB_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLB4_LB_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLB4_LB_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLB4_LB_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLB4_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLB4_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLB4_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLB4_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLB4_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLB4_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLB4_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLB4_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLB4_LB_BUFFER_STATUS_DEFAULT 0x00000002
-#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-#define mmLB4_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
-#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
-#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
-#define mmLB4_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dcfe4_dispdec
-#define mmDCFE4_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFE4_DCFE_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFE4_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFE4_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFE4_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFE4_DCFE_MISC_DEFAULT 0x00000001
-#define mmDCFE4_DCFE_FLUSH_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon7_dispdec
-#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmif_pg4_dispdec
-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
-#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIF_PG4_DPG_DVMM_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_scl4_dispdec
-#define mmSCL4_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCL4_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCL4_SCL_MODE_DEFAULT 0x00000000
-#define mmSCL4_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL4_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL4_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL4_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCL4_SCL_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCL4_SCL_UPDATE_DEFAULT 0x00000000
-#define mmSCL4_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmSCL4_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCL4_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCL4_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCL4_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCL4_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCL4_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCL4_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blnd4_dispdec
-#define mmBLND4_BLND_CONTROL_DEFAULT 0xff0220ff
-#define mmBLND4_BLND_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLND4_BLND_CONTROL2_DEFAULT 0x00000010
-#define mmBLND4_BLND_UPDATE_DEFAULT 0x00000000
-#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLND4_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLND4_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtc4_dispdec
-#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTC4_CRTC_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VBI_END_DEFAULT 0x00000003
-#define mmCRTC4_CRTC_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CONTROL_DEFAULT 0x80400110
-#define mmCRTC4_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTC4_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTC4_CRTC_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTC4_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_GSL_CONTROL_DEFAULT 0x00020000
-#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC4_CRTC_DRR_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_fmt4_dispdec
-#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT4_FMT_CRC_CNTL_DEFAULT 0x01000040
-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
-#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT4_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcp5_dispdec
-#define mmDCP5_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmDCP5_GRPH_CONTROL_DEFAULT 0x20002040
-#define mmDCP5_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_PITCH_DEFAULT 0x00000000
-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
-#define mmDCP5_GRPH_X_START_DEFAULT 0x00000000
-#define mmDCP5_GRPH_Y_START_DEFAULT 0x00000000
-#define mmDCP5_GRPH_X_END_DEFAULT 0x00000000
-#define mmDCP5_GRPH_Y_END_DEFAULT 0x00000000
-#define mmDCP5_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmDCP5_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
-#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
-#define mmDCP5_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_GRPH_DFQ_STATUS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
-#define mmDCP5_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
-#define mmDCP5_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
-#define mmDCP5_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
-#define mmDCP5_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
-#define mmDCP5_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_INPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP5_INPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP5_INPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP5_INPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP5_INPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP5_INPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP5_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
-#define mmDCP5_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
-#define mmDCP5_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
-#define mmDCP5_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
-#define mmDCP5_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
-#define mmDCP5_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
-#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
-#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
-#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
-#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
-#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
-#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
-#define mmDCP5_DENORM_CONTROL_DEFAULT 0x00000003
-#define mmDCP5_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
-#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
-#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
-#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
-#define mmDCP5_KEY_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_KEY_RANGE_ALPHA_DEFAULT 0x00000000
-#define mmDCP5_KEY_RANGE_RED_DEFAULT 0x00000000
-#define mmDCP5_KEY_RANGE_GREEN_DEFAULT 0x00000000
-#define mmDCP5_KEY_RANGE_BLUE_DEFAULT 0x00000000
-#define mmDCP5_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmDCP5_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmDCP5_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmDCP5_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmDCP5_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmDCP5_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
-#define mmDCP5_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
-#define mmDCP5_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmDCP5_CUR_CONTROL_DEFAULT 0x00000810
-#define mmDCP5_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP5_CUR_SIZE_DEFAULT 0x00000000
-#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP5_CUR_POSITION_DEFAULT 0x00000000
-#define mmDCP5_CUR_HOT_SPOT_DEFAULT 0x00000000
-#define mmDCP5_CUR_COLOR1_DEFAULT 0x00000000
-#define mmDCP5_CUR_COLOR2_DEFAULT 0x00000000
-#define mmDCP5_CUR_UPDATE_DEFAULT 0x00000000
-#define mmDCP5_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
-#define mmDCP5_CUR_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_RW_MODE_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP5_DC_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
-#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
-#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
-#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
-#define mmDCP5_DCP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_DCP_CRC_MASK_DEFAULT 0x00000000
-#define mmDCP5_DCP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmDCP5_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmDCP5_DCP_CRC_LAST_DEFAULT 0x00000000
-#define mmDCP5_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmDCP5_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
-#define mmDCP5_DCP_GSL_CONTROL_DEFAULT 0x60000020
-#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
-#define mmDCP5_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
-#define mmDCP5_HW_ROTATION_DEFAULT 0x00000000
-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
-#define mmDCP5_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmDCP5_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmDCP5_ALPHA_CONTROL_DEFAULT 0x00000002
-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
-#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
-#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
-#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
-#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_lb5_dispdec
-#define mmLB5_LB_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLB5_LB_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLB5_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLB5_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLB5_LB_VLINE_START_END_DEFAULT 0x00000000
-#define mmLB5_LB_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLB5_LB_V_COUNTER_DEFAULT 0x00000000
-#define mmLB5_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLB5_LB_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLB5_LB_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLB5_LB_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLB5_LB_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLB5_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLB5_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLB5_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLB5_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLB5_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLB5_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLB5_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLB5_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLB5_LB_BUFFER_STATUS_DEFAULT 0x00000002
-#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-#define mmLB5_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
-#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
-#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
-#define mmLB5_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dcfe5_dispdec
-#define mmDCFE5_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFE5_DCFE_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFE5_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFE5_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFE5_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFE5_DCFE_MISC_DEFAULT 0x00000001
-#define mmDCFE5_DCFE_FLUSH_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon8_dispdec
-#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmif_pg5_dispdec
-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
-#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIF_PG5_DPG_DVMM_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_scl5_dispdec
-#define mmSCL5_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCL5_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCL5_SCL_MODE_DEFAULT 0x00000000
-#define mmSCL5_SCL_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL5_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL5_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCL5_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCL5_SCL_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCL5_SCL_UPDATE_DEFAULT 0x00000000
-#define mmSCL5_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
-#define mmSCL5_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCL5_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCL5_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCL5_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCL5_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCL5_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCL5_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blnd5_dispdec
-#define mmBLND5_BLND_CONTROL_DEFAULT 0xff0220ff
-#define mmBLND5_BLND_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLND5_BLND_CONTROL2_DEFAULT 0x00000010
-#define mmBLND5_BLND_UPDATE_DEFAULT 0x00000000
-#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLND5_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLND5_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtc5_dispdec
-#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTC5_CRTC_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VBI_END_DEFAULT 0x00000003
-#define mmCRTC5_CRTC_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CONTROL_DEFAULT 0x80400110
-#define mmCRTC5_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTC5_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTC5_CRTC_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTC5_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_GSL_CONTROL_DEFAULT 0x00020000
-#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTC5_CRTC_DRR_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_fmt5_dispdec
-#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
-#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
-#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
-#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
-#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000
-#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
-#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
-#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
-#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
-#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000
-#define mmFMT5_FMT_CRC_CNTL_DEFAULT 0x01000040
-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
-#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmFMT5_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_unp0_dispdec
-#define mmUNP0_UNP_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmUNP0_UNP_GRPH_CONTROL_DEFAULT 0x0a008008
-#define mmUNP0_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000
-#define mmUNP0_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PITCH_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_PITCH_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_X_START_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_X_START_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_Y_START_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_Y_START_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_X_END_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_X_END_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_Y_END_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_Y_END_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff
-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000
-#define mmUNP0_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000
-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220
-#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020
-#define mmUNP0_UNP_FLIP_CONTROL_DEFAULT 0x00000001
-#define mmUNP0_UNP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmUNP0_UNP_CRC_MASK_DEFAULT 0x00000000
-#define mmUNP0_UNP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmUNP0_UNP_CRC_LAST_DEFAULT 0x00000000
-#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100
-#define mmUNP0_UNP_HW_ROTATION_DEFAULT 0x00000010
-
-
-// addressBlock: dce_dc_lbv0_dispdec
-#define mmLBV0_LBV_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLBV0_LBV_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLBV0_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLBV0_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLBV0_LBV_VLINE_START_END_DEFAULT 0x00000000
-#define mmLBV0_LBV_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLBV0_LBV_V_COUNTER_DEFAULT 0x00000000
-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLBV0_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000
-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000
-#define mmLBV0_LBV_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLBV0_LBV_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLBV0_LBV_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLBV0_LBV_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLBV0_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLBV0_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLBV0_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLBV0_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLBV0_LBV_BUFFER_STATUS_DEFAULT 0x12000002
-#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_sclv0_dispdec
-#define mmSCLV0_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_MODE_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCLV0_SCLV_UPDATE_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000
-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-
-
-// addressBlock: dce_dc_col_man0_dispdec
-#define mmCOL_MAN0_COL_MAN_UPDATE_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000
-#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000
-#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000
-#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000
-#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000
-#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000
-#define mmCOL_MAN0_PRESCALE_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_PRESCALE_VALUES_R_DEFAULT 0x20000000
-#define mmCOL_MAN0_PRESCALE_VALUES_G_DEFAULT 0x20000000
-#define mmCOL_MAN0_PRESCALE_VALUES_B_DEFAULT 0x20000000
-#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000
-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000
-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000
-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000
-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000
-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000
-#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff
-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff
-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff
-#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmCOL_MAN0_PACK_FIFO_ERROR_DEFAULT 0x00000000
-#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000
-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000
-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000
-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000
-#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-
-
-// addressBlock: dce_dc_dcfev0_dispdec
-#define mmDCFEV0_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_L_FLUSH_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_C_FLUSH_DEFAULT 0x00000000
-#define mmDCFEV0_DCFEV_MISC_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dc_perfmon11_dispdec
-#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmifv_pg0_dispdec
-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
-#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000
-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
-#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
-#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
-#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000
-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
-#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
-#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blndv0_dispdec
-#define mmBLNDV0_BLNDV_CONTROL_DEFAULT 0xff0220ff
-#define mmBLNDV0_BLNDV_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLNDV0_BLNDV_CONTROL2_DEFAULT 0x00000010
-#define mmBLNDV0_BLNDV_UPDATE_DEFAULT 0x00000000
-#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtcv0_dispdec
-#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTCV0_CRTCV_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VBI_END_DEFAULT 0x00000003
-#define mmCRTCV0_CRTCV_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CONTROL_DEFAULT 0x80400110
-#define mmCRTCV0_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTCV0_CRTCV_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTCV0_CRTCV_GSL_CONTROL_DEFAULT 0x00020000
-
-
-// addressBlock: dce_dc_unp1_dispdec
-#define mmUNP1_UNP_GRPH_ENABLE_DEFAULT 0x00000001
-#define mmUNP1_UNP_GRPH_CONTROL_DEFAULT 0x0a008008
-#define mmUNP1_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000
-#define mmUNP1_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PITCH_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_PITCH_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_X_START_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_X_START_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_Y_START_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_Y_START_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_X_END_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_X_END_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_Y_END_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_Y_END_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_UPDATE_DEFAULT 0x00000000
-#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff
-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000
-#define mmUNP1_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000
-#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000
-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220
-#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020
-#define mmUNP1_UNP_FLIP_CONTROL_DEFAULT 0x00000001
-#define mmUNP1_UNP_CRC_CONTROL_DEFAULT 0x00000000
-#define mmUNP1_UNP_CRC_MASK_DEFAULT 0x00000000
-#define mmUNP1_UNP_CRC_CURRENT_DEFAULT 0x00000000
-#define mmUNP1_UNP_CRC_LAST_DEFAULT 0x00000000
-#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100
-#define mmUNP1_UNP_HW_ROTATION_DEFAULT 0x00000010
-
-
-// addressBlock: dce_dc_lbv1_dispdec
-#define mmLBV1_LBV_DATA_FORMAT_DEFAULT 0x00000000
-#define mmLBV1_LBV_MEMORY_CTRL_DEFAULT 0x000006b0
-#define mmLBV1_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
-#define mmLBV1_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000
-#define mmLBV1_LBV_VLINE_START_END_DEFAULT 0x00000000
-#define mmLBV1_LBV_VLINE2_START_END_DEFAULT 0x00000000
-#define mmLBV1_LBV_V_COUNTER_DEFAULT 0x00000000
-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
-#define mmLBV1_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000
-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000
-#define mmLBV1_LBV_INTERRUPT_MASK_DEFAULT 0x00000000
-#define mmLBV1_LBV_VLINE_STATUS_DEFAULT 0x00000000
-#define mmLBV1_LBV_VLINE2_STATUS_DEFAULT 0x00000000
-#define mmLBV1_LBV_VBLANK_STATUS_DEFAULT 0x00000000
-#define mmLBV1_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002
-#define mmLBV1_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000
-#define mmLBV1_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000
-#define mmLBV1_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
-#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
-#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
-#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
-#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
-#define mmLBV1_LBV_BUFFER_STATUS_DEFAULT 0x12000002
-#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_sclv1_dispdec
-#define mmSCLV1_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_MODE_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_TAP_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_ROUND_OFFSET_DEFAULT 0x80000000
-#define mmSCLV1_SCLV_UPDATE_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_ALU_CONTROL_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VIEWPORT_START_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000
-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000
-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000
-
-
-// addressBlock: dce_dc_col_man1_dispdec
-#define mmCOL_MAN1_COL_MAN_UPDATE_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000
-#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000
-#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000
-#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000
-#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000
-#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000
-#define mmCOL_MAN1_PRESCALE_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_PRESCALE_VALUES_R_DEFAULT 0x20000000
-#define mmCOL_MAN1_PRESCALE_VALUES_G_DEFAULT 0x20000000
-#define mmCOL_MAN1_PRESCALE_VALUES_B_DEFAULT 0x20000000
-#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000
-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000
-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000
-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000
-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000
-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000
-#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff
-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff
-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff
-#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
-#define mmCOL_MAN1_PACK_FIFO_ERROR_DEFAULT 0x00000000
-#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000
-#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000
-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000
-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000
-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000
-#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
-
-
-// addressBlock: dce_dc_dcfev1_dispdec
-#define mmDCFEV1_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_SOFT_RESET_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_L_FLUSH_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_C_FLUSH_DEFAULT 0x00000000
-#define mmDCFEV1_DCFEV_MISC_DEFAULT 0x00000001
-
-
-// addressBlock: dce_dc_dc_perfmon12_dispdec
-#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dmifv_pg1_dispdec
-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
-#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000
-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
-#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
-#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
-#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000
-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
-#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
-#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000
-#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_blndv1_dispdec
-#define mmBLNDV1_BLNDV_CONTROL_DEFAULT 0xff0220ff
-#define mmBLNDV1_BLNDV_SM_CONTROL2_DEFAULT 0x00000000
-#define mmBLNDV1_BLNDV_CONTROL2_DEFAULT 0x00000010
-#define mmBLNDV1_BLNDV_UPDATE_DEFAULT 0x00000000
-#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
-#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000
-#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_crtcv1_dispdec
-#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
-#define mmCRTCV1_CRTCV_H_TOTAL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_H_SYNC_A_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_H_SYNC_B_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VBI_END_DEFAULT 0x00000003
-#define mmCRTCV1_CRTCV_V_TOTAL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_SYNC_A_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_SYNC_B_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CONTROL_DEFAULT 0x80400110
-#define mmCRTCV1_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STATUS_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_COUNT_RESET_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STEREO_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002
-#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
-#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
-#define mmCRTCV1_CRTCV_MVP_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_MASTER_EN_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
-#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_BLACK_COLOR_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC_CNTL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
-#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
-#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_GSL_WINDOW_DEFAULT 0x00000000
-#define mmCRTCV1_CRTCV_GSL_CONTROL_DEFAULT 0x00020000
-
-
-// addressBlock: dce_dc_hpd0_dispdec
-#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hpd1_dispdec
-#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hpd2_dispdec
-#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hpd3_dispdec
-#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hpd4_dispdec
-#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_hpd5_dispdec
-#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000
-#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
-#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
-#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
-#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon2_dispdec
-#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp_aux0_dispdec
-#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp_aux1_dispdec
-#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp_aux2_dispdec
-#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp_aux3_dispdec
-#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp_aux4_dispdec
-#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp_aux5_dispdec
-#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000
-#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
-#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
-#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
-#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig0_dispdec
-#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp0_dispdec
-#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP0_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP0_DP_VID_N_DEFAULT 0x00002000
-#define mmDP0_DP_VID_M_DEFAULT 0x00000000
-#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig1_dispdec
-#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp1_dispdec
-#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP1_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP1_DP_VID_N_DEFAULT 0x00002000
-#define mmDP1_DP_VID_M_DEFAULT 0x00000000
-#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig2_dispdec
-#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp2_dispdec
-#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP2_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP2_DP_VID_N_DEFAULT 0x00002000
-#define mmDP2_DP_VID_M_DEFAULT 0x00000000
-#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig3_dispdec
-#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp3_dispdec
-#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP3_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP3_DP_VID_N_DEFAULT 0x00002000
-#define mmDP3_DP_VID_M_DEFAULT 0x00000000
-#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig4_dispdec
-#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp4_dispdec
-#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP4_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP4_DP_VID_N_DEFAULT 0x00002000
-#define mmDP4_DP_VID_M_DEFAULT 0x00000000
-#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig5_dispdec
-#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp5_dispdec
-#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP5_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP5_DP_VID_N_DEFAULT 0x00002000
-#define mmDP5_DP_VID_M_DEFAULT 0x00000000
-#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dig6_dispdec
-#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000
-#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
-#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
-#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060
-#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
-#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001
-#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000
-#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
-#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
-#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GC_DEFAULT 0x00000004
-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AVI_INFO0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AVI_INFO1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AVI_INFO2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AVI_INFO3_DEFAULT 0x02000000
-#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000
-#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000
-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
-#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
-#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
-#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
-#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
-#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
-#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
-#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000
-#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001
-#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
-#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000
-#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
-#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
-#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000
-#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000
-#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dp6_dispdec
-#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
-#define mmDP6_DP_CONFIG_DEFAULT 0x00000000
-#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
-#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000
-#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000
-#define mmDP6_DP_VID_N_DEFAULT 0x00002000
-#define mmDP6_DP_VID_M_DEFAULT 0x00000000
-#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
-#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
-#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000
-#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
-#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
-#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
-#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
-#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200
-#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000
-#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
-#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
-#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
-#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
-#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
-#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
-#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy0_dispdec
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs0_dispdec
-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs0_dispdec
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs0_dispdec
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy1_dispdec
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs1_dispdec
-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs1_dispdec
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs1_dispdec
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy2_dispdec
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs2_dispdec
-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs2_dispdec
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs2_dispdec
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy3_dispdec
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs3_dispdec
-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs3_dispdec
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs3_dispdec
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy4_dispdec
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs4_dispdec
-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs4_dispdec
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs4_dispdec
-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy5_dispdec
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs5_dispdec
-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs5_dispdec
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs5_dispdec
-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy6_dispdec
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs6_dispdec
-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs6_dispdec
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs6_dispdec
-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dcio_uniphy8_dispdec
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophycmregs8_dispdec
-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
-#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_DEFAULT 0x00000007
-#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_DEFAULT 0x000000ff
-#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_DEFAULT 0x00000000
-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophytxregs8_dispdec
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_combophypllregs8_dispdec
-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_DEFAULT 0x00280000
-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_DEFAULT 0x00e80000
-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_DEFAULT 0x00000001
-#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_DEFAULT 0x64000000
-#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_DEFAULT 0x00000090
-#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_DEFAULT 0x00000000
-#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dsi0_dispdec
-#define mmDSI0_DISP_DSI_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_STATUS_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000
-#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101
-#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e
-#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900
-#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066
-#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c
-#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900
-#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211
-#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02
-#define mmDSI0_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_EXT_MUX_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_EXT_RESET_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888
-#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff
-#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff
-#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08
-#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f
-#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222
-#define mmDSI0_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001
-#define mmDSI0_DISP_DSI_TE_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000
-#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dsi1_dispdec
-#define mmDSI1_DISP_DSI_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_STATUS_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000
-#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101
-#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e
-#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900
-#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066
-#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c
-#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900
-#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211
-#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02
-#define mmDSI1_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_EXT_MUX_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_EXT_RESET_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888
-#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff
-#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff
-#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08
-#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f
-#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222
-#define mmDSI1_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001
-#define mmDSI1_DISP_DSI_TE_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000
-#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dprx_sd0_dispdec
-#define mmDPRX_SD0_DPRX_SD_CONTROL_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA0_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA1_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA2_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA3_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA4_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA5_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA6_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA7_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA8_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_VBID_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff
-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff
-#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff
-#define mmDPRX_SD0_DPRX_SD_SDP_STEER_DEFAULT 0x00000001
-#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_SDP_DATA_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001
-#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000
-#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dprx_sd1_dispdec
-#define mmDPRX_SD1_DPRX_SD_CONTROL_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA0_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA1_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA2_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA3_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA4_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA5_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA6_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA7_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA8_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_VBID_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff
-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff
-#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff
-#define mmDPRX_SD1_DPRX_SD_SDP_STEER_DEFAULT 0x00000001
-#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_SDP_DATA_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001
-#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000
-#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_perfmon10_dispdec
-#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100
-#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000
-#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dc_zcalregs_dispdec
-#define mmCOMP_EN_CTL_DEFAULT 0x00080000
-#define mmCOMP_EN_DFX_DEFAULT 0x00000000
-#define mmZCAL_FUSES_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
-
-
-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
-
-
-// addressBlock: dce_dc_dispdec[948..986]
-
-
-// addressBlock: dce_dc_azdec
-#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000
-#define mmCORB_READ_POINTER_DEFAULT 0x00000000
-#define mmCORB_CONTROL_DEFAULT 0x00000000
-#define mmCORB_STATUS_DEFAULT 0x00000000
-#define mmCORB_SIZE_DEFAULT 0x00000002
-#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000
-#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000
-#define mmRIRB_CONTROL_DEFAULT 0x00000000
-#define mmRIRB_STATUS_DEFAULT 0x00000000
-#define mmRIRB_SIZE_DEFAULT 0x00000002
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
-#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000
-#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000
-#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream0_azdec
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream1_azdec
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream2_azdec
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream3_azdec
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream4_azdec
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream5_azdec
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream6_azdec
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: dce_dc_azstream7_azdec
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream0_streamind
-#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream1_streamind
-#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream2_streamind
-#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream3_streamind
-#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream4_streamind
-#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream5_streamind
-#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream6_streamind
-#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream7_streamind
-#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream8_streamind
-#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream9_streamind
-#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream10_streamind
-#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream11_streamind
-#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream12_streamind
-#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream13_streamind
-#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream14_streamind
-#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0stream15_streamind
-#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
-#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
-#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint0_endpointind
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint1_endpointind
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint2_endpointind
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint3_endpointind
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint4_endpointind
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint5_endpointind
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint6_endpointind
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0endpoint7_endpointind
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint0_inputendpointind
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint1_inputendpointind
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint2_inputendpointind
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint3_inputendpointind
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint4_inputendpointind
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint5_inputendpointind
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint6_inputendpointind
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: azf0inputendpoint7_inputendpointind
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-
-
-// addressBlock: f2codecind
-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4
-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
-
-
-// addressBlock: descriptorind
-#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000
-#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000
-
-
-// addressBlock: sinkinfoind
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000
-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000
-#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000
-
-
-// addressBlock: azinputcrc0resultind
-#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azinputcrc1resultind
-#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azcrc0resultind
-#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: azcrc1resultind
-#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000
-#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000
-
-
-// addressBlock: vgaseqind
-#define ixSEQ00_DEFAULT 0x00000003
-#define ixSEQ01_DEFAULT 0x00000021
-#define ixSEQ02_DEFAULT 0x00000000
-#define ixSEQ03_DEFAULT 0x00000000
-#define ixSEQ04_DEFAULT 0x00000000
-
-
-// addressBlock: vgacrtind
-#define ixCRT00_DEFAULT 0x00000000
-#define ixCRT01_DEFAULT 0x00000000
-#define ixCRT02_DEFAULT 0x00000000
-#define ixCRT03_DEFAULT 0x00000000
-#define ixCRT04_DEFAULT 0x00000000
-#define ixCRT05_DEFAULT 0x00000000
-#define ixCRT06_DEFAULT 0x00000000
-#define ixCRT07_DEFAULT 0x00000000
-#define ixCRT08_DEFAULT 0x00000000
-#define ixCRT09_DEFAULT 0x00000000
-#define ixCRT0A_DEFAULT 0x00000000
-#define ixCRT0B_DEFAULT 0x00000000
-#define ixCRT0C_DEFAULT 0x00000000
-#define ixCRT0D_DEFAULT 0x00000000
-#define ixCRT0E_DEFAULT 0x00000000
-#define ixCRT0F_DEFAULT 0x00000000
-#define ixCRT10_DEFAULT 0x00000000
-#define ixCRT11_DEFAULT 0x00000000
-#define ixCRT12_DEFAULT 0x00000000
-#define ixCRT13_DEFAULT 0x00000000
-#define ixCRT14_DEFAULT 0x00000000
-#define ixCRT15_DEFAULT 0x00000000
-#define ixCRT16_DEFAULT 0x00000000
-#define ixCRT17_DEFAULT 0x00000000
-#define ixCRT18_DEFAULT 0x00000000
-#define ixCRT1E_DEFAULT 0x00000000
-#define ixCRT1F_DEFAULT 0x00000000
-#define ixCRT22_DEFAULT 0x00000000
-
-
-// addressBlock: vgagrphind
-#define ixGRA00_DEFAULT 0x00000000
-#define ixGRA01_DEFAULT 0x00000000
-#define ixGRA02_DEFAULT 0x00000000
-#define ixGRA03_DEFAULT 0x00000000
-#define ixGRA04_DEFAULT 0x00000000
-#define ixGRA05_DEFAULT 0x00000000
-#define ixGRA06_DEFAULT 0x00000000
-#define ixGRA07_DEFAULT 0x00000000
-#define ixGRA08_DEFAULT 0x00000000
-
-
-// addressBlock: vgaattrind
-#define ixATTR00_DEFAULT 0x00000000
-#define ixATTR01_DEFAULT 0x00000000
-#define ixATTR02_DEFAULT 0x00000000
-#define ixATTR03_DEFAULT 0x00000000
-#define ixATTR04_DEFAULT 0x00000000
-#define ixATTR05_DEFAULT 0x00000000
-#define ixATTR06_DEFAULT 0x00000000
-#define ixATTR07_DEFAULT 0x00000000
-#define ixATTR08_DEFAULT 0x00000000
-#define ixATTR09_DEFAULT 0x00000000
-#define ixATTR0A_DEFAULT 0x00000000
-#define ixATTR0B_DEFAULT 0x00000000
-#define ixATTR0C_DEFAULT 0x00000000
-#define ixATTR0D_DEFAULT 0x00000000
-#define ixATTR0E_DEFAULT 0x00000000
-#define ixATTR0F_DEFAULT 0x00000000
-#define ixATTR10_DEFAULT 0x00000000
-#define ixATTR11_DEFAULT 0x00000000
-#define ixATTR12_DEFAULT 0x00000000
-#define ixATTR13_DEFAULT 0x00000000
-#define ixATTR14_DEFAULT 0x00000000
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
deleted file mode 100644
index 864690c..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _hdp_4_0_DEFAULT_HEADER
-#define _hdp_4_0_DEFAULT_HEADER
-
-
-// addressBlock: hdp_hdpdec
-#define mmHDP_MMHUB_TLVL_DEFAULT 0x00006666
-#define mmHDP_MMHUB_UNITID_DEFAULT 0x00000000
-#define mmHDP_NONSURFACE_BASE_DEFAULT 0x00000000
-#define mmHDP_NONSURFACE_INFO_DEFAULT 0x00000000
-#define mmHDP_NONSURFACE_BASE_HI_DEFAULT 0x00000000
-#define mmHDP_NONSURF_FLAGS_DEFAULT 0x00000000
-#define mmHDP_NONSURF_FLAGS_CLR_DEFAULT 0x00000000
-#define mmHDP_HOST_PATH_CNTL_DEFAULT 0x00680000
-#define mmHDP_SW_SEMAPHORE_DEFAULT 0x00000000
-#define mmHDP_DEBUG0_DEFAULT 0x00000000
-#define mmHDP_LAST_SURFACE_HIT_DEFAULT 0x00000003
-#define mmHDP_READ_CACHE_INVALIDATE_DEFAULT 0x00000000
-#define mmHDP_OUTSTANDING_REQ_DEFAULT 0x00000000
-#define mmHDP_MISC_CNTL_DEFAULT 0x2d200861
-#define mmHDP_MEM_POWER_LS_DEFAULT 0x00000901
-#define mmHDP_MMHUB_CNTL_DEFAULT 0x00000000
-#define mmHDP_EDC_CNT_DEFAULT 0x00000000
-#define mmHDP_VERSION_DEFAULT 0x00000400
-#define mmHDP_CLK_CNTL_DEFAULT 0x0000000f
-#define mmHDP_MEMIO_CNTL_DEFAULT 0x00000000
-#define mmHDP_MEMIO_ADDR_DEFAULT 0x00000000
-#define mmHDP_MEMIO_STATUS_DEFAULT 0x00000000
-#define mmHDP_MEMIO_WR_DATA_DEFAULT 0x00000000
-#define mmHDP_MEMIO_RD_DATA_DEFAULT 0xdeadbeef
-#define mmHDP_XDP_DIRECT2HDP_FIRST_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_FLUSH_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_BAR_UPDATE_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_3_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_4_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_5_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_6_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_7_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_8_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_9_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_10_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_11_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_12_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_13_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_14_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_15_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_16_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_17_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_18_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_19_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_20_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_21_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_22_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_23_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_24_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_25_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_26_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_27_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_28_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_29_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_30_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_31_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_32_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_33_DEFAULT 0x00000000
-#define mmHDP_XDP_D2H_RSVD_34_DEFAULT 0x00000000
-#define mmHDP_XDP_DIRECT2HDP_LAST_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR_CFG_DEFAULT 0x0000000f
-#define mmHDP_XDP_P2P_MBX_OFFSET_DEFAULT 0x000011bc
-#define mmHDP_XDP_P2P_MBX_ADDR0_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_MBX_ADDR1_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_MBX_ADDR2_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_MBX_ADDR3_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_MBX_ADDR4_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_MBX_ADDR5_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_MBX_ADDR6_DEFAULT 0x00000000
-#define mmHDP_XDP_HDP_MBX_MC_CFG_DEFAULT 0x00000000
-#define mmHDP_XDP_HDP_MC_CFG_DEFAULT 0x00020000
-#define mmHDP_XDP_HST_CFG_DEFAULT 0x0000001b
-#define mmHDP_XDP_HDP_IPH_CFG_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR0_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR1_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR2_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR3_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR4_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR5_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR6_DEFAULT 0x00000000
-#define mmHDP_XDP_P2P_BAR7_DEFAULT 0x00000000
-#define mmHDP_XDP_FLUSH_ARMED_STS_DEFAULT 0x00000000
-#define mmHDP_XDP_FLUSH_CNTR0_STS_DEFAULT 0x00000000
-#define mmHDP_XDP_BUSY_STS_DEFAULT 0x00000000
-#define mmHDP_XDP_STICKY_DEFAULT 0x00000000
-#define mmHDP_XDP_CHKN_DEFAULT 0x48584450
-#define mmHDP_XDP_BARS_ADDR_39_36_DEFAULT 0x00000000
-#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
-#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmHDP_XDP_MMHUB_ERROR_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
deleted file mode 100644
index fbad771..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _hdp_4_0_OFFSET_HEADER
-#define _hdp_4_0_OFFSET_HEADER
-
-
-
-// addressBlock: hdp_hdpdec
-// base address: 0x3c80
-#define mmHDP_MMHUB_TLVL 0x0000
-#define mmHDP_MMHUB_TLVL_BASE_IDX 0
-#define mmHDP_MMHUB_UNITID 0x0001
-#define mmHDP_MMHUB_UNITID_BASE_IDX 0
-#define mmHDP_NONSURFACE_BASE 0x0040
-#define mmHDP_NONSURFACE_BASE_BASE_IDX 0
-#define mmHDP_NONSURFACE_INFO 0x0041
-#define mmHDP_NONSURFACE_INFO_BASE_IDX 0
-#define mmHDP_NONSURFACE_BASE_HI 0x0042
-#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0
-#define mmHDP_NONSURF_FLAGS 0x00c8
-#define mmHDP_NONSURF_FLAGS_BASE_IDX 0
-#define mmHDP_NONSURF_FLAGS_CLR 0x00c9
-#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
-#define mmHDP_HOST_PATH_CNTL 0x00cc
-#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0
-#define mmHDP_SW_SEMAPHORE 0x00cd
-#define mmHDP_SW_SEMAPHORE_BASE_IDX 0
-#define mmHDP_DEBUG0 0x00ce
-#define mmHDP_DEBUG0_BASE_IDX 0
-#define mmHDP_LAST_SURFACE_HIT 0x00d0
-#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0
-#define mmHDP_READ_CACHE_INVALIDATE 0x00d1
-#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0
-#define mmHDP_OUTSTANDING_REQ 0x00d2
-#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0
-#define mmHDP_MISC_CNTL 0x00d3
-#define mmHDP_MISC_CNTL_BASE_IDX 0
-#define mmHDP_MEM_POWER_LS 0x00d4
-#define mmHDP_MEM_POWER_LS_BASE_IDX 0
-#define mmHDP_MMHUB_CNTL 0x00d5
-#define mmHDP_MMHUB_CNTL_BASE_IDX 0
-#define mmHDP_EDC_CNT 0x00d6
-#define mmHDP_EDC_CNT_BASE_IDX 0
-#define mmHDP_VERSION 0x00d7
-#define mmHDP_VERSION_BASE_IDX 0
-#define mmHDP_CLK_CNTL 0x00d8
-#define mmHDP_CLK_CNTL_BASE_IDX 0
-#define mmHDP_MEMIO_CNTL 0x00f6
-#define mmHDP_MEMIO_CNTL_BASE_IDX 0
-#define mmHDP_MEMIO_ADDR 0x00f7
-#define mmHDP_MEMIO_ADDR_BASE_IDX 0
-#define mmHDP_MEMIO_STATUS 0x00f8
-#define mmHDP_MEMIO_STATUS_BASE_IDX 0
-#define mmHDP_MEMIO_WR_DATA 0x00f9
-#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0
-#define mmHDP_MEMIO_RD_DATA 0x00fa
-#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0
-#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100
-#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
-#define mmHDP_XDP_D2H_FLUSH 0x0101
-#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0
-#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102
-#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_3 0x0103
-#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_4 0x0104
-#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_5 0x0105
-#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_6 0x0106
-#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_7 0x0107
-#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_8 0x0108
-#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_9 0x0109
-#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_10 0x010a
-#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_11 0x010b
-#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_12 0x010c
-#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_13 0x010d
-#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_14 0x010e
-#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_15 0x010f
-#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_16 0x0110
-#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_17 0x0111
-#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_18 0x0112
-#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_19 0x0113
-#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_20 0x0114
-#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_21 0x0115
-#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_22 0x0116
-#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_23 0x0117
-#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_24 0x0118
-#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_25 0x0119
-#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_26 0x011a
-#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_27 0x011b
-#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_28 0x011c
-#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_29 0x011d
-#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_30 0x011e
-#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_31 0x011f
-#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_32 0x0120
-#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_33 0x0121
-#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0
-#define mmHDP_XDP_D2H_RSVD_34 0x0122
-#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0
-#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123
-#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR_CFG 0x0124
-#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125
-#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126
-#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127
-#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128
-#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129
-#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a
-#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b
-#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
-#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c
-#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
-#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d
-#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
-#define mmHDP_XDP_HDP_MC_CFG 0x012e
-#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0
-#define mmHDP_XDP_HST_CFG 0x012f
-#define mmHDP_XDP_HST_CFG_BASE_IDX 0
-#define mmHDP_XDP_HDP_IPH_CFG 0x0131
-#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR0 0x0134
-#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR1 0x0135
-#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR2 0x0136
-#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR3 0x0137
-#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR4 0x0138
-#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR5 0x0139
-#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR6 0x013a
-#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0
-#define mmHDP_XDP_P2P_BAR7 0x013b
-#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0
-#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c
-#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
-#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d
-#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
-#define mmHDP_XDP_BUSY_STS 0x013e
-#define mmHDP_XDP_BUSY_STS_BASE_IDX 0
-#define mmHDP_XDP_STICKY 0x013f
-#define mmHDP_XDP_STICKY_BASE_IDX 0
-#define mmHDP_XDP_CHKN 0x0140
-#define mmHDP_XDP_CHKN_BASE_IDX 0
-#define mmHDP_XDP_BARS_ADDR_39_36 0x0144
-#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
-#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
-#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
-#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
-#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
-#define mmHDP_XDP_MMHUB_ERROR 0x0149
-#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
deleted file mode 100644
index 5861875..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
+++ /dev/null
@@ -1,601 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _hdp_4_0_SH_MASK_HEADER
-#define _hdp_4_0_SH_MASK_HEADER
-
-
-// addressBlock: hdp_hdpdec
-//HDP_MMHUB_TLVL
-#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
-#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
-#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
-#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
-#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
-#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
-#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
-#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
-#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
-#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
-//HDP_MMHUB_UNITID
-#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0
-#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8
-#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
-#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL
-#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L
-#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L
-//HDP_NONSURFACE_BASE
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
-//HDP_NONSURFACE_INFO
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
-#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L
-#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L
-//HDP_NONSURFACE_BASE_HI
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
-//HDP_NONSURF_FLAGS
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
-//HDP_NONSURF_FLAGS_CLR
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
-//HDP_HOST_PATH_CNTL
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
-#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
-#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
-#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
-#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
-//HDP_SW_SEMAPHORE
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL
-//HDP_DEBUG0
-#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
-#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL
-//HDP_LAST_SURFACE_HIT
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L
-//HDP_READ_CACHE_INVALIDATE
-#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0
-#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L
-//HDP_OUTSTANDING_REQ
-#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
-#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
-#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL
-#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L
-//HDP_MISC_CNTL
-#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
-#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
-#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
-#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
-#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19
-#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a
-#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b
-#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c
-#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e
-#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
-#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
-#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
-#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L
-#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L
-#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L
-#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L
-#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L
-#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L
-//HDP_MEM_POWER_LS
-#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
-#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
-#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L
-#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L
-//HDP_MMHUB_CNTL
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L
-//HDP_EDC_CNT
-#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0
-#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2
-#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L
-#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL
-//HDP_VERSION
-#define HDP_VERSION__MINVER__SHIFT 0x0
-#define HDP_VERSION__MAJVER__SHIFT 0x8
-#define HDP_VERSION__REV__SHIFT 0x10
-#define HDP_VERSION__MINVER_MASK 0x000000FFL
-#define HDP_VERSION__MAJVER_MASK 0x0000FF00L
-#define HDP_VERSION__REV_MASK 0x00FF0000L
-//HDP_CLK_CNTL
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0
-#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL
-#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
-//HDP_MEMIO_CNTL
-#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
-#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
-#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
-#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
-#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
-#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
-#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
-#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
-#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L
-#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L
-//HDP_MEMIO_ADDR
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL
-//HDP_MEMIO_STATUS
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
-//HDP_MEMIO_WR_DATA
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL
-//HDP_MEMIO_RD_DATA
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_FIRST
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_FLUSH
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
-//HDP_XDP_D2H_BAR_UPDATE
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
-//HDP_XDP_D2H_RSVD_3
-#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_4
-#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_5
-#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_6
-#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_7
-#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_8
-#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_9
-#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_10
-#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_11
-#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_12
-#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_13
-#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_14
-#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_15
-#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_16
-#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_17
-#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_18
-#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_19
-#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_20
-#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_21
-#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_22
-#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_23
-#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_24
-#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_25
-#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_26
-#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_27
-#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_28
-#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_29
-#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_30
-#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_31
-#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_32
-#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_33
-#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_34
-#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_LAST
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_P2P_BAR_CFG
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
-//HDP_XDP_P2P_MBX_OFFSET
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL
-//HDP_XDP_P2P_MBX_ADDR0
-#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR1
-#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR2
-#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR3
-#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR4
-#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR5
-#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR6
-#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_HDP_MBX_MC_CFG
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L
-//HDP_XDP_HDP_MC_CFG
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L
-//HDP_XDP_HST_CFG
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L
-//HDP_XDP_HDP_IPH_CFG
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
-//HDP_XDP_P2P_BAR0
-#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR1
-#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR2
-#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR3
-#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR4
-#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR5
-#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR6
-#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR7
-#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
-//HDP_XDP_FLUSH_ARMED_STS
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL
-//HDP_XDP_FLUSH_CNTR0_STS
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL
-//HDP_XDP_BUSY_STS
-#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
-#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL
-//HDP_XDP_STICKY
-#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
-#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
-#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL
-#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L
-//HDP_XDP_CHKN
-#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
-#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
-#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
-#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
-#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL
-#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L
-#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L
-#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L
-//HDP_XDP_BARS_ADDR_39_36
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L
-//HDP_XDP_MC_VM_FB_LOCATION_BASE
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL
-//HDP_XDP_GPU_IOV_VIOLATION_LOG
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//HDP_XDP_MMHUB_ERROR
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
deleted file mode 100644
index 98ba7d8..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mp_9_0_DEFAULT_HEADER
-#define _mp_9_0_DEFAULT_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-#define mmMP0_SMN_C2PMSG_32_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_33_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_34_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_35_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_36_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_37_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_38_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_39_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_40_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_41_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_42_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_43_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_44_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_45_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_46_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_47_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_48_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_49_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_50_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_51_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_52_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_53_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_54_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_55_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_56_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_57_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_58_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_59_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_60_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_61_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_62_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_63_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_64_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_65_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_66_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_67_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_68_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_69_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_70_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_71_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_72_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_73_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_74_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_75_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_76_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_77_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_78_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_79_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_80_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_81_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_82_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_83_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_84_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_85_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_86_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_87_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_88_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_89_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_90_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_91_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_92_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_93_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_94_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_95_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_96_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_97_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_98_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_99_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_100_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_101_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_102_DEFAULT 0x00000000
-#define mmMP0_SMN_C2PMSG_103_DEFAULT 0x00000000
-#define mmMP0_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmMP0_SMN_IH_CREDIT_DEFAULT 0x00000000
-#define mmMP0_SMN_IH_SW_INT_DEFAULT 0x00000000
-#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-#define mmMP1_SMN_ACP2MP_RESP_DEFAULT 0x00000000
-#define mmMP1_SMN_DC2MP_RESP_DEFAULT 0x00000000
-#define mmMP1_SMN_UVD2MP_RESP_DEFAULT 0x00000000
-#define mmMP1_SMN_VCE2MP_RESP_DEFAULT 0x00000000
-#define mmMP1_SMN_RLC2MP_RESP_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_32_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_33_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_34_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_35_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_36_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_37_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_38_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_39_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_40_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_41_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_42_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_43_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_44_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_45_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_46_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_47_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_48_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_49_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_50_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_51_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_52_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_53_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_54_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_55_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_56_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_57_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_58_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_59_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_60_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_61_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_62_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_63_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_64_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_65_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_66_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_67_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_68_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_69_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_70_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_71_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_72_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_73_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_74_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_75_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_76_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_77_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_78_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_79_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_80_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_81_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_82_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_83_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_84_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_85_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_86_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_87_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_88_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_89_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_90_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_91_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_92_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_93_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_94_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_95_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_96_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_97_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_98_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_99_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_100_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_101_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_102_DEFAULT 0x00000000
-#define mmMP1_SMN_C2PMSG_103_DEFAULT 0x00000000
-#define mmMP1_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmMP1_SMN_IH_CREDIT_DEFAULT 0x00000000
-#define mmMP1_SMN_IH_SW_INT_DEFAULT 0x00000000
-#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000
-#define mmMP1_SMN_FPS_CNT_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH0_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH1_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH2_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH3_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH4_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH5_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH6_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH7_DEFAULT 0x00000000
-#define mmMP1_SMN_EXT_SCRATCH8_DEFAULT 0x00000000
-
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-#define mmMP1_SMN_PUB_CTRL_DEFAULT 0x00000001
-#define smnMP1_FIRMWARE_FLAGS_DEFAULT 0x00000000
-#define smnMP1_PUB_SCRATCH0_DEFAULT 0x00000000
-#define smnMP1_PUB_SCRATCH1_DEFAULT 0x00000000
-#define smnMP1_PUB_SCRATCH2_DEFAULT 0x00000000
-#define smnMP1_PUB_SCRATCH3_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_0_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_1_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_2_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_3_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_4_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_5_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_6_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_7_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_8_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_9_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_10_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_11_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_12_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_13_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_14_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_15_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_16_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_17_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_18_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_19_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_20_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_21_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_22_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_23_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_24_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_25_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_26_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_27_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_28_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_29_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_30_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_31_DEFAULT 0x00000000
-#define smnMP1_P2CMSG_0_DEFAULT 0x00000000
-#define smnMP1_P2CMSG_1_DEFAULT 0x00000000
-#define smnMP1_P2CMSG_2_DEFAULT 0x00000000
-#define smnMP1_P2CMSG_3_DEFAULT 0x00000000
-#define smnMP1_P2CMSG_INTEN_DEFAULT 0x00000000
-#define smnMP1_P2CMSG_INTSTS_DEFAULT 0x00000000
-#define smnMP1_P2SMSG_0_DEFAULT 0x00000000
-#define smnMP1_P2SMSG_1_DEFAULT 0x00000000
-#define smnMP1_P2SMSG_2_DEFAULT 0x00000000
-#define smnMP1_P2SMSG_3_DEFAULT 0x00000000
-#define smnMP1_P2SMSG_INTSTS_DEFAULT 0x00000000
-#define smnMP1_S2PMSG_0_DEFAULT 0x00000000
-#define smnMP1_ACP2MP_RESP_DEFAULT 0x00000000
-#define smnMP1_DC2MP_RESP_DEFAULT 0x00000000
-#define smnMP1_UVD2MP_RESP_DEFAULT 0x00000000
-#define smnMP1_VCE2MP_RESP_DEFAULT 0x00000000
-#define smnMP1_RLC2MP_RESP_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_32_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_33_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_34_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_35_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_36_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_37_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_38_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_39_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_40_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_41_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_42_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_43_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_44_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_45_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_46_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_47_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_48_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_49_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_50_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_51_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_52_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_53_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_54_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_55_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_56_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_57_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_58_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_59_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_60_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_61_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_62_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_63_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_64_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_65_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_66_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_67_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_68_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_69_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_70_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_71_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_72_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_73_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_74_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_75_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_76_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_77_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_78_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_79_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_80_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_81_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_82_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_83_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_84_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_85_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_86_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_87_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_88_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_89_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_90_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_91_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_92_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_93_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_94_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_95_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_96_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_97_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_98_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_99_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_100_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_101_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_102_DEFAULT 0x00000000
-#define smnMP1_C2PMSG_103_DEFAULT 0x00000000
-#define smnMP1_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define smnMP1_IH_CREDIT_DEFAULT 0x00000000
-#define smnMP1_IH_SW_INT_DEFAULT 0x00000000
-#define smnMP1_IH_SW_INT_CTRL_DEFAULT 0x00000000
-#define smnMP1_FPS_CNT_DEFAULT 0x00000000
-#define smnMP1_PUB_CTRL_DEFAULT 0x00000001
-#define smnMP1_EXT_SCRATCH0_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH1_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH2_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH3_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH4_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH5_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH6_DEFAULT 0x00000000
-#define smnMP1_EXT_SCRATCH7_DEFAULT 0x00000000
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
deleted file mode 100644
index 621e880..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mp_9_0_OFFSET_HEADER
-#define _mp_9_0_OFFSET_HEADER
-
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-// base address: 0x0
-#define mmMP0_SMN_C2PMSG_32 0x0060
-#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_33 0x0061
-#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_34 0x0062
-#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_35 0x0063
-#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_36 0x0064
-#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_37 0x0065
-#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_38 0x0066
-#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_39 0x0067
-#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_40 0x0068
-#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_41 0x0069
-#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_42 0x006a
-#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_43 0x006b
-#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_44 0x006c
-#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_45 0x006d
-#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_46 0x006e
-#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_47 0x006f
-#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_48 0x0070
-#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_49 0x0071
-#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_50 0x0072
-#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_51 0x0073
-#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_52 0x0074
-#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_53 0x0075
-#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_54 0x0076
-#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_55 0x0077
-#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_56 0x0078
-#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_57 0x0079
-#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_58 0x007a
-#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_59 0x007b
-#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_60 0x007c
-#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_61 0x007d
-#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_62 0x007e
-#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_63 0x007f
-#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_64 0x0080
-#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_65 0x0081
-#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_66 0x0082
-#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_67 0x0083
-#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_68 0x0084
-#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_69 0x0085
-#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_70 0x0086
-#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_71 0x0087
-#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_72 0x0088
-#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_73 0x0089
-#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_74 0x008a
-#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_75 0x008b
-#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_76 0x008c
-#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_77 0x008d
-#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_78 0x008e
-#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_79 0x008f
-#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_80 0x0090
-#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_81 0x0091
-#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_82 0x0092
-#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_83 0x0093
-#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_84 0x0094
-#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_85 0x0095
-#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_86 0x0096
-#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_87 0x0097
-#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_88 0x0098
-#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_89 0x0099
-#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_90 0x009a
-#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_91 0x009b
-#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_92 0x009c
-#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_93 0x009d
-#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_94 0x009e
-#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_95 0x009f
-#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_96 0x00a0
-#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_97 0x00a1
-#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_98 0x00a2
-#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_99 0x00a3
-#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_100 0x00a4
-#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_101 0x00a5
-#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_102 0x00a6
-#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0
-#define mmMP0_SMN_C2PMSG_103 0x00a7
-#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0
-#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0
-#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmMP0_SMN_IH_CREDIT 0x00c1
-#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0
-#define mmMP0_SMN_IH_SW_INT 0x00c2
-#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0
-#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3
-#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-// base address: 0x0
-#define mmMP1_SMN_ACP2MP_RESP 0x0240
-#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0
-#define mmMP1_SMN_DC2MP_RESP 0x0241
-#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0
-#define mmMP1_SMN_UVD2MP_RESP 0x0242
-#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0
-#define mmMP1_SMN_VCE2MP_RESP 0x0243
-#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0
-#define mmMP1_SMN_RLC2MP_RESP 0x0244
-#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_32 0x0260
-#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_33 0x0261
-#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_34 0x0262
-#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_35 0x0263
-#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_36 0x0264
-#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_37 0x0265
-#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_38 0x0266
-#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_39 0x0267
-#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_40 0x0268
-#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_41 0x0269
-#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_42 0x026a
-#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_43 0x026b
-#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_44 0x026c
-#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_45 0x026d
-#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_46 0x026e
-#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_47 0x026f
-#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_48 0x0270
-#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_49 0x0271
-#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_50 0x0272
-#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_51 0x0273
-#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_52 0x0274
-#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_53 0x0275
-#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_54 0x0276
-#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_55 0x0277
-#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_56 0x0278
-#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_57 0x0279
-#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_58 0x027a
-#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_59 0x027b
-#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_60 0x027c
-#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_61 0x027d
-#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_62 0x027e
-#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_63 0x027f
-#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_64 0x0280
-#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_65 0x0281
-#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_66 0x0282
-#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_67 0x0283
-#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_68 0x0284
-#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_69 0x0285
-#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_70 0x0286
-#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_71 0x0287
-#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_72 0x0288
-#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_73 0x0289
-#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_74 0x028a
-#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_75 0x028b
-#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_76 0x028c
-#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_77 0x028d
-#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_78 0x028e
-#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_79 0x028f
-#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_80 0x0290
-#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_81 0x0291
-#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_82 0x0292
-#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_83 0x0293
-#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_84 0x0294
-#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_85 0x0295
-#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_86 0x0296
-#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_87 0x0297
-#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_88 0x0298
-#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_89 0x0299
-#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_90 0x029a
-#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_91 0x029b
-#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_92 0x029c
-#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_93 0x029d
-#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_94 0x029e
-#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_95 0x029f
-#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_96 0x02a0
-#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_97 0x02a1
-#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_98 0x02a2
-#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_99 0x02a3
-#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_100 0x02a4
-#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_101 0x02a5
-#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_102 0x02a6
-#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0
-#define mmMP1_SMN_C2PMSG_103 0x02a7
-#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0
-#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0
-#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmMP1_SMN_IH_CREDIT 0x02c1
-#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0
-#define mmMP1_SMN_IH_SW_INT 0x02c2
-#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0
-#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3
-#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
-#define mmMP1_SMN_FPS_CNT 0x02c4
-#define mmMP1_SMN_FPS_CNT_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH0 0x03c0
-#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH1 0x03c1
-#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH2 0x03c2
-#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH3 0x03c3
-#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH4 0x03c4
-#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH5 0x03c5
-#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH6 0x03c6
-#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH7 0x03c7
-#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
-#define mmMP1_SMN_EXT_SCRATCH8 0x03c8
-#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
-
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-// base address: 0x0
-#define mmMP1_SMN_PUB_CTRL 0x02c5
-#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0
-
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
deleted file mode 100644
index ae7b518..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
+++ /dev/null
@@ -1,1463 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mp_9_0_SH_MASK_HEADER
-#define _mp_9_0_SH_MASK_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-//MP0_SMN_C2PMSG_32
-#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_33
-#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_34
-#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_35
-#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_36
-#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_37
-#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_38
-#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_39
-#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_40
-#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_41
-#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_42
-#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_43
-#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_44
-#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_45
-#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_46
-#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_47
-#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_48
-#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_49
-#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_50
-#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_51
-#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_52
-#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_53
-#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_54
-#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_55
-#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_56
-#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_57
-#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_58
-#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_59
-#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_60
-#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_61
-#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_62
-#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_63
-#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_64
-#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_65
-#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_66
-#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_67
-#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_68
-#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_69
-#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_70
-#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_71
-#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_72
-#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_73
-#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_74
-#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_75
-#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_76
-#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_77
-#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_78
-#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_79
-#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_80
-#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_81
-#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_82
-#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_83
-#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_84
-#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_85
-#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_86
-#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_87
-#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_88
-#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_89
-#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_90
-#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_91
-#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_92
-#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_93
-#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_94
-#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_95
-#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_96
-#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_97
-#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_98
-#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_99
-#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_100
-#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_101
-#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_102
-#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_103
-#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_ACTIVE_FCN_ID
-#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//MP0_SMN_IH_CREDIT
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-//MP0_SMN_IH_SW_INT
-#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1
-#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L
-#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL
-//MP0_SMN_IH_SW_INT_CTRL
-#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
-#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
-#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-//MP1_SMN_ACP2MP_RESP
-#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_DC2MP_RESP
-#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_UVD2MP_RESP
-#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_VCE2MP_RESP
-#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_RLC2MP_RESP
-#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_32
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_33
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_34
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_35
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_36
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_37
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_38
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_39
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_40
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_41
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_42
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_43
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_44
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_45
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_46
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_47
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_48
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_49
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_50
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_51
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_52
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_53
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_54
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_55
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_56
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_57
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_58
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_59
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_60
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_61
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_62
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_63
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_64
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_65
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_66
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_67
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_68
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_69
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_70
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_71
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_72
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_73
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_74
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_75
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_76
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_77
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_78
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_79
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_80
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_81
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_82
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_83
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_84
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_85
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_86
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_87
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_88
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_89
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_90
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_91
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_92
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_93
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_94
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_95
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_96
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_97
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_98
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_99
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_100
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_101
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_102
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_103
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_ACTIVE_FCN_ID
-#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//MP1_SMN_IH_CREDIT
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-//MP1_SMN_IH_SW_INT
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1
-#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L
-#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL
-//MP1_SMN_IH_SW_INT_CTRL
-#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
-#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
-//MP1_SMN_FPS_CNT
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH0
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH1
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH2
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH3
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH4
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH5
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH6
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH7
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH8
-#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
-
-
-
-
-// addressBlock: mp_SmuMp0Pub_CruDec
-//MP0_SOC_INFO
-#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0
-#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2
-#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L
-#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL
-//MP0_PUB_SCRATCH0
-#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0
-#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-//MP0_PUB_SCRATCH1
-#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0
-#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-//MP0_PUB_SCRATCH2
-#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0
-#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-//MP0_PUB_SCRATCH3
-#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0
-#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-//MP0_FW_INTF
-#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13
-#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L
-//MP0_C2PMSG_0
-#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_1
-#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_2
-#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_3
-#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_4
-#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_5
-#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_6
-#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_7
-#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_8
-#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_9
-#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_10
-#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_11
-#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_12
-#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_13
-#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_14
-#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_15
-#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_16
-#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_17
-#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_18
-#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_19
-#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_20
-#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_21
-#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_22
-#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_23
-#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_24
-#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_25
-#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_26
-#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_27
-#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_28
-#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_29
-#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_30
-#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_31
-#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2CMSG_0
-#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0
-#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2CMSG_1
-#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0
-#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2CMSG_2
-#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0
-#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2CMSG_3
-#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0
-#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2CMSG_INTEN
-#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0
-#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
-//MP0_P2CMSG_INTSTS
-#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
-#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
-#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
-#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
-#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
-#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
-#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
-#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
-//MP0_C2PMSG_ATTR_0
-#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_ATTR_1
-#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_ATTR_2
-#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_ATTR_3
-#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_ATTR_4
-#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_ATTR_5
-#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_ATTR_6
-#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0
-#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL
-//MP0_P2CMSG_ATTR
-#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0
-#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
-//MP0_P2SMSG_0
-#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0
-#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2SMSG_1
-#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0
-#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2SMSG_2
-#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0
-#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2SMSG_3
-#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0
-#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
-//MP0_P2SMSG_ATTR
-#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0
-#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
-//MP0_S2PMSG_ATTR
-#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0
-#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L
-//MP0_P2SMSG_INTSTS
-#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
-#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
-#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
-#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
-#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
-#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
-#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
-#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
-//MP0_S2PMSG_0
-#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0
-#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_32
-#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_33
-#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_34
-#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_35
-#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_36
-#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_37
-#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_38
-#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_39
-#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_40
-#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_41
-#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_42
-#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_43
-#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_44
-#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_45
-#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_46
-#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_47
-#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_48
-#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_49
-#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_50
-#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_51
-#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_52
-#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_53
-#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_54
-#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_55
-#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_56
-#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_57
-#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_58
-#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_59
-#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_60
-#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_61
-#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_62
-#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_63
-#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_64
-#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_65
-#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_66
-#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_67
-#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_68
-#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_69
-#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_70
-#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_71
-#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_72
-#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_73
-#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_74
-#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_75
-#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_76
-#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_77
-#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_78
-#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_79
-#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_80
-#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_81
-#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_82
-#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_83
-#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_84
-#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_85
-#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_86
-#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_87
-#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_88
-#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_89
-#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_90
-#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_91
-#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_92
-#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_93
-#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_94
-#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_95
-#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_96
-#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_97
-#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_98
-#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_99
-#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_100
-#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_101
-#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_102
-#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-//MP0_C2PMSG_103
-#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-//MP0_ACTIVE_FCN_ID
-#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//MP0_IH_CREDIT
-#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-//MP0_IH_SW_INT
-#define MP0_IH_SW_INT__ID__SHIFT 0x0
-#define MP0_IH_SW_INT__VALID__SHIFT 0x8
-#define MP0_IH_SW_INT__ID_MASK 0x000000FFL
-#define MP0_IH_SW_INT__VALID_MASK 0x00000100L
-//MP0_IH_SW_INT_CTRL
-#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
-#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
-#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
-#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
-
-
-//CGTT_DRM_CLK_CTRL0
-#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc
-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15
-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
-#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L
-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L
-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
-//DRM_LIGHT_SLEEP_CTRL
-#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0
-#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L
-
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-//MP1_SMN_PUB_CTRL
-#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0
-#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L
-//MP1_FIRMWARE_FLAGS
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
-#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
-#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
-//MP1_PUB_SCRATCH0
-#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
-#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-//MP1_PUB_SCRATCH1
-#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
-#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-//MP1_PUB_SCRATCH2
-#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
-#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-//MP1_PUB_SCRATCH3
-#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
-#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_0
-#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_1
-#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_2
-#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_3
-#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_4
-#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_5
-#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_6
-#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_7
-#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_8
-#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_9
-#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_10
-#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_11
-#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_12
-#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_13
-#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_14
-#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_15
-#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_16
-#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_17
-#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_18
-#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_19
-#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_20
-#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_21
-#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_22
-#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_23
-#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_24
-#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_25
-#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_26
-#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_27
-#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_28
-#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_29
-#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_30
-#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_31
-#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2CMSG_0
-#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
-#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2CMSG_1
-#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
-#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2CMSG_2
-#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
-#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2CMSG_3
-#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
-#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2CMSG_INTEN
-#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
-#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
-//MP1_P2CMSG_INTSTS
-#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
-#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
-#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
-#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
-#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
-#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
-#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
-#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
-//MP1_P2SMSG_0
-#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
-#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2SMSG_1
-#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
-#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2SMSG_2
-#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
-#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2SMSG_3
-#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
-#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
-//MP1_P2SMSG_INTSTS
-#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
-#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
-#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
-#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
-#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
-#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
-#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
-#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
-//MP1_S2PMSG_0
-#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
-#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
-//MP1_ACP2MP_RESP
-#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_DC2MP_RESP
-#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_UVD2MP_RESP
-#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_VCE2MP_RESP
-#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_RLC2MP_RESP
-#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
-#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_32
-#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_33
-#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_34
-#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_35
-#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_36
-#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_37
-#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_38
-#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_39
-#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_40
-#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_41
-#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_42
-#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_43
-#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_44
-#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_45
-#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_46
-#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_47
-#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_48
-#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_49
-#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_50
-#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_51
-#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_52
-#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_53
-#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_54
-#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_55
-#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_56
-#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_57
-#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_58
-#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_59
-#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_60
-#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_61
-#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_62
-#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_63
-#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_64
-#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_65
-#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_66
-#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_67
-#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_68
-#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_69
-#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_70
-#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_71
-#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_72
-#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_73
-#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_74
-#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_75
-#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_76
-#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_77
-#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_78
-#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_79
-#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_80
-#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_81
-#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_82
-#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_83
-#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_84
-#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_85
-#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_86
-#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_87
-#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_88
-#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_89
-#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_90
-#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_91
-#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_92
-#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_93
-#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_94
-#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_95
-#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_96
-#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_97
-#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_98
-#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_99
-#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_100
-#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_101
-#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_102
-#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-//MP1_C2PMSG_103
-#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-//MP1_ACTIVE_FCN_ID
-#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//MP1_IH_CREDIT
-#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-//MP1_IH_SW_INT
-#define MP1_IH_SW_INT__ID__SHIFT 0x0
-#define MP1_IH_SW_INT__VALID__SHIFT 0x8
-#define MP1_IH_SW_INT__ID_MASK 0x000000FFL
-#define MP1_IH_SW_INT__VALID_MASK 0x00000100L
-//MP1_IH_SW_INT_CTRL
-#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
-#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
-#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
-#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
-//MP1_FPS_CNT
-#define MP1_FPS_CNT__COUNT__SHIFT 0x0
-#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
-//MP1_PUB_CTRL
-#define MP1_PUB_CTRL__RESET__SHIFT 0x0
-#define MP1_PUB_CTRL__RESET_MASK 0x00000001L
-//MP1_EXT_SCRATCH0
-#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH1
-#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH2
-#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH3
-#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH4
-#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH5
-#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH6
-#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
-//MP1_EXT_SCRATCH7
-#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
-#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
deleted file mode 100644
index daa7eae..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
+++ /dev/null
@@ -1,1271 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _nbif_6_1_DEFAULT_HEADER
-#define _nbif_6_1_DEFAULT_HEADER
-
-
-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
-// base address: 0x0
-#define cfgVENDOR_ID_DEFAULT 0x00000000
-#define cfgDEVICE_ID_DEFAULT 0x00000000
-#define cfgCOMMAND_DEFAULT 0x00000000
-#define cfgSTATUS_DEFAULT 0x00000000
-#define cfgREVISION_ID_DEFAULT 0x00000000
-#define cfgPROG_INTERFACE_DEFAULT 0x00000000
-#define cfgSUB_CLASS_DEFAULT 0x00000000
-#define cfgBASE_CLASS_DEFAULT 0x00000000
-#define cfgCACHE_LINE_DEFAULT 0x00000000
-#define cfgLATENCY_DEFAULT 0x00000000
-#define cfgHEADER_DEFAULT 0x00000000
-#define cfgBIST_DEFAULT 0x00000000
-#define cfgBASE_ADDR_1_DEFAULT 0x00000000
-#define cfgBASE_ADDR_2_DEFAULT 0x00000000
-#define cfgBASE_ADDR_3_DEFAULT 0x00000000
-#define cfgBASE_ADDR_4_DEFAULT 0x00000000
-#define cfgBASE_ADDR_5_DEFAULT 0x00000000
-#define cfgBASE_ADDR_6_DEFAULT 0x00000000
-#define cfgADAPTER_ID_DEFAULT 0x00000000
-#define cfgROM_BASE_ADDR_DEFAULT 0x00000000
-#define cfgCAP_PTR_DEFAULT 0x00000000
-#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff
-#define cfgINTERRUPT_PIN_DEFAULT 0x00000000
-#define cfgMIN_GRANT_DEFAULT 0x00000000
-#define cfgMAX_LATENCY_DEFAULT 0x00000000
-#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000
-#define cfgADAPTER_ID_W_DEFAULT 0x00000000
-#define cfgPMI_CAP_LIST_DEFAULT 0x00000000
-#define cfgPMI_CAP_DEFAULT 0x00000000
-#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000
-#define cfgPCIE_CAP_DEFAULT 0x00000002
-#define cfgDEVICE_CAP_DEFAULT 0x10000000
-#define cfgDEVICE_CNTL_DEFAULT 0x00002810
-#define cfgDEVICE_STATUS_DEFAULT 0x00000000
-#define cfgLINK_CAP_DEFAULT 0x00011c03
-#define cfgLINK_CNTL_DEFAULT 0x00000000
-#define cfgLINK_STATUS_DEFAULT 0x00000001
-#define cfgDEVICE_CAP2_DEFAULT 0x00000000
-#define cfgDEVICE_CNTL2_DEFAULT 0x00000000
-#define cfgDEVICE_STATUS2_DEFAULT 0x00000000
-#define cfgLINK_CAP2_DEFAULT 0x0000000e
-#define cfgLINK_CNTL2_DEFAULT 0x00000003
-#define cfgLINK_STATUS2_DEFAULT 0x00000000
-#define cfgSLOT_CAP2_DEFAULT 0x00000000
-#define cfgSLOT_CNTL2_DEFAULT 0x00000000
-#define cfgSLOT_STATUS2_DEFAULT 0x00000000
-#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000
-#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080
-#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000
-#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000
-#define cfgMSI_MSG_DATA_DEFAULT 0x00000000
-#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000
-#define cfgMSI_MASK_DEFAULT 0x00000000
-#define cfgMSI_PENDING_DEFAULT 0x00000000
-#define cfgMSI_MASK_64_DEFAULT 0x00000000
-#define cfgMSI_PENDING_64_DEFAULT 0x00000000
-#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000
-#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000
-#define cfgMSIX_TABLE_DEFAULT 0x00000000
-#define cfgMSIX_PBA_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
-#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
-#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
-#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
-#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
-#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
-#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
-#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
-#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
-#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
-#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
-#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
-#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
-#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
-#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
-#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000
-#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000
-#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000
-#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000
-#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000
-#define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000
-#define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000
-#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
-#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
-#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
-#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
-#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
-#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000
-#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020
-#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000
-#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000
-#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000
-#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000
-#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000
-#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
-#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
-#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
-#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
-#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
-#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000
-#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
-#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100
-#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
-#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
-#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000
-#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
-#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
-#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000
-#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
-#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000
-#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
-#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
-#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
-#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
-#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000
-#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
-#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000
-#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
-#define cfgPCIE_MC_CAP_DEFAULT 0x00000000
-#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000
-#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000
-#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000
-#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000
-#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
-#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
-#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
-#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
-#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
-#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000
-#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
-#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000
-#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
-#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
-#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
-
-
-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
-// base address: 0x0
-#define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
-#define mmIO_BASE_LIMIT_DEFAULT 0x00000000
-#define mmSECONDARY_STATUS_DEFAULT 0x00000000
-#define mmMEM_BASE_LIMIT_DEFAULT 0x00000000
-#define mmPREF_BASE_LIMIT_DEFAULT 0x00000000
-#define mmPREF_BASE_UPPER_DEFAULT 0x00000000
-#define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000
-#define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000
-#define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000
-#define mmSLOT_CAP_DEFAULT 0x00000000
-#define mmSLOT_CNTL_DEFAULT 0x00000000
-#define mmSLOT_STATUS_DEFAULT 0x00000000
-#define mmSSID_CAP_LIST_DEFAULT 0x00000000
-#define mmSSID_CAP_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_shadow_reg_shadowdec
-// base address: 0x0
-#define ixSHADOW_COMMAND_DEFAULT 0x00000000
-#define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
-#define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
-#define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
-#define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
-#define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
-#define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
-#define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
-#define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
-#define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
-#define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
-#define ixSUC_INDEX_DEFAULT 0x00000000
-#define ixSUC_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: bif_bx_pf_SUMDEC
-// base address: 0x0
-#define ixSUM_INDEX_DEFAULT 0x00000000
-#define ixSUM_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: gdc_GDCDEC
-// base address: 0x1400000
-#define mmA2S_CNTL_CL0_DEFAULT 0x00280540
-#define mmA2S_CNTL_CL1_DEFAULT 0x00282540
-#define mmA2S_CNTL_CL2_DEFAULT 0x002825a0
-#define mmA2S_CNTL_CL3_DEFAULT 0x00282550
-#define mmA2S_CNTL_CL4_DEFAULT 0x00282550
-#define mmA2S_CNTL_SW0_DEFAULT 0x08080005
-#define mmA2S_CNTL_SW1_DEFAULT 0x08080205
-#define mmA2S_CNTL_SW2_DEFAULT 0x08080200
-#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080
-#define mmA2S_MISC_CNTL_DEFAULT 0x00000003
-#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f
-#define mmNGDC_RESERVED_0_DEFAULT 0x00000000
-#define mmNGDC_RESERVED_1_DEFAULT 0x00000000
-#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
-#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
-#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
-#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
-#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
-#define mmS2A_MISC_CNTL_DEFAULT 0x00000000
-#define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006
-#define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006
-#define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006
-#define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006
-#define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006
-
-
-// addressBlock: nbif_sion_SIONDEC
-// base address: 0x1400000
-#define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
-#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
-#define ixSION_CNTL_REG0_DEFAULT 0x00000000
-#define ixSION_CNTL_REG1_DEFAULT 0x00000000
-
-
-// addressBlock: syshub_mmreg_direct_syshubdirect
-// base address: 0x1400000
-#define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
-#define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
-#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
-#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
-#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
-#define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000
-#define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000
-#define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100
-#define ixSYSHUB_SCRATCH_DEFAULT 0x00000040
-#define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
-#define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
-#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
-#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
-#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
-#define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
-
-
-// addressBlock: gdc_ras_gdc_ras_regblk
-// base address: 0x1400000
-#define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000
-#define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000
-#define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000
-#define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000
-#define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000
-#define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000
-
-
-// addressBlock: gdc_rst_GDCRST_DEC
-// base address: 0x1400000
-#define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000
-#define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000
-#define ixSHUB_LINK_RESET_DEFAULT 0x00000000
-#define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000
-#define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b
-#define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009
-#define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000
-
-
-// addressBlock: bif_bx_pf_SYSDEC
-// base address: 0x0
-#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
-#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
-#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
-#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
-#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
-#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
-#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
-#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
-#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
-
-
-// addressBlock: bif_bx_pf_SYSPFVFDEC
-// base address: 0x0
-#define mmMM_INDEX_DEFAULT 0x00000000
-#define mmMM_DATA_DEFAULT 0x00000000
-#define mmMM_INDEX_HI_DEFAULT 0x00000000
-#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
-#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
-#define mmPCIE_INDEX_DEFAULT 0x00000000
-#define mmPCIE_DATA_DEFAULT 0x00000000
-#define mmPCIE_INDEX2_DEFAULT 0x00000000
-#define mmPCIE_DATA2_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_dwn_BIFDEC1
-// base address: 0x0
-#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000
-#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000
-#define mmDN_PCIE_CNTL_DEFAULT 0x00000000
-#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
-#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
-#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
-#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
-#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001
-#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000
-#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_dwnp_BIFDEC1
-// base address: 0x0
-#define mmPCIEP_RESERVED_DEFAULT 0x00000000
-#define mmPCIEP_SCRATCH_DEFAULT 0x00000000
-#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500
-#define mmPCIE_RX_CNTL_DEFAULT 0x00000000
-#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
-#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000
-#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000
-#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_ep_BIFDEC1
-// base address: 0x0
-#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000
-#define mmEP_PCIE_CNTL_DEFAULT 0x00000100
-#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000
-#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000
-#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
-#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
-#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
-#define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774
-#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468
-#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000
-#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
-#define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000
-#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
-#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
-#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
-#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
-#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000
-#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000
-#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
-#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
-#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000
-#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: bif_bx_pf_BIFDEC1
-// base address: 0x0
-#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
-#define mmBUS_CNTL_DEFAULT 0x00000000
-#define mmBIF_SCRATCH0_DEFAULT 0x00000000
-#define mmBIF_SCRATCH1_DEFAULT 0x00000000
-#define mmBX_RESET_EN_DEFAULT 0x00010003
-#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000
-#define mmBX_RESET_CNTL_DEFAULT 0x00000000
-#define mmINTERRUPT_CNTL_DEFAULT 0x00000010
-#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000
-#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
-#define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000
-#define mmBIF_CLK_CTRL_DEFAULT 0x00000000
-#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
-#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000
-#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
-#define mmBIF_SLVARB_MODE_DEFAULT 0x00000000
-#define mmBIF_FB_EN_DEFAULT 0x00000000
-#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f
-#define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
-#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
-#define mmBACO_CNTL_DEFAULT 0x00000000
-#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
-#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100
-#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
-#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400
-#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100
-#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000
-#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000
-#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc
-#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000
-#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc
-#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000
-#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc
-#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000
-#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc
-#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00
-#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc
-#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00
-#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc
-#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000
-#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000
-#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780
-#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc
-#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800
-#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c
-#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
-#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
-#define mmBIF_RB_CNTL_DEFAULT 0x00000000
-#define mmBIF_RB_BASE_DEFAULT 0x00000000
-#define mmBIF_RB_RPTR_DEFAULT 0x00000000
-#define mmBIF_RB_WPTR_DEFAULT 0x00000000
-#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmMAILBOX_INDEX_DEFAULT 0x00000000
-#define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000
-#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
-#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
-#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
-#define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020
-#define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000
-#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
-#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
-#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
-#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
-
-
-// addressBlock: rcc_pf_0_BIFDEC1
-// base address: 0x0
-#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
-#define mmRCC_RESET_EN_DEFAULT 0x00008000
-#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000
-#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
-#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
-#define mmRCC_BUS_CNTL_DEFAULT 0x00000000
-#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000
-#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
-#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
-#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
-#define mmRCC_XDMA_LO_DEFAULT 0x00000000
-#define mmRCC_XDMA_HI_DEFAULT 0x00000000
-#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
-#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
-#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000
-#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000
-#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
-#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
-#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000
-#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
-#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
-#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
-#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
-#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
-#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
-#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
-#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
-#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
-#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
-#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
-#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000
-#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
-#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
-#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_pf_0_BIFDEC2
-// base address: 0x0
-#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
-#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
-#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
-#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
-#define mmGFXMSIX_PBA_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_strap_BIFDEC1
-// base address: 0x0
-#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0
-#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e
-#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009
-#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
-#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
-#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002
-#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
-#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
-#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000
-#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001
-#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042
-#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022
-#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002
-#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000
-#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001
-#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
-#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022
-#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
-
-
-// addressBlock: bif_bx_pf_BIFPFVFDEC1
-// base address: 0x0
-#define mmBIF_BME_STATUS_DEFAULT 0x00000000
-#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
-#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
-#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
-#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000
-#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
-#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
-#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
-#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
-#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
-#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
-#define mmMAILBOX_CONTROL_DEFAULT 0x00000000
-#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000
-#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_pf_0_BIFPFVFDEC1
-// base address: 0x0
-#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000
-#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
-#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000
-#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
-
-
-// addressBlock: syshub_mmreg_ind_syshubdec
-// base address: 0x0
-#define mmSYSHUB_INDEX_DEFAULT 0x00000000
-#define mmSYSHUB_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_strap_rcc_strap_internal
-// base address: 0x10100000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000
-#define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000
-
-
-// addressBlock: bif_rst_bif_rst_regblk
-// base address: 0x10100000
-#define ixHARD_RST_CTRL_DEFAULT 0xb0000055
-#define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000
-#define ixSELF_SOFT_RST_DEFAULT 0x00000000
-#define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9
-#define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644
-#define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000
-#define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900
-#define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000
-#define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9
-#define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009
-#define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000
-#define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000
-#define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000
-#define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000
-#define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000
-#define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000
-#define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000
-#define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000
-#define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff
-#define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000
-#define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000
-#define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000
-#define ixBIF_PF_FLR_RST_DEFAULT 0x00000000
-#define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000
-#define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
-#define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000
-
-
-// addressBlock: bif_misc_bif_misc_regblk
-// base address: 0x10100000
-#define ixMISC_SCRATCH_DEFAULT 0x00000000
-#define ixINTR_LINE_POLARITY_DEFAULT 0x00000000
-#define ixINTR_LINE_ENABLE_DEFAULT 0x00000000
-#define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf
-#define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004
-#define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004
-#define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000
-#define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000
-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000
-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000
-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000
-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000
-#define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000
-#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
-#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
-#define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000
-#define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000
-#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000
-#define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080
-#define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000
-#define ixSMN_MST_CNTL0_DEFAULT 0x00000001
-#define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000
-#define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000
-#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
-#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
-#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000
-#define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000
-#define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa
-#define ixBIFC_THT_CNTL_DEFAULT 0x00000222
-#define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000
-#define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0
-#define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000
-#define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf
-#define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000
-#define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000
-#define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000
-#define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000
-#define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000
-#define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000
-#define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000
-#define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000
-#define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000
-#define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f
-#define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: bif_ras_bif_ras_regblk
-// base address: 0x10100000
-#define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000
-#define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000
-#define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000
-#define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000
-#define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000
-#define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
-// base address: 0x10134000
-#define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000
-#define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000
-#define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
-#define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
-#define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
-#define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
-#define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
-#define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
-#define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
-// base address: 0x10134200
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
-#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: pciemsix_amdgfx_MSIXTDEC
-// base address: 0x10170000
-#define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000
-#define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000
-
-
-// addressBlock: pciemsix_amdgfx_MSIXPDEC
-// base address: 0x10171000
-#define ixPCIEMSIX_PBA_DEFAULT 0x00000000
-
-
-// addressBlock: syshub_mmreg_ind_syshubind
-// base address: 0x0
-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000
-#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100
-#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040
-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
deleted file mode 100644
index 1fddd0f..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _osssys_4_0_DEFAULT_HEADER
-#define _osssys_4_0_DEFAULT_HEADER
-
-
-// addressBlock: osssys_osssysdec
-#define mmIH_VMID_0_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_1_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_2_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_3_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_4_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_5_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_6_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_7_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_8_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_9_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_10_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_11_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_12_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_13_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_14_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_15_LUT_DEFAULT 0x00000000
-#define mmIH_VMID_0_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_1_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_2_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_3_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_4_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_5_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_6_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_7_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_8_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_9_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_10_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_11_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_12_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_13_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_14_LUT_MM_DEFAULT 0x00000000
-#define mmIH_VMID_15_LUT_MM_DEFAULT 0x00000000
-#define mmIH_COOKIE_0_DEFAULT 0x00000000
-#define mmIH_COOKIE_1_DEFAULT 0x00000000
-#define mmIH_COOKIE_2_DEFAULT 0x00000000
-#define mmIH_COOKIE_3_DEFAULT 0x00000000
-#define mmIH_COOKIE_4_DEFAULT 0x00000000
-#define mmIH_COOKIE_5_DEFAULT 0x00000000
-#define mmIH_COOKIE_6_DEFAULT 0x00000000
-#define mmIH_COOKIE_7_DEFAULT 0x00000000
-#define mmIH_REGISTER_LAST_PART0_DEFAULT 0x00000000
-#define mmSEM_REQ_INPUT_0_DEFAULT 0x00000000
-#define mmSEM_REQ_INPUT_1_DEFAULT 0x00000000
-#define mmSEM_REQ_INPUT_2_DEFAULT 0x00000000
-#define mmSEM_REQ_INPUT_3_DEFAULT 0x00000000
-#define mmSEM_REGISTER_LAST_PART0_DEFAULT 0x00000000
-#define mmIH_RB_CNTL_DEFAULT 0x10610000
-#define mmIH_RB_BASE_DEFAULT 0x00000000
-#define mmIH_RB_BASE_HI_DEFAULT 0x00000000
-#define mmIH_RB_RPTR_DEFAULT 0x00000000
-#define mmIH_RB_WPTR_DEFAULT 0x00000000
-#define mmIH_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmIH_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmIH_DOORBELL_RPTR_DEFAULT 0x00000000
-#define mmIH_RB_CNTL_RING1_DEFAULT 0x10410000
-#define mmIH_RB_BASE_RING1_DEFAULT 0x00000000
-#define mmIH_RB_BASE_HI_RING1_DEFAULT 0x00000000
-#define mmIH_RB_RPTR_RING1_DEFAULT 0x00000000
-#define mmIH_RB_WPTR_RING1_DEFAULT 0x00000000
-#define mmIH_DOORBELL_RPTR_RING1_DEFAULT 0x00000000
-#define mmIH_RB_CNTL_RING2_DEFAULT 0x10410000
-#define mmIH_RB_BASE_RING2_DEFAULT 0x00000000
-#define mmIH_RB_BASE_HI_RING2_DEFAULT 0x00000000
-#define mmIH_RB_RPTR_RING2_DEFAULT 0x00000000
-#define mmIH_RB_WPTR_RING2_DEFAULT 0x00000000
-#define mmIH_DOORBELL_RPTR_RING2_DEFAULT 0x00000000
-#define mmIH_VERSION_DEFAULT 0x00000400
-#define mmIH_CNTL_DEFAULT 0x01000000
-#define mmIH_CNTL2_DEFAULT 0x000000ff
-#define mmIH_STATUS_DEFAULT 0x00040847
-#define mmIH_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmIH_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmIH_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmIH_DSM_MATCH_VALUE_BIT_31_0_DEFAULT 0x00000000
-#define mmIH_DSM_MATCH_VALUE_BIT_63_32_DEFAULT 0x00000000
-#define mmIH_DSM_MATCH_VALUE_BIT_95_64_DEFAULT 0x00000000
-#define mmIH_DSM_MATCH_FIELD_CONTROL_DEFAULT 0x0000007f
-#define mmIH_DSM_MATCH_DATA_CONTROL_DEFAULT 0x0fffffff
-#define mmIH_DSM_MATCH_FCN_ID_DEFAULT 0x00000000
-#define mmIH_LIMIT_INT_RATE_CNTL_DEFAULT 0x00000000
-#define mmIH_VF_RB_STATUS_DEFAULT 0x00000000
-#define mmIH_VF_RB_STATUS2_DEFAULT 0x00000000
-#define mmIH_VF_RB1_STATUS_DEFAULT 0x00000000
-#define mmIH_VF_RB1_STATUS2_DEFAULT 0x00000000
-#define mmIH_VF_RB2_STATUS_DEFAULT 0x00000000
-#define mmIH_VF_RB2_STATUS2_DEFAULT 0x00000000
-#define mmIH_INT_FLOOD_CNTL_DEFAULT 0x00000000
-#define mmIH_RB0_INT_FLOOD_STATUS_DEFAULT 0x00000000
-#define mmIH_RB1_INT_FLOOD_STATUS_DEFAULT 0x00000000
-#define mmIH_RB2_INT_FLOOD_STATUS_DEFAULT 0x00000000
-#define mmIH_INT_FLOOD_STATUS_DEFAULT 0x00000000
-#define mmIH_STORM_CLIENT_LIST_CNTL_DEFAULT 0x00000000
-#define mmIH_CLK_CTRL_DEFAULT 0x00000000
-#define mmIH_INT_FLAGS_DEFAULT 0x00000000
-#define mmIH_LAST_INT_INFO0_DEFAULT 0x00000000
-#define mmIH_LAST_INT_INFO1_DEFAULT 0x00000000
-#define mmIH_LAST_INT_INFO2_DEFAULT 0x00000000
-#define mmIH_SCRATCH_DEFAULT 0x00000000
-#define mmIH_CLIENT_CREDIT_ERROR_DEFAULT 0x00000000
-#define mmIH_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmIH_COOKIE_REC_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmIH_CREDIT_STATUS_DEFAULT 0xfffffffe
-#define mmIH_MMHUB_ERROR_DEFAULT 0x00000000
-#define mmIH_REGISTER_LAST_PART2_DEFAULT 0x00000000
-#define mmSEM_CLK_CTRL_DEFAULT 0x00000100
-#define mmSEM_UTC_CREDIT_DEFAULT 0x00000510
-#define mmSEM_UTC_CONFIG_DEFAULT 0x00000020
-#define mmSEM_UTCL2_TRAN_EN_LUT_DEFAULT 0x800000ff
-#define mmSEM_MCIF_CONFIG_DEFAULT 0x00001040
-#define mmSEM_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmSEM_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmSEM_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmSEM_STATUS_DEFAULT 0x80f90003
-#define mmSEM_MAILBOX_CLIENTCONFIG_DEFAULT 0x00fac688
-#define mmSEM_MAILBOX_DEFAULT 0x00000000
-#define mmSEM_MAILBOX_CONTROL_DEFAULT 0x00000000
-#define mmSEM_CHICKEN_BITS_DEFAULT 0x00084ad6
-#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_DEFAULT 0x00000008
-#define mmSEM_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmSEM_OUTSTANDING_THRESHOLD_DEFAULT 0x00000010
-#define mmSEM_REGISTER_LAST_PART2_DEFAULT 0x00000000
-#define mmIH_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmIH_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmIH_CLIENT_CFG_DEFAULT 0x0000001f
-#define mmIH_CLIENT_CFG_INDEX_DEFAULT 0x00000000
-#define mmIH_CLIENT_CFG_DATA_DEFAULT 0x00000000
-#define mmIH_CID_REMAP_INDEX_DEFAULT 0x00000000
-#define mmIH_CID_REMAP_DATA_DEFAULT 0x00000000
-#define mmIH_CHICKEN_DEFAULT 0x00000000
-#define mmIH_MMHUB_CNTL_DEFAULT 0x00000001
-#define mmIH_REGISTER_LAST_PART1_DEFAULT 0x00000000
-#define mmSEM_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmSEM_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmSEM_RESP_SDMA0_DEFAULT 0x0004950c
-#define mmSEM_RESP_SDMA1_DEFAULT 0x0004958c
-#define mmSEM_RESP_UVD_DEFAULT 0x0004860c
-#define mmSEM_RESP_VCE_0_DEFAULT 0x0004900c
-#define mmSEM_RESP_ACP_DEFAULT 0x0004870c
-#define mmSEM_RESP_ISP_DEFAULT 0x00000000
-#define mmSEM_RESP_VCE_1_DEFAULT 0x0004908c
-#define mmSEM_RESP_VP8_DEFAULT 0x00000000
-#define mmSEM_RESP_GC_DEFAULT 0x0004858c
-#define mmSEM_CID_REMAP_INDEX_DEFAULT 0x00000000
-#define mmSEM_CID_REMAP_DATA_DEFAULT 0x00000000
-#define mmSEM_ATOMIC_OP_LUT_DEFAULT 0x040a102f
-#define mmSEM_EDC_CONFIG_DEFAULT 0x00000002
-#define mmSEM_CHICKEN_BITS2_DEFAULT 0x00000000
-#define mmSEM_MMHUB_CNTL_DEFAULT 0x00000000
-#define mmSEM_REGISTER_LAST_PART1_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
deleted file mode 100644
index afd15bd..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma0_4_0_DEFAULT_HEADER
-#define _sdma0_4_0_DEFAULT_HEADER
-
-
-// addressBlock: sdma0_sdma0dec
-#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
-#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
-#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
-#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
-#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
-#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
-#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
-#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
-#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000
-#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882
-#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
-#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
-#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000
-#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100
-#define mmSDMA0_CNTL_DEFAULT 0x00000002
-#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07
-#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012
-#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
-#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
-#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
-#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
-#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
-#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
-#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
-#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003
-#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
-#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
-#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
-#define mmSDMA0_FREEZE_DEFAULT 0x00000000
-#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA_POWER_GATING_DEFAULT 0x00000000
-#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000
-#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000
-#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000
-#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
-#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
-#define mmSDMA0_ID_DEFAULT 0x00000001
-#define mmSDMA0_VERSION_DEFAULT 0x00000400
-#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
-#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
-#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
-#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
-#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019
-#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
-#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff
-#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff
-#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600
-#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001
-#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0
-#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200
-#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
-#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005
-#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000
-#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f
-#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
-#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
-#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
-#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
-#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
-#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000
-#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd
-#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
-#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0
-#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000
-#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
-#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
-#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
deleted file mode 100644
index b100c4e..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma0_4_0_OFFSET_HEADER
-#define _sdma0_4_0_OFFSET_HEADER
-
-
-
-// addressBlock: sdma0_sdma0dec
-// base address: 0x4980
-#define mmSDMA0_UCODE_ADDR 0x0000
-#define mmSDMA0_UCODE_ADDR_BASE_IDX 0
-#define mmSDMA0_UCODE_DATA 0x0001
-#define mmSDMA0_UCODE_DATA_BASE_IDX 0
-#define mmSDMA0_VM_CNTL 0x0004
-#define mmSDMA0_VM_CNTL_BASE_IDX 0
-#define mmSDMA0_VM_CTX_LO 0x0005
-#define mmSDMA0_VM_CTX_LO_BASE_IDX 0
-#define mmSDMA0_VM_CTX_HI 0x0006
-#define mmSDMA0_VM_CTX_HI_BASE_IDX 0
-#define mmSDMA0_ACTIVE_FCN_ID 0x0007
-#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmSDMA0_VM_CTX_CNTL 0x0008
-#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0
-#define mmSDMA0_VIRT_RESET_REQ 0x0009
-#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0
-#define mmSDMA0_VF_ENABLE 0x000a
-#define mmSDMA0_VF_ENABLE_BASE_IDX 0
-#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b
-#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0
-#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c
-#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0
-#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d
-#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0
-#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e
-#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0
-#define mmSDMA0_PUB_REG_TYPE0 0x000f
-#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0
-#define mmSDMA0_PUB_REG_TYPE1 0x0010
-#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0
-#define mmSDMA0_PUB_REG_TYPE2 0x0011
-#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0
-#define mmSDMA0_PUB_REG_TYPE3 0x0012
-#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0
-#define mmSDMA0_MMHUB_CNTL 0x0013
-#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0
-#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019
-#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
-#define mmSDMA0_POWER_CNTL 0x001a
-#define mmSDMA0_POWER_CNTL_BASE_IDX 0
-#define mmSDMA0_CLK_CTRL 0x001b
-#define mmSDMA0_CLK_CTRL_BASE_IDX 0
-#define mmSDMA0_CNTL 0x001c
-#define mmSDMA0_CNTL_BASE_IDX 0
-#define mmSDMA0_CHICKEN_BITS 0x001d
-#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0
-#define mmSDMA0_GB_ADDR_CONFIG 0x001e
-#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
-#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f
-#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0
-#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020
-#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0
-#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
-#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
-#define mmSDMA0_RB_RPTR_FETCH 0x0022
-#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0
-#define mmSDMA0_IB_OFFSET_FETCH 0x0023
-#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0
-#define mmSDMA0_PROGRAM 0x0024
-#define mmSDMA0_PROGRAM_BASE_IDX 0
-#define mmSDMA0_STATUS_REG 0x0025
-#define mmSDMA0_STATUS_REG_BASE_IDX 0
-#define mmSDMA0_STATUS1_REG 0x0026
-#define mmSDMA0_STATUS1_REG_BASE_IDX 0
-#define mmSDMA0_RD_BURST_CNTL 0x0027
-#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0
-#define mmSDMA0_HBM_PAGE_CONFIG 0x0028
-#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0
-#define mmSDMA0_UCODE_CHECKSUM 0x0029
-#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0
-#define mmSDMA0_F32_CNTL 0x002a
-#define mmSDMA0_F32_CNTL_BASE_IDX 0
-#define mmSDMA0_FREEZE 0x002b
-#define mmSDMA0_FREEZE_BASE_IDX 0
-#define mmSDMA0_PHASE0_QUANTUM 0x002c
-#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0
-#define mmSDMA0_PHASE1_QUANTUM 0x002d
-#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0
-#define mmSDMA_POWER_GATING 0x002e
-#define mmSDMA_POWER_GATING_BASE_IDX 0
-#define mmSDMA_PGFSM_CONFIG 0x002f
-#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0
-#define mmSDMA_PGFSM_WRITE 0x0030
-#define mmSDMA_PGFSM_WRITE_BASE_IDX 0
-#define mmSDMA_PGFSM_READ 0x0031
-#define mmSDMA_PGFSM_READ_BASE_IDX 0
-#define mmSDMA0_EDC_CONFIG 0x0032
-#define mmSDMA0_EDC_CONFIG_BASE_IDX 0
-#define mmSDMA0_BA_THRESHOLD 0x0033
-#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0
-#define mmSDMA0_ID 0x0034
-#define mmSDMA0_ID_BASE_IDX 0
-#define mmSDMA0_VERSION 0x0035
-#define mmSDMA0_VERSION_BASE_IDX 0
-#define mmSDMA0_EDC_COUNTER 0x0036
-#define mmSDMA0_EDC_COUNTER_BASE_IDX 0
-#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037
-#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0
-#define mmSDMA0_STATUS2_REG 0x0038
-#define mmSDMA0_STATUS2_REG_BASE_IDX 0
-#define mmSDMA0_ATOMIC_CNTL 0x0039
-#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0
-#define mmSDMA0_ATOMIC_PREOP_LO 0x003a
-#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0
-#define mmSDMA0_ATOMIC_PREOP_HI 0x003b
-#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0
-#define mmSDMA0_UTCL1_CNTL 0x003c
-#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0
-#define mmSDMA0_UTCL1_WATERMK 0x003d
-#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0
-#define mmSDMA0_UTCL1_RD_STATUS 0x003e
-#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0
-#define mmSDMA0_UTCL1_WR_STATUS 0x003f
-#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0
-#define mmSDMA0_UTCL1_INV0 0x0040
-#define mmSDMA0_UTCL1_INV0_BASE_IDX 0
-#define mmSDMA0_UTCL1_INV1 0x0041
-#define mmSDMA0_UTCL1_INV1_BASE_IDX 0
-#define mmSDMA0_UTCL1_INV2 0x0042
-#define mmSDMA0_UTCL1_INV2_BASE_IDX 0
-#define mmSDMA0_UTCL1_RD_XNACK0 0x0043
-#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0
-#define mmSDMA0_UTCL1_RD_XNACK1 0x0044
-#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0
-#define mmSDMA0_UTCL1_WR_XNACK0 0x0045
-#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0
-#define mmSDMA0_UTCL1_WR_XNACK1 0x0046
-#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0
-#define mmSDMA0_UTCL1_TIMEOUT 0x0047
-#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0
-#define mmSDMA0_UTCL1_PAGE 0x0048
-#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0
-#define mmSDMA0_POWER_CNTL_IDLE 0x0049
-#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0
-#define mmSDMA0_RELAX_ORDERING_LUT 0x004a
-#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0
-#define mmSDMA0_CHICKEN_BITS_2 0x004b
-#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0
-#define mmSDMA0_STATUS3_REG 0x004c
-#define mmSDMA0_STATUS3_REG_BASE_IDX 0
-#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d
-#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e
-#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_PHASE2_QUANTUM 0x004f
-#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0
-#define mmSDMA0_ERROR_LOG 0x0050
-#define mmSDMA0_ERROR_LOG_BASE_IDX 0
-#define mmSDMA0_PUB_DUMMY_REG0 0x0051
-#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0
-#define mmSDMA0_PUB_DUMMY_REG1 0x0052
-#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0
-#define mmSDMA0_PUB_DUMMY_REG2 0x0053
-#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0
-#define mmSDMA0_PUB_DUMMY_REG3 0x0054
-#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0
-#define mmSDMA0_F32_COUNTER 0x0055
-#define mmSDMA0_F32_COUNTER_BASE_IDX 0
-#define mmSDMA0_UNBREAKABLE 0x0056
-#define mmSDMA0_UNBREAKABLE_BASE_IDX 0
-#define mmSDMA0_PERFMON_CNTL 0x0057
-#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0
-#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058
-#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0
-#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059
-#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0
-#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
-#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
-#define mmSDMA0_CRD_CNTL 0x005b
-#define mmSDMA0_CRD_CNTL_BASE_IDX 0
-#define mmSDMA0_MMHUB_TRUSTLVL 0x005c
-#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0
-#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d
-#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
-#define mmSDMA0_ULV_CNTL 0x005e
-#define mmSDMA0_ULV_CNTL_BASE_IDX 0
-#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060
-#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0
-#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061
-#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0
-#define mmSDMA0_GFX_RB_CNTL 0x0080
-#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0
-#define mmSDMA0_GFX_RB_BASE 0x0081
-#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0
-#define mmSDMA0_GFX_RB_BASE_HI 0x0082
-#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_GFX_RB_RPTR 0x0083
-#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0
-#define mmSDMA0_GFX_RB_RPTR_HI 0x0084
-#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA0_GFX_RB_WPTR 0x0085
-#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0
-#define mmSDMA0_GFX_RB_WPTR_HI 0x0086
-#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
-#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088
-#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
-#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_GFX_IB_CNTL 0x008a
-#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0
-#define mmSDMA0_GFX_IB_RPTR 0x008b
-#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0
-#define mmSDMA0_GFX_IB_OFFSET 0x008c
-#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0
-#define mmSDMA0_GFX_IB_BASE_LO 0x008d
-#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA0_GFX_IB_BASE_HI 0x008e
-#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_GFX_IB_SIZE 0x008f
-#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0
-#define mmSDMA0_GFX_SKIP_CNTL 0x0090
-#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091
-#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA0_GFX_DOORBELL 0x0092
-#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0
-#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093
-#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0
-#define mmSDMA0_GFX_STATUS 0x00a8
-#define mmSDMA0_GFX_STATUS_BASE_IDX 0
-#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9
-#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA0_GFX_WATERMARK 0x00aa
-#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0
-#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab
-#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac
-#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad
-#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af
-#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA0_GFX_PREEMPT 0x00b0
-#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0
-#define mmSDMA0_GFX_DUMMY_REG 0x00b1
-#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4
-#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5
-#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0
-#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1
-#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2
-#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3
-#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4
-#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5
-#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6
-#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7
-#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8
-#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9
-#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_CNTL 0x00e0
-#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_BASE 0x00e1
-#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2
-#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_RPTR 0x00e3
-#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4
-#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_WPTR 0x00e5
-#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6
-#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
-#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_CNTL 0x00ea
-#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_RPTR 0x00eb
-#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_OFFSET 0x00ec
-#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed
-#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee
-#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_SIZE 0x00ef
-#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0
-#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0
-#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1
-#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA0_PAGE_DOORBELL 0x00f2
-#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0
-#define mmSDMA0_PAGE_STATUS 0x0108
-#define mmSDMA0_PAGE_STATUS_BASE_IDX 0
-#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109
-#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA0_PAGE_WATERMARK 0x010a
-#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0
-#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b
-#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c
-#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d
-#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f
-#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA0_PAGE_PREEMPT 0x0110
-#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0
-#define mmSDMA0_PAGE_DUMMY_REG 0x0111
-#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114
-#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115
-#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120
-#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121
-#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122
-#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123
-#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124
-#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125
-#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126
-#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127
-#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128
-#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129
-#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_CNTL 0x0140
-#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_BASE 0x0141
-#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_BASE_HI 0x0142
-#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_RPTR 0x0143
-#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144
-#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_WPTR 0x0145
-#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146
-#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
-#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_CNTL 0x014a
-#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_RPTR 0x014b
-#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_OFFSET 0x014c
-#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_BASE_LO 0x014d
-#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_BASE_HI 0x014e
-#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_SIZE 0x014f
-#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0
-#define mmSDMA0_RLC0_SKIP_CNTL 0x0150
-#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151
-#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA0_RLC0_DOORBELL 0x0152
-#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0
-#define mmSDMA0_RLC0_STATUS 0x0168
-#define mmSDMA0_RLC0_STATUS_BASE_IDX 0
-#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169
-#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA0_RLC0_WATERMARK 0x016a
-#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0
-#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b
-#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c
-#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d
-#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f
-#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA0_RLC0_PREEMPT 0x0170
-#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0
-#define mmSDMA0_RLC0_DUMMY_REG 0x0171
-#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174
-#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175
-#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180
-#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181
-#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182
-#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183
-#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184
-#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185
-#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186
-#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187
-#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188
-#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189
-#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_CNTL 0x01a0
-#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_BASE 0x01a1
-#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2
-#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_RPTR 0x01a3
-#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4
-#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_WPTR 0x01a5
-#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6
-#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7
-#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_CNTL 0x01aa
-#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_RPTR 0x01ab
-#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_OFFSET 0x01ac
-#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad
-#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae
-#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_SIZE 0x01af
-#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0
-#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0
-#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1
-#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA0_RLC1_DOORBELL 0x01b2
-#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0
-#define mmSDMA0_RLC1_STATUS 0x01c8
-#define mmSDMA0_RLC1_STATUS_BASE_IDX 0
-#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9
-#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA0_RLC1_WATERMARK 0x01ca
-#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0
-#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb
-#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc
-#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd
-#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf
-#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA0_RLC1_PREEMPT 0x01d0
-#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0
-#define mmSDMA0_RLC1_DUMMY_REG 0x01d1
-#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4
-#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5
-#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0
-#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1
-#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2
-#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3
-#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4
-#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5
-#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6
-#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7
-#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8
-#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9
-#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
deleted file mode 100644
index 412ae45..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
+++ /dev/null
@@ -1,1852 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma0_4_0_SH_MASK_HEADER
-#define _sdma0_4_0_SH_MASK_HEADER
-
-
-// addressBlock: sdma0_sdma0dec
-//SDMA0_UCODE_ADDR
-#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
-#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
-//SDMA0_UCODE_DATA
-#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
-#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_VM_CNTL
-#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
-#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
-//SDMA0_VM_CTX_LO
-#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
-#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_VM_CTX_HI
-#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
-#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_ACTIVE_FCN_ID
-#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//SDMA0_VM_CTX_CNTL
-#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
-#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
-#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L
-#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L
-//SDMA0_VIRT_RESET_REQ
-#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//SDMA0_VF_ENABLE
-#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
-#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
-//SDMA0_CONTEXT_REG_TYPE0
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L
-//SDMA0_CONTEXT_REG_TYPE1
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
-#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
-#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L
-#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
-#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
-//SDMA0_CONTEXT_REG_TYPE2
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
-//SDMA0_CONTEXT_REG_TYPE3
-#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
-//SDMA0_PUB_REG_TYPE0
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE1
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE2
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE3
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
-//SDMA0_MMHUB_CNTL
-#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
-#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
-//SDMA0_CONTEXT_GROUP_BOUNDARY
-#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
-#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
-//SDMA0_POWER_CNTL
-#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
-#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
-#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
-#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
-#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
-#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
-#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
-#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
-#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
-#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
-#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
-#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
-//SDMA0_CLK_CTRL
-#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//SDMA0_CNTL
-#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
-#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
-#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
-#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
-#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
-#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
-#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
-#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
-#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
-#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
-#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
-#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
-#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
-#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
-#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
-#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
-#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
-#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
-#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
-#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
-//SDMA0_CHICKEN_BITS
-#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
-#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
-#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
-#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
-#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
-#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
-#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
-#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
-#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
-#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
-#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
-#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
-#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
-#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
-#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
-#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
-#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
-#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
-#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
-#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
-#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
-#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
-//SDMA0_GB_ADDR_CONFIG
-#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA0_GB_ADDR_CONFIG_READ
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
-#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
-#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA0_RB_RPTR_FETCH_HI
-#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
-//SDMA0_RB_RPTR_FETCH
-#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
-#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
-//SDMA0_IB_OFFSET_FETCH
-#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
-#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
-//SDMA0_PROGRAM
-#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
-#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
-//SDMA0_STATUS_REG
-#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
-#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
-#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
-#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
-#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
-#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
-#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
-#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
-#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
-#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
-#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
-#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
-#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
-#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
-#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
-#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
-#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
-#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
-#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
-#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
-#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
-#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
-#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
-#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
-#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
-#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
-#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
-#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
-#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
-#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
-#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
-#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
-#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
-#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
-#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
-#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
-#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
-#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
-#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
-#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
-#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
-#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
-#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
-#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
-#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
-#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
-#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
-#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
-#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
-#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
-#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
-#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
-#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
-#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
-#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
-#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
-#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
-#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
-//SDMA0_STATUS1_REG
-#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
-#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
-#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
-#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
-#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
-#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
-#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
-#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
-#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
-#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
-#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
-#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
-#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
-#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
-#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
-#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
-#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
-#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
-#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
-#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
-#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
-#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
-#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
-#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
-#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
-#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
-#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
-#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
-//SDMA0_RD_BURST_CNTL
-#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
-#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
-//SDMA0_HBM_PAGE_CONFIG
-#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
-#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
-//SDMA0_UCODE_CHECKSUM
-#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
-#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
-//SDMA0_F32_CNTL
-#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
-#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
-#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
-#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
-//SDMA0_FREEZE
-#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
-#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
-#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
-#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
-#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
-#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
-#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
-#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
-//SDMA0_PHASE0_QUANTUM
-#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA0_PHASE1_QUANTUM
-#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA_POWER_GATING
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
-#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
-#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
-//SDMA_PGFSM_CONFIG
-#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
-#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
-#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
-#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
-#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
-#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
-#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
-#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
-#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
-#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
-#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
-#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
-#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
-#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
-#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
-#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
-#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
-#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
-//SDMA_PGFSM_WRITE
-#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
-#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
-//SDMA_PGFSM_READ
-#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
-#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
-//SDMA0_EDC_CONFIG
-#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
-#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
-//SDMA0_BA_THRESHOLD
-#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
-#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
-#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
-#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
-//SDMA0_ID
-#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
-#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
-//SDMA0_VERSION
-#define SDMA0_VERSION__MINVER__SHIFT 0x0
-#define SDMA0_VERSION__MAJVER__SHIFT 0x8
-#define SDMA0_VERSION__REV__SHIFT 0x10
-#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
-#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
-#define SDMA0_VERSION__REV_MASK 0x003F0000L
-//SDMA0_EDC_COUNTER
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
-#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
-#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
-#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
-#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
-#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
-#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
-#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
-#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
-#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
-#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
-//SDMA0_EDC_COUNTER_CLEAR
-#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
-#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
-//SDMA0_STATUS2_REG
-#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
-#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
-#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
-#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
-#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
-#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
-//SDMA0_ATOMIC_CNTL
-#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
-#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
-#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
-#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
-//SDMA0_ATOMIC_PREOP_LO
-#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
-#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
-//SDMA0_ATOMIC_PREOP_HI
-#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
-#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_CNTL
-#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
-#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
-#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
-#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
-#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
-#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
-#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
-#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
-#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
-#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
-#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
-#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
-//SDMA0_UTCL1_WATERMK
-#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
-#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
-#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
-#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
-#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
-#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
-#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
-#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
-//SDMA0_UTCL1_RD_STATUS
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
-#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
-#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
-#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
-#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
-#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
-#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
-#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
-#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
-#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
-#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
-//SDMA0_UTCL1_WR_STATUS
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
-#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
-#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
-#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
-#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
-//SDMA0_UTCL1_INV0
-#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
-#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
-#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
-#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
-#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
-#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
-#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
-#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
-#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
-#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
-#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
-#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
-#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
-#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
-#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
-#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
-#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
-#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
-#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
-#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
-#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
-#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
-#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
-#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
-#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
-#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
-#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
-#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
-//SDMA0_UTCL1_INV1
-#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_INV2
-#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
-#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_RD_XNACK0
-#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_RD_XNACK1
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA0_UTCL1_WR_XNACK0
-#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_WR_XNACK1
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA0_UTCL1_TIMEOUT
-#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
-#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
-#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
-#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
-//SDMA0_UTCL1_PAGE
-#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
-#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
-#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
-#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
-#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
-#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
-#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
-#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
-//SDMA0_POWER_CNTL_IDLE
-#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
-#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
-#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
-#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
-#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
-#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
-//SDMA0_RELAX_ORDERING_LUT
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
-#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
-#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
-#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
-#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
-#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
-#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
-#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
-#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
-#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
-#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
-#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
-#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
-#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
-#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
-#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
-#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
-#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
-#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
-#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
-#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
-#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
-#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
-#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
-#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
-#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
-#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
-#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
-#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
-//SDMA0_CHICKEN_BITS_2
-#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
-#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
-//SDMA0_STATUS3_REG
-#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
-#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
-#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
-#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
-#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
-#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
-//SDMA0_PHYSICAL_ADDR_LO
-#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
-#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
-#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
-#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
-#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
-#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
-#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
-#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
-//SDMA0_PHYSICAL_ADDR_HI
-#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
-//SDMA0_PHASE2_QUANTUM
-#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA0_ERROR_LOG
-#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0
-#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10
-#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
-#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L
-//SDMA0_PUB_DUMMY_REG0
-#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG1
-#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG2
-#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG3
-#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_F32_COUNTER
-#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
-#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_UNBREAKABLE
-#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0
-#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L
-//SDMA0_PERFMON_CNTL
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
-#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
-#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
-#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
-#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
-//SDMA0_PERFCOUNTER0_RESULT
-#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA0_PERFCOUNTER1_RESULT
-#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
-//SDMA0_CRD_CNTL
-#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
-#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
-#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
-#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
-//SDMA0_MMHUB_TRUSTLVL
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
-//SDMA0_GPU_IOV_VIOLATION_LOG
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
-#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//SDMA0_ULV_CNTL
-#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0
-#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
-#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
-#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
-#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
-#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
-#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
-#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
-//SDMA0_EA_DBIT_ADDR_DATA
-#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
-#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_EA_DBIT_ADDR_INDEX
-#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
-#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
-//SDMA0_GFX_RB_CNTL
-#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_GFX_RB_BASE
-#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_BASE_HI
-#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_GFX_RB_RPTR
-#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_RPTR_HI
-#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR
-#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_HI
-#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_CNTL
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_GFX_RB_RPTR_ADDR_HI
-#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_RPTR_ADDR_LO
-#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_IB_CNTL
-#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_GFX_IB_RPTR
-#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_GFX_IB_OFFSET
-#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_GFX_IB_BASE_LO
-#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_GFX_IB_BASE_HI
-#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_IB_SIZE
-#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_GFX_SKIP_CNTL
-#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_GFX_CONTEXT_STATUS
-#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_GFX_DOORBELL
-#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_GFX_CONTEXT_CNTL
-#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
-#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
-//SDMA0_GFX_STATUS
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_GFX_DOORBELL_LOG
-#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_GFX_WATERMARK
-#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_GFX_DOORBELL_OFFSET
-#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_GFX_CSA_ADDR_LO
-#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_CSA_ADDR_HI
-#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_IB_SUB_REMAIN
-#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_GFX_PREEMPT
-#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_GFX_DUMMY_REG
-#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_RB_AQL_CNTL
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_GFX_MINOR_PTR_UPDATE
-#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_GFX_MIDCMD_DATA0
-#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA1
-#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA2
-#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA3
-#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA4
-#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA5
-#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA6
-#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA7
-#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA8
-#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_CNTL
-#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_PAGE_RB_CNTL
-#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_PAGE_RB_BASE
-#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_BASE_HI
-#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_PAGE_RB_RPTR
-#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_RPTR_HI
-#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_WPTR
-#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_WPTR_HI
-#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_WPTR_POLL_CNTL
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_PAGE_RB_RPTR_ADDR_HI
-#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_RPTR_ADDR_LO
-#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_PAGE_IB_CNTL
-#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_PAGE_IB_RPTR
-#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_PAGE_IB_OFFSET
-#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_PAGE_IB_BASE_LO
-#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_PAGE_IB_BASE_HI
-#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_IB_SIZE
-#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_PAGE_SKIP_CNTL
-#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_PAGE_CONTEXT_STATUS
-#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_PAGE_DOORBELL
-#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_PAGE_STATUS
-#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_PAGE_DOORBELL_LOG
-#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_PAGE_WATERMARK
-#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_PAGE_DOORBELL_OFFSET
-#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_PAGE_CSA_ADDR_LO
-#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_PAGE_CSA_ADDR_HI
-#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_IB_SUB_REMAIN
-#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_PAGE_PREEMPT
-#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_PAGE_DUMMY_REG
-#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_PAGE_RB_AQL_CNTL
-#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_PAGE_MINOR_PTR_UPDATE
-#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_PAGE_MIDCMD_DATA0
-#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA1
-#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA2
-#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA3
-#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA4
-#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA5
-#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA6
-#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA7
-#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_DATA8
-#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_PAGE_MIDCMD_CNTL
-#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_RLC0_RB_CNTL
-#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_RLC0_RB_BASE
-#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_BASE_HI
-#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_RLC0_RB_RPTR
-#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_RPTR_HI
-#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR
-#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_HI
-#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_CNTL
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_RLC0_RB_RPTR_ADDR_HI
-#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_RPTR_ADDR_LO
-#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_IB_CNTL
-#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_RLC0_IB_RPTR
-#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC0_IB_OFFSET
-#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC0_IB_BASE_LO
-#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_RLC0_IB_BASE_HI
-#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_IB_SIZE
-#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_RLC0_SKIP_CNTL
-#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_RLC0_CONTEXT_STATUS
-#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_RLC0_DOORBELL
-#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_RLC0_STATUS
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_RLC0_DOORBELL_LOG
-#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_WATERMARK
-#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_RLC0_DOORBELL_OFFSET
-#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_RLC0_CSA_ADDR_LO
-#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_CSA_ADDR_HI
-#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_IB_SUB_REMAIN
-#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_RLC0_PREEMPT
-#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_RLC0_DUMMY_REG
-#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_RB_AQL_CNTL
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_RLC0_MINOR_PTR_UPDATE
-#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_RLC0_MIDCMD_DATA0
-#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA1
-#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA2
-#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA3
-#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA4
-#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA5
-#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA6
-#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA7
-#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA8
-#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_CNTL
-#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_RLC1_RB_CNTL
-#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_RLC1_RB_BASE
-#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_BASE_HI
-#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_RLC1_RB_RPTR
-#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_RPTR_HI
-#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR
-#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_HI
-#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_CNTL
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_RLC1_RB_RPTR_ADDR_HI
-#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_RPTR_ADDR_LO
-#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_IB_CNTL
-#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_RLC1_IB_RPTR
-#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC1_IB_OFFSET
-#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC1_IB_BASE_LO
-#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_RLC1_IB_BASE_HI
-#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_IB_SIZE
-#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_RLC1_SKIP_CNTL
-#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_RLC1_CONTEXT_STATUS
-#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_RLC1_DOORBELL
-#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_RLC1_STATUS
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_RLC1_DOORBELL_LOG
-#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_WATERMARK
-#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_RLC1_DOORBELL_OFFSET
-#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_RLC1_CSA_ADDR_LO
-#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_CSA_ADDR_HI
-#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_IB_SUB_REMAIN
-#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_RLC1_PREEMPT
-#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_RLC1_DUMMY_REG
-#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_RB_AQL_CNTL
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_RLC1_MINOR_PTR_UPDATE
-#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_RLC1_MIDCMD_DATA0
-#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA1
-#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA2
-#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA3
-#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA4
-#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA5
-#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA6
-#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA7
-#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA8
-#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_CNTL
-#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
deleted file mode 100644
index 85c5c5e..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma1_4_0_DEFAULT_HEADER
-#define _sdma1_4_0_DEFAULT_HEADER
-
-
-// addressBlock: sdma1_sdma1dec
-#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
-#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
-#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
-#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
-#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
-#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
-#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
-#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
-#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000
-#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882
-#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
-#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
-#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000
-#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100
-#define mmSDMA1_CNTL_DEFAULT 0x00000002
-#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07
-#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012
-#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
-#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
-#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000
-#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000
-#define mmSDMA1_PROGRAM_DEFAULT 0x00000000
-#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557
-#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff
-#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003
-#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000
-#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000
-#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001
-#define mmSDMA1_FREEZE_DEFAULT 0x00000000
-#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002
-#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff
-#define mmSDMA1_ID_DEFAULT 0x00000001
-#define mmSDMA1_VERSION_DEFAULT 0x00000400
-#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000
-#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
-#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001
-#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200
-#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019
-#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
-#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff
-#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff
-#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600
-#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001
-#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0
-#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200
-#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
-#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005
-#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000
-#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f
-#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000
-#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000
-#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000
-#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000
-#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000
-#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000
-#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd
-#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
-#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0
-#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000
-#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
-#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
-#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
deleted file mode 100644
index 92150d6..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
+++ /dev/null
@@ -1,539 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma1_4_0_OFFSET_HEADER
-#define _sdma1_4_0_OFFSET_HEADER
-
-
-
-// addressBlock: sdma1_sdma1dec
-// base address: 0x5180
-#define mmSDMA1_UCODE_ADDR 0x0000
-#define mmSDMA1_UCODE_ADDR_BASE_IDX 0
-#define mmSDMA1_UCODE_DATA 0x0001
-#define mmSDMA1_UCODE_DATA_BASE_IDX 0
-#define mmSDMA1_VM_CNTL 0x0004
-#define mmSDMA1_VM_CNTL_BASE_IDX 0
-#define mmSDMA1_VM_CTX_LO 0x0005
-#define mmSDMA1_VM_CTX_LO_BASE_IDX 0
-#define mmSDMA1_VM_CTX_HI 0x0006
-#define mmSDMA1_VM_CTX_HI_BASE_IDX 0
-#define mmSDMA1_ACTIVE_FCN_ID 0x0007
-#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmSDMA1_VM_CTX_CNTL 0x0008
-#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0
-#define mmSDMA1_VIRT_RESET_REQ 0x0009
-#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0
-#define mmSDMA1_VF_ENABLE 0x000a
-#define mmSDMA1_VF_ENABLE_BASE_IDX 0
-#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b
-#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0
-#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c
-#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0
-#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d
-#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0
-#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e
-#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0
-#define mmSDMA1_PUB_REG_TYPE0 0x000f
-#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0
-#define mmSDMA1_PUB_REG_TYPE1 0x0010
-#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0
-#define mmSDMA1_PUB_REG_TYPE2 0x0011
-#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0
-#define mmSDMA1_PUB_REG_TYPE3 0x0012
-#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0
-#define mmSDMA1_MMHUB_CNTL 0x0013
-#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0
-#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019
-#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
-#define mmSDMA1_POWER_CNTL 0x001a
-#define mmSDMA1_POWER_CNTL_BASE_IDX 0
-#define mmSDMA1_CLK_CTRL 0x001b
-#define mmSDMA1_CLK_CTRL_BASE_IDX 0
-#define mmSDMA1_CNTL 0x001c
-#define mmSDMA1_CNTL_BASE_IDX 0
-#define mmSDMA1_CHICKEN_BITS 0x001d
-#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0
-#define mmSDMA1_GB_ADDR_CONFIG 0x001e
-#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0
-#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f
-#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0
-#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020
-#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0
-#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
-#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
-#define mmSDMA1_RB_RPTR_FETCH 0x0022
-#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0
-#define mmSDMA1_IB_OFFSET_FETCH 0x0023
-#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0
-#define mmSDMA1_PROGRAM 0x0024
-#define mmSDMA1_PROGRAM_BASE_IDX 0
-#define mmSDMA1_STATUS_REG 0x0025
-#define mmSDMA1_STATUS_REG_BASE_IDX 0
-#define mmSDMA1_STATUS1_REG 0x0026
-#define mmSDMA1_STATUS1_REG_BASE_IDX 0
-#define mmSDMA1_RD_BURST_CNTL 0x0027
-#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0
-#define mmSDMA1_HBM_PAGE_CONFIG 0x0028
-#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0
-#define mmSDMA1_UCODE_CHECKSUM 0x0029
-#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0
-#define mmSDMA1_F32_CNTL 0x002a
-#define mmSDMA1_F32_CNTL_BASE_IDX 0
-#define mmSDMA1_FREEZE 0x002b
-#define mmSDMA1_FREEZE_BASE_IDX 0
-#define mmSDMA1_PHASE0_QUANTUM 0x002c
-#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0
-#define mmSDMA1_PHASE1_QUANTUM 0x002d
-#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0
-#define mmSDMA1_EDC_CONFIG 0x0032
-#define mmSDMA1_EDC_CONFIG_BASE_IDX 0
-#define mmSDMA1_BA_THRESHOLD 0x0033
-#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0
-#define mmSDMA1_ID 0x0034
-#define mmSDMA1_ID_BASE_IDX 0
-#define mmSDMA1_VERSION 0x0035
-#define mmSDMA1_VERSION_BASE_IDX 0
-#define mmSDMA1_EDC_COUNTER 0x0036
-#define mmSDMA1_EDC_COUNTER_BASE_IDX 0
-#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037
-#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0
-#define mmSDMA1_STATUS2_REG 0x0038
-#define mmSDMA1_STATUS2_REG_BASE_IDX 0
-#define mmSDMA1_ATOMIC_CNTL 0x0039
-#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0
-#define mmSDMA1_ATOMIC_PREOP_LO 0x003a
-#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0
-#define mmSDMA1_ATOMIC_PREOP_HI 0x003b
-#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0
-#define mmSDMA1_UTCL1_CNTL 0x003c
-#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0
-#define mmSDMA1_UTCL1_WATERMK 0x003d
-#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0
-#define mmSDMA1_UTCL1_RD_STATUS 0x003e
-#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0
-#define mmSDMA1_UTCL1_WR_STATUS 0x003f
-#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0
-#define mmSDMA1_UTCL1_INV0 0x0040
-#define mmSDMA1_UTCL1_INV0_BASE_IDX 0
-#define mmSDMA1_UTCL1_INV1 0x0041
-#define mmSDMA1_UTCL1_INV1_BASE_IDX 0
-#define mmSDMA1_UTCL1_INV2 0x0042
-#define mmSDMA1_UTCL1_INV2_BASE_IDX 0
-#define mmSDMA1_UTCL1_RD_XNACK0 0x0043
-#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0
-#define mmSDMA1_UTCL1_RD_XNACK1 0x0044
-#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0
-#define mmSDMA1_UTCL1_WR_XNACK0 0x0045
-#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0
-#define mmSDMA1_UTCL1_WR_XNACK1 0x0046
-#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0
-#define mmSDMA1_UTCL1_TIMEOUT 0x0047
-#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0
-#define mmSDMA1_UTCL1_PAGE 0x0048
-#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0
-#define mmSDMA1_POWER_CNTL_IDLE 0x0049
-#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0
-#define mmSDMA1_RELAX_ORDERING_LUT 0x004a
-#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0
-#define mmSDMA1_CHICKEN_BITS_2 0x004b
-#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0
-#define mmSDMA1_STATUS3_REG 0x004c
-#define mmSDMA1_STATUS3_REG_BASE_IDX 0
-#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d
-#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e
-#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_PHASE2_QUANTUM 0x004f
-#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0
-#define mmSDMA1_ERROR_LOG 0x0050
-#define mmSDMA1_ERROR_LOG_BASE_IDX 0
-#define mmSDMA1_PUB_DUMMY_REG0 0x0051
-#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0
-#define mmSDMA1_PUB_DUMMY_REG1 0x0052
-#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0
-#define mmSDMA1_PUB_DUMMY_REG2 0x0053
-#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0
-#define mmSDMA1_PUB_DUMMY_REG3 0x0054
-#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0
-#define mmSDMA1_F32_COUNTER 0x0055
-#define mmSDMA1_F32_COUNTER_BASE_IDX 0
-#define mmSDMA1_UNBREAKABLE 0x0056
-#define mmSDMA1_UNBREAKABLE_BASE_IDX 0
-#define mmSDMA1_PERFMON_CNTL 0x0057
-#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0
-#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058
-#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0
-#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059
-#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0
-#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
-#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
-#define mmSDMA1_CRD_CNTL 0x005b
-#define mmSDMA1_CRD_CNTL_BASE_IDX 0
-#define mmSDMA1_MMHUB_TRUSTLVL 0x005c
-#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0
-#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d
-#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
-#define mmSDMA1_ULV_CNTL 0x005e
-#define mmSDMA1_ULV_CNTL_BASE_IDX 0
-#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060
-#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0
-#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061
-#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0
-#define mmSDMA1_GFX_RB_CNTL 0x0080
-#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0
-#define mmSDMA1_GFX_RB_BASE 0x0081
-#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0
-#define mmSDMA1_GFX_RB_BASE_HI 0x0082
-#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_GFX_RB_RPTR 0x0083
-#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0
-#define mmSDMA1_GFX_RB_RPTR_HI 0x0084
-#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA1_GFX_RB_WPTR 0x0085
-#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0
-#define mmSDMA1_GFX_RB_WPTR_HI 0x0086
-#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087
-#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088
-#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089
-#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_GFX_IB_CNTL 0x008a
-#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0
-#define mmSDMA1_GFX_IB_RPTR 0x008b
-#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0
-#define mmSDMA1_GFX_IB_OFFSET 0x008c
-#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0
-#define mmSDMA1_GFX_IB_BASE_LO 0x008d
-#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA1_GFX_IB_BASE_HI 0x008e
-#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_GFX_IB_SIZE 0x008f
-#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0
-#define mmSDMA1_GFX_SKIP_CNTL 0x0090
-#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091
-#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA1_GFX_DOORBELL 0x0092
-#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0
-#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093
-#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0
-#define mmSDMA1_GFX_STATUS 0x00a8
-#define mmSDMA1_GFX_STATUS_BASE_IDX 0
-#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9
-#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA1_GFX_WATERMARK 0x00aa
-#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0
-#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab
-#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac
-#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad
-#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af
-#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA1_GFX_PREEMPT 0x00b0
-#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0
-#define mmSDMA1_GFX_DUMMY_REG 0x00b1
-#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4
-#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5
-#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0
-#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1
-#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2
-#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3
-#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4
-#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5
-#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6
-#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7
-#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8
-#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9
-#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_CNTL 0x00e0
-#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_BASE 0x00e1
-#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2
-#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_RPTR 0x00e3
-#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4
-#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_WPTR 0x00e5
-#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6
-#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7
-#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_CNTL 0x00ea
-#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_RPTR 0x00eb
-#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_OFFSET 0x00ec
-#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed
-#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee
-#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_SIZE 0x00ef
-#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0
-#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0
-#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1
-#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA1_PAGE_DOORBELL 0x00f2
-#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0
-#define mmSDMA1_PAGE_STATUS 0x0108
-#define mmSDMA1_PAGE_STATUS_BASE_IDX 0
-#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109
-#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA1_PAGE_WATERMARK 0x010a
-#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0
-#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b
-#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c
-#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d
-#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f
-#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA1_PAGE_PREEMPT 0x0110
-#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0
-#define mmSDMA1_PAGE_DUMMY_REG 0x0111
-#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114
-#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115
-#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120
-#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121
-#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122
-#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123
-#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124
-#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125
-#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126
-#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127
-#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128
-#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129
-#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_CNTL 0x0140
-#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_BASE 0x0141
-#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_BASE_HI 0x0142
-#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_RPTR 0x0143
-#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144
-#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_WPTR 0x0145
-#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146
-#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147
-#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_CNTL 0x014a
-#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_RPTR 0x014b
-#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_OFFSET 0x014c
-#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_BASE_LO 0x014d
-#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_BASE_HI 0x014e
-#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_SIZE 0x014f
-#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0
-#define mmSDMA1_RLC0_SKIP_CNTL 0x0150
-#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151
-#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA1_RLC0_DOORBELL 0x0152
-#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0
-#define mmSDMA1_RLC0_STATUS 0x0168
-#define mmSDMA1_RLC0_STATUS_BASE_IDX 0
-#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169
-#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA1_RLC0_WATERMARK 0x016a
-#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0
-#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b
-#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c
-#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d
-#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f
-#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA1_RLC0_PREEMPT 0x0170
-#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0
-#define mmSDMA1_RLC0_DUMMY_REG 0x0171
-#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174
-#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175
-#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180
-#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181
-#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182
-#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183
-#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184
-#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185
-#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186
-#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187
-#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188
-#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189
-#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_CNTL 0x01a0
-#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_BASE 0x01a1
-#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2
-#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_RPTR 0x01a3
-#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4
-#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_WPTR 0x01a5
-#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6
-#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7
-#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_CNTL 0x01aa
-#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_RPTR 0x01ab
-#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_OFFSET 0x01ac
-#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad
-#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae
-#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_SIZE 0x01af
-#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0
-#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0
-#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1
-#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0
-#define mmSDMA1_RLC1_DOORBELL 0x01b2
-#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0
-#define mmSDMA1_RLC1_STATUS 0x01c8
-#define mmSDMA1_RLC1_STATUS_BASE_IDX 0
-#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9
-#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0
-#define mmSDMA1_RLC1_WATERMARK 0x01ca
-#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0
-#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb
-#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0
-#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc
-#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd
-#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf
-#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0
-#define mmSDMA1_RLC1_PREEMPT 0x01d0
-#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0
-#define mmSDMA1_RLC1_DUMMY_REG 0x01d1
-#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
-#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4
-#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0
-#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5
-#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0
-#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1
-#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2
-#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3
-#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4
-#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5
-#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6
-#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7
-#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8
-#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0
-#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9
-#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
deleted file mode 100644
index 25decdf9..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
+++ /dev/null
@@ -1,1810 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma1_4_0_SH_MASK_HEADER
-#define _sdma1_4_0_SH_MASK_HEADER
-
-
-// addressBlock: sdma1_sdma1dec
-//SDMA1_UCODE_ADDR
-#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
-#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL
-//SDMA1_UCODE_DATA
-#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
-#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_VM_CNTL
-#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
-#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL
-//SDMA1_VM_CTX_LO
-#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
-#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_VM_CTX_HI
-#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
-#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_ACTIVE_FCN_ID
-#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//SDMA1_VM_CTX_CNTL
-#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
-#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
-#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L
-#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L
-//SDMA1_VIRT_RESET_REQ
-#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//SDMA1_VF_ENABLE
-#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
-#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
-//SDMA1_CONTEXT_REG_TYPE0
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L
-#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L
-//SDMA1_CONTEXT_REG_TYPE1
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
-#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
-#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L
-#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L
-#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
-#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
-//SDMA1_CONTEXT_REG_TYPE2
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9
-#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L
-#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L
-#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
-//SDMA1_CONTEXT_REG_TYPE3
-#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
-#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
-//SDMA1_PUB_REG_TYPE0
-#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
-#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
-#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6
-#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9
-#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12
-#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13
-#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
-#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
-#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e
-#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f
-#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L
-#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L
-#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L
-#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L
-#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L
-//SDMA1_PUB_REG_TYPE1
-#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0
-#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
-#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2
-#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3
-#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4
-#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5
-#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6
-#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7
-#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9
-#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
-#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb
-#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc
-#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd
-#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
-#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
-#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
-#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
-#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12
-#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14
-#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15
-#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16
-#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17
-#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f
-#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L
-#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
-#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
-#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
-#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L
-#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L
-//SDMA1_PUB_REG_TYPE2
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8
-#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9
-#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
-#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb
-#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf
-#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14
-#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
-#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b
-#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c
-#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
-#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e
-#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
-#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L
-#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
-//SDMA1_PUB_REG_TYPE3
-#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0
-#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1
-#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
-#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L
-#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
-#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
-//SDMA1_MMHUB_CNTL
-#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
-#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
-//SDMA1_CONTEXT_GROUP_BOUNDARY
-#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
-#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
-//SDMA1_POWER_CNTL
-#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
-#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
-#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
-#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
-#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
-#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
-#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
-#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
-#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
-#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
-//SDMA1_CLK_CTRL
-#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//SDMA1_CNTL
-#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
-#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1
-#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
-#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
-#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
-#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
-#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
-#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
-#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
-#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
-#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
-#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L
-#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
-#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
-#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
-#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
-#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
-#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
-#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
-#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
-#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
-//SDMA1_CHICKEN_BITS
-#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
-#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
-#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
-#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
-#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
-#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
-#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
-#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
-#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
-#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
-#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
-#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
-#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
-#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
-#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
-#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
-#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
-#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
-#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
-#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
-#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
-#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
-#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
-#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
-#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
-#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
-//SDMA1_GB_ADDR_CONFIG
-#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA1_GB_ADDR_CONFIG_READ
-#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
-#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
-#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
-#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
-#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA1_RB_RPTR_FETCH_HI
-#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
-#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
-#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
-#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
-//SDMA1_RB_RPTR_FETCH
-#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
-#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
-//SDMA1_IB_OFFSET_FETCH
-#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
-#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
-//SDMA1_PROGRAM
-#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
-#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL
-//SDMA1_STATUS_REG
-#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
-#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
-#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
-#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
-#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
-#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
-#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
-#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
-#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
-#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
-#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
-#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
-#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
-#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
-#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
-#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
-#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
-#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
-#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
-#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
-#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
-#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
-#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
-#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
-#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
-#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
-#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
-#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
-#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
-#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L
-#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L
-#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L
-#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L
-#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
-#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
-#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
-#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
-#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
-#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L
-#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L
-#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
-#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L
-#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
-#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
-#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
-#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
-#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
-#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
-#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
-#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
-#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
-#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
-#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
-#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L
-#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
-#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
-#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L
-#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
-//SDMA1_STATUS1_REG
-#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
-#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
-#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
-#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
-#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
-#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
-#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
-#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
-#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
-#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
-#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
-#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf
-#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
-#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
-#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
-#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
-#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
-#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
-#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
-#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
-#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
-#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
-#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
-#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
-#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
-#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L
-#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
-#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
-//SDMA1_RD_BURST_CNTL
-#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
-#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
-//SDMA1_HBM_PAGE_CONFIG
-#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
-#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L
-//SDMA1_UCODE_CHECKSUM
-#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0
-#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
-//SDMA1_F32_CNTL
-#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
-#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
-#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L
-#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L
-//SDMA1_FREEZE
-#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0
-#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
-#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
-#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
-#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L
-#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L
-#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L
-#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L
-//SDMA1_PHASE0_QUANTUM
-#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA1_PHASE1_QUANTUM
-#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA1_EDC_CONFIG
-#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
-#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
-//SDMA1_BA_THRESHOLD
-#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
-#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
-#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
-#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
-//SDMA1_ID
-#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
-#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL
-//SDMA1_VERSION
-#define SDMA1_VERSION__MINVER__SHIFT 0x0
-#define SDMA1_VERSION__MAJVER__SHIFT 0x8
-#define SDMA1_VERSION__REV__SHIFT 0x10
-#define SDMA1_VERSION__MINVER_MASK 0x0000007FL
-#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L
-#define SDMA1_VERSION__REV_MASK 0x003F0000L
-//SDMA1_EDC_COUNTER
-#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
-#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
-#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
-#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
-#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
-#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
-#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
-#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
-#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
-#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
-#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
-#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
-#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
-#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
-#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
-#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
-#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
-#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
-#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
-//SDMA1_EDC_COUNTER_CLEAR
-#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
-#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
-//SDMA1_STATUS2_REG
-#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
-#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
-#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
-#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L
-#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
-#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
-//SDMA1_ATOMIC_CNTL
-#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
-#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
-#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
-#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
-//SDMA1_ATOMIC_PREOP_LO
-#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
-#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
-//SDMA1_ATOMIC_PREOP_HI
-#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
-#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
-//SDMA1_UTCL1_CNTL
-#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
-#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
-#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
-#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
-#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
-#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
-#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
-#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
-#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
-#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
-#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
-#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
-//SDMA1_UTCL1_WATERMK
-#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
-#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
-#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
-#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
-#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
-#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
-#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
-#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
-//SDMA1_UTCL1_RD_STATUS
-#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
-#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
-#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
-#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
-#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
-#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
-#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
-#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
-#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
-#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
-#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
-#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
-//SDMA1_UTCL1_WR_STATUS
-#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
-#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
-#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
-#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
-#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
-#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
-#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
-#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
-#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
-#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
-#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
-#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
-#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
-#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
-//SDMA1_UTCL1_INV0
-#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
-#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
-#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
-#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
-#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
-#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
-#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
-#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
-#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
-#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
-#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
-#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
-#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
-#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
-#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
-#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
-#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
-#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
-#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
-#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
-#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
-#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
-#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
-#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
-#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
-#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
-#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
-#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
-//SDMA1_UTCL1_INV1
-#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
-#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA1_UTCL1_INV2
-#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
-#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
-//SDMA1_UTCL1_RD_XNACK0
-#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA1_UTCL1_RD_XNACK1
-#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA1_UTCL1_WR_XNACK0
-#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA1_UTCL1_WR_XNACK1
-#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA1_UTCL1_TIMEOUT
-#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
-#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
-#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
-#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
-//SDMA1_UTCL1_PAGE
-#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
-#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
-#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
-#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
-#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
-#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
-#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
-#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
-//SDMA1_POWER_CNTL_IDLE
-#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
-#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
-#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
-#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
-#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
-#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
-//SDMA1_RELAX_ORDERING_LUT
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
-#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
-#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
-#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
-#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
-#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
-#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
-#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
-#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
-#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
-#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
-#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
-#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
-#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
-#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
-#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
-#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
-#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
-#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
-#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
-#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
-#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
-#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
-#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
-#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
-#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
-#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
-#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
-#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
-#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
-//SDMA1_CHICKEN_BITS_2
-#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
-#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
-//SDMA1_STATUS3_REG
-#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
-#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
-#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
-#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
-#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
-#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
-//SDMA1_PHYSICAL_ADDR_LO
-#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
-#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
-#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
-#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
-#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
-#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
-#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
-#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
-//SDMA1_PHYSICAL_ADDR_HI
-#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
-//SDMA1_PHASE2_QUANTUM
-#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA1_ERROR_LOG
-#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0
-#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10
-#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
-#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L
-//SDMA1_PUB_DUMMY_REG0
-#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
-#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_PUB_DUMMY_REG1
-#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
-#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_PUB_DUMMY_REG2
-#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
-#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_PUB_DUMMY_REG3
-#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
-#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_F32_COUNTER
-#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0
-#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_UNBREAKABLE
-#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0
-#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L
-//SDMA1_PERFMON_CNTL
-#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
-#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
-#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
-#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
-#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
-#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
-#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
-#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
-#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
-#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
-#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
-#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
-//SDMA1_PERFCOUNTER0_RESULT
-#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA1_PERFCOUNTER1_RESULT
-#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
-#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
-#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
-#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
-#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
-#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
-#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
-//SDMA1_CRD_CNTL
-#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
-#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
-#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
-#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
-//SDMA1_MMHUB_TRUSTLVL
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
-#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
-//SDMA1_GPU_IOV_VIOLATION_LOG
-#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
-#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
-#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
-#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
-#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//SDMA1_ULV_CNTL
-#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0
-#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
-#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
-#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
-#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
-#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
-#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
-#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
-//SDMA1_EA_DBIT_ADDR_DATA
-#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
-#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA1_EA_DBIT_ADDR_INDEX
-#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
-#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
-//SDMA1_GFX_RB_CNTL
-#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA1_GFX_RB_BASE
-#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_BASE_HI
-#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA1_GFX_RB_RPTR
-#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_RPTR_HI
-#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_WPTR
-#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_WPTR_HI
-#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_WPTR_POLL_CNTL
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA1_GFX_RB_RPTR_ADDR_HI
-#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_RPTR_ADDR_LO
-#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_GFX_IB_CNTL
-#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA1_GFX_IB_RPTR
-#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA1_GFX_IB_OFFSET
-#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA1_GFX_IB_BASE_LO
-#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA1_GFX_IB_BASE_HI
-#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_GFX_IB_SIZE
-#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA1_GFX_SKIP_CNTL
-#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA1_GFX_CONTEXT_STATUS
-#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA1_GFX_DOORBELL
-#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA1_GFX_CONTEXT_CNTL
-#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
-#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
-//SDMA1_GFX_STATUS
-#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA1_GFX_DOORBELL_LOG
-#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA1_GFX_WATERMARK
-#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA1_GFX_DOORBELL_OFFSET
-#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA1_GFX_CSA_ADDR_LO
-#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_GFX_CSA_ADDR_HI
-#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_GFX_IB_SUB_REMAIN
-#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA1_GFX_PREEMPT
-#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA1_GFX_DUMMY_REG
-#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
-#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
-#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_GFX_RB_AQL_CNTL
-#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA1_GFX_MINOR_PTR_UPDATE
-#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA1_GFX_MIDCMD_DATA0
-#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA1
-#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA2
-#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA3
-#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA4
-#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA5
-#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA6
-#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA7
-#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_DATA8
-#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA1_GFX_MIDCMD_CNTL
-#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA1_PAGE_RB_CNTL
-#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA1_PAGE_RB_BASE
-#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_BASE_HI
-#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA1_PAGE_RB_RPTR
-#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_RPTR_HI
-#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_WPTR
-#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_WPTR_HI
-#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_WPTR_POLL_CNTL
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA1_PAGE_RB_RPTR_ADDR_HI
-#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_RPTR_ADDR_LO
-#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_PAGE_IB_CNTL
-#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA1_PAGE_IB_RPTR
-#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA1_PAGE_IB_OFFSET
-#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA1_PAGE_IB_BASE_LO
-#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA1_PAGE_IB_BASE_HI
-#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_IB_SIZE
-#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA1_PAGE_SKIP_CNTL
-#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA1_PAGE_CONTEXT_STATUS
-#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA1_PAGE_DOORBELL
-#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA1_PAGE_STATUS
-#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA1_PAGE_DOORBELL_LOG
-#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA1_PAGE_WATERMARK
-#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA1_PAGE_DOORBELL_OFFSET
-#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA1_PAGE_CSA_ADDR_LO
-#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_PAGE_CSA_ADDR_HI
-#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_IB_SUB_REMAIN
-#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA1_PAGE_PREEMPT
-#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA1_PAGE_DUMMY_REG
-#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
-#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
-#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_PAGE_RB_AQL_CNTL
-#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA1_PAGE_MINOR_PTR_UPDATE
-#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA1_PAGE_MIDCMD_DATA0
-#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA1
-#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA2
-#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA3
-#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA4
-#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA5
-#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA6
-#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA7
-#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_DATA8
-#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA1_PAGE_MIDCMD_CNTL
-#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA1_RLC0_RB_CNTL
-#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA1_RLC0_RB_BASE
-#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_BASE_HI
-#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA1_RLC0_RB_RPTR
-#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_RPTR_HI
-#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_WPTR
-#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_WPTR_HI
-#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_WPTR_POLL_CNTL
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA1_RLC0_RB_RPTR_ADDR_HI
-#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_RPTR_ADDR_LO
-#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_RLC0_IB_CNTL
-#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA1_RLC0_IB_RPTR
-#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA1_RLC0_IB_OFFSET
-#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA1_RLC0_IB_BASE_LO
-#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA1_RLC0_IB_BASE_HI
-#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_IB_SIZE
-#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA1_RLC0_SKIP_CNTL
-#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA1_RLC0_CONTEXT_STATUS
-#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA1_RLC0_DOORBELL
-#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA1_RLC0_STATUS
-#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA1_RLC0_DOORBELL_LOG
-#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA1_RLC0_WATERMARK
-#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA1_RLC0_DOORBELL_OFFSET
-#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA1_RLC0_CSA_ADDR_LO
-#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_RLC0_CSA_ADDR_HI
-#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_IB_SUB_REMAIN
-#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA1_RLC0_PREEMPT
-#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA1_RLC0_DUMMY_REG
-#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
-#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
-#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_RLC0_RB_AQL_CNTL
-#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA1_RLC0_MINOR_PTR_UPDATE
-#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA1_RLC0_MIDCMD_DATA0
-#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA1
-#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA2
-#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA3
-#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA4
-#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA5
-#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA6
-#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA7
-#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_DATA8
-#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA1_RLC0_MIDCMD_CNTL
-#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA1_RLC1_RB_CNTL
-#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA1_RLC1_RB_BASE
-#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_BASE_HI
-#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA1_RLC1_RB_RPTR
-#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_RPTR_HI
-#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_WPTR
-#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_WPTR_HI
-#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_WPTR_POLL_CNTL
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA1_RLC1_RB_RPTR_ADDR_HI
-#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_RPTR_ADDR_LO
-#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_RLC1_IB_CNTL
-#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA1_RLC1_IB_RPTR
-#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA1_RLC1_IB_OFFSET
-#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA1_RLC1_IB_BASE_LO
-#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA1_RLC1_IB_BASE_HI
-#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_IB_SIZE
-#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA1_RLC1_SKIP_CNTL
-#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA1_RLC1_CONTEXT_STATUS
-#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA1_RLC1_DOORBELL
-#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA1_RLC1_STATUS
-#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA1_RLC1_DOORBELL_LOG
-#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA1_RLC1_WATERMARK
-#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA1_RLC1_DOORBELL_OFFSET
-#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA1_RLC1_CSA_ADDR_LO
-#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_RLC1_CSA_ADDR_HI
-#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_IB_SUB_REMAIN
-#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA1_RLC1_PREEMPT
-#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA1_RLC1_DUMMY_REG
-#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
-#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
-#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA1_RLC1_RB_AQL_CNTL
-#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA1_RLC1_MINOR_PTR_UPDATE
-#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA1_RLC1_MIDCMD_DATA0
-#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA1
-#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA2
-#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA3
-#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA4
-#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA5
-#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA6
-#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA7
-#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_DATA8
-#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA1_RLC1_MIDCMD_CNTL
-#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
deleted file mode 100644
index 5c186c2..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _smuio_9_0_DEFAULT_HEADER
-#define _smuio_9_0_DEFAULT_HEADER
-
-
-// addressBlock: smuio_smuio_SmuSmuioDec
-#define mmROM_CNTL_DEFAULT 0x00000000
-#define mmROM_STATUS_DEFAULT 0x00000000
-#define mmCGTT_ROM_CLK_CTRL0_DEFAULT 0xc0000100
-#define mmROM_INDEX_DEFAULT 0x00000000
-#define mmROM_DATA_DEFAULT 0x00000000
-#define mmROM_START_DEFAULT 0x00000000
-#define mmROM_SW_CNTL_DEFAULT 0x00000000
-#define mmROM_SW_STATUS_DEFAULT 0x00000000
-#define mmROM_SW_COMMAND_DEFAULT 0x00000000
-#define mmROM_SW_DATA_1_DEFAULT 0x00000000
-#define mmROM_SW_DATA_2_DEFAULT 0x00000000
-#define mmROM_SW_DATA_3_DEFAULT 0x00000000
-#define mmROM_SW_DATA_4_DEFAULT 0x00000000
-#define mmROM_SW_DATA_5_DEFAULT 0x00000000
-#define mmROM_SW_DATA_6_DEFAULT 0x00000000
-#define mmROM_SW_DATA_7_DEFAULT 0x00000000
-#define mmROM_SW_DATA_8_DEFAULT 0x00000000
-#define mmROM_SW_DATA_9_DEFAULT 0x00000000
-#define mmROM_SW_DATA_10_DEFAULT 0x00000000
-#define mmROM_SW_DATA_11_DEFAULT 0x00000000
-#define mmROM_SW_DATA_12_DEFAULT 0x00000000
-#define mmROM_SW_DATA_13_DEFAULT 0x00000000
-#define mmROM_SW_DATA_14_DEFAULT 0x00000000
-#define mmROM_SW_DATA_15_DEFAULT 0x00000000
-#define mmROM_SW_DATA_16_DEFAULT 0x00000000
-#define mmROM_SW_DATA_17_DEFAULT 0x00000000
-#define mmROM_SW_DATA_18_DEFAULT 0x00000000
-#define mmROM_SW_DATA_19_DEFAULT 0x00000000
-#define mmROM_SW_DATA_20_DEFAULT 0x00000000
-#define mmROM_SW_DATA_21_DEFAULT 0x00000000
-#define mmROM_SW_DATA_22_DEFAULT 0x00000000
-#define mmROM_SW_DATA_23_DEFAULT 0x00000000
-#define mmROM_SW_DATA_24_DEFAULT 0x00000000
-#define mmROM_SW_DATA_25_DEFAULT 0x00000000
-#define mmROM_SW_DATA_26_DEFAULT 0x00000000
-#define mmROM_SW_DATA_27_DEFAULT 0x00000000
-#define mmROM_SW_DATA_28_DEFAULT 0x00000000
-#define mmROM_SW_DATA_29_DEFAULT 0x00000000
-#define mmROM_SW_DATA_30_DEFAULT 0x00000000
-#define mmROM_SW_DATA_31_DEFAULT 0x00000000
-#define mmROM_SW_DATA_32_DEFAULT 0x00000000
-#define mmROM_SW_DATA_33_DEFAULT 0x00000000
-#define mmROM_SW_DATA_34_DEFAULT 0x00000000
-#define mmROM_SW_DATA_35_DEFAULT 0x00000000
-#define mmROM_SW_DATA_36_DEFAULT 0x00000000
-#define mmROM_SW_DATA_37_DEFAULT 0x00000000
-#define mmROM_SW_DATA_38_DEFAULT 0x00000000
-#define mmROM_SW_DATA_39_DEFAULT 0x00000000
-#define mmROM_SW_DATA_40_DEFAULT 0x00000000
-#define mmROM_SW_DATA_41_DEFAULT 0x00000000
-#define mmROM_SW_DATA_42_DEFAULT 0x00000000
-#define mmROM_SW_DATA_43_DEFAULT 0x00000000
-#define mmROM_SW_DATA_44_DEFAULT 0x00000000
-#define mmROM_SW_DATA_45_DEFAULT 0x00000000
-#define mmROM_SW_DATA_46_DEFAULT 0x00000000
-#define mmROM_SW_DATA_47_DEFAULT 0x00000000
-#define mmROM_SW_DATA_48_DEFAULT 0x00000000
-#define mmROM_SW_DATA_49_DEFAULT 0x00000000
-#define mmROM_SW_DATA_50_DEFAULT 0x00000000
-#define mmROM_SW_DATA_51_DEFAULT 0x00000000
-#define mmROM_SW_DATA_52_DEFAULT 0x00000000
-#define mmROM_SW_DATA_53_DEFAULT 0x00000000
-#define mmROM_SW_DATA_54_DEFAULT 0x00000000
-#define mmROM_SW_DATA_55_DEFAULT 0x00000000
-#define mmROM_SW_DATA_56_DEFAULT 0x00000000
-#define mmROM_SW_DATA_57_DEFAULT 0x00000000
-#define mmROM_SW_DATA_58_DEFAULT 0x00000000
-#define mmROM_SW_DATA_59_DEFAULT 0x00000000
-#define mmROM_SW_DATA_60_DEFAULT 0x00000000
-#define mmROM_SW_DATA_61_DEFAULT 0x00000000
-#define mmROM_SW_DATA_62_DEFAULT 0x00000000
-#define mmROM_SW_DATA_63_DEFAULT 0x00000000
-#define mmROM_SW_DATA_64_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
deleted file mode 100644
index 48963ca..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _uvd_7_0_DEFAULT_HEADER
-#define _uvd_7_0_DEFAULT_HEADER
-
-
-// addressBlock: uvd0_uvd_pg_dec
-#define mmUVD_POWER_STATUS_DEFAULT 0x00000000
-#define mmUVD_DPG_RBC_RB_CNTL_DEFAULT 0x01000101
-#define mmUVD_DPG_RBC_RB_BASE_LOW_DEFAULT 0x00000000
-#define mmUVD_DPG_RBC_RB_BASE_HIGH_DEFAULT 0x00000000
-#define mmUVD_DPG_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000
-#define mmUVD_DPG_RBC_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_DPG_RBC_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
-
-
-// addressBlock: uvd0_uvdnpdec
-#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000
-#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000
-#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000
-#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010
-#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000
-#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_POWER_STATUS_U_DEFAULT 0x00000000
-#define mmUVD_NO_OP_DEFAULT 0x00000000
-#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE2_DEFAULT 0x00000000
-#define mmUVD_RB_RPTR2_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR2_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE_DEFAULT 0x00000000
-#define mmUVD_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000
-#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000
-
-
-// addressBlock: uvd0_uvddec
-#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003
-#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000
-#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_RB_RPTR3_DEFAULT 0x00000000
-#define mmUVD_RB_WPTR3_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000
-#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000
-#define mmUVD_RB_SIZE3_DEFAULT 0x00000000
-#define mmJPEG_CGC_GATE_DEFAULT 0x00300000
-#define mmUVD_CTX_INDEX_DEFAULT 0x00000000
-#define mmUVD_CTX_DATA_DEFAULT 0x00000000
-#define mmUVD_CGC_GATE_DEFAULT 0x000fffff
-#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d
-#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000
-#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000
-#define mmUVD_MASTINT_EN_DEFAULT 0x00000000
-#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d
-#define mmUVD_LMI_CTRL_DEFAULT 0x00104340
-#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000
-#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000
-#define mmUVD_MP_SWAP_CNTL_DEFAULT 0x00000000
-#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040
-#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000
-#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040
-#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000
-#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088
-#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
-#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
-#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000
-#define mmUVD_SOFT_RESET_DEFAULT 0x00000008
-#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000
-#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000
-#define mmUVD_LMI_RBC_RB_VMID_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000
-#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101
-#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000
-#define mmUVD_STATUS_DEFAULT 0x00000000
-#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000
-#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000
-#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000
-#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000
-#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000
-#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 7343aed..7214731 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -25,6 +25,145 @@
#define PP_MAX_CLOCK_LEVELS 8
+enum amd_pp_display_config_type{
+ AMD_PP_DisplayConfigType_None = 0,
+ AMD_PP_DisplayConfigType_DP54 ,
+ AMD_PP_DisplayConfigType_DP432 ,
+ AMD_PP_DisplayConfigType_DP324 ,
+ AMD_PP_DisplayConfigType_DP27,
+ AMD_PP_DisplayConfigType_DP243,
+ AMD_PP_DisplayConfigType_DP216,
+ AMD_PP_DisplayConfigType_DP162,
+ AMD_PP_DisplayConfigType_HDMI6G ,
+ AMD_PP_DisplayConfigType_HDMI297 ,
+ AMD_PP_DisplayConfigType_HDMI162,
+ AMD_PP_DisplayConfigType_LVDS,
+ AMD_PP_DisplayConfigType_DVI,
+ AMD_PP_DisplayConfigType_WIRELESS,
+ AMD_PP_DisplayConfigType_VGA
+};
+
+struct single_display_configuration
+{
+ uint32_t controller_index;
+ uint32_t controller_id;
+ uint32_t signal_type;
+ uint32_t display_state;
+ /* phy id for the primary internal transmitter */
+ uint8_t primary_transmitter_phyi_d;
+ /* bitmap with the active lanes */
+ uint8_t primary_transmitter_active_lanemap;
+ /* phy id for the secondary internal transmitter (for dual-link dvi) */
+ uint8_t secondary_transmitter_phy_id;
+ /* bitmap with the active lanes */
+ uint8_t secondary_transmitter_active_lanemap;
+ /* misc phy settings for SMU. */
+ uint32_t config_flags;
+ uint32_t display_type;
+ uint32_t view_resolution_cx;
+ uint32_t view_resolution_cy;
+ enum amd_pp_display_config_type displayconfigtype;
+ uint32_t vertical_refresh; /* for active display */
+};
+
+#define MAX_NUM_DISPLAY 32
+
+struct amd_pp_display_configuration {
+ bool nb_pstate_switch_disable;/* controls NB PState switch */
+ bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
+ bool cpu_pstate_disable;
+ uint32_t cpu_pstate_separation_time;
+
+ uint32_t num_display; /* total number of display*/
+ uint32_t num_path_including_non_display;
+ uint32_t crossfire_display_index;
+ uint32_t min_mem_set_clock;
+ uint32_t min_core_set_clock;
+ /* unit 10KHz x bit*/
+ uint32_t min_bus_bandwidth;
+ /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
+ uint32_t min_core_set_clock_in_sr;
+
+ struct single_display_configuration displays[MAX_NUM_DISPLAY];
+
+ uint32_t vrefresh; /* for active display*/
+
+ uint32_t min_vblank_time; /* for active display*/
+ bool multi_monitor_in_sync;
+ /* Controller Index of primary display - used in MCLK SMC switching hang
+ * SW Workaround*/
+ uint32_t crtc_index;
+ /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
+ uint32_t line_time_in_us;
+ bool invalid_vblank_time;
+
+ uint32_t display_clk;
+ /*
+ * for given display configuration if multimonitormnsync == false then
+ * Memory clock DPMS with this latency or below is allowed, DPMS with
+ * higher latency not allowed.
+ */
+ uint32_t dce_tolerable_mclk_in_active_latency;
+ uint32_t min_dcef_set_clk;
+ uint32_t min_dcef_deep_sleep_set_clk;
+};
+
+struct amd_pp_simple_clock_info {
+ uint32_t engine_max_clock;
+ uint32_t memory_max_clock;
+ uint32_t level;
+};
+
+enum PP_DAL_POWERLEVEL {
+ PP_DAL_POWERLEVEL_INVALID = 0,
+ PP_DAL_POWERLEVEL_ULTRALOW,
+ PP_DAL_POWERLEVEL_LOW,
+ PP_DAL_POWERLEVEL_NOMINAL,
+ PP_DAL_POWERLEVEL_PERFORMANCE,
+
+ PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
+ PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
+ PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
+ PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
+ PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
+ PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
+ PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
+ PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
+};
+
+struct amd_pp_clock_info {
+ uint32_t min_engine_clock;
+ uint32_t max_engine_clock;
+ uint32_t min_memory_clock;
+ uint32_t max_memory_clock;
+ uint32_t min_bus_bandwidth;
+ uint32_t max_bus_bandwidth;
+ uint32_t max_engine_clock_in_sr;
+ uint32_t min_engine_clock_in_sr;
+ enum PP_DAL_POWERLEVEL max_clocks_state;
+};
+
+enum amd_pp_clock_type {
+ amd_pp_disp_clock = 1,
+ amd_pp_sys_clock,
+ amd_pp_mem_clock,
+ amd_pp_dcef_clock,
+ amd_pp_soc_clock,
+ amd_pp_pixel_clock,
+ amd_pp_phy_clock,
+ amd_pp_dcf_clock,
+ amd_pp_dpp_clock,
+ amd_pp_f_clock = amd_pp_dcef_clock,
+};
+
+#define MAX_NUM_CLOCKS 16
+
+struct amd_pp_clocks {
+ uint32_t count;
+ uint32_t clock[MAX_NUM_CLOCKS];
+ uint32_t latency[MAX_NUM_CLOCKS];
+};
+
struct pp_clock_with_latency {
uint32_t clocks_in_khz;
uint32_t latency_in_us;
@@ -45,6 +184,11 @@
struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
};
+struct pp_display_clock_request {
+ enum amd_pp_clock_type clock_type;
+ uint32_t clock_freq_in_khz;
+};
+
#define PP_MAX_WM_SETS 4
enum pp_wm_set_id {
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index f516fd1..a6752bd 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -46,6 +46,28 @@
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
};
+struct kfd_cu_info {
+ uint32_t num_shader_engines;
+ uint32_t num_shader_arrays_per_engine;
+ uint32_t num_cu_per_sh;
+ uint32_t cu_active_number;
+ uint32_t cu_ao_mask;
+ uint32_t simd_per_cu;
+ uint32_t max_waves_per_simd;
+ uint32_t wave_front_size;
+ uint32_t max_scratch_slots_per_cu;
+ uint32_t lds_size;
+ uint32_t cu_bitmap[4][4];
+};
+
+/* For getting GPU local memory information from KGD */
+struct kfd_local_mem_info {
+ uint64_t local_mem_size_private;
+ uint64_t local_mem_size_public;
+ uint32_t vram_width;
+ uint32_t mem_clk_max;
+};
+
enum kgd_memory_pool {
KGD_POOL_SYSTEM_CACHEABLE = 1,
KGD_POOL_SYSTEM_WRITECOMBINE = 2,
@@ -106,7 +128,7 @@
*
* @free_gtt_mem: Frees a buffer that was allocated on the gart aperture
*
- * @get_vmem_size: Retrieves (physical) size of VRAM
+ * @get_local_mem_info: Retrieves information about GPU local memory
*
* @get_gpu_clock_counter: Retrieves GPU clock counter
*
@@ -131,6 +153,12 @@
* @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
* used only for no HWS mode.
*
+ * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
+ * Array is allocated with kmalloc, needs to be freed with kfree by caller.
+ *
+ * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
+ * Array is allocated with kmalloc, needs to be freed with kfree by caller.
+ *
* @hqd_is_occupies: Checks if a hqd slot is occupied.
*
* @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
@@ -147,6 +175,10 @@
*
* @get_tile_config: Returns GPU-specific tiling mode information
*
+ * @get_cu_info: Retrieves activated cu info
+ *
+ * @get_vram_usage: Returns current VRAM usage
+ *
* This structure contains function pointers to services that the kgd driver
* provides to amdkfd driver.
*
@@ -158,7 +190,8 @@
void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj);
- uint64_t (*get_vmem_size)(struct kgd_dev *kgd);
+ void (*get_local_mem_info)(struct kgd_dev *kgd,
+ struct kfd_local_mem_info *mem_info);
uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd);
uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd);
@@ -184,7 +217,16 @@
uint32_t wptr_shift, uint32_t wptr_mask,
struct mm_struct *mm);
- int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd);
+ int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
+ uint32_t __user *wptr, struct mm_struct *mm);
+
+ int (*hqd_dump)(struct kgd_dev *kgd,
+ uint32_t pipe_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs);
+
+ int (*hqd_sdma_dump)(struct kgd_dev *kgd,
+ uint32_t engine_id, uint32_t queue_id,
+ uint32_t (**dump)[2], uint32_t *n_regs);
bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
@@ -224,6 +266,10 @@
void (*set_scratch_backing_va)(struct kgd_dev *kgd,
uint64_t va, uint32_t vmid);
int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
+
+ void (*get_cu_info)(struct kgd_dev *kgd,
+ struct kfd_cu_info *cu_info);
+ uint64_t (*get_vram_usage)(struct kgd_dev *kgd);
};
/**
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
new file mode 100644
index 0000000..ed27626
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -0,0 +1,294 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __KGD_PP_INTERFACE_H__
+#define __KGD_PP_INTERFACE_H__
+
+extern const struct amd_ip_funcs pp_ip_funcs;
+extern const struct amd_pm_funcs pp_dpm_funcs;
+
+struct amd_vce_state {
+ /* vce clocks */
+ u32 evclk;
+ u32 ecclk;
+ /* gpu clocks */
+ u32 sclk;
+ u32 mclk;
+ u8 clk_idx;
+ u8 pstate;
+};
+
+
+enum amd_dpm_forced_level {
+ AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
+ AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
+ AMD_DPM_FORCED_LEVEL_LOW = 0x4,
+ AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
+ AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
+ AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
+ AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
+};
+
+enum amd_pm_state_type {
+ /* not used for dpm */
+ POWER_STATE_TYPE_DEFAULT,
+ POWER_STATE_TYPE_POWERSAVE,
+ /* user selectable states */
+ POWER_STATE_TYPE_BATTERY,
+ POWER_STATE_TYPE_BALANCED,
+ POWER_STATE_TYPE_PERFORMANCE,
+ /* internal states */
+ POWER_STATE_TYPE_INTERNAL_UVD,
+ POWER_STATE_TYPE_INTERNAL_UVD_SD,
+ POWER_STATE_TYPE_INTERNAL_UVD_HD,
+ POWER_STATE_TYPE_INTERNAL_UVD_HD2,
+ POWER_STATE_TYPE_INTERNAL_UVD_MVC,
+ POWER_STATE_TYPE_INTERNAL_BOOT,
+ POWER_STATE_TYPE_INTERNAL_THERMAL,
+ POWER_STATE_TYPE_INTERNAL_ACPI,
+ POWER_STATE_TYPE_INTERNAL_ULV,
+ POWER_STATE_TYPE_INTERNAL_3DPERF,
+};
+
+#define AMD_MAX_VCE_LEVELS 6
+
+enum amd_vce_level {
+ AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
+ AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
+ AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
+ AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
+ AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
+ AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
+};
+
+enum amd_pp_profile_type {
+ AMD_PP_GFX_PROFILE,
+ AMD_PP_COMPUTE_PROFILE,
+};
+
+struct amd_pp_profile {
+ enum amd_pp_profile_type type;
+ uint32_t min_sclk;
+ uint32_t min_mclk;
+ uint16_t activity_threshold;
+ uint8_t up_hyst;
+ uint8_t down_hyst;
+};
+
+enum amd_fan_ctrl_mode {
+ AMD_FAN_CTRL_NONE = 0,
+ AMD_FAN_CTRL_MANUAL = 1,
+ AMD_FAN_CTRL_AUTO = 2,
+};
+
+enum pp_clock_type {
+ PP_SCLK,
+ PP_MCLK,
+ PP_PCIE,
+};
+
+enum amd_pp_sensors {
+ AMDGPU_PP_SENSOR_GFX_SCLK = 0,
+ AMDGPU_PP_SENSOR_VDDNB,
+ AMDGPU_PP_SENSOR_VDDGFX,
+ AMDGPU_PP_SENSOR_UVD_VCLK,
+ AMDGPU_PP_SENSOR_UVD_DCLK,
+ AMDGPU_PP_SENSOR_VCE_ECCLK,
+ AMDGPU_PP_SENSOR_GPU_LOAD,
+ AMDGPU_PP_SENSOR_GFX_MCLK,
+ AMDGPU_PP_SENSOR_GPU_TEMP,
+ AMDGPU_PP_SENSOR_VCE_POWER,
+ AMDGPU_PP_SENSOR_UVD_POWER,
+ AMDGPU_PP_SENSOR_GPU_POWER,
+};
+
+enum amd_pp_task {
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
+ AMD_PP_TASK_ENABLE_USER_STATE,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ AMD_PP_TASK_COMPLETE_INIT,
+ AMD_PP_TASK_MAX
+};
+
+struct amd_pp_init {
+ struct cgs_device *device;
+ uint32_t chip_family;
+ uint32_t chip_id;
+ bool pm_en;
+ uint32_t feature_mask;
+};
+
+
+
+enum {
+ PP_GROUP_UNKNOWN = 0,
+ PP_GROUP_GFX = 1,
+ PP_GROUP_SYS,
+ PP_GROUP_MAX
+};
+
+struct pp_states_info {
+ uint32_t nums;
+ uint32_t states[16];
+};
+
+struct pp_gpu_power {
+ uint32_t vddc_power;
+ uint32_t vddci_power;
+ uint32_t max_gpu_power;
+ uint32_t average_gpu_power;
+};
+
+#define PP_GROUP_MASK 0xF0000000
+#define PP_GROUP_SHIFT 28
+
+#define PP_BLOCK_MASK 0x0FFFFF00
+#define PP_BLOCK_SHIFT 8
+
+#define PP_BLOCK_GFX_CG 0x01
+#define PP_BLOCK_GFX_MG 0x02
+#define PP_BLOCK_GFX_3D 0x04
+#define PP_BLOCK_GFX_RLC 0x08
+#define PP_BLOCK_GFX_CP 0x10
+#define PP_BLOCK_SYS_BIF 0x01
+#define PP_BLOCK_SYS_MC 0x02
+#define PP_BLOCK_SYS_ROM 0x04
+#define PP_BLOCK_SYS_DRM 0x08
+#define PP_BLOCK_SYS_HDP 0x10
+#define PP_BLOCK_SYS_SDMA 0x20
+
+#define PP_STATE_MASK 0x0000000F
+#define PP_STATE_SHIFT 0
+#define PP_STATE_SUPPORT_MASK 0x000000F0
+#define PP_STATE_SUPPORT_SHIFT 0
+
+#define PP_STATE_CG 0x01
+#define PP_STATE_LS 0x02
+#define PP_STATE_DS 0x04
+#define PP_STATE_SD 0x08
+#define PP_STATE_SUPPORT_CG 0x10
+#define PP_STATE_SUPPORT_LS 0x20
+#define PP_STATE_SUPPORT_DS 0x40
+#define PP_STATE_SUPPORT_SD 0x80
+
+#define PP_CG_MSG_ID(group, block, support, state) \
+ ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
+ (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
+
+struct seq_file;
+enum amd_pp_clock_type;
+struct amd_pp_simple_clock_info;
+struct amd_pp_display_configuration;
+struct amd_pp_clock_info;
+struct pp_display_clock_request;
+struct pp_wm_sets_with_clock_ranges_soc15;
+struct pp_clock_levels_with_voltage;
+struct pp_clock_levels_with_latency;
+struct amd_pp_clocks;
+
+struct amd_pm_funcs {
+/* export for dpm on ci and si */
+ int (*pre_set_power_state)(void *handle);
+ int (*set_power_state)(void *handle);
+ void (*post_set_power_state)(void *handle);
+ void (*display_configuration_changed)(void *handle);
+ void (*print_power_state)(void *handle, void *ps);
+ bool (*vblank_too_short)(void *handle);
+ void (*enable_bapm)(void *handle, bool enable);
+ int (*check_state_equal)(void *handle,
+ void *cps,
+ void *rps,
+ bool *equal);
+/* export for sysfs */
+ int (*get_temperature)(void *handle);
+ void (*set_fan_control_mode)(void *handle, u32 mode);
+ u32 (*get_fan_control_mode)(void *handle);
+ int (*set_fan_speed_percent)(void *handle, u32 speed);
+ int (*get_fan_speed_percent)(void *handle, u32 *speed);
+ int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
+ int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
+ int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
+ int (*get_sclk_od)(void *handle);
+ int (*set_sclk_od)(void *handle, uint32_t value);
+ int (*get_mclk_od)(void *handle);
+ int (*set_mclk_od)(void *handle, uint32_t value);
+ int (*read_sensor)(void *handle, int idx, void *value, int *size);
+ enum amd_dpm_forced_level (*get_performance_level)(void *handle);
+ enum amd_pm_state_type (*get_current_power_state)(void *handle);
+ int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
+ int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
+ int (*get_pp_table)(void *handle, char **table);
+ int (*set_pp_table)(void *handle, const char *buf, size_t size);
+ void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
+
+ int (*reset_power_profile_state)(void *handle,
+ struct amd_pp_profile *request);
+ int (*get_power_profile_state)(void *handle,
+ struct amd_pp_profile *query);
+ int (*set_power_profile_state)(void *handle,
+ struct amd_pp_profile *request);
+ int (*switch_power_profile)(void *handle,
+ enum amd_pp_profile_type type);
+/* export to amdgpu */
+ void (*powergate_uvd)(void *handle, bool gate);
+ void (*powergate_vce)(void *handle, bool gate);
+ struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
+ int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
+ void *input, void *output);
+ int (*load_firmware)(void *handle);
+ int (*wait_for_fw_loading_complete)(void *handle);
+ int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
+ int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low,
+ uint32_t virtual_addr_hi,
+ uint32_t mc_addr_low,
+ uint32_t mc_addr_hi,
+ uint32_t size);
+/* export to DC */
+ u32 (*get_sclk)(void *handle, bool low);
+ u32 (*get_mclk)(void *handle, bool low);
+ int (*display_configuration_change)(void *handle,
+ const struct amd_pp_display_configuration *input);
+ int (*get_display_power_level)(void *handle,
+ struct amd_pp_simple_clock_info *output);
+ int (*get_current_clocks)(void *handle,
+ struct amd_pp_clock_info *clocks);
+ int (*get_clock_by_type)(void *handle,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
+ int (*get_clock_by_type_with_latency)(void *handle,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_latency *clocks);
+ int (*get_clock_by_type_with_voltage)(void *handle,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks);
+ int (*set_watermarks_for_clocks_ranges)(void *handle,
+ struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+ int (*display_clock_voltage_request)(void *handle,
+ struct pp_display_clock_request *clock);
+ int (*get_display_mode_validation_clocks)(void *handle,
+ struct amd_pp_simple_clock_info *clocks);
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h b/drivers/gpu/drm/amd/include/soc15ip.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
rename to drivers/gpu/drm/amd/include/soc15ip.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h b/drivers/gpu/drm/amd/include/vega10_enum.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
rename to drivers/gpu/drm/amd/include/vega10_enum.h
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
index 2023482..717fbae 100644
--- a/drivers/gpu/drm/amd/include/vi_structs.h
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -153,6 +153,8 @@
uint32_t reserved_125;
uint32_t reserved_126;
uint32_t reserved_127;
+ uint32_t sdma_engine_id;
+ uint32_t sdma_queue_id;
};
struct vi_mqd {
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 5a56057..4c3223a 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -718,6 +718,8 @@
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
+ memset(data, 0, sizeof(*data));
+
ret = pp_check(pp_handle);
if (ret)
@@ -780,6 +782,26 @@
return size;
}
+static int amd_powerplay_reset(void *handle)
+{
+ struct pp_instance *instance = (struct pp_instance *)handle;
+ int ret;
+
+ ret = pp_check(instance);
+ if (ret)
+ return ret;
+
+ ret = pp_hw_fini(instance);
+ if (ret)
+ return ret;
+
+ ret = hwmgr_hw_init(instance);
+ if (ret)
+ return ret;
+
+ return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
+}
+
static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
struct pp_hwmgr *hwmgr;
@@ -1138,64 +1160,41 @@
return 0;
}
-const struct amd_pm_funcs pp_dpm_funcs = {
- .get_temperature = pp_dpm_get_temperature,
- .load_firmware = pp_dpm_load_fw,
- .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
- .force_performance_level = pp_dpm_force_performance_level,
- .get_performance_level = pp_dpm_get_performance_level,
- .get_current_power_state = pp_dpm_get_current_power_state,
- .get_sclk = pp_dpm_get_sclk,
- .get_mclk = pp_dpm_get_mclk,
- .powergate_vce = pp_dpm_powergate_vce,
- .powergate_uvd = pp_dpm_powergate_uvd,
- .dispatch_tasks = pp_dpm_dispatch_tasks,
- .set_fan_control_mode = pp_dpm_set_fan_control_mode,
- .get_fan_control_mode = pp_dpm_get_fan_control_mode,
- .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
- .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
- .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
- .get_pp_num_states = pp_dpm_get_pp_num_states,
- .get_pp_table = pp_dpm_get_pp_table,
- .set_pp_table = pp_dpm_set_pp_table,
- .force_clock_level = pp_dpm_force_clock_level,
- .print_clock_levels = pp_dpm_print_clock_levels,
- .get_sclk_od = pp_dpm_get_sclk_od,
- .set_sclk_od = pp_dpm_set_sclk_od,
- .get_mclk_od = pp_dpm_get_mclk_od,
- .set_mclk_od = pp_dpm_set_mclk_od,
- .read_sensor = pp_dpm_read_sensor,
- .get_vce_clock_state = pp_dpm_get_vce_clock_state,
- .reset_power_profile_state = pp_dpm_reset_power_profile_state,
- .get_power_profile_state = pp_dpm_get_power_profile_state,
- .set_power_profile_state = pp_dpm_set_power_profile_state,
- .switch_power_profile = pp_dpm_switch_power_profile,
- .set_clockgating_by_smu = pp_set_clockgating_by_smu,
-};
-
-int amd_powerplay_reset(void *handle)
+static int pp_dpm_notify_smu_memory_info(void *handle,
+ uint32_t virtual_addr_low,
+ uint32_t virtual_addr_hi,
+ uint32_t mc_addr_low,
+ uint32_t mc_addr_hi,
+ uint32_t size)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
- int ret;
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ int ret = 0;
- ret = pp_check(instance);
+ ret = pp_check(pp_handle);
+
if (ret)
return ret;
- ret = pp_hw_fini(instance);
- if (ret)
- return ret;
+ hwmgr = pp_handle->hwmgr;
- ret = hwmgr_hw_init(instance);
- if (ret)
- return ret;
+ if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
- return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
+ mutex_lock(&pp_handle->pp_lock);
+
+ ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
+ virtual_addr_hi, mc_addr_low, mc_addr_hi,
+ size);
+
+ mutex_unlock(&pp_handle->pp_lock);
+
+ return ret;
}
-/* export this function to DAL */
-
-int amd_powerplay_display_configuration_change(void *handle,
+static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
struct pp_hwmgr *hwmgr;
@@ -1214,7 +1213,7 @@
return 0;
}
-int amd_powerplay_get_display_power_level(void *handle,
+static int pp_get_display_power_level(void *handle,
struct amd_pp_simple_clock_info *output)
{
struct pp_hwmgr *hwmgr;
@@ -1237,7 +1236,7 @@
return ret;
}
-int amd_powerplay_get_current_clocks(void *handle,
+static int pp_get_current_clocks(void *handle,
struct amd_pp_clock_info *clocks)
{
struct amd_pp_simple_clock_info simple_clocks;
@@ -1291,7 +1290,7 @@
return 0;
}
-int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
+static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
@@ -1313,7 +1312,7 @@
return ret;
}
-int amd_powerplay_get_clock_by_type_with_latency(void *handle,
+static int pp_get_clock_by_type_with_latency(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
@@ -1335,7 +1334,7 @@
return ret;
}
-int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
+static int pp_get_clock_by_type_with_voltage(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks)
{
@@ -1360,7 +1359,7 @@
return ret;
}
-int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
+static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
struct pp_hwmgr *hwmgr;
@@ -1384,7 +1383,7 @@
return ret;
}
-int amd_powerplay_display_clock_voltage_request(void *handle,
+static int pp_display_clock_voltage_request(void *handle,
struct pp_display_clock_request *clock)
{
struct pp_hwmgr *hwmgr;
@@ -1407,7 +1406,7 @@
return ret;
}
-int amd_powerplay_get_display_mode_validation_clocks(void *handle,
+static int pp_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *clocks)
{
struct pp_hwmgr *hwmgr;
@@ -1433,3 +1432,48 @@
return ret;
}
+const struct amd_pm_funcs pp_dpm_funcs = {
+ .get_temperature = pp_dpm_get_temperature,
+ .load_firmware = pp_dpm_load_fw,
+ .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+ .force_performance_level = pp_dpm_force_performance_level,
+ .get_performance_level = pp_dpm_get_performance_level,
+ .get_current_power_state = pp_dpm_get_current_power_state,
+ .powergate_vce = pp_dpm_powergate_vce,
+ .powergate_uvd = pp_dpm_powergate_uvd,
+ .dispatch_tasks = pp_dpm_dispatch_tasks,
+ .set_fan_control_mode = pp_dpm_set_fan_control_mode,
+ .get_fan_control_mode = pp_dpm_get_fan_control_mode,
+ .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
+ .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
+ .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
+ .get_pp_num_states = pp_dpm_get_pp_num_states,
+ .get_pp_table = pp_dpm_get_pp_table,
+ .set_pp_table = pp_dpm_set_pp_table,
+ .force_clock_level = pp_dpm_force_clock_level,
+ .print_clock_levels = pp_dpm_print_clock_levels,
+ .get_sclk_od = pp_dpm_get_sclk_od,
+ .set_sclk_od = pp_dpm_set_sclk_od,
+ .get_mclk_od = pp_dpm_get_mclk_od,
+ .set_mclk_od = pp_dpm_set_mclk_od,
+ .read_sensor = pp_dpm_read_sensor,
+ .get_vce_clock_state = pp_dpm_get_vce_clock_state,
+ .reset_power_profile_state = pp_dpm_reset_power_profile_state,
+ .get_power_profile_state = pp_dpm_get_power_profile_state,
+ .set_power_profile_state = pp_dpm_set_power_profile_state,
+ .switch_power_profile = pp_dpm_switch_power_profile,
+ .set_clockgating_by_smu = pp_set_clockgating_by_smu,
+ .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
+/* export to DC */
+ .get_sclk = pp_dpm_get_sclk,
+ .get_mclk = pp_dpm_get_mclk,
+ .display_configuration_change = pp_display_configuration_change,
+ .get_display_power_level = pp_get_display_power_level,
+ .get_current_clocks = pp_get_current_clocks,
+ .get_clock_by_type = pp_get_clock_by_type,
+ .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
+ .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
+ .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
+ .display_clock_voltage_request = pp_display_clock_voltage_request,
+ .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
+};
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index ad1f6b5..b314d09d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -728,9 +728,6 @@
if (clock < stable_pstate_sclk)
clock = stable_pstate_sclk;
- } else {
- if (clock < hwmgr->gfx_arbiter.sclk)
- clock = hwmgr->gfx_arbiter.sclk;
}
if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
@@ -1085,14 +1082,8 @@
uint32_t num_of_active_displays = 0;
struct cgs_display_info info = {0};
- cz_ps->evclk = hwmgr->vce_arbiter.evclk;
- cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
-
cz_ps->need_dfs_bypass = true;
- cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
- hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
-
cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
@@ -1105,9 +1096,6 @@
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
- if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
- clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-
force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
|| (num_of_active_displays >= 3);
@@ -1339,22 +1327,13 @@
cz_hwmgr->vce_dpm.hard_min_clk,
PPSMC_MSG_SetEclkHardMin));
} else {
- /*Program HardMin based on the vce_arbiter.ecclk */
- if (hwmgr->vce_arbiter.ecclk == 0) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetEclkHardMin, 0);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetEclkHardMin, 0);
/* disable ECLK DPM 0. Otherwise VCE could hang if
* switching SCLK from DPM 0 to 6/7 */
- smum_send_msg_to_smc_with_parameter(hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkSoftMin, 1);
- } else {
- cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetEclkHardMin,
- cz_get_eclk_level(hwmgr,
- cz_hwmgr->vce_dpm.hard_min_clk,
- PPSMC_MSG_SetEclkHardMin));
- }
}
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
index c6ba0d6..4112a93 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
@@ -43,4 +43,4 @@
extern int pp_override_get_default_fuse_value(uint64_t key,
struct phm_fuses_default *result);
-#endif
\ No newline at end of file
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index c062844..560c1c1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -542,4 +542,4 @@
boot_values->ulDCEFClk = frequency;
return 0;
-}
\ No newline at end of file
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index a651ebcf..b49d65c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -523,8 +523,7 @@
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else
- pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
- Disregarding the excess entries... \n");
+ pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n");
pcie_table->count = pcie_count;
for (i = 0; i < pcie_count; i++) {
@@ -563,8 +562,7 @@
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else
- pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
- Disregarding the excess entries... \n");
+ pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n");
pcie_table->count = pcie_count;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index afae32e..c3e7e34 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -394,8 +394,8 @@
dep_table->entries[i].clk =
((unsigned long)table->entries[i].ucClockHigh << 16) |
le16_to_cpu(table->entries[i].usClockLow);
- dep_table->entries[i].v =
- (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
+ dep_table->entries[i].v =
+ (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
}
*ptable = dep_table;
@@ -1042,7 +1042,7 @@
static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
- int result;
+ int result = 0;
uint8_t frev, crev;
uint16_t size;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 3e0b267..569073e3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -159,7 +159,6 @@
static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
struct PP_Clocks clocks = {0};
struct pp_display_clock_request clock_req;
@@ -170,39 +169,6 @@
PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
"Attempt to set DCF Clock Failed!", return -EINVAL);
- if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||
- ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
- rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
- rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetSoftMinVcn,
- (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
- }
-
- if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
- ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetHardMinSocclkByFreq,
- hwmgr->gfx_arbiter.sclk_hard_min / 100);
- rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
- }
-
- if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
- (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetMinVideoGfxclkFreq,
- hwmgr->gfx_arbiter.gfxclk / 100);
- rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
- }
-
- if ((hwmgr->gfx_arbiter.fclk != 0) &&
- (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetMinVideoFclkFreq,
- hwmgr->gfx_arbiter.fclk / 100);
- rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
- }
-
return 0;
}
@@ -518,17 +484,161 @@
static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
+ if (hwmgr->smu_version < 0x1E3700) {
+ pr_info("smu firmware version too old, can not set dpm level\n");
+ return 0;
+ }
+
+ switch (level) {
+ case AMD_DPM_FORCED_LEVEL_HIGH:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinSocclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinVcn,
+ RAVEN_UMD_PSTATE_VCE);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxSocclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxVcn,
+ RAVEN_UMD_PSTATE_VCE);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinSocclkByFreq,
+ RAVEN_UMD_PSTATE_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinVcn,
+ RAVEN_UMD_PSTATE_VCE);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxSocclkByFreq,
+ RAVEN_UMD_PSTATE_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxVcn,
+ RAVEN_UMD_PSTATE_VCE);
+ break;
+ case AMD_DPM_FORCED_LEVEL_AUTO:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinSocclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinVcn,
+ RAVEN_UMD_PSTATE_MIN_VCE);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxSocclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxVcn,
+ RAVEN_UMD_PSTATE_VCE);
+ break;
+ case AMD_DPM_FORCED_LEVEL_LOW:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ break;
+ case AMD_DPM_FORCED_LEVEL_MANUAL:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ default:
+ break;
+ }
return 0;
}
static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
- return 0;
+ struct rv_hwmgr *data;
+
+ if (hwmgr == NULL)
+ return -EINVAL;
+
+ data = (struct rv_hwmgr *)(hwmgr->backend);
+
+ if (low)
+ return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
+ else
+ return data->clock_vol_info.vdd_dep_on_fclk->entries[
+ data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
}
static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
- return 0;
+ struct rv_hwmgr *data;
+
+ if (hwmgr == NULL)
+ return -EINVAL;
+
+ data = (struct rv_hwmgr *)(hwmgr->backend);
+
+ if (low)
+ return data->gfx_min_freq_limit;
+ else
+ return data->gfx_max_freq_limit;
}
static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 9dc5030..c3bc311 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -304,4 +304,19 @@
int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
+/* UMD PState Raven Msg Parameters in MHz */
+#define RAVEN_UMD_PSTATE_GFXCLK 700
+#define RAVEN_UMD_PSTATE_SOCCLK 626
+#define RAVEN_UMD_PSTATE_FCLK 933
+#define RAVEN_UMD_PSTATE_VCE 0x03C00320
+
+#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100
+#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757
+#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200
+
+#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200
+#define RAVEN_UMD_PSTATE_MIN_FCLK 400
+#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200
+#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
index 9a01493..ae59a3f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
@@ -25,17 +25,17 @@
#define RAVEN_INC_H
-#include "asic_reg/raven1/MP/mp_10_0_default.h"
-#include "asic_reg/raven1/MP/mp_10_0_offset.h"
-#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h"
+#include "asic_reg/mp/mp_10_0_default.h"
+#include "asic_reg/mp/mp_10_0_offset.h"
+#include "asic_reg/mp/mp_10_0_sh_mask.h"
-#include "asic_reg/raven1/NBIO/nbio_7_0_default.h"
-#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h"
-#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h"
+#include "asic_reg/nbio/nbio_7_0_default.h"
+#include "asic_reg/nbio/nbio_7_0_offset.h"
+#include "asic_reg/nbio/nbio_7_0_sh_mask.h"
-#include "asic_reg/raven1/THM/thm_10_0_default.h"
-#include "asic_reg/raven1/THM/thm_10_0_offset.h"
-#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h"
+#include "asic_reg/thm/thm_10_0_default.h"
+#include "asic_reg/thm/thm_10_0_offset.h"
+#include "asic_reg/thm/thm_10_0_sh_mask.h"
#define ixDDI_PHY_GEN_STATUS 0x3FCE8
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6688cdb..08e8a79 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2722,9 +2722,6 @@
}
}
- smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
- smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
-
cgs_get_active_displays_info(hwmgr->device, &info);
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
@@ -2754,38 +2751,6 @@
minimum_clocks.memoryClock = stable_pstate_mclk;
}
- if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
- minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
-
- if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
- minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-
- smu7_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-
- if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
- hwmgr->platform_descriptor.overdriveLimit.engineClock),
- "Overdrive sclk exceeds limit",
- hwmgr->gfx_arbiter.sclk_over_drive =
- hwmgr->platform_descriptor.overdriveLimit.engineClock);
-
- if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
- smu7_ps->performance_levels[1].engine_clock =
- hwmgr->gfx_arbiter.sclk_over_drive;
- }
-
- if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
- hwmgr->platform_descriptor.overdriveLimit.memoryClock),
- "Overdrive mclk exceeds limit",
- hwmgr->gfx_arbiter.mclk_over_drive =
- hwmgr->platform_descriptor.overdriveLimit.memoryClock);
-
- if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
- smu7_ps->performance_levels[1].memory_clock =
- hwmgr->gfx_arbiter.mclk_over_drive;
- }
-
disable_mclk_switching_for_frame_lock = phm_cap_enabled(
hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
@@ -4342,9 +4307,9 @@
for (i = 0; i < pcie_table->count; i++)
size += sprintf(buf + size, "%d: %s %s\n", i,
- (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
- (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
- (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
+ (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
+ (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
+ (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
(i == now) ? "*" : "");
break;
default:
@@ -4682,6 +4647,25 @@
return 0;
}
+static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
+ struct amd_pp_simple_clock_info *clocks)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
+ struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
+
+ if (clocks == NULL)
+ return -EINVAL;
+
+ clocks->memory_max_clock = mclk_table->count > 1 ?
+ mclk_table->dpm_levels[mclk_table->count-1].value :
+ mclk_table->dpm_levels[0].value;
+ clocks->engine_max_clock = sclk_table->count > 1 ?
+ sclk_table->dpm_levels[sclk_table->count-1].value :
+ sclk_table->dpm_levels[0].value;
+ return 0;
+}
+
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4734,6 +4718,7 @@
.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
.start_thermal_controller = smu7_start_thermal_controller,
.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
+ .get_max_high_clocks = smu7_get_max_high_clocks,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 9acbefb..5f9c3ef 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -426,9 +426,9 @@
data->smu_features[GNLD_VR0HOT].supported = true;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
- vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
+ vega10_read_arg_from_smc(hwmgr, &(hwmgr->smu_version));
/* ACG firmware has major version 5 */
- if ((data->smu_version & 0xff000000) == 0x5000000)
+ if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true;
if (data->registry_data.didt_support)
@@ -546,8 +546,7 @@
}
if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
- pr_info("Voltage value looks like a Leakage ID \
- but it's not patched\n");
+ pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
}
/**
@@ -701,18 +700,14 @@
table_info->vdd_dep_on_mclk;
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
- "VDD dependency on SCLK table is missing. \
- This table is mandatory", return -EINVAL);
+ "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
- "VDD dependency on SCLK table is empty. \
- This table is mandatory", return -EINVAL);
+ "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
- "VDD dependency on MCLK table is missing. \
- This table is mandatory", return -EINVAL);
+ "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
- "VDD dependency on MCLK table is empty. \
- This table is mandatory", return -EINVAL);
+ "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL);
table_info->max_clock_voltage_on_ac.sclk =
allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
@@ -2884,8 +2879,8 @@
"DPM is already running right , skipping re-enablement!",
return 0);
- if ((data->smu_version == 0x001c2c00) ||
- (data->smu_version == 0x001c2d00)) {
+ if ((hwmgr->smu_version == 0x001c2c00) ||
+ (hwmgr->smu_version == 0x001c2d00)) {
tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
PP_ASSERT_WITH_CODE(!tmp_result,
@@ -3129,9 +3124,6 @@
}
}
- vega10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
- vega10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
-
cgs_get_active_displays_info(hwmgr->device, &info);
/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
@@ -3170,38 +3162,6 @@
minimum_clocks.memoryClock = stable_pstate_mclk;
}
- if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
- minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
-
- if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
- minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-
- vega10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-
- if (hwmgr->gfx_arbiter.sclk_over_drive) {
- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
- hwmgr->platform_descriptor.overdriveLimit.engineClock),
- "Overdrive sclk exceeds limit",
- hwmgr->gfx_arbiter.sclk_over_drive =
- hwmgr->platform_descriptor.overdriveLimit.engineClock);
-
- if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
- vega10_ps->performance_levels[1].gfx_clock =
- hwmgr->gfx_arbiter.sclk_over_drive;
- }
-
- if (hwmgr->gfx_arbiter.mclk_over_drive) {
- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
- hwmgr->platform_descriptor.overdriveLimit.memoryClock),
- "Overdrive mclk exceeds limit",
- hwmgr->gfx_arbiter.mclk_over_drive =
- hwmgr->platform_descriptor.overdriveLimit.memoryClock);
-
- if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
- vega10_ps->performance_levels[1].mem_clock =
- hwmgr->gfx_arbiter.mclk_over_drive;
- }
-
disable_mclk_switching_for_frame_lock = phm_cap_enabled(
hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
@@ -3419,8 +3379,7 @@
DPMTABLE_OD_UPDATE_SCLK)) {
result = vega10_populate_all_graphic_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
- "Failed to populate SCLK during \
- PopulateNewDPMClocksStates Function!",
+ "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
return result);
}
@@ -3429,8 +3388,7 @@
DPMTABLE_OD_UPDATE_MCLK)){
result = vega10_populate_all_memory_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
- "Failed to populate MCLK during \
- PopulateNewDPMClocksStates Function!",
+ "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
return result);
}
} else {
@@ -3547,8 +3505,7 @@
data->apply_optimized_settings) {
result = vega10_populate_all_graphic_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
- "Failed to populate SCLK during \
- PopulateNewDPMClocksStates Function!",
+ "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
return result);
}
@@ -3556,8 +3513,7 @@
(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
result = vega10_populate_all_memory_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
- "Failed to populate MCLK during \
- PopulateNewDPMClocksStates Function!",
+ "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
return result);
}
}
@@ -3831,10 +3787,7 @@
uint32_t low_sclk_interrupt_threshold = 0;
if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
- (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
+ (data->low_sclk_interrupt_threshold != 0)) {
low_sclk_interrupt_threshold =
data->low_sclk_interrupt_threshold;
@@ -4657,9 +4610,9 @@
for (i = 0; i < pcie_table->count; i++)
size += sprintf(buf + size, "%d: %s %s\n", i,
- (pcie_table->pcie_gen[i] == 0) ? "2.5GB, x1" :
- (pcie_table->pcie_gen[i] == 1) ? "5.0GB, x16" :
- (pcie_table->pcie_gen[i] == 2) ? "8.0GB, x16" : "",
+ (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
+ (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
+ (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
(i == now) ? "*" : "");
break;
default:
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 8f7358c..e8507ff 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -387,7 +387,6 @@
struct vega10_smc_state_table smc_state_table;
uint32_t config_telemetry;
- uint32_t smu_version;
uint32_t acg_loop_state;
uint32_t mem_channels;
};
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
index 8c55eaa..faf7ac0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
@@ -24,21 +24,20 @@
#ifndef VEGA10_INC_H
#define VEGA10_INC_H
-#include "asic_reg/vega10/THM/thm_9_0_default.h"
-#include "asic_reg/vega10/THM/thm_9_0_offset.h"
-#include "asic_reg/vega10/THM/thm_9_0_sh_mask.h"
+#include "asic_reg/thm/thm_9_0_default.h"
+#include "asic_reg/thm/thm_9_0_offset.h"
+#include "asic_reg/thm/thm_9_0_sh_mask.h"
-#include "asic_reg/vega10/MP/mp_9_0_default.h"
-#include "asic_reg/vega10/MP/mp_9_0_offset.h"
-#include "asic_reg/vega10/MP/mp_9_0_sh_mask.h"
+#include "asic_reg/mp/mp_9_0_offset.h"
+#include "asic_reg/mp/mp_9_0_sh_mask.h"
-#include "asic_reg/vega10/GC/gc_9_0_default.h"
-#include "asic_reg/vega10/GC/gc_9_0_offset.h"
-#include "asic_reg/vega10/GC/gc_9_0_sh_mask.h"
+#include "asic_reg/gc/gc_9_0_default.h"
+#include "asic_reg/gc/gc_9_0_offset.h"
+#include "asic_reg/gc/gc_9_0_sh_mask.h"
-#include "asic_reg/vega10/NBIO/nbio_6_1_default.h"
-#include "asic_reg/vega10/NBIO/nbio_6_1_offset.h"
-#include "asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h"
+#include "asic_reg/nbio/nbio_6_1_default.h"
+#include "asic_reg/nbio/nbio_6_1_offset.h"
+#include "asic_reg/nbio/nbio_6_1_sh_mask.h"
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 95932cc..152e70d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -29,280 +29,7 @@
#include "amd_shared.h"
#include "cgs_common.h"
#include "dm_pp_interface.h"
-
-extern const struct amd_ip_funcs pp_ip_funcs;
-extern const struct amd_pm_funcs pp_dpm_funcs;
-
-enum amd_pp_sensors {
- AMDGPU_PP_SENSOR_GFX_SCLK = 0,
- AMDGPU_PP_SENSOR_VDDNB,
- AMDGPU_PP_SENSOR_VDDGFX,
- AMDGPU_PP_SENSOR_UVD_VCLK,
- AMDGPU_PP_SENSOR_UVD_DCLK,
- AMDGPU_PP_SENSOR_VCE_ECCLK,
- AMDGPU_PP_SENSOR_GPU_LOAD,
- AMDGPU_PP_SENSOR_GFX_MCLK,
- AMDGPU_PP_SENSOR_GPU_TEMP,
- AMDGPU_PP_SENSOR_VCE_POWER,
- AMDGPU_PP_SENSOR_UVD_POWER,
- AMDGPU_PP_SENSOR_GPU_POWER,
-};
-
-enum amd_pp_task {
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
- AMD_PP_TASK_ENABLE_USER_STATE,
- AMD_PP_TASK_READJUST_POWER_STATE,
- AMD_PP_TASK_COMPLETE_INIT,
- AMD_PP_TASK_MAX
-};
-
-struct amd_pp_init {
- struct cgs_device *device;
- uint32_t chip_family;
- uint32_t chip_id;
- bool pm_en;
- uint32_t feature_mask;
-};
-
-enum amd_pp_display_config_type{
- AMD_PP_DisplayConfigType_None = 0,
- AMD_PP_DisplayConfigType_DP54 ,
- AMD_PP_DisplayConfigType_DP432 ,
- AMD_PP_DisplayConfigType_DP324 ,
- AMD_PP_DisplayConfigType_DP27,
- AMD_PP_DisplayConfigType_DP243,
- AMD_PP_DisplayConfigType_DP216,
- AMD_PP_DisplayConfigType_DP162,
- AMD_PP_DisplayConfigType_HDMI6G ,
- AMD_PP_DisplayConfigType_HDMI297 ,
- AMD_PP_DisplayConfigType_HDMI162,
- AMD_PP_DisplayConfigType_LVDS,
- AMD_PP_DisplayConfigType_DVI,
- AMD_PP_DisplayConfigType_WIRELESS,
- AMD_PP_DisplayConfigType_VGA
-};
-
-struct single_display_configuration
-{
- uint32_t controller_index;
- uint32_t controller_id;
- uint32_t signal_type;
- uint32_t display_state;
- /* phy id for the primary internal transmitter */
- uint8_t primary_transmitter_phyi_d;
- /* bitmap with the active lanes */
- uint8_t primary_transmitter_active_lanemap;
- /* phy id for the secondary internal transmitter (for dual-link dvi) */
- uint8_t secondary_transmitter_phy_id;
- /* bitmap with the active lanes */
- uint8_t secondary_transmitter_active_lanemap;
- /* misc phy settings for SMU. */
- uint32_t config_flags;
- uint32_t display_type;
- uint32_t view_resolution_cx;
- uint32_t view_resolution_cy;
- enum amd_pp_display_config_type displayconfigtype;
- uint32_t vertical_refresh; /* for active display */
-};
-
-#define MAX_NUM_DISPLAY 32
-
-struct amd_pp_display_configuration {
- bool nb_pstate_switch_disable;/* controls NB PState switch */
- bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
- bool cpu_pstate_disable;
- uint32_t cpu_pstate_separation_time;
-
- uint32_t num_display; /* total number of display*/
- uint32_t num_path_including_non_display;
- uint32_t crossfire_display_index;
- uint32_t min_mem_set_clock;
- uint32_t min_core_set_clock;
- /* unit 10KHz x bit*/
- uint32_t min_bus_bandwidth;
- /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
- uint32_t min_core_set_clock_in_sr;
-
- struct single_display_configuration displays[MAX_NUM_DISPLAY];
-
- uint32_t vrefresh; /* for active display*/
-
- uint32_t min_vblank_time; /* for active display*/
- bool multi_monitor_in_sync;
- /* Controller Index of primary display - used in MCLK SMC switching hang
- * SW Workaround*/
- uint32_t crtc_index;
- /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
- uint32_t line_time_in_us;
- bool invalid_vblank_time;
-
- uint32_t display_clk;
- /*
- * for given display configuration if multimonitormnsync == false then
- * Memory clock DPMS with this latency or below is allowed, DPMS with
- * higher latency not allowed.
- */
- uint32_t dce_tolerable_mclk_in_active_latency;
- uint32_t min_dcef_set_clk;
- uint32_t min_dcef_deep_sleep_set_clk;
-};
-
-struct amd_pp_simple_clock_info {
- uint32_t engine_max_clock;
- uint32_t memory_max_clock;
- uint32_t level;
-};
-
-enum PP_DAL_POWERLEVEL {
- PP_DAL_POWERLEVEL_INVALID = 0,
- PP_DAL_POWERLEVEL_ULTRALOW,
- PP_DAL_POWERLEVEL_LOW,
- PP_DAL_POWERLEVEL_NOMINAL,
- PP_DAL_POWERLEVEL_PERFORMANCE,
-
- PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
- PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
- PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
- PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
- PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
- PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
- PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
- PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-};
-
-struct amd_pp_clock_info {
- uint32_t min_engine_clock;
- uint32_t max_engine_clock;
- uint32_t min_memory_clock;
- uint32_t max_memory_clock;
- uint32_t min_bus_bandwidth;
- uint32_t max_bus_bandwidth;
- uint32_t max_engine_clock_in_sr;
- uint32_t min_engine_clock_in_sr;
- enum PP_DAL_POWERLEVEL max_clocks_state;
-};
-
-enum amd_pp_clock_type {
- amd_pp_disp_clock = 1,
- amd_pp_sys_clock,
- amd_pp_mem_clock,
- amd_pp_dcef_clock,
- amd_pp_soc_clock,
- amd_pp_pixel_clock,
- amd_pp_phy_clock,
- amd_pp_dcf_clock,
- amd_pp_dpp_clock,
- amd_pp_f_clock = amd_pp_dcef_clock,
-};
-
-#define MAX_NUM_CLOCKS 16
-
-struct amd_pp_clocks {
- uint32_t count;
- uint32_t clock[MAX_NUM_CLOCKS];
- uint32_t latency[MAX_NUM_CLOCKS];
-};
-
-
-enum {
- PP_GROUP_UNKNOWN = 0,
- PP_GROUP_GFX = 1,
- PP_GROUP_SYS,
- PP_GROUP_MAX
-};
-
-struct pp_states_info {
- uint32_t nums;
- uint32_t states[16];
-};
-
-struct pp_gpu_power {
- uint32_t vddc_power;
- uint32_t vddci_power;
- uint32_t max_gpu_power;
- uint32_t average_gpu_power;
-};
-
-struct pp_display_clock_request {
- enum amd_pp_clock_type clock_type;
- uint32_t clock_freq_in_khz;
-};
-
-#define PP_GROUP_MASK 0xF0000000
-#define PP_GROUP_SHIFT 28
-
-#define PP_BLOCK_MASK 0x0FFFFF00
-#define PP_BLOCK_SHIFT 8
-
-#define PP_BLOCK_GFX_CG 0x01
-#define PP_BLOCK_GFX_MG 0x02
-#define PP_BLOCK_GFX_3D 0x04
-#define PP_BLOCK_GFX_RLC 0x08
-#define PP_BLOCK_GFX_CP 0x10
-#define PP_BLOCK_SYS_BIF 0x01
-#define PP_BLOCK_SYS_MC 0x02
-#define PP_BLOCK_SYS_ROM 0x04
-#define PP_BLOCK_SYS_DRM 0x08
-#define PP_BLOCK_SYS_HDP 0x10
-#define PP_BLOCK_SYS_SDMA 0x20
-
-#define PP_STATE_MASK 0x0000000F
-#define PP_STATE_SHIFT 0
-#define PP_STATE_SUPPORT_MASK 0x000000F0
-#define PP_STATE_SUPPORT_SHIFT 0
-
-#define PP_STATE_CG 0x01
-#define PP_STATE_LS 0x02
-#define PP_STATE_DS 0x04
-#define PP_STATE_SD 0x08
-#define PP_STATE_SUPPORT_CG 0x10
-#define PP_STATE_SUPPORT_LS 0x20
-#define PP_STATE_SUPPORT_DS 0x40
-#define PP_STATE_SUPPORT_SD 0x80
-
-#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
- block << PP_BLOCK_SHIFT |\
- support << PP_STATE_SUPPORT_SHIFT |\
- state << PP_STATE_SHIFT)
-
-struct amd_powerplay {
- struct cgs_device *cgs_device;
- void *pp_handle;
- const struct amd_ip_funcs *ip_funcs;
- const struct amd_pm_funcs *pp_funcs;
-};
-
-int amd_powerplay_reset(void *handle);
-
-int amd_powerplay_display_configuration_change(void *handle,
- const struct amd_pp_display_configuration *input);
-
-int amd_powerplay_get_display_power_level(void *handle,
- struct amd_pp_simple_clock_info *output);
-
-int amd_powerplay_get_current_clocks(void *handle,
- struct amd_pp_clock_info *output);
-
-int amd_powerplay_get_clock_by_type(void *handle,
- enum amd_pp_clock_type type,
- struct amd_pp_clocks *clocks);
-
-int amd_powerplay_get_clock_by_type_with_latency(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_latency *clocks);
-
-int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_voltage *clocks);
-
-int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
-
-int amd_powerplay_display_clock_voltage_request(void *handle,
- struct pp_display_clock_request *clock);
-
-int amd_powerplay_get_display_mode_validation_clocks(void *handle,
- struct amd_pp_simple_clock_info *output);
+#include "kgd_pp_interface.h"
#endif /* _AMD_POWERPLAY_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 004a40e..565fe08 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -105,36 +105,6 @@
const struct pp_hw_power_state *pnew_state;
};
-struct phm_acp_arbiter {
- uint32_t acpclk;
-};
-
-struct phm_uvd_arbiter {
- uint32_t vclk;
- uint32_t dclk;
- uint32_t vclk_ceiling;
- uint32_t dclk_ceiling;
- uint32_t vclk_soft_min;
- uint32_t dclk_soft_min;
-};
-
-struct phm_vce_arbiter {
- uint32_t evclk;
- uint32_t ecclk;
-};
-
-struct phm_gfx_arbiter {
- uint32_t sclk;
- uint32_t sclk_hard_min;
- uint32_t mclk;
- uint32_t sclk_over_drive;
- uint32_t mclk_over_drive;
- uint32_t sclk_threshold;
- uint32_t num_cus;
- uint32_t gfxclk;
- uint32_t fclk;
-};
-
struct phm_clock_array {
uint32_t count;
uint32_t values[1];
@@ -722,6 +692,7 @@
struct pp_hwmgr {
uint32_t chip_family;
uint32_t chip_id;
+ uint32_t smu_version;
uint32_t pp_table_version;
void *device;
@@ -737,10 +708,6 @@
enum amd_dpm_forced_level dpm_level;
enum amd_dpm_forced_level saved_dpm_level;
enum amd_dpm_forced_level request_dpm_level;
- struct phm_gfx_arbiter gfx_arbiter;
- struct phm_acp_arbiter acp_arbiter;
- struct phm_uvd_arbiter uvd_arbiter;
- struct phm_vce_arbiter vce_arbiter;
uint32_t usec_timeout;
void *pptable;
struct phm_platform_descriptor platform_descriptor;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
index a511611..b7ab69e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
@@ -23,7 +23,7 @@
#ifndef PP_SOC15_H
#define PP_SOC15_H
-#include "vega10/soc15ip.h"
+#include "soc15ip.h"
inline static uint32_t soc15_get_register_offset(
uint32_t hw_id,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 2b34971..f15f4df 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -75,7 +75,12 @@
#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
#define PPSMC_MSG_SoftReset 0x2E
-#define PPSMC_Message_Count 0x2F
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x30
+#define PPSMC_MSG_SetHardMinGfxClk 0x31
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32
+#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33
+#define PPSMC_MSG_SetSoftMaxVcn 0x34
+#define PPSMC_Message_Count 0x35
typedef uint16_t PPSMC_Result;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 4d672cd..0b4a556 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -1732,8 +1732,7 @@
if (0 != result) {
smu_data->smc_state_table.GraphicsBootLevel = 0;
- pr_err("VBIOS did not find boot engine clock value \
- in dependency table. Using Graphics DPM level 0!");
+ pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
result = 0;
}
@@ -1743,8 +1742,7 @@
if (0 != result) {
smu_data->smc_state_table.MemoryBootLevel = 0;
- pr_err("VBIOS did not find boot engine clock value \
- in dependency table. Using Memory DPM level 0!");
+ pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
result = 0;
}
@@ -2220,10 +2218,7 @@
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
+ && (data->low_sclk_interrupt_threshold != 0)) {
low_sclk_interrupt_threshold =
data->low_sclk_interrupt_threshold;
@@ -2321,6 +2316,7 @@
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
hwmgr->is_kicker = info.is_kicker;
+ hwmgr->smu_version = info.version;
byte_count = info.image_size;
src = (uint8_t *)info.kptr;
start_addr = info.ucode_start_address;
@@ -2602,9 +2598,9 @@
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
}
j++;
+
PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
"Invalid VramInfo table.", return -EINVAL);
-
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
@@ -2617,10 +2613,10 @@
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
+ if (!data->is_memory_gddr5) {
+ PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
for (k = 0; k < table->num_entries; k++) {
@@ -2628,8 +2624,6 @@
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
}
break;
@@ -2644,8 +2638,6 @@
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
break;
default:
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 78ab055..4d3aff3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -709,6 +709,19 @@
{
int ret = 0;
uint32_t fw_to_check = 0;
+ struct cgs_firmware_info info = {0};
+ uint32_t index = SMN_MP1_SRAM_START_ADDR +
+ SMU8_FIRMWARE_HEADER_LOCATION +
+ offsetof(struct SMU8_Firmware_Header, Version);
+
+
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
+ hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
+ info.version = hwmgr->smu_version >> 8;
+ cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
fw_to_check = UCODE_ID_RLC_G_MASK |
UCODE_ID_SDMA0_MASK |
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index f572bef..085d81c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -2385,10 +2385,7 @@
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
+ && (data->low_sclk_interrupt_threshold != 0)) {
low_sclk_interrupt_threshold =
data->low_sclk_interrupt_threshold;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 3412882..1253126 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -204,7 +204,7 @@
pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
return -EINVAL;
}
-
+ hwmgr->smu_version = info.version;
/* wait for smc boot up */
PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
@@ -911,8 +911,7 @@
hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
&graphic_level->MinVddc);
PP_ASSERT_WITH_CODE((0 == result),
- "can not find VDDC voltage value for VDDC \
- engine clock dependency table", return result);
+ "can not find VDDC voltage value for VDDC engine clock dependency table", return result);
/* SCLK frequency in units of 10KHz*/
graphic_level->SclkFrequency = engine_clock;
@@ -1678,8 +1677,7 @@
if (0 != result) {
smu_data->smc_state_table.GraphicsBootLevel = 0;
- pr_err("VBIOS did not find boot engine clock value \
- in dependency table. Using Graphics DPM level 0!");
+ pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
result = 0;
}
@@ -1689,8 +1687,7 @@
if (0 != result) {
smu_data->smc_state_table.MemoryBootLevel = 0;
- pr_err("VBIOS did not find boot engine clock value \
- in dependency table. Using Memory DPM level 0!");
+ pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
result = 0;
}
@@ -2205,10 +2202,7 @@
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
+ && (data->low_sclk_interrupt_threshold != 0)) {
low_sclk_interrupt_threshold =
data->low_sclk_interrupt_threshold;
@@ -2552,9 +2546,9 @@
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
}
j++;
+
PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
"Invalid VramInfo table.", return -EINVAL);
-
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
@@ -2568,10 +2562,10 @@
}
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
+ if (!data->is_memory_gddr5) {
+ PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
for (k = 0; k < table->num_entries; k++) {
@@ -2579,8 +2573,6 @@
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
}
break;
@@ -2595,8 +2587,6 @@
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
break;
default:
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index bd6be77..cdb4765 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -2369,10 +2369,7 @@
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
+ && (data->low_sclk_interrupt_threshold != 0)) {
low_sclk_interrupt_threshold =
data->low_sclk_interrupt_threshold;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index b98ade6..2d662b4 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -305,6 +305,14 @@
static int rv_start_smu(struct pp_hwmgr *hwmgr)
{
+ struct cgs_firmware_info info = {0};
+
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
+ rv_read_arg_from_smc(hwmgr, &hwmgr->smu_version);
+ info.version = hwmgr->smu_version >> 8;
+
+ cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+
if (rv_verify_smc_interface(hwmgr))
return -EINVAL;
if (rv_smc_enable_sdma(hwmgr))
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 7f5359a..311ff37 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -535,7 +535,7 @@
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
hwmgr->is_kicker = info.is_kicker;
-
+ hwmgr->smu_version = info.version;
result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
return result;
@@ -648,6 +648,12 @@
int smu7_smu_fini(struct pp_hwmgr *hwmgr)
{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ smu_free_memory(hwmgr->device, (void *) smu_data->header_buffer.handle);
+ if (!cgs_is_virtualization_enabled(hwmgr->device))
+ smu_free_memory(hwmgr->device, (void *) smu_data->smu_buffer.handle);
+
kfree(hwmgr->smu_backend);
hwmgr->smu_backend = NULL;
cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index b7f1813..f5b3de29 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -2654,10 +2654,7 @@
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
+ && (data->low_sclk_interrupt_threshold != 0)) {
low_sclk_interrupt_threshold =
data->low_sclk_interrupt_threshold;
@@ -3106,9 +3103,9 @@
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
}
j++;
+
PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
"Invalid VramInfo table.", return -EINVAL);
-
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
@@ -3121,18 +3118,16 @@
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
if (!data->is_memory_gddr5) {
+ PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
for (k = 0; k < table->num_entries; k++)
table->mc_reg_table_entry[k].mc_data[j] =
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
j++;
- PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
}
break;
@@ -3147,8 +3142,6 @@
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
}
j++;
- PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
break;
default:
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 2f979fb..f6f39d0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -381,10 +381,8 @@
(rev_id == 0xc1) ||
(rev_id == 0xc3)))) {
if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
- pr_err("Your firmware(0x%x) doesn't match \
- SMU9_DRIVER_IF_VERSION(0x%x). \
- Please update your firmware!\n",
- smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
+ pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
+ smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
return -EINVAL;
}
}
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
deleted file mode 100644
index b590fcc..0000000
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _GPU_SCHEDULER_H_
-#define _GPU_SCHEDULER_H_
-
-#include <linux/kfifo.h>
-#include <linux/dma-fence.h>
-#include "spsc_queue.h"
-
-struct amd_gpu_scheduler;
-struct amd_sched_rq;
-
-enum amd_sched_priority {
- AMD_SCHED_PRIORITY_MIN,
- AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN,
- AMD_SCHED_PRIORITY_NORMAL,
- AMD_SCHED_PRIORITY_HIGH_SW,
- AMD_SCHED_PRIORITY_HIGH_HW,
- AMD_SCHED_PRIORITY_KERNEL,
- AMD_SCHED_PRIORITY_MAX,
- AMD_SCHED_PRIORITY_INVALID = -1,
- AMD_SCHED_PRIORITY_UNSET = -2
-};
-
-
-/**
- * A scheduler entity is a wrapper around a job queue or a group
- * of other entities. Entities take turns emitting jobs from their
- * job queues to corresponding hardware ring based on scheduling
- * policy.
-*/
-struct amd_sched_entity {
- struct list_head list;
- struct amd_sched_rq *rq;
- spinlock_t rq_lock;
- struct amd_gpu_scheduler *sched;
-
- spinlock_t queue_lock;
- struct spsc_queue job_queue;
-
- atomic_t fence_seq;
- uint64_t fence_context;
-
- struct dma_fence *dependency;
- struct dma_fence_cb cb;
- atomic_t *guilty; /* points to ctx's guilty */
-};
-
-/**
- * Run queue is a set of entities scheduling command submissions for
- * one specific ring. It implements the scheduling policy that selects
- * the next entity to emit commands from.
-*/
-struct amd_sched_rq {
- spinlock_t lock;
- struct list_head entities;
- struct amd_sched_entity *current_entity;
-};
-
-struct amd_sched_fence {
- struct dma_fence scheduled;
- struct dma_fence finished;
- struct dma_fence_cb cb;
- struct dma_fence *parent;
- struct amd_gpu_scheduler *sched;
- spinlock_t lock;
- void *owner;
-};
-
-struct amd_sched_job {
- struct spsc_node queue_node;
- struct amd_gpu_scheduler *sched;
- struct amd_sched_fence *s_fence;
- struct dma_fence_cb finish_cb;
- struct work_struct finish_work;
- struct list_head node;
- struct delayed_work work_tdr;
- uint64_t id;
- atomic_t karma;
- enum amd_sched_priority s_priority;
-};
-
-extern const struct dma_fence_ops amd_sched_fence_ops_scheduled;
-extern const struct dma_fence_ops amd_sched_fence_ops_finished;
-static inline struct amd_sched_fence *to_amd_sched_fence(struct dma_fence *f)
-{
- if (f->ops == &amd_sched_fence_ops_scheduled)
- return container_of(f, struct amd_sched_fence, scheduled);
-
- if (f->ops == &amd_sched_fence_ops_finished)
- return container_of(f, struct amd_sched_fence, finished);
-
- return NULL;
-}
-
-static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int threshold)
-{
- return (s_job && atomic_inc_return(&s_job->karma) > threshold);
-}
-
-/**
- * Define the backend operations called by the scheduler,
- * these functions should be implemented in driver side
-*/
-struct amd_sched_backend_ops {
- struct dma_fence *(*dependency)(struct amd_sched_job *sched_job,
- struct amd_sched_entity *s_entity);
- struct dma_fence *(*run_job)(struct amd_sched_job *sched_job);
- void (*timedout_job)(struct amd_sched_job *sched_job);
- void (*free_job)(struct amd_sched_job *sched_job);
-};
-
-/**
- * One scheduler is implemented for each hardware ring
-*/
-struct amd_gpu_scheduler {
- const struct amd_sched_backend_ops *ops;
- uint32_t hw_submission_limit;
- long timeout;
- const char *name;
- struct amd_sched_rq sched_rq[AMD_SCHED_PRIORITY_MAX];
- wait_queue_head_t wake_up_worker;
- wait_queue_head_t job_scheduled;
- atomic_t hw_rq_count;
- atomic64_t job_id_count;
- struct task_struct *thread;
- struct list_head ring_mirror_list;
- spinlock_t job_list_lock;
- int hang_limit;
-};
-
-int amd_sched_init(struct amd_gpu_scheduler *sched,
- const struct amd_sched_backend_ops *ops,
- uint32_t hw_submission, unsigned hang_limit, long timeout, const char *name);
-void amd_sched_fini(struct amd_gpu_scheduler *sched);
-
-int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity,
- struct amd_sched_rq *rq,
- uint32_t jobs, atomic_t* guilty);
-void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity);
-void amd_sched_entity_push_job(struct amd_sched_job *sched_job,
- struct amd_sched_entity *entity);
-void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
- struct amd_sched_rq *rq);
-
-int amd_sched_fence_slab_init(void);
-void amd_sched_fence_slab_fini(void);
-
-struct amd_sched_fence *amd_sched_fence_create(
- struct amd_sched_entity *s_entity, void *owner);
-void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
-void amd_sched_fence_finished(struct amd_sched_fence *fence);
-int amd_sched_job_init(struct amd_sched_job *job,
- struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity,
- void *owner);
-void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *job);
-void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
-bool amd_sched_dependency_optimized(struct dma_fence* fence,
- struct amd_sched_entity *entity);
-void amd_sched_job_kickout(struct amd_sched_job *s_job);
-
-#endif
diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c
deleted file mode 100644
index 33f54d0..0000000
--- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- *
- */
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/sched.h>
-#include <drm/drmP.h>
-#include "gpu_scheduler.h"
-
-static struct kmem_cache *sched_fence_slab;
-
-int amd_sched_fence_slab_init(void)
-{
- sched_fence_slab = kmem_cache_create(
- "amd_sched_fence", sizeof(struct amd_sched_fence), 0,
- SLAB_HWCACHE_ALIGN, NULL);
- if (!sched_fence_slab)
- return -ENOMEM;
-
- return 0;
-}
-
-void amd_sched_fence_slab_fini(void)
-{
- rcu_barrier();
- kmem_cache_destroy(sched_fence_slab);
-}
-
-struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity,
- void *owner)
-{
- struct amd_sched_fence *fence = NULL;
- unsigned seq;
-
- fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL);
- if (fence == NULL)
- return NULL;
-
- fence->owner = owner;
- fence->sched = entity->sched;
- spin_lock_init(&fence->lock);
-
- seq = atomic_inc_return(&entity->fence_seq);
- dma_fence_init(&fence->scheduled, &amd_sched_fence_ops_scheduled,
- &fence->lock, entity->fence_context, seq);
- dma_fence_init(&fence->finished, &amd_sched_fence_ops_finished,
- &fence->lock, entity->fence_context + 1, seq);
-
- return fence;
-}
-
-void amd_sched_fence_scheduled(struct amd_sched_fence *fence)
-{
- int ret = dma_fence_signal(&fence->scheduled);
-
- if (!ret)
- DMA_FENCE_TRACE(&fence->scheduled,
- "signaled from irq context\n");
- else
- DMA_FENCE_TRACE(&fence->scheduled,
- "was already signaled\n");
-}
-
-void amd_sched_fence_finished(struct amd_sched_fence *fence)
-{
- int ret = dma_fence_signal(&fence->finished);
-
- if (!ret)
- DMA_FENCE_TRACE(&fence->finished,
- "signaled from irq context\n");
- else
- DMA_FENCE_TRACE(&fence->finished,
- "was already signaled\n");
-}
-
-static const char *amd_sched_fence_get_driver_name(struct dma_fence *fence)
-{
- return "amd_sched";
-}
-
-static const char *amd_sched_fence_get_timeline_name(struct dma_fence *f)
-{
- struct amd_sched_fence *fence = to_amd_sched_fence(f);
- return (const char *)fence->sched->name;
-}
-
-static bool amd_sched_fence_enable_signaling(struct dma_fence *f)
-{
- return true;
-}
-
-/**
- * amd_sched_fence_free - free up the fence memory
- *
- * @rcu: RCU callback head
- *
- * Free up the fence memory after the RCU grace period.
- */
-static void amd_sched_fence_free(struct rcu_head *rcu)
-{
- struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
- struct amd_sched_fence *fence = to_amd_sched_fence(f);
-
- dma_fence_put(fence->parent);
- kmem_cache_free(sched_fence_slab, fence);
-}
-
-/**
- * amd_sched_fence_release_scheduled - callback that fence can be freed
- *
- * @fence: fence
- *
- * This function is called when the reference count becomes zero.
- * It just RCU schedules freeing up the fence.
- */
-static void amd_sched_fence_release_scheduled(struct dma_fence *f)
-{
- struct amd_sched_fence *fence = to_amd_sched_fence(f);
-
- call_rcu(&fence->finished.rcu, amd_sched_fence_free);
-}
-
-/**
- * amd_sched_fence_release_finished - drop extra reference
- *
- * @f: fence
- *
- * Drop the extra reference from the scheduled fence to the base fence.
- */
-static void amd_sched_fence_release_finished(struct dma_fence *f)
-{
- struct amd_sched_fence *fence = to_amd_sched_fence(f);
-
- dma_fence_put(&fence->scheduled);
-}
-
-const struct dma_fence_ops amd_sched_fence_ops_scheduled = {
- .get_driver_name = amd_sched_fence_get_driver_name,
- .get_timeline_name = amd_sched_fence_get_timeline_name,
- .enable_signaling = amd_sched_fence_enable_signaling,
- .signaled = NULL,
- .wait = dma_fence_default_wait,
- .release = amd_sched_fence_release_scheduled,
-};
-
-const struct dma_fence_ops amd_sched_fence_ops_finished = {
- .get_driver_name = amd_sched_fence_get_driver_name,
- .get_timeline_name = amd_sched_fence_get_timeline_name,
- .enable_signaling = amd_sched_fence_enable_signaling,
- .signaled = NULL,
- .wait = dma_fence_default_wait,
- .release = amd_sched_fence_release_finished,
-};
diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c
index 696a15dc..7b784d9 100644
--- a/drivers/gpu/drm/ast/ast_ttm.c
+++ b/drivers/gpu/drm/ast/ast_ttm.c
@@ -216,9 +216,10 @@
return tt;
}
-static int ast_ttm_tt_populate(struct ttm_tt *ttm)
+static int ast_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
static void ast_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -237,7 +238,6 @@
.verify_access = ast_bo_verify_access,
.io_mem_reserve = &ast_ttm_io_mem_reserve,
.io_mem_free = &ast_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
int ast_mm_init(struct ast_private *ast)
@@ -354,6 +354,7 @@
int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (bo->pin_count) {
@@ -365,7 +366,7 @@
ast_ttm_placement(bo, pl_flag);
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -377,6 +378,7 @@
int ast_bo_unpin(struct ast_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i;
if (!bo->pin_count) {
DRM_ERROR("unpin bad %p\n", bo);
@@ -388,11 +390,12 @@
for (i = 0; i < bo->placement.num_placement ; i++)
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
- return ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ return ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
}
int ast_bo_push_sysram(struct ast_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
DRM_ERROR("unpin bad %p\n", bo);
@@ -409,7 +412,7 @@
for (i = 0; i < bo->placement.num_placement ; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret) {
DRM_ERROR("pushing to VRAM failed\n");
return ret;
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
index 703c2d1..eb7c4cf 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
@@ -889,7 +889,7 @@
drm_object_attach_property(&plane->base.base,
props->alpha, 255);
- if (desc->layout.xstride && desc->layout.pstride) {
+ if (desc->layout.xstride[0] && desc->layout.pstride[0]) {
int ret;
ret = drm_plane_create_rotation_property(&plane->base,
diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c
index c4cadb6..704e879 100644
--- a/drivers/gpu/drm/bochs/bochs_mm.c
+++ b/drivers/gpu/drm/bochs/bochs_mm.c
@@ -205,7 +205,6 @@
.verify_access = bochs_bo_verify_access,
.io_mem_reserve = &bochs_ttm_io_mem_reserve,
.io_mem_free = &bochs_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
int bochs_mm_init(struct bochs_device *bochs)
@@ -283,6 +282,7 @@
int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (bo->pin_count) {
@@ -295,7 +295,7 @@
bochs_ttm_placement(bo, pl_flag);
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -307,6 +307,7 @@
int bochs_bo_unpin(struct bochs_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
@@ -320,7 +321,7 @@
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c b/drivers/gpu/drm/cirrus/cirrus_ttm.c
index 1ff1838..a8e31ea 100644
--- a/drivers/gpu/drm/cirrus/cirrus_ttm.c
+++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c
@@ -216,9 +216,10 @@
return tt;
}
-static int cirrus_ttm_tt_populate(struct ttm_tt *ttm)
+static int cirrus_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
static void cirrus_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -237,7 +238,6 @@
.verify_access = cirrus_bo_verify_access,
.io_mem_reserve = &cirrus_ttm_io_mem_reserve,
.io_mem_free = &cirrus_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
int cirrus_mm_init(struct cirrus_device *cirrus)
@@ -358,6 +358,7 @@
int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (bo->pin_count) {
@@ -369,7 +370,7 @@
cirrus_ttm_placement(bo, pl_flag);
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -381,6 +382,7 @@
int cirrus_bo_push_sysram(struct cirrus_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
DRM_ERROR("unpin bad %p\n", bo);
@@ -397,7 +399,7 @@
for (i = 0; i < bo->placement.num_placement ; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret) {
DRM_ERROR("pushing to VRAM failed\n");
return ret;
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 4ee5af1..40549f6 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -50,7 +50,8 @@
* @state: atomic state
*
* Free all the memory allocated by drm_atomic_state_init.
- * This is useful for drivers that subclass the atomic state.
+ * This should only be used by drivers which are still subclassing
+ * &drm_atomic_state and haven't switched to &drm_private_state yet.
*/
void drm_atomic_state_default_release(struct drm_atomic_state *state)
{
@@ -67,7 +68,8 @@
* @state: atomic state
*
* Default implementation for filling in a new atomic state.
- * This is useful for drivers that subclass the atomic state.
+ * This should only be used by drivers which are still subclassing
+ * &drm_atomic_state and haven't switched to &drm_private_state yet.
*/
int
drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state)
@@ -132,7 +134,8 @@
* @state: atomic state
*
* Default implementation for clearing atomic state.
- * This is useful for drivers that subclass the atomic state.
+ * This should only be used by drivers which are still subclassing
+ * &drm_atomic_state and haven't switched to &drm_private_state yet.
*/
void drm_atomic_state_default_clear(struct drm_atomic_state *state)
{
@@ -955,6 +958,42 @@
}
/**
+ * DOC: handling driver private state
+ *
+ * Very often the DRM objects exposed to userspace in the atomic modeset api
+ * (&drm_connector, &drm_crtc and &drm_plane) do not map neatly to the
+ * underlying hardware. Especially for any kind of shared resources (e.g. shared
+ * clocks, scaler units, bandwidth and fifo limits shared among a group of
+ * planes or CRTCs, and so on) it makes sense to model these as independent
+ * objects. Drivers then need to do similar state tracking and commit ordering for
+ * such private (since not exposed to userpace) objects as the atomic core and
+ * helpers already provide for connectors, planes and CRTCs.
+ *
+ * To make this easier on drivers the atomic core provides some support to track
+ * driver private state objects using struct &drm_private_obj, with the
+ * associated state struct &drm_private_state.
+ *
+ * Similar to userspace-exposed objects, private state structures can be
+ * acquired by calling drm_atomic_get_private_obj_state(). Since this function
+ * does not take care of locking, drivers should wrap it for each type of
+ * private state object they have with the required call to drm_modeset_lock()
+ * for the corresponding &drm_modeset_lock.
+ *
+ * All private state structures contained in a &drm_atomic_state update can be
+ * iterated using for_each_oldnew_private_obj_in_state(),
+ * for_each_new_private_obj_in_state() and for_each_old_private_obj_in_state().
+ * Drivers are recommended to wrap these for each type of driver private state
+ * object they have, filtering on &drm_private_obj.funcs using for_each_if(), at
+ * least if they want to iterate over all objects of a given type.
+ *
+ * An earlier way to handle driver private state was by subclassing struct
+ * &drm_atomic_state. But since that encourages non-standard ways to implement
+ * the check/commit split atomic requires (by using e.g. "check and rollback or
+ * commit instead" of "duplicate state, check, then either commit or release
+ * duplicated state) it is deprecated in favour of using &drm_private_state.
+ */
+
+/**
* drm_atomic_private_obj_init - initialize private object
* @obj: private object
* @state: initial private object state
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index ab40321..ae3cbfe 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1878,6 +1878,8 @@
new_crtc_state->event->base.completion = &commit->flip_done;
new_crtc_state->event->base.completion_release = release_crtc_commit;
drm_crtc_commit_get(commit);
+
+ commit->abort_completion = true;
}
for_each_oldnew_connector_in_state(state, conn, old_conn_state, new_conn_state, i) {
@@ -3421,8 +3423,21 @@
void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state)
{
if (state->commit) {
+ /*
+ * In the event that a non-blocking commit returns
+ * -ERESTARTSYS before the commit_tail work is queued, we will
+ * have an extra reference to the commit object. Release it, if
+ * the event has not been consumed by the worker.
+ *
+ * state->event may be freed, so we can't directly look at
+ * state->event->base.completion.
+ */
+ if (state->event && state->commit->abort_completion)
+ drm_crtc_commit_put(state->commit);
+
kfree(state->commit->event);
state->commit->event = NULL;
+
drm_crtc_commit_put(state->commit);
}
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index aad468d..d9c0f75 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -230,6 +230,12 @@
if (!dev->master)
goto out_unlock;
+ if (file_priv->master->lessor != NULL) {
+ DRM_DEBUG_LEASE("Attempt to drop lessee %d as master\n", file_priv->master->lessee_id);
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
ret = 0;
drm_drop_master(dev, file_priv);
out_unlock:
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index 2e5e089..4c62dff 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -214,9 +214,11 @@
* This function initializes generic mutable zpos property and enables support
* for it in drm core. Drivers can then attach this property to planes to enable
* support for configurable planes arrangement during blending operation.
- * Once mutable zpos property has been enabled, the DRM core will automatically
- * calculate &drm_plane_state.normalized_zpos values. Usually min should be set
- * to 0 and max to maximal number of planes for given crtc - 1.
+ * Drivers that attach a mutable zpos property to any plane should call the
+ * drm_atomic_normalize_zpos() helper during their implementation of
+ * &drm_mode_config_funcs.atomic_check(), which will update the normalized zpos
+ * values and store them in &drm_plane_state.normalized_zpos. Usually min
+ * should be set to 0 and max to maximal number of planes for given crtc - 1.
*
* If zpos of some planes cannot be changed (like fixed background or
* cursor/topmost planes), driver should adjust min/max values and assign those
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 9ae2360..e6a21e6 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -24,6 +24,7 @@
#include <drm/drm_connector.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
+#include <drm/drm_utils.h>
#include "drm_crtc_internal.h"
#include "drm_internal.h"
@@ -231,6 +232,8 @@
mutex_init(&connector->mutex);
connector->edid_blob_ptr = NULL;
connector->status = connector_status_unknown;
+ connector->display_info.panel_orientation =
+ DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
drm_connector_get_cmdline_mode(connector);
@@ -712,6 +715,13 @@
{ DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
};
+static const struct drm_prop_enum_list drm_panel_orientation_enum_list[] = {
+ { DRM_MODE_PANEL_ORIENTATION_NORMAL, "Normal" },
+ { DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP, "Upside Down" },
+ { DRM_MODE_PANEL_ORIENTATION_LEFT_UP, "Left Side Up" },
+ { DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, "Right Side Up" },
+};
+
static const struct drm_prop_enum_list drm_dvi_i_select_enum_list[] = {
{ DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
{ DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */
@@ -820,6 +830,18 @@
*
* CRTC_ID:
* Mode object ID of the &drm_crtc this connector should be connected to.
+ *
+ * Connectors for LCD panels may also have one standardized property:
+ *
+ * panel orientation:
+ * On some devices the LCD panel is mounted in the casing in such a way
+ * that the up/top side of the panel does not match with the top side of
+ * the device. Userspace can use this property to check for this.
+ * Note that input coordinates from touchscreens (input devices with
+ * INPUT_PROP_DIRECT) will still map 1:1 to the actual LCD panel
+ * coordinates, so if userspace rotates the picture to adjust for
+ * the orientation it must also apply the same transformation to the
+ * touchscreen input coordinates.
*/
int drm_connector_create_standard_properties(struct drm_device *dev)
@@ -1308,6 +1330,57 @@
}
EXPORT_SYMBOL(drm_mode_connector_set_link_status_property);
+/**
+ * drm_connector_init_panel_orientation_property -
+ * initialize the connecters panel_orientation property
+ * @connector: connector for which to init the panel-orientation property.
+ * @width: width in pixels of the panel, used for panel quirk detection
+ * @height: height in pixels of the panel, used for panel quirk detection
+ *
+ * This function should only be called for built-in panels, after setting
+ * connector->display_info.panel_orientation first (if known).
+ *
+ * This function will check for platform specific (e.g. DMI based) quirks
+ * overriding display_info.panel_orientation first, then if panel_orientation
+ * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
+ * "panel orientation" property to the connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_init_panel_orientation_property(
+ struct drm_connector *connector, int width, int height)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_display_info *info = &connector->display_info;
+ struct drm_property *prop;
+ int orientation_quirk;
+
+ orientation_quirk = drm_get_panel_orientation_quirk(width, height);
+ if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
+ info->panel_orientation = orientation_quirk;
+
+ if (info->panel_orientation == DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
+ return 0;
+
+ prop = dev->mode_config.panel_orientation_property;
+ if (!prop) {
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
+ "panel orientation",
+ drm_panel_orientation_enum_list,
+ ARRAY_SIZE(drm_panel_orientation_enum_list));
+ if (!prop)
+ return -ENOMEM;
+
+ dev->mode_config.panel_orientation_property = prop;
+ }
+
+ drm_object_attach_property(&connector->base, prop,
+ info->panel_orientation);
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_init_panel_orientation_property);
+
int drm_mode_connector_set_obj_prop(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t value)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 58d05d1..79fa506 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -165,6 +165,24 @@
/* HTC Vive VR Headset */
{ "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
+
+ /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
+ { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
+ { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
+ { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
+
+ /* Windows Mixed Reality Headsets */
+ { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
+ { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
+ { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
+ { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
+ { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
+ { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
+ { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
+ { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
+
+ /* Sony PlayStation VR Headset */
+ { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
};
/*
@@ -4873,6 +4891,11 @@
* @mode: DRM display mode
* @rgb_quant_range: RGB quantization range (Q)
* @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
+ * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
+ *
+ * Note that @is_hdmi2_sink can be derived by looking at the
+ * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
+ * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
*/
void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
index 35b56df..186d00ad 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -23,6 +23,7 @@
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_print.h>
#include <linux/module.h>
#define DEFAULT_FBDEFIO_DELAY_MS 50
@@ -42,7 +43,7 @@
* callback function to create a cma backed framebuffer.
*
* An fbdev framebuffer backed by cma is also available by calling
- * drm_fbdev_cma_init(). drm_fbdev_cma_fini() tears it down.
+ * drm_fb_cma_fbdev_init(). drm_fb_cma_fbdev_fini() tears it down.
* If the &drm_framebuffer_funcs.dirty callback is set, fb_deferred_io will be
* set up automatically. &drm_framebuffer_funcs.dirty is called by
* drm_fb_helper_deferred_io() in process context (&struct delayed_work).
@@ -68,7 +69,7 @@
*
* Initialize::
*
- * fbdev = drm_fbdev_cma_init_with_funcs(dev, 16,
+ * fbdev = drm_fb_cma_fbdev_init_with_funcs(dev, 16,
* dev->mode_config.num_crtc,
* dev->mode_config.num_connector,
* &driver_fb_funcs);
@@ -256,7 +257,7 @@
fbi->screen_size = size;
fbi->fix.smem_len = size;
- if (fbdev_cma->fb_funcs->dirty) {
+ if (fb->funcs->dirty) {
ret = drm_fbdev_cma_defio_init(fbi, obj);
if (ret)
goto err_cma_destroy;
@@ -278,6 +279,118 @@
};
/**
+ * drm_fb_cma_fbdev_init_with_funcs() - Allocate and initialize fbdev emulation
+ * @dev: DRM device
+ * @preferred_bpp: Preferred bits per pixel for the device.
+ * @dev->mode_config.preferred_depth is used if this is zero.
+ * @max_conn_count: Maximum number of connectors.
+ * @dev->mode_config.num_connector is used if this is zero.
+ * @funcs: Framebuffer functions, in particular a custom dirty() callback.
+ * Can be NULL.
+ *
+ * Returns:
+ * Zero on success or negative error code on failure.
+ */
+int drm_fb_cma_fbdev_init_with_funcs(struct drm_device *dev,
+ unsigned int preferred_bpp, unsigned int max_conn_count,
+ const struct drm_framebuffer_funcs *funcs)
+{
+ struct drm_fbdev_cma *fbdev_cma;
+ struct drm_fb_helper *fb_helper;
+ int ret;
+
+ if (!preferred_bpp)
+ preferred_bpp = dev->mode_config.preferred_depth;
+ if (!preferred_bpp)
+ preferred_bpp = 32;
+
+ if (!max_conn_count)
+ max_conn_count = dev->mode_config.num_connector;
+
+ fbdev_cma = kzalloc(sizeof(*fbdev_cma), GFP_KERNEL);
+ if (!fbdev_cma)
+ return -ENOMEM;
+
+ fbdev_cma->fb_funcs = funcs;
+ fb_helper = &fbdev_cma->fb_helper;
+
+ drm_fb_helper_prepare(dev, fb_helper, &drm_fb_cma_helper_funcs);
+
+ ret = drm_fb_helper_init(dev, fb_helper, max_conn_count);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "Failed to initialize fbdev helper.\n");
+ goto err_free;
+ }
+
+ ret = drm_fb_helper_single_add_all_connectors(fb_helper);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "Failed to add connectors.\n");
+ goto err_drm_fb_helper_fini;
+ }
+
+ ret = drm_fb_helper_initial_config(fb_helper, preferred_bpp);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "Failed to set fbdev configuration.\n");
+ goto err_drm_fb_helper_fini;
+ }
+
+ return 0;
+
+err_drm_fb_helper_fini:
+ drm_fb_helper_fini(fb_helper);
+err_free:
+ kfree(fbdev_cma);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(drm_fb_cma_fbdev_init_with_funcs);
+
+/**
+ * drm_fb_cma_fbdev_init() - Allocate and initialize fbdev emulation
+ * @dev: DRM device
+ * @preferred_bpp: Preferred bits per pixel for the device.
+ * @dev->mode_config.preferred_depth is used if this is zero.
+ * @max_conn_count: Maximum number of connectors.
+ * @dev->mode_config.num_connector is used if this is zero.
+ *
+ * Returns:
+ * Zero on success or negative error code on failure.
+ */
+int drm_fb_cma_fbdev_init(struct drm_device *dev, unsigned int preferred_bpp,
+ unsigned int max_conn_count)
+{
+ return drm_fb_cma_fbdev_init_with_funcs(dev, preferred_bpp,
+ max_conn_count, NULL);
+}
+EXPORT_SYMBOL_GPL(drm_fb_cma_fbdev_init);
+
+/**
+ * drm_fb_cma_fbdev_fini() - Teardown fbdev emulation
+ * @dev: DRM device
+ */
+void drm_fb_cma_fbdev_fini(struct drm_device *dev)
+{
+ struct drm_fb_helper *fb_helper = dev->fb_helper;
+
+ if (!fb_helper)
+ return;
+
+ /* Unregister if it hasn't been done already */
+ if (fb_helper->fbdev && fb_helper->fbdev->dev)
+ drm_fb_helper_unregister_fbi(fb_helper);
+
+ if (fb_helper->fbdev)
+ drm_fbdev_cma_defio_fini(fb_helper->fbdev);
+
+ if (fb_helper->fb)
+ drm_framebuffer_remove(fb_helper->fb);
+
+ drm_fb_helper_fini(fb_helper);
+ kfree(to_fbdev_cma(fb_helper));
+}
+EXPORT_SYMBOL_GPL(drm_fb_cma_fbdev_fini);
+
+/**
* drm_fbdev_cma_init_with_funcs() - Allocate and initializes a drm_fbdev_cma struct
* @dev: DRM device
* @preferred_bpp: Preferred bits per pixel for the device
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 09919e8..035784d 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -41,6 +41,7 @@
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
+#include "drm_crtc_internal.h"
#include "drm_crtc_helper_internal.h"
static bool drm_fbdev_emulation = true;
@@ -65,19 +66,23 @@
* helper functions used by many drivers to implement the kernel mode setting
* interfaces.
*
- * Initialization is done as a four-step process with drm_fb_helper_prepare(),
- * drm_fb_helper_init(), drm_fb_helper_single_add_all_connectors() and
- * drm_fb_helper_initial_config(). Drivers with fancier requirements than the
- * default behaviour can override the third step with their own code.
- * Teardown is done with drm_fb_helper_fini() after the fbdev device is
- * unregisters using drm_fb_helper_unregister_fbi().
+ * Setup fbdev emulation by calling drm_fb_helper_fbdev_setup() and tear it
+ * down by calling drm_fb_helper_fbdev_teardown().
*
- * At runtime drivers should restore the fbdev console by calling
- * drm_fb_helper_restore_fbdev_mode_unlocked() from their &drm_driver.lastclose
- * callback. They should also notify the fb helper code from updates to the
- * output configuration by calling drm_fb_helper_hotplug_event(). For easier
- * integration with the output polling code in drm_crtc_helper.c the modeset
- * code provides a &drm_mode_config_funcs.output_poll_changed callback.
+ * Drivers that need to handle connector hotplugging (e.g. dp mst) can't use
+ * the setup helper and will need to do the whole four-step setup process with
+ * drm_fb_helper_prepare(), drm_fb_helper_init(),
+ * drm_fb_helper_single_add_all_connectors(), enable hotplugging and
+ * drm_fb_helper_initial_config() to avoid a possible race window.
+ *
+ * At runtime drivers should restore the fbdev console by using
+ * drm_fb_helper_lastclose() as their &drm_driver.lastclose callback.
+ * They should also notify the fb helper code from updates to the output
+ * configuration by using drm_fb_helper_output_poll_changed() as their
+ * &drm_mode_config_funcs.output_poll_changed callback.
+ *
+ * For suspend/resume consider using drm_mode_config_helper_suspend() and
+ * drm_mode_config_helper_resume() which takes care of fbdev as well.
*
* All other functions exported by the fb helper library can be used to
* implement the fbdev driver interface by the driver.
@@ -102,7 +107,8 @@
* always run in process context since the fb_*() function could be running in
* atomic context. If drm_fb_helper_deferred_io() is used as the deferred_io
* callback it will also schedule dirty_work with the damage collected from the
- * mmap page writes.
+ * mmap page writes. Drivers can use drm_fb_helper_defio_init() to setup
+ * deferred I/O (coupled with drm_fb_helper_fbdev_teardown()).
*/
#define drm_fb_helper_for_each_connector(fbh, i__) \
@@ -177,7 +183,7 @@
*/
int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper *fb_helper)
{
- struct drm_device *dev = fb_helper->dev;
+ struct drm_device *dev;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
int i, ret = 0;
@@ -185,6 +191,8 @@
if (!drm_fbdev_emulation || !fb_helper)
return 0;
+ dev = fb_helper->dev;
+
mutex_lock(&fb_helper->lock);
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
@@ -356,6 +364,7 @@
static int restore_fbdev_mode_atomic(struct drm_fb_helper *fb_helper, bool active)
{
struct drm_device *dev = fb_helper->dev;
+ struct drm_plane_state *plane_state;
struct drm_plane *plane;
struct drm_atomic_state *state;
int i, ret;
@@ -374,8 +383,6 @@
retry:
plane_mask = 0;
drm_for_each_plane(plane, dev) {
- struct drm_plane_state *plane_state;
-
plane_state = drm_atomic_get_plane_state(state, plane);
if (IS_ERR(plane_state)) {
ret = PTR_ERR(plane_state);
@@ -398,6 +405,11 @@
for (i = 0; i < fb_helper->crtc_count; i++) {
struct drm_mode_set *mode_set = &fb_helper->crtc_info[i].mode_set;
+ struct drm_plane *primary = mode_set->crtc->primary;
+
+ /* Cannot fail as we've already gotten the plane state above */
+ plane_state = drm_atomic_get_new_plane_state(state, primary);
+ plane_state->rotation = fb_helper->crtc_info[i].rotation;
ret = __drm_atomic_helper_set_config(mode_set, state);
if (ret != 0)
@@ -829,6 +841,7 @@
if (!fb_helper->crtc_info[i].mode_set.connectors)
goto out_free;
fb_helper->crtc_info[i].mode_set.num_connectors = 0;
+ fb_helper->crtc_info[i].rotation = DRM_MODE_ROTATE_0;
}
i = 0;
@@ -1017,6 +1030,49 @@
EXPORT_SYMBOL(drm_fb_helper_deferred_io);
/**
+ * drm_fb_helper_defio_init - fbdev deferred I/O initialization
+ * @fb_helper: driver-allocated fbdev helper
+ *
+ * This function allocates &fb_deferred_io, sets callback to
+ * drm_fb_helper_deferred_io(), delay to 50ms and calls fb_deferred_io_init().
+ * It should be called from the &drm_fb_helper_funcs->fb_probe callback.
+ * drm_fb_helper_fbdev_teardown() cleans up deferred I/O.
+ *
+ * NOTE: A copy of &fb_ops is made and assigned to &info->fbops. This is done
+ * because fb_deferred_io_cleanup() clears &fbops->fb_mmap and would thereby
+ * affect other instances of that &fb_ops.
+ *
+ * Returns:
+ * 0 on success or a negative error code on failure.
+ */
+int drm_fb_helper_defio_init(struct drm_fb_helper *fb_helper)
+{
+ struct fb_info *info = fb_helper->fbdev;
+ struct fb_deferred_io *fbdefio;
+ struct fb_ops *fbops;
+
+ fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL);
+ fbops = kzalloc(sizeof(*fbops), GFP_KERNEL);
+ if (!fbdefio || !fbops) {
+ kfree(fbdefio);
+ kfree(fbops);
+ return -ENOMEM;
+ }
+
+ info->fbdefio = fbdefio;
+ fbdefio->delay = msecs_to_jiffies(50);
+ fbdefio->deferred_io = drm_fb_helper_deferred_io;
+
+ *fbops = *info->fbops;
+ info->fbops = fbops;
+
+ fb_deferred_io_init(info);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_defio_init);
+
+/**
* drm_fb_helper_sys_read - wrapper around fb_sys_read
* @info: fb_info struct pointer
* @buf: userspace buffer to read from framebuffer memory
@@ -1840,6 +1896,7 @@
if (ret < 0)
return ret;
+ strcpy(fb_helper->fb->comm, "[fbcon]");
return 0;
}
@@ -2357,6 +2414,62 @@
return best_score;
}
+/*
+ * This function checks if rotation is necessary because of panel orientation
+ * and if it is, if it is supported.
+ * If rotation is necessary and supported, its gets set in fb_crtc.rotation.
+ * If rotation is necessary but not supported, a DRM_MODE_ROTATE_* flag gets
+ * or-ed into fb_helper->sw_rotations. In drm_setup_crtcs_fb() we check if only
+ * one bit is set and then we set fb_info.fbcon_rotate_hint to make fbcon do
+ * the unsupported rotation.
+ */
+static void drm_setup_crtc_rotation(struct drm_fb_helper *fb_helper,
+ struct drm_fb_helper_crtc *fb_crtc,
+ struct drm_connector *connector)
+{
+ struct drm_plane *plane = fb_crtc->mode_set.crtc->primary;
+ uint64_t valid_mask = 0;
+ int i, rotation;
+
+ fb_crtc->rotation = DRM_MODE_ROTATE_0;
+
+ switch (connector->display_info.panel_orientation) {
+ case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
+ rotation = DRM_MODE_ROTATE_180;
+ break;
+ case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
+ rotation = DRM_MODE_ROTATE_90;
+ break;
+ case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
+ rotation = DRM_MODE_ROTATE_270;
+ break;
+ default:
+ rotation = DRM_MODE_ROTATE_0;
+ }
+
+ /*
+ * TODO: support 90 / 270 degree hardware rotation,
+ * depending on the hardware this may require the framebuffer
+ * to be in a specific tiling format.
+ */
+ if (rotation != DRM_MODE_ROTATE_180 || !plane->rotation_property) {
+ fb_helper->sw_rotations |= rotation;
+ return;
+ }
+
+ for (i = 0; i < plane->rotation_property->num_values; i++)
+ valid_mask |= (1ULL << plane->rotation_property->values[i]);
+
+ if (!(rotation & valid_mask)) {
+ fb_helper->sw_rotations |= rotation;
+ return;
+ }
+
+ fb_crtc->rotation = rotation;
+ /* Rotating in hardware, fbcon should not rotate */
+ fb_helper->sw_rotations |= DRM_MODE_ROTATE_0;
+}
+
static void drm_setup_crtcs(struct drm_fb_helper *fb_helper,
u32 width, u32 height)
{
@@ -2416,6 +2529,7 @@
drm_fb_helper_modeset_release(fb_helper,
&fb_helper->crtc_info[i].mode_set);
+ fb_helper->sw_rotations = 0;
drm_fb_helper_for_each_connector(fb_helper, i) {
struct drm_display_mode *mode = modes[i];
struct drm_fb_helper_crtc *fb_crtc = crtcs[i];
@@ -2435,6 +2549,7 @@
modeset->mode = drm_mode_duplicate(dev,
fb_crtc->desired_mode);
drm_connector_get(connector);
+ drm_setup_crtc_rotation(fb_helper, fb_crtc, connector);
modeset->connectors[modeset->num_connectors++] = connector;
modeset->x = offset->x;
modeset->y = offset->y;
@@ -2476,6 +2591,28 @@
}
}
mutex_unlock(&fb_helper->dev->mode_config.mutex);
+
+ switch (fb_helper->sw_rotations) {
+ case DRM_MODE_ROTATE_0:
+ info->fbcon_rotate_hint = FB_ROTATE_UR;
+ break;
+ case DRM_MODE_ROTATE_90:
+ info->fbcon_rotate_hint = FB_ROTATE_CCW;
+ break;
+ case DRM_MODE_ROTATE_180:
+ info->fbcon_rotate_hint = FB_ROTATE_UD;
+ break;
+ case DRM_MODE_ROTATE_270:
+ info->fbcon_rotate_hint = FB_ROTATE_CW;
+ break;
+ default:
+ /*
+ * Multiple bits are set / multiple rotations requested
+ * fbcon cannot handle separate rotation settings per
+ * output, so fallback to unrotated.
+ */
+ info->fbcon_rotate_hint = FB_ROTATE_UR;
+ }
}
/* Note: Drops fb_helper->lock before returning. */
@@ -2642,6 +2779,120 @@
EXPORT_SYMBOL(drm_fb_helper_hotplug_event);
/**
+ * drm_fb_helper_fbdev_setup() - Setup fbdev emulation
+ * @dev: DRM device
+ * @fb_helper: fbdev helper structure to set up
+ * @funcs: fbdev helper functions
+ * @preferred_bpp: Preferred bits per pixel for the device.
+ * @dev->mode_config.preferred_depth is used if this is zero.
+ * @max_conn_count: Maximum number of connectors.
+ * @dev->mode_config.num_connector is used if this is zero.
+ *
+ * This function sets up fbdev emulation and registers fbdev for access by
+ * userspace. If all connectors are disconnected, setup is deferred to the next
+ * time drm_fb_helper_hotplug_event() is called.
+ * The caller must to provide a &drm_fb_helper_funcs->fb_probe callback
+ * function.
+ *
+ * See also: drm_fb_helper_initial_config()
+ *
+ * Returns:
+ * Zero on success or negative error code on failure.
+ */
+int drm_fb_helper_fbdev_setup(struct drm_device *dev,
+ struct drm_fb_helper *fb_helper,
+ const struct drm_fb_helper_funcs *funcs,
+ unsigned int preferred_bpp,
+ unsigned int max_conn_count)
+{
+ int ret;
+
+ if (!preferred_bpp)
+ preferred_bpp = dev->mode_config.preferred_depth;
+ if (!preferred_bpp)
+ preferred_bpp = 32;
+
+ if (!max_conn_count)
+ max_conn_count = dev->mode_config.num_connector;
+ if (!max_conn_count) {
+ DRM_DEV_ERROR(dev->dev, "No connectors\n");
+ return -EINVAL;
+ }
+
+ drm_fb_helper_prepare(dev, fb_helper, funcs);
+
+ ret = drm_fb_helper_init(dev, fb_helper, max_conn_count);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "Failed to initialize fbdev helper\n");
+ return ret;
+ }
+
+ ret = drm_fb_helper_single_add_all_connectors(fb_helper);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "Failed to add connectors\n");
+ goto err_drm_fb_helper_fini;
+ }
+
+ if (!drm_drv_uses_atomic_modeset(dev))
+ drm_helper_disable_unused_functions(dev);
+
+ ret = drm_fb_helper_initial_config(fb_helper, preferred_bpp);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "Failed to set fbdev configuration\n");
+ goto err_drm_fb_helper_fini;
+ }
+
+ return 0;
+
+err_drm_fb_helper_fini:
+ drm_fb_helper_fini(fb_helper);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_fb_helper_fbdev_setup);
+
+/**
+ * drm_fb_helper_fbdev_teardown - Tear down fbdev emulation
+ * @dev: DRM device
+ *
+ * This function unregisters fbdev if not already done and cleans up the
+ * associated resources including the &drm_framebuffer.
+ * The driver is responsible for freeing the &drm_fb_helper structure which is
+ * stored in &drm_device->fb_helper. Do note that this pointer has been cleared
+ * when this function returns.
+ *
+ * In order to support device removal/unplug while file handles are still open,
+ * drm_fb_helper_unregister_fbi() should be called on device removal and
+ * drm_fb_helper_fbdev_teardown() in the &drm_driver->release callback when
+ * file handles are closed.
+ */
+void drm_fb_helper_fbdev_teardown(struct drm_device *dev)
+{
+ struct drm_fb_helper *fb_helper = dev->fb_helper;
+ struct fb_ops *fbops = NULL;
+
+ if (!fb_helper)
+ return;
+
+ /* Unregister if it hasn't been done already */
+ if (fb_helper->fbdev && fb_helper->fbdev->dev)
+ drm_fb_helper_unregister_fbi(fb_helper);
+
+ if (fb_helper->fbdev && fb_helper->fbdev->fbdefio) {
+ fb_deferred_io_cleanup(fb_helper->fbdev);
+ kfree(fb_helper->fbdev->fbdefio);
+ fbops = fb_helper->fbdev->fbops;
+ }
+
+ drm_fb_helper_fini(fb_helper);
+ kfree(fbops);
+
+ if (fb_helper->fb)
+ drm_framebuffer_remove(fb_helper->fb);
+}
+EXPORT_SYMBOL(drm_fb_helper_fbdev_teardown);
+
+/**
* drm_fb_helper_lastclose - DRM driver lastclose helper for fbdev emulation
* @dev: DRM device
*
diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index b967bf4..2dc5e8b 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -675,6 +675,7 @@
INIT_LIST_HEAD(&fb->filp_head);
fb->funcs = funcs;
+ strcpy(fb->comm, current->comm);
ret = __drm_mode_object_add(dev, &fb->base, DRM_MODE_OBJECT_FB,
false, drm_framebuffer_free);
@@ -989,6 +990,7 @@
struct drm_format_name_buf format_name;
unsigned int i;
+ drm_printf_indent(p, indent, "allocated by = %s\n", fb->comm);
drm_printf_indent(p, indent, "refcount=%u\n",
drm_framebuffer_read_refcount(fb));
drm_printf_indent(p, indent, "format=%s\n",
diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
index aa8cb9b..4d682a6 100644
--- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
+++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
@@ -272,7 +272,8 @@
* @sizes: fbdev size description
* @pitch_align: Optional pitch alignment
* @obj: GEM object backing the framebuffer
- * @funcs: vtable to be used for the new framebuffer object
+ * @funcs: Optional vtable to be used for the new framebuffer object when the
+ * dirty callback is needed.
*
* This function creates a framebuffer from a &drm_fb_helper_surface_size
* description for use in the &drm_fb_helper_funcs.fb_probe callback.
@@ -300,6 +301,9 @@
if (obj->size < mode_cmd.pitches[0] * mode_cmd.height)
return ERR_PTR(-EINVAL);
+ if (!funcs)
+ funcs = &drm_gem_fb_funcs;
+
return drm_gem_fb_alloc(dev, &mode_cmd, &obj, 1, funcs);
}
EXPORT_SYMBOL(drm_gem_fbdev_fb_create);
diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c
index 256de73..e5c6533 100644
--- a/drivers/gpu/drm/drm_mode_config.c
+++ b/drivers/gpu/drm/drm_mode_config.c
@@ -472,6 +472,9 @@
*/
WARN_ON(!list_empty(&dev->mode_config.fb_list));
list_for_each_entry_safe(fb, fbt, &dev->mode_config.fb_list, head) {
+ struct drm_printer p = drm_debug_printer("[leaked fb]");
+ drm_printf(&p, "framebuffer[%u]:\n", fb->base.id);
+ drm_framebuffer_print_info(&p, 1, fb);
drm_framebuffer_free(&fb->base.refcount);
}
diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c
index 9cb1eed..f1c24ab 100644
--- a/drivers/gpu/drm/drm_modeset_helper.c
+++ b/drivers/gpu/drm/drm_modeset_helper.c
@@ -20,6 +20,9 @@
* OF THIS SOFTWARE.
*/
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
#include <drm/drm_modeset_helper.h>
#include <drm/drm_plane_helper.h>
@@ -156,3 +159,76 @@
NULL);
}
EXPORT_SYMBOL(drm_crtc_init);
+
+/**
+ * drm_mode_config_helper_suspend - Modeset suspend helper
+ * @dev: DRM device
+ *
+ * This helper function takes care of suspending the modeset side. It disables
+ * output polling if initialized, suspends fbdev if used and finally calls
+ * drm_atomic_helper_suspend().
+ * If suspending fails, fbdev and polling is re-enabled.
+ *
+ * Returns:
+ * Zero on success, negative error code on error.
+ *
+ * See also:
+ * drm_kms_helper_poll_disable() and drm_fb_helper_set_suspend_unlocked().
+ */
+int drm_mode_config_helper_suspend(struct drm_device *dev)
+{
+ struct drm_atomic_state *state;
+
+ if (!dev)
+ return 0;
+
+ drm_kms_helper_poll_disable(dev);
+ drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 1);
+ state = drm_atomic_helper_suspend(dev);
+ if (IS_ERR(state)) {
+ drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
+ drm_kms_helper_poll_enable(dev);
+ return PTR_ERR(state);
+ }
+
+ dev->mode_config.suspend_state = state;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_mode_config_helper_suspend);
+
+/**
+ * drm_mode_config_helper_resume - Modeset resume helper
+ * @dev: DRM device
+ *
+ * This helper function takes care of resuming the modeset side. It calls
+ * drm_atomic_helper_resume(), resumes fbdev if used and enables output polling
+ * if initiaized.
+ *
+ * Returns:
+ * Zero on success, negative error code on error.
+ *
+ * See also:
+ * drm_fb_helper_set_suspend_unlocked() and drm_kms_helper_poll_enable().
+ */
+int drm_mode_config_helper_resume(struct drm_device *dev)
+{
+ int ret;
+
+ if (!dev)
+ return 0;
+
+ if (WARN_ON(!dev->mode_config.suspend_state))
+ return -EINVAL;
+
+ ret = drm_atomic_helper_resume(dev, dev->mode_config.suspend_state);
+ if (ret)
+ DRM_ERROR("Failed to resume (%d)\n", ret);
+ dev->mode_config.suspend_state = NULL;
+
+ drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
+ drm_kms_helper_poll_enable(dev);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_mode_config_helper_resume);
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c
new file mode 100644
index 0000000..1f2af70
--- /dev/null
+++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * drm_panel_orientation_quirks.c -- Quirks for non-normal panel orientation
+ *
+ * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Note the quirks in this file are shared with fbdev/efifb and as such
+ * must not depend on other drm code.
+ */
+
+#include <linux/dmi.h>
+#include <linux/module.h>
+#include <drm/drm_connector.h>
+
+#ifdef CONFIG_DMI
+
+/*
+ * Some x86 clamshell design devices use portrait tablet screens and a display
+ * engine which cannot rotate in hardware, so we need to rotate the fbcon to
+ * compensate. Unfortunately these (cheap) devices also typically have quite
+ * generic DMI data, so we match on a combination of DMI data, screen resolution
+ * and a list of known BIOS dates to avoid false positives.
+ */
+
+struct drm_dmi_panel_orientation_data {
+ int width;
+ int height;
+ const char * const *bios_dates;
+ int orientation;
+};
+
+static const struct drm_dmi_panel_orientation_data asus_t100ha = {
+ .width = 800,
+ .height = 1280,
+ .orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP,
+};
+
+static const struct drm_dmi_panel_orientation_data gpd_pocket = {
+ .width = 1200,
+ .height = 1920,
+ .bios_dates = (const char * const []){ "05/26/2017", "06/28/2017",
+ "07/05/2017", "08/07/2017", NULL },
+ .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
+static const struct drm_dmi_panel_orientation_data gpd_win = {
+ .width = 720,
+ .height = 1280,
+ .bios_dates = (const char * const []){
+ "10/25/2016", "11/18/2016", "12/23/2016", "12/26/2016",
+ "02/21/2017", "03/20/2017", "05/25/2017", NULL },
+ .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
+static const struct drm_dmi_panel_orientation_data itworks_tw891 = {
+ .width = 800,
+ .height = 1280,
+ .bios_dates = (const char * const []){ "10/16/2015", NULL },
+ .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
+static const struct drm_dmi_panel_orientation_data vios_lth17 = {
+ .width = 800,
+ .height = 1280,
+ .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
+static const struct dmi_system_id orientation_data[] = {
+ { /* Asus T100HA */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
+ },
+ .driver_data = (void *)&asus_t100ha,
+ }, { /*
+ * GPD Pocket, note that the the DMI data is less generic then
+ * it seems, devices with a board-vendor of "AMI Corporation"
+ * are quite rare, as are devices which have both board- *and*
+ * product-id set to "Default String"
+ */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
+ DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
+ },
+ .driver_data = (void *)&gpd_pocket,
+ }, { /* GPD Win (same note on DMI match as GPD Pocket) */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
+ DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
+ },
+ .driver_data = (void *)&gpd_win,
+ }, { /* I.T.Works TW891 */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "To be filled by O.E.M."),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "TW891"),
+ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "To be filled by O.E.M."),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "TW891"),
+ },
+ .driver_data = (void *)&itworks_tw891,
+ }, { /* VIOS LTH17 */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "VIOS"),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "LTH17"),
+ },
+ .driver_data = (void *)&vios_lth17,
+ },
+ {}
+};
+
+/**
+ * drm_get_panel_orientation_quirk - Check for panel orientation quirks
+ * @width: width in pixels of the panel
+ * @height: height in pixels of the panel
+ *
+ * This function checks for platform specific (e.g. DMI based) quirks
+ * providing info on panel_orientation for systems where this cannot be
+ * probed from the hard-/firm-ware. To avoid false-positive this function
+ * takes the panel resolution as argument and checks that against the
+ * resolution expected by the quirk-table entry.
+ *
+ * Note this function is also used outside of the drm-subsys, by for example
+ * the efifb code. Because of this this function gets compiled into its own
+ * kernel-module when built as a module.
+ *
+ * Returns:
+ * A DRM_MODE_PANEL_ORIENTATION_* value if there is a quirk for this system,
+ * or DRM_MODE_PANEL_ORIENTATION_UNKNOWN if there is no quirk.
+ */
+int drm_get_panel_orientation_quirk(int width, int height)
+{
+ const struct dmi_system_id *match;
+ const struct drm_dmi_panel_orientation_data *data;
+ const char *bios_date;
+ int i;
+
+ for (match = dmi_first_match(orientation_data);
+ match;
+ match = dmi_first_match(match + 1)) {
+ data = match->driver_data;
+
+ if (data->width != width ||
+ data->height != height)
+ continue;
+
+ if (!data->bios_dates)
+ return data->orientation;
+
+ bios_date = dmi_get_system_info(DMI_BIOS_DATE);
+ if (!bios_date)
+ continue;
+
+ for (i = 0; data->bios_dates[i]; i++) {
+ if (!strcmp(data->bios_dates[i], bios_date))
+ return data->orientation;
+ }
+ }
+
+ return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+}
+EXPORT_SYMBOL(drm_get_panel_orientation_quirk);
+
+#else
+
+/* There are no quirks for non x86 devices yet */
+int drm_get_panel_orientation_quirk(int width, int height)
+{
+ return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+}
+EXPORT_SYMBOL(drm_get_panel_orientation_quirk);
+
+#endif
+
+MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 68a69e9..ca09ce7 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -218,8 +218,9 @@
sgt = prime_attach->sgt;
if (sgt) {
if (prime_attach->dir != DMA_NONE)
- dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents,
- prime_attach->dir);
+ dma_unmap_sg_attrs(attach->dev, sgt->sgl, sgt->nents,
+ prime_attach->dir,
+ DMA_ATTR_SKIP_CPU_SYNC);
sg_free_table(sgt);
}
@@ -278,7 +279,8 @@
sgt = obj->dev->driver->gem_prime_get_sg_table(obj);
if (!IS_ERR(sgt)) {
- if (!dma_map_sg(attach->dev, sgt->sgl, sgt->nents, dir)) {
+ if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
+ DMA_ATTR_SKIP_CPU_SYNC)) {
sg_free_table(sgt);
kfree(sgt);
sgt = ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
index 7a6b2dc..00b8445b 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -216,8 +216,7 @@
* suspend/resume.
*
* Drivers can call this helper from their device resume implementation. It is
- * an error to call this when the output polling support has not yet been set
- * up.
+ * not an error to call this even when output polling isn't enabled.
*
* Note that calls to enable and disable polling must be strictly ordered, which
* is automatically the case when they're only call from suspend/resume
diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c
index bae50e6..d2375cf 100644
--- a/drivers/gpu/drm/drm_property.c
+++ b/drivers/gpu/drm/drm_property.c
@@ -516,7 +516,7 @@
drm_mode_object_unregister(blob->dev, &blob->base);
- kfree(blob);
+ kvfree(blob);
}
/**
@@ -543,7 +543,7 @@
if (!length || length > ULONG_MAX - sizeof(struct drm_property_blob))
return ERR_PTR(-EINVAL);
- blob = kzalloc(sizeof(struct drm_property_blob)+length, GFP_KERNEL);
+ blob = kvzalloc(sizeof(struct drm_property_blob)+length, GFP_KERNEL);
if (!blob)
return ERR_PTR(-ENOMEM);
@@ -559,7 +559,7 @@
ret = __drm_mode_object_add(dev, &blob->base, DRM_MODE_OBJECT_BLOB,
true, drm_property_free_blob);
if (ret) {
- kfree(blob);
+ kvfree(blob);
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 1231f4d..0b7b0d1 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -29,9 +29,9 @@
/**
* DOC: Overview
*
- * DRM synchronisation objects (syncobj) are a persistent objects,
- * that contain an optional fence. The fence can be updated with a new
- * fence, or be NULL.
+ * DRM synchronisation objects (syncobj, see struct &drm_syncobj) are
+ * persistent objects that contain an optional fence. The fence can be updated
+ * with a new fence, or be NULL.
*
* syncobj's can be waited upon, where it will wait for the underlying
* fence.
@@ -61,7 +61,8 @@
* @file_private: drm file private pointer
* @handle: sync object handle to lookup.
*
- * Returns a reference to the syncobj pointed to by handle or NULL.
+ * Returns a reference to the syncobj pointed to by handle or NULL. The
+ * reference must be released by calling drm_syncobj_put().
*/
struct drm_syncobj *drm_syncobj_find(struct drm_file *file_private,
u32 handle)
@@ -229,6 +230,19 @@
return 0;
}
+/**
+ * drm_syncobj_find_fence - lookup and reference the fence in a sync object
+ * @file_private: drm file private pointer
+ * @handle: sync object handle to lookup.
+ * @fence: out parameter for the fence
+ *
+ * This is just a convenience function that combines drm_syncobj_find() and
+ * drm_syncobj_fence_get().
+ *
+ * Returns 0 on success or a negative error value on failure. On success @fence
+ * contains a reference to the fence, which must be released by calling
+ * dma_fence_put().
+ */
int drm_syncobj_find_fence(struct drm_file *file_private,
u32 handle,
struct dma_fence **fence)
@@ -269,6 +283,12 @@
* @out_syncobj: returned syncobj
* @flags: DRM_SYNCOBJ_* flags
* @fence: if non-NULL, the syncobj will represent this fence
+ *
+ * This is the first function to create a sync object. After creating, drivers
+ * probably want to make it available to userspace, either through
+ * drm_syncobj_get_handle() or drm_syncobj_get_fd().
+ *
+ * Returns 0 on success or a negative error value on failure.
*/
int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
struct dma_fence *fence)
@@ -302,6 +322,14 @@
/**
* drm_syncobj_get_handle - get a handle from a syncobj
+ * @file_private: drm file private pointer
+ * @syncobj: Sync object to export
+ * @handle: out parameter with the new handle
+ *
+ * Exports a sync object created with drm_syncobj_create() as a handle on
+ * @file_private to userspace.
+ *
+ * Returns 0 on success or a negative error value on failure.
*/
int drm_syncobj_get_handle(struct drm_file *file_private,
struct drm_syncobj *syncobj, u32 *handle)
@@ -371,6 +399,15 @@
.release = drm_syncobj_file_release,
};
+/**
+ * drm_syncobj_get_fd - get a file descriptor from a syncobj
+ * @syncobj: Sync object to export
+ * @p_fd: out parameter with the new file descriptor
+ *
+ * Exports a sync object created with drm_syncobj_create() as a file descriptor.
+ *
+ * Returns 0 on success or a negative error value on failure.
+ */
int drm_syncobj_get_fd(struct drm_syncobj *syncobj, int *p_fd)
{
struct file *file;
diff --git a/drivers/gpu/drm/evdi/Kconfig b/drivers/gpu/drm/evdi/Kconfig
new file mode 100644
index 0000000..134ba74
--- /dev/null
+++ b/drivers/gpu/drm/evdi/Kconfig
@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License v2. See the file COPYING in the main directory of this archive for
+# more details.
+#
+
+config DRM_EVDI
+ tristate "Extensible Virtual Display Interface"
+ depends on DRM
+ select FB_SYS_FILLRECT
+ select FB_SYS_COPYAREA
+ select FB_SYS_IMAGEBLIT
+ select DRM_KMS_HELPER
+ select DRM_KMS_FB_HELPER
+ help
+ This is a KMS interface driver allowing user-space programs to
+ register a virtual display (that imitates physical monitor) and
+ retrieve contents (as a frame buffer) that system renders on it.
+ Say M/Y to add support for these devices via DRM/KMS interfaces.
+
diff --git a/drivers/gpu/drm/evdi/Makefile b/drivers/gpu/drm/evdi/Makefile
new file mode 100644
index 0000000..2cd3ced
--- /dev/null
+++ b/drivers/gpu/drm/evdi/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License v2. See the file COPYING in the main directory of this archive for
+# more details.
+#
+ccflags-y := -Iinclude/drm
+
+evdi-y := evdi_drv.o evdi_modeset.o evdi_connector.o evdi_encoder.o evdi_main.o evdi_fb.o evdi_gem.o evdi_stats.o evdi_painter.o evdi_debug.o evdi_cursor.o
+
+evdi-$(CONFIG_COMPAT) += evdi_ioc32.o
+
+obj-$(CONFIG_DRM_EVDI) := evdi.o
+
diff --git a/drivers/gpu/drm/evdi/evdi_connector.c b/drivers/gpu/drm/evdi/evdi_connector.c
new file mode 100644
index 0000000..c96bd1d
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_connector.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * Based on parts on udlfb.c:
+ * Copyright (C) 2009 its respective authors
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_atomic_helper.h>
+#include "evdi_drv.h"
+
+/*
+ * dummy connector to just get EDID,
+ * all EVDI appear to have a DVI-D
+ */
+
+static int evdi_get_modes(struct drm_connector *connector)
+{
+ struct evdi_device *evdi = connector->dev->dev_private;
+ struct edid *edid = NULL;
+ int ret = 0;
+
+ edid = (struct edid *)evdi_painter_get_edid_copy(evdi);
+
+ if (!edid) {
+ drm_mode_connector_update_edid_property(connector, NULL);
+ return 0;
+ }
+
+ ret = drm_mode_connector_update_edid_property(connector, edid);
+ if (!ret)
+ drm_add_edid_modes(connector, edid);
+ else
+ EVDI_ERROR("Failed to set edid modes! error: %d", ret);
+
+ kfree(edid);
+ return ret;
+}
+
+static int evdi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct evdi_device *evdi = connector->dev->dev_private;
+ uint32_t mode_area = mode->hdisplay * mode->vdisplay;
+
+ if (evdi->sku_area_limit == 0)
+ return MODE_OK;
+
+ if (mode_area > evdi->sku_area_limit) {
+ EVDI_WARN("(dev=%d) Mode %dx%d@%d rejected\n",
+ evdi->dev_index,
+ mode->hdisplay,
+ mode->vdisplay,
+ drm_mode_vrefresh(mode));
+ return MODE_BAD;
+ }
+
+ return MODE_OK;
+}
+
+static enum drm_connector_status
+evdi_detect(struct drm_connector *connector, __always_unused bool force)
+{
+ struct evdi_device *evdi = connector->dev->dev_private;
+
+ EVDI_CHECKPT();
+ if (evdi_painter_is_connected(evdi)) {
+ EVDI_DEBUG("(dev=%d) Painter is connected\n", evdi->dev_index);
+ return connector_status_connected;
+ }
+ EVDI_DEBUG("(dev=%d) Painter is disconnected\n", evdi->dev_index);
+ return connector_status_disconnected;
+}
+
+static void evdi_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+}
+
+static struct drm_connector_helper_funcs evdi_connector_helper_funcs = {
+ .get_modes = evdi_get_modes,
+ .mode_valid = evdi_mode_valid,
+};
+
+static const struct drm_connector_funcs evdi_connector_funcs = {
+ .detect = evdi_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = evdi_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state
+};
+
+int evdi_connector_init(struct drm_device *dev, struct drm_encoder *encoder)
+{
+ struct drm_connector *connector;
+
+ connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
+ if (!connector)
+ return -ENOMEM;
+
+ /* TODO: Initialize connector with actual connector type */
+ drm_connector_init(dev, connector, &evdi_connector_funcs,
+ DRM_MODE_CONNECTOR_DVII);
+ drm_connector_helper_add(connector, &evdi_connector_helper_funcs);
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+ drm_connector_register(connector);
+ drm_mode_connector_attach_encoder(connector, encoder);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/evdi/evdi_cursor.c b/drivers/gpu/drm/evdi/evdi_cursor.c
new file mode 100644
index 0000000..ebc9952
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_cursor.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * evdi_cursor.c
+ *
+ * Copyright (c) 2016 The Chromium OS Authors
+ * Copyright (c) 2016 - 2017 DisplayLink (UK) Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <linux/compiler.h>
+#include <linux/mutex.h>
+
+#include "evdi_cursor.h"
+#include "evdi_drv.h"
+
+/*
+ * EVDI drm cursor private structure.
+ */
+struct evdi_cursor {
+ bool enabled;
+ int32_t x;
+ int32_t y;
+ uint32_t width;
+ uint32_t height;
+ int32_t hot_x;
+ int32_t hot_y;
+ uint32_t pixel_format;
+ uint32_t stride;
+ struct evdi_gem_object *obj;
+ struct mutex lock;
+};
+
+static void evdi_cursor_set_gem(struct evdi_cursor *cursor,
+ struct evdi_gem_object *obj)
+{
+ if (obj)
+ drm_gem_object_reference(&obj->base);
+ if (cursor->obj)
+ drm_gem_object_unreference_unlocked(&cursor->obj->base);
+
+ cursor->obj = obj;
+}
+
+struct evdi_gem_object *evdi_cursor_gem(struct evdi_cursor *cursor)
+{
+ return cursor->obj;
+}
+
+int evdi_cursor_init(struct evdi_cursor **cursor)
+{
+ if (WARN_ON(*cursor))
+ return -EINVAL;
+
+ *cursor = kzalloc(sizeof(struct evdi_cursor), GFP_KERNEL);
+ if (*cursor) {
+ mutex_init(&(*cursor)->lock);
+ return 0;
+ } else {
+ return -ENOMEM;
+ }
+}
+
+void evdi_cursor_lock(struct evdi_cursor *cursor)
+{
+ mutex_lock(&cursor->lock);
+}
+
+void evdi_cursor_unlock(struct evdi_cursor *cursor)
+{
+ mutex_unlock(&cursor->lock);
+}
+
+void evdi_cursor_free(struct evdi_cursor *cursor)
+{
+ if (WARN_ON(!cursor))
+ return;
+ evdi_cursor_set_gem(cursor, NULL);
+ kfree(cursor);
+}
+
+bool evdi_cursor_enabled(struct evdi_cursor *cursor)
+{
+ return cursor->enabled;
+}
+
+void evdi_cursor_enable(struct evdi_cursor *cursor, bool enable)
+{
+ evdi_cursor_lock(cursor);
+ cursor->enabled = enable;
+ if (!enable)
+ evdi_cursor_set_gem(cursor, NULL);
+ evdi_cursor_unlock(cursor);
+}
+
+void evdi_cursor_set(struct evdi_cursor *cursor,
+ struct evdi_gem_object *obj,
+ uint32_t width, uint32_t height,
+ int32_t hot_x, int32_t hot_y,
+ uint32_t pixel_format, uint32_t stride)
+{
+ int err = 0;
+
+ evdi_cursor_lock(cursor);
+ if (obj && !obj->vmapping)
+ err = evdi_gem_vmap(obj);
+
+ if (err != 0) {
+ EVDI_ERROR("Failed to map cursor.\n");
+ obj = NULL;
+ }
+
+ cursor->enabled = obj != NULL;
+ cursor->width = width;
+ cursor->height = height;
+ cursor->hot_x = hot_x;
+ cursor->hot_y = hot_y;
+ cursor->pixel_format = pixel_format;
+ cursor->stride = stride;
+ evdi_cursor_set_gem(cursor, obj);
+
+ evdi_cursor_unlock(cursor);
+}
+
+void evdi_cursor_move(struct evdi_cursor *cursor, int32_t x, int32_t y)
+{
+ evdi_cursor_lock(cursor);
+ cursor->x = x;
+ cursor->y = y;
+ evdi_cursor_unlock(cursor);
+}
+
+static inline uint32_t blend_component(uint32_t pixel,
+ uint32_t blend,
+ uint32_t alpha)
+{
+ uint32_t pre_blend = (pixel * (255 - alpha) + blend * alpha);
+
+ return (pre_blend + ((pre_blend + 1) << 8)) >> 16;
+}
+
+static inline uint32_t blend_alpha(const uint32_t pixel_val32,
+ uint32_t blend_val32)
+{
+ uint32_t alpha = (blend_val32 >> 24);
+
+ return blend_component(pixel_val32 & 0xff,
+ blend_val32 & 0xff, alpha) |
+ blend_component((pixel_val32 & 0xff00) >> 8,
+ (blend_val32 & 0xff00) >> 8, alpha) << 8 |
+ blend_component((pixel_val32 & 0xff0000) >> 16,
+ (blend_val32 & 0xff0000) >> 16, alpha) << 16;
+}
+
+static int evdi_cursor_compose_pixel(char __user *buffer,
+ int const cursor_value,
+ int const fb_value,
+ int cmd_offset)
+{
+ int const composed_value = blend_alpha(fb_value, cursor_value);
+
+ return copy_to_user(buffer + cmd_offset, &composed_value, 4);
+}
+
+int evdi_cursor_compose_and_copy(struct evdi_cursor *cursor,
+ struct evdi_framebuffer *ufb,
+ char __user *buffer,
+ int buf_byte_stride)
+{
+ int x, y;
+ struct drm_framebuffer *fb = &ufb->base;
+ const int h_cursor_w = cursor->width >> 1;
+ const int h_cursor_h = cursor->height >> 1;
+ uint32_t *cursor_buffer = NULL;
+ uint32_t bytespp = 0;
+
+ if (!cursor->enabled)
+ return 0;
+
+ if (!cursor->obj)
+ return -EINVAL;
+
+ if (!cursor->obj->vmapping)
+ return -EINVAL;
+
+ bytespp = evdi_fb_get_bpp(cursor->pixel_format);
+ bytespp = DIV_ROUND_UP(bytespp, 8);
+ if (bytespp != 4) {
+ EVDI_ERROR("Unsupported cursor format bpp=%u\n", bytespp);
+ return -EINVAL;
+ }
+
+ if (cursor->width * cursor->height * bytespp >
+ cursor->obj->base.size){
+ EVDI_ERROR("Wrong cursor size\n");
+ return -EINVAL;
+ }
+
+ cursor_buffer = (uint32_t *)cursor->obj->vmapping;
+
+ for (y = -h_cursor_h; y < h_cursor_h; ++y) {
+ for (x = -h_cursor_w; x < h_cursor_w; ++x) {
+ uint32_t curs_val;
+ int *fbsrc;
+ int fb_value;
+ int cmd_offset;
+ int cursor_pix;
+ int const mouse_pix_x = cursor->x + x + h_cursor_w;
+ int const mouse_pix_y = cursor->y + y + h_cursor_h;
+ bool const is_pix_sane =
+ mouse_pix_x >= 0 &&
+ mouse_pix_y >= 0 &&
+ mouse_pix_x < fb->width &&
+ mouse_pix_y < fb->height;
+
+ if (!is_pix_sane)
+ continue;
+
+ cursor_pix = h_cursor_w+x +
+ (h_cursor_h+y)*cursor->width;
+ curs_val = le32_to_cpu(cursor_buffer[cursor_pix]);
+ fbsrc = (int *)ufb->obj->vmapping;
+ fb_value = *(fbsrc + ((fb->pitches[0]>>2) *
+ mouse_pix_y + mouse_pix_x));
+ cmd_offset = (buf_byte_stride * mouse_pix_y) +
+ (mouse_pix_x * bytespp);
+ if (evdi_cursor_compose_pixel(buffer,
+ curs_val,
+ fb_value,
+ cmd_offset)) {
+ EVDI_ERROR("Failed to compose cursor pixel\n");
+ return -EFAULT;
+ }
+ }
+ }
+
+ return 0;
+}
+
+void evdi_cursor_position(struct evdi_cursor *cursor, int32_t *x, int32_t *y)
+{
+ *x = cursor->x;
+ *y = cursor->y;
+}
+
+void evdi_cursor_hotpoint(struct evdi_cursor *cursor,
+ int32_t *hot_x, int32_t *hot_y)
+{
+ *hot_x = cursor->hot_x;
+ *hot_y = cursor->hot_y;
+}
+
+void evdi_cursor_size(struct evdi_cursor *cursor,
+ uint32_t *width, uint32_t *height)
+{
+ *width = cursor->width;
+ *height = cursor->height;
+}
+
+void evdi_cursor_format(struct evdi_cursor *cursor, uint32_t *format)
+{
+ *format = cursor->pixel_format;
+}
+
+void evdi_cursor_stride(struct evdi_cursor *cursor, uint32_t *stride)
+{
+ *stride = cursor->stride;
+}
+
diff --git a/drivers/gpu/drm/evdi/evdi_cursor.h b/drivers/gpu/drm/evdi/evdi_cursor.h
new file mode 100644
index 0000000..5e8ca4c
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_cursor.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * evdi_cursor.h
+ *
+ * Copyright (c) 2016 The Chromium OS Authors
+ * Copyright (c) 2016 - 2017 DisplayLink (UK) Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _EVDI_CURSOR_H_
+#define _EVDI_CURSOR_H_
+
+#include <linux/module.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+
+struct evdi_cursor;
+struct evdi_framebuffer;
+struct evdi_gem_object;
+
+int evdi_cursor_init(struct evdi_cursor **cursor);
+void evdi_cursor_free(struct evdi_cursor *cursor);
+void evdi_cursor_lock(struct evdi_cursor *cursor);
+void evdi_cursor_unlock(struct evdi_cursor *cursor);
+bool evdi_cursor_enabled(struct evdi_cursor *cursor);
+void evdi_cursor_enable(struct evdi_cursor *cursor, bool enabled);
+void evdi_cursor_set(struct evdi_cursor *cursor,
+ struct evdi_gem_object *obj,
+ uint32_t width, uint32_t height,
+ int32_t hot_x, int32_t hot_y,
+ uint32_t pixel_format, uint32_t stride);
+
+void evdi_cursor_move(struct evdi_cursor *cursor, int32_t x, int32_t y);
+void evdi_cursor_position(struct evdi_cursor *cursor, int32_t *x, int32_t *y);
+void evdi_cursor_hotpoint(struct evdi_cursor *cursor,
+ int32_t *hot_x, int32_t *hot_y);
+void evdi_cursor_size(struct evdi_cursor *cursor,
+ uint32_t *width, uint32_t *height);
+void evdi_cursor_format(struct evdi_cursor *cursor, uint32_t *format);
+void evdi_cursor_stride(struct evdi_cursor *cursor, uint32_t *stride);
+struct evdi_gem_object *evdi_cursor_gem(struct evdi_cursor *cursor);
+
+int evdi_cursor_compose_and_copy(struct evdi_cursor *cursor,
+ struct evdi_framebuffer *ufb,
+ char __user *buffer,
+ int buf_byte_stride);
+#endif
diff --git a/drivers/gpu/drm/evdi/evdi_debug.c b/drivers/gpu/drm/evdi/evdi_debug.c
new file mode 100644
index 0000000..e3659b3
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_debug.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015 - 2016 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#include "evdi_debug.h"
+
+unsigned int evdi_loglevel = EVDI_LOGLEVEL_DEBUG;
+
+module_param_named(initial_loglevel, evdi_loglevel, int, 0400);
+MODULE_PARM_DESC(initial_loglevel, "Initial log level");
diff --git a/drivers/gpu/drm/evdi/evdi_debug.h b/drivers/gpu/drm/evdi/evdi_debug.h
new file mode 100644
index 0000000..fcd25d1
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_debug.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2015 - 2016 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef EVDI_DEBUG_H
+#define EVDI_DEBUG_H
+
+#define EVDI_LOGLEVEL_ALWAYS 0
+#define EVDI_LOGLEVEL_FATAL 1
+#define EVDI_LOGLEVEL_ERROR 2
+#define EVDI_LOGLEVEL_WARN 3
+#define EVDI_LOGLEVEL_INFO 4
+#define EVDI_LOGLEVEL_DEBUG 5
+#define EVDI_LOGLEVEL_VERBOSE 6
+
+extern unsigned int evdi_loglevel;
+
+#define EVDI_PRINTK(KERN_LEVEL, lEVEL, FORMAT_STR, ...) do { \
+ if (lEVEL <= evdi_loglevel) {\
+ printk(KERN_LEVEL "evdi: " FORMAT_STR, ##__VA_ARGS__); \
+ } \
+} while (0)
+
+#define EVDI_FATAL(FORMAT_STR, ...) \
+ EVDI_PRINTK(KERN_CRIT, EVDI_LOGLEVEL_FATAL,\
+ "[F] %s:%d " FORMAT_STR, __func__, __LINE__, ##__VA_ARGS__)
+
+#define EVDI_ERROR(FORMAT_STR, ...) \
+ EVDI_PRINTK(KERN_ERR, EVDI_LOGLEVEL_ERROR,\
+ "[E] %s:%d " FORMAT_STR, __func__, __LINE__, ##__VA_ARGS__)
+
+#define EVDI_WARN(FORMAT_STR, ...) \
+ EVDI_PRINTK(KERN_WARNING, EVDI_LOGLEVEL_WARN,\
+ "[W] %s:%d " FORMAT_STR, __func__, __LINE__, ##__VA_ARGS__)
+
+#define EVDI_INFO(FORMAT_STR, ...) \
+ EVDI_PRINTK(KERN_DEFAULT, EVDI_LOGLEVEL_INFO,\
+ "[I] " FORMAT_STR, ##__VA_ARGS__)
+
+#define EVDI_DEBUG(FORMAT_STR, ...) \
+ EVDI_PRINTK(KERN_DEFAULT, EVDI_LOGLEVEL_DEBUG,\
+ "[D] %s:%d " FORMAT_STR, __func__, __LINE__, ##__VA_ARGS__)
+
+#define EVDI_VERBOSE(FORMAT_STR, ...) \
+ EVDI_PRINTK(KERN_DEFAULT, EVDI_LOGLEVEL_VERBOSE,\
+ "[V] %s:%d " FORMAT_STR, __func__, __LINE__, ##__VA_ARGS__)
+
+#define EVDI_CHECKPT() EVDI_VERBOSE("\n")
+#define EVDI_ENTER() EVDI_VERBOSE("enter\n")
+#define EVDI_EXIT() EVDI_VERBOSE("exit\n")
+
+#endif /* EVDI_DEBUG_H */
+
diff --git a/drivers/gpu/drm/evdi/evdi_drv.c b/drivers/gpu/drm/evdi/evdi_drv.c
new file mode 100644
index 0000000..26ba8916
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_drv.c
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_crtc_helper.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "evdi_drv.h"
+#include <uapi/drm/evdi_drm.h>
+#include "evdi_debug.h"
+#include "evdi_cursor.h"
+
+MODULE_AUTHOR("DisplayLink (UK) Ltd.");
+MODULE_DESCRIPTION("Extensible Virtual Display Interface");
+MODULE_LICENSE("GPL");
+
+#define EVDI_DEVICE_COUNT_MAX 16
+
+static struct evdi_context {
+ struct device *root_dev;
+ unsigned int dev_count;
+ struct platform_device *devices[EVDI_DEVICE_COUNT_MAX];
+} evdi_context;
+
+static struct drm_driver driver;
+
+struct drm_ioctl_desc evdi_painter_ioctls[] = {
+ DRM_IOCTL_DEF_DRV(EVDI_CONNECT, evdi_painter_connect_ioctl,
+ DRM_UNLOCKED),
+ DRM_IOCTL_DEF_DRV(EVDI_REQUEST_UPDATE,
+ evdi_painter_request_update_ioctl,
+ DRM_UNLOCKED),
+ DRM_IOCTL_DEF_DRV(EVDI_GRABPIX, evdi_painter_grabpix_ioctl,
+ DRM_UNLOCKED),
+};
+
+static const struct vm_operations_struct evdi_gem_vm_ops = {
+ .fault = evdi_gem_fault,
+ .open = drm_gem_vm_open,
+ .close = drm_gem_vm_close,
+};
+
+static const struct file_operations evdi_driver_fops = {
+ .owner = THIS_MODULE,
+ .open = drm_open,
+ .mmap = evdi_drm_gem_mmap,
+ .poll = drm_poll,
+ .read = drm_read,
+ .unlocked_ioctl = drm_ioctl,
+ .release = drm_release,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = evdi_compat_ioctl,
+#endif
+ .llseek = noop_llseek,
+};
+
+static int evdi_enable_vblank(__always_unused struct drm_device *dev,
+ __always_unused unsigned int pipe)
+{
+ return 1;
+}
+
+static void evdi_disable_vblank(__always_unused struct drm_device *dev,
+ __always_unused unsigned int pipe)
+{
+}
+
+static struct drm_driver driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
+ DRIVER_ATOMIC,
+ .load = evdi_driver_load,
+ .unload = evdi_driver_unload,
+ .preclose = evdi_driver_preclose,
+
+ /* gem hooks */
+ .gem_free_object = evdi_gem_free_object,
+ .gem_vm_ops = &evdi_gem_vm_ops,
+
+ .dumb_create = evdi_dumb_create,
+ .dumb_map_offset = evdi_gem_mmap,
+ .dumb_destroy = drm_gem_dumb_destroy,
+
+ .ioctls = evdi_painter_ioctls,
+ .num_ioctls = ARRAY_SIZE(evdi_painter_ioctls),
+
+ .fops = &evdi_driver_fops,
+
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_import = evdi_gem_prime_import,
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .gem_prime_export = evdi_gem_prime_export,
+
+ .enable_vblank = evdi_enable_vblank,
+ .disable_vblank = evdi_disable_vblank,
+
+ .name = DRIVER_NAME,
+ .desc = DRIVER_DESC,
+ .date = DRIVER_DATE,
+ .major = DRIVER_MAJOR,
+ .minor = DRIVER_MINOR,
+ .patchlevel = DRIVER_PATCHLEVEL,
+};
+
+static void evdi_add_device(void)
+{
+ struct platform_device_info pdevinfo = {
+ .parent = NULL,
+ .name = "evdi",
+ .id = evdi_context.dev_count,
+ .res = NULL,
+ .num_res = 0,
+ .data = NULL,
+ .size_data = 0,
+ .dma_mask = DMA_BIT_MASK(32),
+ };
+
+ evdi_context.devices[evdi_context.dev_count] =
+ platform_device_register_full(&pdevinfo);
+ if (dma_set_mask(&evdi_context.devices[evdi_context.dev_count]->dev,
+ DMA_BIT_MASK(64))) {
+ EVDI_DEBUG("Unable to change dma mask to 64 bit. ");
+ EVDI_DEBUG("Sticking with 32 bit\n");
+ }
+ evdi_context.dev_count++;
+}
+
+
+int evdi_driver_setup_early(struct drm_device *dev)
+{
+ struct platform_device *platdev = NULL;
+ struct evdi_device *evdi;
+ int ret;
+
+ EVDI_CHECKPT();
+ evdi = kzalloc(sizeof(struct evdi_device), GFP_KERNEL);
+ if (!evdi)
+ return -ENOMEM;
+
+ evdi->ddev = dev;
+ dev->dev_private = evdi;
+
+ ret = evdi_cursor_init(&evdi->cursor);
+ if (ret)
+ goto err;
+
+ EVDI_CHECKPT();
+ evdi_modeset_init(dev);
+
+ if (ret)
+ goto err;
+
+ ret = evdi_fbdev_init(dev);
+ if (ret)
+ goto err;
+
+ ret = drm_vblank_init(dev, 1);
+ if (ret)
+ goto err_fb;
+
+ ret = evdi_painter_init(evdi);
+ if (ret)
+ goto err_fb;
+
+ drm_kms_helper_poll_init(dev);
+
+ platdev = to_platform_device(dev->dev);
+ platform_set_drvdata(platdev, dev);
+
+ return 0;
+
+err_fb:
+ evdi_fbdev_cleanup(dev);
+err:
+ kfree(evdi);
+ EVDI_ERROR("%d\n", ret);
+ if (evdi->cursor)
+ evdi_cursor_free(evdi->cursor);
+ return ret;
+}
+
+static int evdi_platform_probe(struct platform_device *pdev)
+{
+ struct drm_device *dev;
+ int ret;
+
+ EVDI_CHECKPT();
+
+ dev = drm_dev_alloc(&driver, &pdev->dev);
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
+
+ ret = evdi_driver_setup_early(dev);
+ if (ret)
+ goto err_free;
+
+ ret = drm_dev_register(dev, 0);
+ if (ret)
+ goto err_free;
+
+ evdi_driver_setup_late(dev);
+
+ return 0;
+
+err_free:
+ drm_dev_unref(dev);
+ return ret;
+}
+
+static int evdi_platform_remove(struct platform_device *pdev)
+{
+ struct drm_device *drm_dev =
+ (struct drm_device *)platform_get_drvdata(pdev);
+ EVDI_CHECKPT();
+
+ drm_dev_unplug(drm_dev);
+
+ return 0;
+}
+
+static void evdi_remove_all(void)
+{
+ int i;
+
+ EVDI_DEBUG("removing all evdi devices\n");
+ for (i = 0; i < evdi_context.dev_count; ++i) {
+ if (evdi_context.devices[i]) {
+ EVDI_DEBUG("removing evdi %d\n", i);
+
+ platform_device_unregister(evdi_context.devices[i]);
+ evdi_context.devices[i] = NULL;
+ }
+ }
+ evdi_context.dev_count = 0;
+}
+
+static struct platform_driver evdi_platform_driver = {
+ .probe = evdi_platform_probe,
+ .remove = evdi_platform_remove,
+ .driver = {
+ .name = "evdi",
+ .mod_name = KBUILD_MODNAME,
+ .owner = THIS_MODULE,
+ }
+};
+
+static ssize_t version_show(__always_unused struct device *dev,
+ __always_unused struct device_attribute *attr,
+ char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%u.%u.%u\n", DRIVER_MAJOR,
+ DRIVER_MINOR, DRIVER_PATCHLEVEL);
+}
+
+static ssize_t count_show(__always_unused struct device *dev,
+ __always_unused struct device_attribute *attr,
+ char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%u\n", evdi_context.dev_count);
+}
+
+static ssize_t add_store(__always_unused struct device *dev,
+ __always_unused struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned int val;
+
+ if (kstrtouint(buf, 10, &val)) {
+ EVDI_ERROR("Invalid device count \"%s\"\n", buf);
+ return -EINVAL;
+ }
+ if (val == 0) {
+ EVDI_WARN("Adding 0 devices has no effect\n");
+ return count;
+ }
+ if (val > EVDI_DEVICE_COUNT_MAX - evdi_context.dev_count) {
+ EVDI_ERROR("Evdi device add failed. Too many devices.\n");
+ return -EINVAL;
+ }
+
+ EVDI_DEBUG("Increasing device count to %u\n",
+ evdi_context.dev_count + val);
+ while (val--)
+ evdi_add_device();
+
+ return count;
+}
+
+static ssize_t remove_all_store(__always_unused struct device *dev,
+ __always_unused struct device_attribute *attr,
+ __always_unused const char *buf,
+ size_t count)
+{
+ evdi_remove_all();
+ return count;
+}
+
+static ssize_t loglevel_show(__always_unused struct device *dev,
+ __always_unused struct device_attribute *attr,
+ char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%u\n", evdi_loglevel);
+}
+
+static ssize_t loglevel_store(__always_unused struct device *dev,
+ __always_unused struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ unsigned int val;
+
+ if (kstrtouint(buf, 10, &val)) {
+ EVDI_ERROR("Unable to parse %u\n", val);
+ return -EINVAL;
+ }
+ if (val > EVDI_LOGLEVEL_VERBOSE) {
+ EVDI_ERROR("Invalid loglevel %u\n", val);
+ return -EINVAL;
+ }
+
+ EVDI_INFO("Setting loglevel to %u\n", val);
+ evdi_loglevel = val;
+ return count;
+}
+
+static struct device_attribute evdi_device_attributes[] = {
+ __ATTR_RO(count),
+ __ATTR_RO(version),
+ __ATTR_RW(loglevel),
+ __ATTR_WO(add),
+ __ATTR_WO(remove_all)
+};
+
+static int __init evdi_init(void)
+{
+ int i;
+
+ EVDI_INFO("Initialising logging on level %u\n", evdi_loglevel);
+ EVDI_INFO("Atomic driver:%s",
+ (driver.driver_features & DRIVER_ATOMIC) ? "yes" : "no");
+ evdi_context.root_dev = root_device_register("evdi");
+ if (!PTR_RET(evdi_context.root_dev))
+ for (i = 0; i < ARRAY_SIZE(evdi_device_attributes); i++) {
+ device_create_file(evdi_context.root_dev,
+ &evdi_device_attributes[i]);
+ }
+
+ return platform_driver_register(&evdi_platform_driver);
+}
+
+static void __exit evdi_exit(void)
+{
+ int i;
+
+ EVDI_CHECKPT();
+ evdi_remove_all();
+ platform_driver_unregister(&evdi_platform_driver);
+
+ if (!PTR_RET(evdi_context.root_dev)) {
+ for (i = 0; i < ARRAY_SIZE(evdi_device_attributes); i++) {
+ device_remove_file(evdi_context.root_dev,
+ &evdi_device_attributes[i]);
+ }
+ root_device_unregister(evdi_context.root_dev);
+ }
+}
+
+module_init(evdi_init);
+module_exit(evdi_exit);
+
+bool evdi_enable_cursor_blending __read_mostly = true;
+module_param_named(enable_cursor_blending,
+ evdi_enable_cursor_blending, bool, 0644);
+MODULE_PARM_DESC(enable_cursor_blending, "Enables cursor compositing on user supplied framebuffer via EVDI_GRABPIX ioctl. (default: true)");
+
diff --git a/drivers/gpu/drm/evdi/evdi_drv.h b/drivers/gpu/drm/evdi/evdi_drv.h
new file mode 100644
index 0000000..4e17b458
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_drv.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * Based on parts on udlfb.c:
+ * Copyright (C) 2009 its respective authors
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef EVDI_DRV_H
+#define EVDI_DRV_H
+
+#include <linux/module.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_rect.h>
+# include <drm/drm_gem.h>
+#include <drm/drm_cache.h>
+#include <linux/reservation.h>
+#include "evdi_debug.h"
+
+#define DRIVER_NAME "evdi"
+#define DRIVER_DESC "Extensible Virtual Display Interface"
+#define DRIVER_DATE "20180315"
+
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 5
+#define DRIVER_PATCHLEVEL 0
+
+struct evdi_fbdev;
+struct evdi_painter;
+
+extern bool evdi_enable_cursor_blending __read_mostly;
+
+struct evdi_device {
+ struct device *dev;
+ struct drm_device *ddev;
+ struct evdi_cursor *cursor;
+ uint32_t sku_area_limit;
+
+ struct evdi_fbdev *fbdev;
+ struct evdi_painter *painter;
+
+ atomic_t frame_count;
+
+ int dev_index;
+};
+
+struct evdi_gem_object {
+ struct drm_gem_object base;
+ struct page **pages;
+ void *vmapping;
+ struct sg_table *sg;
+ struct reservation_object *resv;
+ struct reservation_object _resv;
+};
+
+#define to_evdi_bo(x) container_of(x, struct evdi_gem_object, base)
+
+struct evdi_framebuffer {
+ struct drm_framebuffer base;
+ struct evdi_gem_object *obj;
+ bool active;
+};
+
+#define to_evdi_fb(x) container_of(x, struct evdi_framebuffer, base)
+
+/* modeset */
+void evdi_modeset_init(struct drm_device *dev);
+void evdi_modeset_cleanup(struct drm_device *dev);
+int evdi_connector_init(struct drm_device *dev, struct drm_encoder *encoder);
+
+struct drm_encoder *evdi_encoder_init(struct drm_device *dev);
+
+int evdi_driver_load(struct drm_device *dev, unsigned long flags);
+void evdi_driver_unload(struct drm_device *dev);
+void evdi_driver_preclose(struct drm_device *dev, struct drm_file *file_priv);
+
+#ifdef CONFIG_COMPAT
+long evdi_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
+#endif
+
+int evdi_fbdev_init(struct drm_device *dev);
+void evdi_fbdev_cleanup(struct drm_device *dev);
+void evdi_fbdev_unplug(struct drm_device *dev);
+struct drm_framebuffer *evdi_fb_user_fb_create(
+ struct drm_device *dev,
+ struct drm_file *file,
+ const struct drm_mode_fb_cmd2 *mode_cmd);
+
+int evdi_dumb_create(struct drm_file *file_priv,
+ struct drm_device *dev, struct drm_mode_create_dumb *args);
+int evdi_gem_mmap(struct drm_file *file_priv,
+ struct drm_device *dev, uint32_t handle, uint64_t *offset);
+
+void evdi_gem_free_object(struct drm_gem_object *gem_obj);
+struct evdi_gem_object *evdi_gem_alloc_object(struct drm_device *dev,
+ size_t size);
+uint32_t evdi_gem_object_handle_lookup(struct drm_file *filp,
+ struct drm_gem_object *obj);
+
+struct drm_gem_object *evdi_gem_prime_import(struct drm_device *dev,
+ struct dma_buf *dma_buf);
+struct dma_buf *evdi_gem_prime_export(struct drm_device *dev,
+ struct drm_gem_object *obj, int flags);
+
+int evdi_gem_vmap(struct evdi_gem_object *obj);
+void evdi_gem_vunmap(struct evdi_gem_object *obj);
+int evdi_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+int evdi_gem_fault(struct vm_fault *vmf);
+void evdi_stats_init(struct evdi_device *evdi);
+void evdi_stats_cleanup(struct evdi_device *evdi);
+
+bool evdi_painter_is_connected(struct evdi_device *evdi);
+void evdi_painter_close(struct evdi_device *evdi, struct drm_file *file);
+u8 *evdi_painter_get_edid_copy(struct evdi_device *evdi);
+void evdi_painter_mark_dirty(struct evdi_device *evdi,
+ const struct drm_clip_rect *rect);
+void evdi_painter_send_update_ready_if_needed(struct evdi_device *evdi);
+void evdi_painter_dpms_notify(struct evdi_device *evdi, int mode);
+void evdi_painter_mode_changed_notify(struct evdi_device *evdi,
+ struct drm_display_mode *mode);
+void evdi_painter_crtc_state_notify(struct evdi_device *evdi, int state);
+unsigned int evdi_painter_poll(struct file *filp,
+ struct poll_table_struct *wait);
+
+int evdi_painter_status_ioctl(struct drm_device *drm_dev, void *data,
+ struct drm_file *file);
+int evdi_painter_connect_ioctl(struct drm_device *drm_dev, void *data,
+ struct drm_file *file);
+int evdi_painter_grabpix_ioctl(struct drm_device *drm_dev, void *data,
+ struct drm_file *file);
+int evdi_painter_request_update_ioctl(struct drm_device *drm_dev, void *data,
+ struct drm_file *file);
+
+int evdi_painter_init(struct evdi_device *evdi);
+void evdi_painter_cleanup(struct evdi_device *evdi);
+void evdi_painter_set_new_scanout_buffer(struct evdi_device *evdi,
+ struct evdi_framebuffer *buffer);
+void evdi_painter_commit_scanout_buffer(struct evdi_device *evdi);
+
+struct drm_clip_rect evdi_framebuffer_sanitize_rect(
+ const struct evdi_framebuffer *fb,
+ const struct drm_clip_rect *rect);
+
+int evdi_driver_setup_early(struct drm_device *dev);
+void evdi_driver_setup_late(struct drm_device *dev);
+
+void evdi_painter_send_cursor_set(struct evdi_painter *painter,
+ struct evdi_cursor *cursor);
+void evdi_painter_send_cursor_move(struct evdi_painter *painter,
+ struct evdi_cursor *cursor);
+bool evdi_painter_needs_full_modeset(struct evdi_device *evdi);
+
+int evdi_fb_get_bpp(uint32_t format);
+#endif
+
diff --git a/drivers/gpu/drm/evdi/evdi_encoder.c b/drivers/gpu/drm/evdi/evdi_encoder.c
new file mode 100644
index 0000000..7adfe0d
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_encoder.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * Based on parts on udlfb.c:
+ * Copyright (C) 2009 its respective authors
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include "evdi_drv.h"
+
+/* dummy encoder */
+static void evdi_enc_destroy(struct drm_encoder *encoder)
+{
+ drm_encoder_cleanup(encoder);
+ kfree(encoder);
+}
+
+static const struct drm_encoder_funcs evdi_enc_funcs = {
+ .destroy = evdi_enc_destroy,
+};
+
+struct drm_encoder *evdi_encoder_init(struct drm_device *dev)
+{
+ struct drm_encoder *encoder;
+ int ret = 0;
+
+ encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
+ if (!encoder)
+ goto err;
+
+ ret = drm_encoder_init(dev, encoder, &evdi_enc_funcs,
+ DRM_MODE_ENCODER_TMDS, NULL);
+ if (ret) {
+ EVDI_ERROR("Failed to initialize encoder: %d\n", ret);
+ goto err_encoder;
+ }
+
+ encoder->possible_crtcs = 1;
+ return encoder;
+
+err_encoder:
+ kfree(encoder);
+err:
+ return NULL;
+}
diff --git a/drivers/gpu/drm/evdi/evdi_fb.c b/drivers/gpu/drm/evdi/evdi_fb.c
new file mode 100644
index 0000000..f5f4724
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_fb.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * Based on parts on udlfb.c:
+ * Copyright (C) 2009 its respective authors
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/dma-buf.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
+#include "evdi_drv.h"
+
+
+struct evdi_fbdev {
+ struct drm_fb_helper helper;
+ struct evdi_framebuffer ufb;
+ struct list_head fbdev_list;
+ int fb_count;
+};
+
+struct drm_clip_rect evdi_framebuffer_sanitize_rect(
+ const struct evdi_framebuffer *fb,
+ const struct drm_clip_rect *dirty_rect)
+{
+ struct drm_clip_rect rect = *dirty_rect;
+
+ if (rect.x1 > rect.x2) {
+ unsigned short tmp = rect.x2;
+
+ EVDI_WARN("Wrong clip rect: x1 > x2\n");
+ rect.x2 = rect.x1;
+ rect.x1 = tmp;
+ }
+
+ if (rect.y1 > rect.y2) {
+ unsigned short tmp = rect.y2;
+
+ EVDI_WARN("Wrong clip rect: y1 > y2\n");
+ rect.y2 = rect.y1;
+ rect.y1 = tmp;
+ }
+
+
+ if (rect.x1 > fb->base.width) {
+ EVDI_WARN("Wrong clip rect: x1 > fb.width\n");
+ rect.x1 = fb->base.width;
+ }
+
+ if (rect.y1 > fb->base.height) {
+ EVDI_WARN("Wrong clip rect: y1 > fb.height\n");
+ rect.y1 = fb->base.height;
+ }
+
+ if (rect.x2 > fb->base.width) {
+ EVDI_VERBOSE("Wrong clip rect: x2 > fb.width\n");
+ rect.x2 = fb->base.width;
+ }
+
+ if (rect.y2 > fb->base.height) {
+ EVDI_VERBOSE("Wrong clip rect: y2 > fb.height\n");
+ rect.y2 = fb->base.height;
+ }
+
+ return rect;
+}
+
+static int evdi_handle_damage(struct evdi_framebuffer *fb,
+ int x, int y, int width, int height)
+{
+ const struct drm_clip_rect dirty_rect = { x, y, x + width, y + height };
+ const struct drm_clip_rect rect =
+ evdi_framebuffer_sanitize_rect(fb, &dirty_rect);
+ struct drm_device *dev = fb->base.dev;
+ struct evdi_device *evdi = dev->dev_private;
+
+ EVDI_CHECKPT();
+
+ if (!fb->active)
+ return 0;
+ evdi_painter_set_new_scanout_buffer(evdi, fb);
+ evdi_painter_commit_scanout_buffer(evdi);
+ evdi_painter_mark_dirty(evdi, &rect);
+
+ return 0;
+}
+
+static int evdi_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+ unsigned long start = vma->vm_start;
+ unsigned long size = vma->vm_end - vma->vm_start;
+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+ unsigned long page, pos;
+
+ if (offset > info->fix.smem_len ||
+ size > info->fix.smem_len - offset)
+ return -EINVAL;
+
+ pos = (unsigned long)info->fix.smem_start + offset;
+
+ pr_notice("mmap() framebuffer addr:%lu size:%lu\n", pos, size);
+
+ while (size > 0) {
+ page = vmalloc_to_pfn((void *)pos);
+ if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
+ return -EAGAIN;
+
+ start += PAGE_SIZE;
+ pos += PAGE_SIZE;
+ if (size > PAGE_SIZE)
+ size -= PAGE_SIZE;
+ else
+ size = 0;
+ }
+
+ return 0;
+}
+
+static void evdi_fb_fillrect(struct fb_info *info,
+ const struct fb_fillrect *rect)
+{
+ struct evdi_fbdev *ufbdev = info->par;
+
+ EVDI_CHECKPT();
+ sys_fillrect(info, rect);
+ evdi_handle_damage(&ufbdev->ufb, rect->dx, rect->dy, rect->width,
+ rect->height);
+}
+
+static void evdi_fb_copyarea(struct fb_info *info,
+ const struct fb_copyarea *region)
+{
+ struct evdi_fbdev *ufbdev = info->par;
+
+ EVDI_CHECKPT();
+ sys_copyarea(info, region);
+ evdi_handle_damage(&ufbdev->ufb, region->dx, region->dy, region->width,
+ region->height);
+}
+
+static void evdi_fb_imageblit(struct fb_info *info,
+ const struct fb_image *image)
+{
+ struct evdi_fbdev *ufbdev = info->par;
+
+ EVDI_CHECKPT();
+ sys_imageblit(info, image);
+ evdi_handle_damage(&ufbdev->ufb, image->dx, image->dy, image->width,
+ image->height);
+}
+
+/*
+ * It's common for several clients to have framebuffer open simultaneously.
+ * e.g. both fbcon and X. Makes things interesting.
+ * Assumes caller is holding info->lock (for open and release at least)
+ */
+static int evdi_fb_open(struct fb_info *info, int user)
+{
+ struct evdi_fbdev *ufbdev = info->par;
+
+ ufbdev->fb_count++;
+ pr_notice("open /dev/fb%d user=%d fb_info=%p count=%d\n",
+ info->node, user, info, ufbdev->fb_count);
+
+ return 0;
+}
+
+/*
+ * Assumes caller is holding info->lock mutex (for open and release at least)
+ */
+static int evdi_fb_release(struct fb_info *info, int user)
+{
+ struct evdi_fbdev *ufbdev = info->par;
+
+ ufbdev->fb_count--;
+
+ pr_warn("released /dev/fb%d user=%d count=%d\n",
+ info->node, user, ufbdev->fb_count);
+
+ return 0;
+}
+
+static struct fb_ops evdifb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = drm_fb_helper_check_var,
+ .fb_set_par = drm_fb_helper_set_par,
+ .fb_fillrect = evdi_fb_fillrect,
+ .fb_copyarea = evdi_fb_copyarea,
+ .fb_imageblit = evdi_fb_imageblit,
+ .fb_pan_display = drm_fb_helper_pan_display,
+ .fb_blank = drm_fb_helper_blank,
+ .fb_setcmap = drm_fb_helper_setcmap,
+ .fb_debug_enter = drm_fb_helper_debug_enter,
+ .fb_debug_leave = drm_fb_helper_debug_leave,
+ .fb_mmap = evdi_fb_mmap,
+ .fb_open = evdi_fb_open,
+ .fb_release = evdi_fb_release,
+};
+
+static int evdi_user_framebuffer_dirty(struct drm_framebuffer *fb,
+ __always_unused struct drm_file *file,
+ __always_unused unsigned int flags,
+ __always_unused unsigned int color,
+ struct drm_clip_rect *clips,
+ unsigned int num_clips)
+{
+ struct evdi_framebuffer *ufb = to_evdi_fb(fb);
+ struct drm_device *dev = ufb->base.dev;
+ struct evdi_device *evdi = dev->dev_private;
+ int i;
+ int ret = 0;
+
+ EVDI_CHECKPT();
+ drm_modeset_lock_all(fb->dev);
+
+ if (!ufb->active)
+ goto unlock;
+
+ if (ufb->obj->base.import_attach) {
+ ret =
+ dma_buf_begin_cpu_access(
+ ufb->obj->base.import_attach->dmabuf,
+ DMA_FROM_DEVICE);
+ if (ret)
+ goto unlock;
+ }
+
+ for (i = 0; i < num_clips; i++) {
+ ret = evdi_handle_damage(ufb, clips[i].x1, clips[i].y1,
+ clips[i].x2 - clips[i].x1,
+ clips[i].y2 - clips[i].y1);
+ if (ret)
+ goto unlock;
+ }
+
+ if (ufb->obj->base.import_attach)
+ dma_buf_end_cpu_access(ufb->obj->base.import_attach->dmabuf,
+ DMA_FROM_DEVICE);
+ atomic_add(1, &evdi->frame_count);
+ unlock:
+ drm_modeset_unlock_all(fb->dev);
+ return ret;
+}
+
+static int evdi_user_framebuffer_create_handle(struct drm_framebuffer *fb,
+ struct drm_file *file_priv,
+ unsigned int *handle)
+{
+ struct evdi_framebuffer *efb = to_evdi_fb(fb);
+
+ return drm_gem_handle_create(file_priv, &efb->obj->base, handle);
+}
+
+static void evdi_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
+ struct evdi_framebuffer *ufb = to_evdi_fb(fb);
+
+ EVDI_CHECKPT();
+
+ if (ufb->obj)
+ drm_gem_object_unreference_unlocked(&ufb->obj->base);
+
+ drm_framebuffer_cleanup(fb);
+ kfree(ufb);
+}
+
+static const struct drm_framebuffer_funcs evdifb_funcs = {
+ .create_handle = evdi_user_framebuffer_create_handle,
+ .destroy = evdi_user_framebuffer_destroy,
+ .dirty = evdi_user_framebuffer_dirty,
+};
+
+static int
+evdi_framebuffer_init(struct drm_device *dev,
+ struct evdi_framebuffer *ufb,
+ const struct drm_mode_fb_cmd2 *mode_cmd,
+ struct evdi_gem_object *obj)
+{
+ ufb->obj = obj;
+ drm_helper_mode_fill_fb_struct(dev, &ufb->base, mode_cmd);
+ return drm_framebuffer_init(dev, &ufb->base, &evdifb_funcs);
+}
+
+static int evdifb_create(struct drm_fb_helper *helper,
+ struct drm_fb_helper_surface_size *sizes)
+{
+ struct evdi_fbdev *ufbdev = (struct evdi_fbdev *)helper;
+ struct drm_device *dev = ufbdev->helper.dev;
+ struct fb_info *info;
+ struct device *device = dev->dev;
+ struct drm_framebuffer *fb;
+ struct drm_mode_fb_cmd2 mode_cmd;
+ struct evdi_gem_object *obj;
+ uint32_t size;
+ int ret = 0;
+
+ if (sizes->surface_bpp == 24) {
+ sizes->surface_bpp = 32;
+ } else if (sizes->surface_bpp != 32) {
+ EVDI_ERROR("Not supported pixel format (bpp=%d)\n",
+ sizes->surface_bpp);
+ return -EINVAL;
+ }
+
+ mode_cmd.width = sizes->surface_width;
+ mode_cmd.height = sizes->surface_height;
+ mode_cmd.pitches[0] = mode_cmd.width * ((sizes->surface_bpp + 7) / 8);
+
+ mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
+ sizes->surface_depth);
+
+ size = mode_cmd.pitches[0] * mode_cmd.height;
+ size = ALIGN(size, PAGE_SIZE);
+
+ obj = evdi_gem_alloc_object(dev, size);
+ if (!obj)
+ goto out;
+
+ ret = evdi_gem_vmap(obj);
+ if (ret) {
+ DRM_ERROR("failed to vmap fb\n");
+ goto out_gfree;
+ }
+
+ info = framebuffer_alloc(0, device);
+ if (!info) {
+ ret = -ENOMEM;
+ goto out_gfree;
+ }
+ info->par = ufbdev;
+
+ ret = evdi_framebuffer_init(dev, &ufbdev->ufb, &mode_cmd, obj);
+ if (ret)
+ goto out_gfree;
+
+ fb = &ufbdev->ufb.base;
+
+ ufbdev->helper.fb = fb;
+ ufbdev->helper.fbdev = info;
+
+ strcpy(info->fix.id, "evdidrmfb");
+
+ info->screen_base = ufbdev->ufb.obj->vmapping;
+ info->fix.smem_len = size;
+ info->fix.smem_start = (unsigned long)ufbdev->ufb.obj->vmapping;
+
+ info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
+ info->fbops = &evdifb_ops;
+ drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
+ drm_fb_helper_fill_var(info, &ufbdev->helper, sizes->fb_width,
+ sizes->fb_height);
+
+ ret = fb_alloc_cmap(&info->cmap, 256, 0);
+ if (ret) {
+ ret = -ENOMEM;
+ goto out_gfree;
+ }
+
+ DRM_DEBUG_KMS("allocated %dx%d vmal %p\n",
+ fb->width, fb->height, ufbdev->ufb.obj->vmapping);
+
+ return ret;
+ out_gfree:
+ drm_gem_object_unreference_unlocked(&ufbdev->ufb.obj->base);
+ out:
+ return ret;
+}
+
+static struct drm_fb_helper_funcs evdi_fb_helper_funcs = {
+ .fb_probe = evdifb_create,
+};
+
+static void evdi_fbdev_destroy(__always_unused struct drm_device *dev,
+ struct evdi_fbdev *ufbdev)
+{
+ struct fb_info *info;
+
+ if (ufbdev->helper.fbdev) {
+ info = ufbdev->helper.fbdev;
+ unregister_framebuffer(info);
+
+ if (info->cmap.len)
+ fb_dealloc_cmap(&info->cmap);
+
+ framebuffer_release(info);
+ }
+ drm_fb_helper_fini(&ufbdev->helper);
+ drm_framebuffer_unregister_private(&ufbdev->ufb.base);
+ drm_framebuffer_cleanup(&ufbdev->ufb.base);
+ drm_gem_object_unreference_unlocked(&ufbdev->ufb.obj->base);
+}
+
+int evdi_fbdev_init(struct drm_device *dev)
+{
+ struct evdi_device *evdi;
+ struct evdi_fbdev *ufbdev;
+ int ret;
+
+ evdi = dev->dev_private;
+ ufbdev = kzalloc(sizeof(struct evdi_fbdev), GFP_KERNEL);
+ if (!ufbdev)
+ return -ENOMEM;
+
+ evdi->fbdev = ufbdev;
+ drm_fb_helper_prepare(dev, &ufbdev->helper, &evdi_fb_helper_funcs);
+
+ ret = drm_fb_helper_init(dev, &ufbdev->helper, 1);
+ if (ret) {
+ kfree(ufbdev);
+ return ret;
+ }
+
+ drm_fb_helper_single_add_all_connectors(&ufbdev->helper);
+
+ ret = drm_fb_helper_initial_config(&ufbdev->helper, 32);
+ if (ret) {
+ drm_fb_helper_fini(&ufbdev->helper);
+ kfree(ufbdev);
+ }
+ return ret;
+}
+
+void evdi_fbdev_cleanup(struct drm_device *dev)
+{
+ struct evdi_device *evdi = dev->dev_private;
+
+ if (!evdi->fbdev)
+ return;
+
+ evdi_fbdev_destroy(dev, evdi->fbdev);
+ kfree(evdi->fbdev);
+ evdi->fbdev = NULL;
+}
+
+void evdi_fbdev_unplug(struct drm_device *dev)
+{
+ struct evdi_device *evdi = dev->dev_private;
+ struct evdi_fbdev *ufbdev;
+
+ if (!evdi->fbdev)
+ return;
+
+ ufbdev = evdi->fbdev;
+ if (ufbdev->helper.fbdev) {
+ struct fb_info *info;
+
+ info = ufbdev->helper.fbdev;
+ unlink_framebuffer(info);
+ }
+}
+
+int evdi_fb_get_bpp(uint32_t format)
+{
+ const struct drm_format_info *info;
+
+ info = drm_format_info(format);
+ if (info && info->depth)
+ return info->cpp[0] * 8;
+ return 0;
+}
+
+struct drm_framebuffer *evdi_fb_user_fb_create(
+ struct drm_device *dev,
+ struct drm_file *file,
+ const struct drm_mode_fb_cmd2 *mode_cmd)
+{
+ struct drm_gem_object *obj;
+ struct evdi_framebuffer *ufb;
+ int ret;
+ uint32_t size;
+
+ int bpp = evdi_fb_get_bpp(mode_cmd->pixel_format);
+
+ if (bpp != 32) {
+ EVDI_ERROR("Unsupported bpp (%d)\n", bpp);
+ return ERR_PTR(-EINVAL);
+ }
+
+ obj = drm_gem_object_lookup(file, mode_cmd->handles[0]);
+ if (obj == NULL)
+ return ERR_PTR(-ENOENT);
+
+ size = mode_cmd->pitches[0] * mode_cmd->height;
+ size = ALIGN(size, PAGE_SIZE);
+
+ if (size > obj->size) {
+ DRM_ERROR("object size not sufficient for fb %d %zu %d %d\n",
+ size, obj->size, mode_cmd->pitches[0],
+ mode_cmd->height);
+ goto err_no_mem;
+ }
+
+ ufb = kzalloc(sizeof(*ufb), GFP_KERNEL);
+ if (ufb == NULL)
+ goto err_no_mem;
+
+ ret = evdi_framebuffer_init(dev, ufb, mode_cmd, to_evdi_bo(obj));
+ if (ret)
+ goto err_inval;
+ return &ufb->base;
+
+ err_no_mem:
+ drm_gem_object_unreference(obj);
+ return ERR_PTR(-ENOMEM);
+ err_inval:
+ kfree(ufb);
+ drm_gem_object_unreference(obj);
+ return ERR_PTR(-EINVAL);
+}
diff --git a/drivers/gpu/drm/evdi/evdi_gem.c b/drivers/gpu/drm/evdi/evdi_gem.c
new file mode 100644
index 0000000..2795554
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_gem.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <drm/drmP.h>
+#include "evdi_drv.h"
+#include <linux/shmem_fs.h>
+#include <linux/dma-buf.h>
+
+uint32_t evdi_gem_object_handle_lookup(struct drm_file *filp,
+ struct drm_gem_object *obj)
+{
+ uint32_t it_handle = 0;
+ struct drm_gem_object *it_obj = NULL;
+
+ spin_lock(&filp->table_lock);
+ idr_for_each_entry(&filp->object_idr, it_obj, it_handle) {
+ if (it_obj == obj)
+ break;
+ }
+ spin_unlock(&filp->table_lock);
+
+ if (!it_obj)
+ it_handle = 0;
+
+ return it_handle;
+}
+
+struct evdi_gem_object *evdi_gem_alloc_object(struct drm_device *dev,
+ size_t size)
+{
+ struct evdi_gem_object *obj;
+
+ obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+ if (obj == NULL)
+ return NULL;
+
+ if (drm_gem_object_init(dev, &obj->base, size) != 0) {
+ kfree(obj);
+ return NULL;
+ }
+
+ reservation_object_init(&obj->_resv);
+ obj->resv = &obj->_resv;
+
+ return obj;
+}
+
+static int
+evdi_gem_create(struct drm_file *file,
+ struct drm_device *dev, uint64_t size, uint32_t *handle_p)
+{
+ struct evdi_gem_object *obj;
+ int ret;
+ u32 handle;
+
+ size = roundup(size, PAGE_SIZE);
+
+ obj = evdi_gem_alloc_object(dev, size);
+ if (obj == NULL)
+ return -ENOMEM;
+
+ ret = drm_gem_handle_create(file, &obj->base, &handle);
+ if (ret) {
+ drm_gem_object_release(&obj->base);
+ kfree(obj);
+ return ret;
+ }
+
+ drm_gem_object_unreference_unlocked(&obj->base);
+ *handle_p = handle;
+ return 0;
+}
+
+int evdi_dumb_create(struct drm_file *file,
+ struct drm_device *dev, struct drm_mode_create_dumb *args)
+{
+ args->pitch = args->width * DIV_ROUND_UP(args->bpp, 8);
+ args->size = args->pitch * args->height;
+ return evdi_gem_create(file, dev, args->size, &args->handle);
+}
+
+int evdi_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ int ret;
+
+ ret = drm_gem_mmap(filp, vma);
+ if (ret)
+ return ret;
+
+ vma->vm_flags &= ~VM_PFNMAP;
+ vma->vm_flags |= VM_MIXEDMAP;
+
+ return ret;
+}
+
+int evdi_gem_fault(struct vm_fault *vmf)
+{
+ struct vm_area_struct *vma = vmf->vma;
+ struct evdi_gem_object *obj = to_evdi_bo(vma->vm_private_data);
+ struct page *page;
+ unsigned int page_offset;
+ int ret = 0;
+
+ page_offset = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
+
+ if (!obj->pages)
+ return VM_FAULT_SIGBUS;
+
+ page = obj->pages[page_offset];
+ ret = vm_insert_page(vma, (unsigned long)vmf->address, page);
+ switch (ret) {
+ case -EAGAIN:
+ case 0:
+ case -ERESTARTSYS:
+ return VM_FAULT_NOPAGE;
+ case -ENOMEM:
+ return VM_FAULT_OOM;
+ default:
+ return VM_FAULT_SIGBUS;
+ }
+ return VM_FAULT_SIGBUS;
+}
+
+static int evdi_gem_get_pages(struct evdi_gem_object *obj)
+{
+ struct page **pages;
+
+ if (obj->pages)
+ return 0;
+
+ pages = drm_gem_get_pages(&obj->base);
+ if (IS_ERR(pages))
+ return PTR_ERR(pages);
+
+ obj->pages = pages;
+
+#if defined(CONFIG_X86)
+ drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
+#endif
+
+ return 0;
+}
+
+static void evdi_gem_put_pages(struct evdi_gem_object *obj)
+{
+ if (obj->base.import_attach) {
+ kvfree(obj->pages);
+ obj->pages = NULL;
+ return;
+ }
+ if (obj->pages)
+ drm_gem_put_pages(&obj->base, obj->pages, false, false);
+ obj->pages = NULL;
+}
+
+int evdi_gem_vmap(struct evdi_gem_object *obj)
+{
+ int page_count = obj->base.size / PAGE_SIZE;
+ int ret;
+
+ if (obj->base.import_attach) {
+ obj->vmapping = dma_buf_vmap(obj->base.import_attach->dmabuf);
+ if (!obj->vmapping)
+ return -ENOMEM;
+ return 0;
+ }
+
+ ret = evdi_gem_get_pages(obj);
+ if (ret)
+ return ret;
+
+ obj->vmapping = vmap(obj->pages, page_count, 0, PAGE_KERNEL);
+ if (!obj->vmapping)
+ return -ENOMEM;
+ return 0;
+}
+
+void evdi_gem_vunmap(struct evdi_gem_object *obj)
+{
+ if (obj->base.import_attach) {
+ dma_buf_vunmap(obj->base.import_attach->dmabuf, obj->vmapping);
+ obj->vmapping = NULL;
+ return;
+ }
+
+ if (obj->vmapping) {
+ vunmap(obj->vmapping);
+ obj->vmapping = NULL;
+ }
+
+ evdi_gem_put_pages(obj);
+}
+
+void evdi_gem_free_object(struct drm_gem_object *gem_obj)
+{
+ struct evdi_gem_object *obj = to_evdi_bo(gem_obj);
+
+ if (obj->vmapping)
+ evdi_gem_vunmap(obj);
+
+ if (gem_obj->import_attach) {
+ drm_prime_gem_destroy(gem_obj, obj->sg);
+ put_device(gem_obj->dev->dev);
+ }
+
+ if (obj->pages)
+ evdi_gem_put_pages(obj);
+
+ if (gem_obj->dev->vma_offset_manager)
+ drm_gem_free_mmap_offset(gem_obj);
+
+ reservation_object_fini(&obj->_resv);
+ obj->resv = NULL;
+}
+
+/*
+ * the dumb interface doesn't work with the GEM straight MMAP
+ * interface, it expects to do MMAP on the drm fd, like normal
+ */
+int evdi_gem_mmap(struct drm_file *file,
+ struct drm_device *dev, uint32_t handle, uint64_t *offset)
+{
+ struct evdi_gem_object *gobj;
+ struct drm_gem_object *obj;
+ int ret = 0;
+
+ mutex_lock(&dev->struct_mutex);
+ obj = drm_gem_object_lookup(file, handle);
+ if (obj == NULL) {
+ ret = -ENOENT;
+ goto unlock;
+ }
+ gobj = to_evdi_bo(obj);
+
+ ret = evdi_gem_get_pages(gobj);
+ if (ret)
+ goto out;
+
+ ret = drm_gem_create_mmap_offset(obj);
+ if (ret)
+ goto out;
+
+ *offset = drm_vma_node_offset_addr(&gobj->base.vma_node);
+
+ out:
+ drm_gem_object_unreference(&gobj->base);
+ unlock:
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
+}
+
+static int evdi_prime_create(struct drm_device *dev,
+ size_t size,
+ struct sg_table *sg,
+ struct evdi_gem_object **obj_p)
+{
+ struct evdi_gem_object *obj;
+ int npages;
+
+ npages = size / PAGE_SIZE;
+
+ *obj_p = NULL;
+ obj = evdi_gem_alloc_object(dev, npages * PAGE_SIZE);
+ if (!obj)
+ return -ENOMEM;
+
+ obj->sg = sg;
+ obj->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
+ if (obj->pages == NULL) {
+ DRM_ERROR("obj pages is NULL %d\n", npages);
+ return -ENOMEM;
+ }
+
+ drm_prime_sg_to_page_addr_arrays(sg, obj->pages, NULL, npages);
+
+ *obj_p = obj;
+ return 0;
+}
+
+struct evdi_drm_dmabuf_attachment {
+ struct sg_table sgt;
+ enum dma_data_direction dir;
+ bool is_mapped;
+};
+
+static int evdi_attach_dma_buf(__always_unused struct dma_buf *dmabuf,
+ __always_unused struct device *dev,
+ struct dma_buf_attachment *attach)
+{
+ struct evdi_drm_dmabuf_attachment *evdi_attach;
+
+ evdi_attach = kzalloc(sizeof(*evdi_attach), GFP_KERNEL);
+ if (!evdi_attach)
+ return -ENOMEM;
+
+ evdi_attach->dir = DMA_NONE;
+ attach->priv = evdi_attach;
+
+ return 0;
+}
+
+static void evdi_detach_dma_buf(__always_unused struct dma_buf *dmabuf,
+ struct dma_buf_attachment *attach)
+{
+ struct evdi_drm_dmabuf_attachment *evdi_attach = attach->priv;
+ struct sg_table *sgt;
+
+ if (!evdi_attach)
+ return;
+
+ sgt = &evdi_attach->sgt;
+
+ if (evdi_attach->dir != DMA_NONE)
+ dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents,
+ evdi_attach->dir);
+
+ sg_free_table(sgt);
+ kfree(evdi_attach);
+ attach->priv = NULL;
+}
+
+static struct sg_table *evdi_map_dma_buf(struct dma_buf_attachment *attach,
+ enum dma_data_direction dir)
+{
+ struct evdi_drm_dmabuf_attachment *evdi_attach = attach->priv;
+ struct evdi_gem_object *obj = to_evdi_bo(attach->dmabuf->priv);
+ struct drm_device *dev = obj->base.dev;
+ struct scatterlist *rd, *wr;
+ struct sg_table *sgt = NULL;
+ unsigned int i;
+ int page_count;
+ int nents, ret;
+
+ DRM_DEBUG_PRIME("[DEV:%s] size:%zd dir=%d\n", dev_name(attach->dev),
+ attach->dmabuf->size, dir);
+
+ /* just return current sgt if already requested. */
+ if (evdi_attach->dir == dir && evdi_attach->is_mapped)
+ return &evdi_attach->sgt;
+
+ if (!obj->pages) {
+ ret = evdi_gem_get_pages(obj);
+ if (ret) {
+ DRM_ERROR("failed to map pages.\n");
+ return ERR_PTR(ret);
+ }
+ }
+
+ page_count = obj->base.size / PAGE_SIZE;
+ obj->sg = drm_prime_pages_to_sg(obj->pages, page_count);
+ if (IS_ERR(obj->sg)) {
+ DRM_ERROR("failed to allocate sgt.\n");
+ return ERR_CAST(obj->sg);
+ }
+
+ sgt = &evdi_attach->sgt;
+
+ ret = sg_alloc_table(sgt, obj->sg->orig_nents, GFP_KERNEL);
+ if (ret) {
+ DRM_ERROR("failed to alloc sgt.\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ mutex_lock(&dev->struct_mutex);
+
+ rd = obj->sg->sgl;
+ wr = sgt->sgl;
+ for (i = 0; i < sgt->orig_nents; ++i) {
+ sg_set_page(wr, sg_page(rd), rd->length, rd->offset);
+ rd = sg_next(rd);
+ wr = sg_next(wr);
+ }
+
+ if (dir != DMA_NONE) {
+ nents = dma_map_sg(attach->dev, sgt->sgl, sgt->orig_nents, dir);
+ if (!nents) {
+ DRM_ERROR("failed to map sgl with iommu.\n");
+ sg_free_table(sgt);
+ sgt = ERR_PTR(-EIO);
+ goto err_unlock;
+ }
+ }
+
+ evdi_attach->is_mapped = true;
+ evdi_attach->dir = dir;
+ attach->priv = evdi_attach;
+
+ err_unlock:
+ mutex_unlock(&dev->struct_mutex);
+ return sgt;
+}
+
+static void evdi_unmap_dma_buf(
+ __always_unused struct dma_buf_attachment *attach,
+ __always_unused struct sg_table *sgt,
+ __always_unused enum dma_data_direction dir)
+{
+}
+
+static void *evdi_dmabuf_kmap(__always_unused struct dma_buf *dma_buf,
+ __always_unused unsigned long page_num)
+{
+ return NULL;
+}
+
+static void *evdi_dmabuf_kmap_atomic(__always_unused struct dma_buf *dma_buf,
+ __always_unused unsigned long page_num)
+{
+ return NULL;
+}
+
+static void evdi_dmabuf_kunmap(
+ __always_unused struct dma_buf *dma_buf,
+ __always_unused unsigned long page_num,
+ __always_unused void *addr)
+{
+}
+
+static void evdi_dmabuf_kunmap_atomic(
+ __always_unused struct dma_buf *dma_buf,
+ __always_unused unsigned long page_num,
+ __always_unused void *addr)
+{
+}
+
+static int evdi_dmabuf_mmap(__always_unused struct dma_buf *dma_buf,
+ __always_unused struct vm_area_struct *vma)
+{
+ return -EINVAL;
+}
+
+static struct dma_buf_ops evdi_dmabuf_ops = {
+
+ .attach = evdi_attach_dma_buf,
+ .detach = evdi_detach_dma_buf,
+ .map_dma_buf = evdi_map_dma_buf,
+ .unmap_dma_buf = evdi_unmap_dma_buf,
+ .map = evdi_dmabuf_kmap,
+ .map_atomic = evdi_dmabuf_kmap_atomic,
+ .unmap = evdi_dmabuf_kunmap,
+ .unmap_atomic = evdi_dmabuf_kunmap_atomic,
+ .mmap = evdi_dmabuf_mmap,
+ .release = drm_gem_dmabuf_release,
+};
+
+struct drm_gem_object *evdi_gem_prime_import(struct drm_device *dev,
+ struct dma_buf *dma_buf)
+{
+ struct dma_buf_attachment *attach;
+ struct sg_table *sg;
+ struct evdi_gem_object *uobj;
+ int ret;
+
+ /* check if our object */
+ if (dma_buf->ops == &evdi_dmabuf_ops) {
+ uobj = to_evdi_bo(dma_buf->priv);
+ if (uobj->base.dev == dev) {
+ drm_gem_object_reference(&uobj->base);
+ return &uobj->base;
+ }
+ }
+
+ /* need to attach */
+ get_device(dev->dev);
+ attach = dma_buf_attach(dma_buf, dev->dev);
+ if (IS_ERR(attach)) {
+ put_device(dev->dev);
+ return ERR_CAST(attach);
+ }
+
+ get_dma_buf(dma_buf);
+
+ sg = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
+ if (IS_ERR(sg)) {
+ ret = PTR_ERR(sg);
+ goto fail_detach;
+ }
+
+ ret = evdi_prime_create(dev, dma_buf->size, sg, &uobj);
+ if (ret)
+ goto fail_unmap;
+
+ uobj->base.import_attach = attach;
+ uobj->resv = attach->dmabuf->resv;
+
+ return &uobj->base;
+
+ fail_unmap:
+ dma_buf_unmap_attachment(attach, sg, DMA_BIDIRECTIONAL);
+ fail_detach:
+ dma_buf_detach(dma_buf, attach);
+ dma_buf_put(dma_buf);
+ put_device(dev->dev);
+ return ERR_PTR(ret);
+}
+
+struct dma_buf *evdi_gem_prime_export(struct drm_device *dev,
+ struct drm_gem_object *obj, int flags)
+{
+ DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
+ struct evdi_gem_object *evdi_obj = to_evdi_bo(obj);
+
+ exp_info.exp_name = "evdi",
+ exp_info.ops = &evdi_dmabuf_ops,
+ exp_info.size = obj->size,
+ exp_info.flags = flags,
+ exp_info.resv = evdi_obj->resv,
+ exp_info.priv = obj;
+
+ return drm_gem_dmabuf_export(dev, &exp_info);
+}
diff --git a/drivers/gpu/drm/evdi/evdi_ioc32.c b/drivers/gpu/drm/evdi/evdi_ioc32.c
new file mode 100644
index 0000000..28f6f17
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_ioc32.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/**
+ * evdi_ioc32.c
+ *
+ * Copyright (c) 2016 The Chromium OS Authors
+ * Copyright (c) 2018 DisplayLink (UK) Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/compat.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_edid.h>
+#include <uapi/drm/evdi_drm.h>
+
+#include "evdi_drv.h"
+
+struct drm_evdi_connect32 {
+ int32_t connected;
+ int32_t dev_index;
+ uint32_t edid_ptr32;
+ uint32_t edid_length;
+ uint32_t sku_area_limit;
+};
+
+struct drm_evdi_grabpix32 {
+ uint32_t mode;
+ int32_t buf_width;
+ int32_t buf_height;
+ int32_t buf_byte_stride;
+ uint32_t buffer_ptr32;
+ int32_t num_rects;
+ uint32_t rects_ptr32;
+};
+
+static int compat_evdi_connect(struct file *file,
+ unsigned int __always_unused cmd,
+ unsigned long arg)
+{
+ struct drm_evdi_connect32 req32;
+ struct drm_evdi_connect __user *request;
+
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
+ return -EFAULT;
+
+ request = compat_alloc_user_space(sizeof(*request));
+ if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
+ || __put_user(req32.connected, &request->connected)
+ || __put_user(req32.dev_index, &request->dev_index)
+ || __put_user((void __user *)(unsigned long)req32.edid_ptr32,
+ &request->edid)
+ || __put_user(req32.edid_length, &request->edid_length)
+ || __put_user(req32.sku_area_limit, &request->sku_area_limit))
+ return -EFAULT;
+
+ return drm_ioctl(file, DRM_IOCTL_EVDI_CONNECT,
+ (unsigned long)request);
+}
+
+static int compat_evdi_grabpix(struct file *file,
+ unsigned int __always_unused cmd,
+ unsigned long arg)
+{
+ struct drm_evdi_grabpix32 req32;
+ struct drm_evdi_grabpix __user *request;
+
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
+ return -EFAULT;
+
+ request = compat_alloc_user_space(sizeof(*request));
+ if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
+ || __put_user(req32.mode, &request->mode)
+ || __put_user(req32.buf_width, &request->buf_width)
+ || __put_user(req32.buf_height, &request->buf_height)
+ || __put_user(req32.buf_byte_stride, &request->buf_byte_stride)
+ || __put_user((void __user *)(unsigned long)req32.buffer_ptr32,
+ &request->buffer)
+ || __put_user(req32.num_rects, &request->num_rects)
+ || __put_user((void __user *)(unsigned long)req32.rects_ptr32,
+ &request->rects))
+ return -EFAULT;
+
+ return drm_ioctl(file, DRM_IOCTL_EVDI_GRABPIX,
+ (unsigned long)request);
+}
+
+static drm_ioctl_compat_t *evdi_compat_ioctls[] = {
+ [DRM_EVDI_CONNECT] = compat_evdi_connect,
+ [DRM_EVDI_GRABPIX] = compat_evdi_grabpix,
+};
+
+/**
+ * Called whenever a 32-bit process running under a 64-bit kernel
+ * performs an ioctl on /dev/dri/card<n>.
+ *
+ * \param filp file pointer.
+ * \param cmd command.
+ * \param arg user argument.
+ * \return zero on success or negative number on failure.
+ */
+long evdi_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ unsigned int nr = DRM_IOCTL_NR(cmd);
+ drm_ioctl_compat_t *fn = NULL;
+ int ret;
+
+ if (nr < DRM_COMMAND_BASE || nr >= DRM_COMMAND_END)
+ return drm_compat_ioctl(filp, cmd, arg);
+
+ if (nr < DRM_COMMAND_BASE + ARRAY_SIZE(evdi_compat_ioctls))
+ fn = evdi_compat_ioctls[nr - DRM_COMMAND_BASE];
+
+ if (fn != NULL)
+ ret = (*fn) (filp, cmd, arg);
+ else
+ ret = drm_ioctl(filp, cmd, arg);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/evdi/evdi_main.c b/drivers/gpu/drm/evdi/evdi_main.c
new file mode 100644
index 0000000..95c3d05
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_main.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * Based on parts on udlfb.c:
+ * Copyright (C) 2009 its respective authors
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <linux/platform_device.h>
+#include <drm/drmP.h>
+#include "evdi_drv.h"
+#include "evdi_cursor.h"
+
+int evdi_driver_load(struct drm_device *dev,
+ __always_unused unsigned long flags)
+{
+ struct platform_device *platdev = NULL;
+ struct evdi_device *evdi;
+ int ret;
+
+ EVDI_CHECKPT();
+ evdi = kzalloc(sizeof(struct evdi_device), GFP_KERNEL);
+ if (!evdi)
+ return -ENOMEM;
+
+ evdi->ddev = dev;
+ dev->dev_private = evdi;
+
+ ret = evdi_cursor_init(&evdi->cursor);
+ if (ret)
+ goto err;
+
+ EVDI_CHECKPT();
+ evdi_modeset_init(dev);
+
+ ret = evdi_fbdev_init(dev);
+ if (ret)
+ goto err;
+
+ ret = drm_vblank_init(dev, 1);
+ if (ret)
+ goto err_fb;
+
+ ret = evdi_painter_init(evdi);
+ if (ret)
+ goto err_fb;
+
+ evdi_stats_init(evdi);
+
+ drm_kms_helper_poll_init(dev);
+
+ platdev = to_platform_device(dev->dev);
+ platform_set_drvdata(platdev, dev);
+
+ return 0;
+
+err_fb:
+ evdi_fbdev_cleanup(dev);
+err:
+ kfree(evdi);
+ EVDI_ERROR("%d\n", ret);
+ if (evdi->cursor)
+ evdi_cursor_free(evdi->cursor);
+ return ret;
+}
+
+void evdi_driver_setup_late(struct drm_device *dev)
+{
+ evdi_stats_init(dev->dev_private);
+}
+
+void evdi_driver_unload(struct drm_device *dev)
+{
+ struct evdi_device *evdi = dev->dev_private;
+
+ EVDI_CHECKPT();
+
+ drm_kms_helper_poll_fini(dev);
+ evdi_fbdev_unplug(dev);
+ if (evdi->cursor)
+ evdi_cursor_free(evdi->cursor);
+ evdi_painter_cleanup(evdi);
+ evdi_stats_cleanup(evdi);
+ evdi_fbdev_cleanup(dev);
+ evdi_modeset_cleanup(dev);
+
+ kfree(evdi);
+}
+
+void evdi_driver_preclose(struct drm_device *drm_dev, struct drm_file *file)
+{
+ struct evdi_device *evdi = drm_dev->dev_private;
+
+ EVDI_CHECKPT();
+ if (evdi)
+ evdi_painter_close(evdi, file);
+}
+
diff --git a/drivers/gpu/drm/evdi/evdi_modeset.c b/drivers/gpu/drm/evdi/evdi_modeset.c
new file mode 100644
index 0000000..1cd75e8
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_modeset.c
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Red Hat
+ * Copyright (c) 2015 - 2018 DisplayLink (UK) Ltd.
+ *
+ * Based on parts on udlfb.c:
+ * Copyright (C) 2009 its respective authors
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_atomic_helper.h>
+#include <uapi/drm/evdi_drm.h>
+#include "evdi_drv.h"
+#include "evdi_cursor.h"
+
+static void evdi_crtc_dpms(
+ __always_unused struct drm_crtc *crtc,
+ __always_unused int mode)
+{
+ EVDI_CHECKPT();
+}
+
+static void evdi_crtc_destroy(struct drm_crtc *crtc)
+{
+ EVDI_CHECKPT();
+ drm_crtc_cleanup(crtc);
+ kfree(crtc);
+}
+
+static void evdi_crtc_commit(__always_unused struct drm_crtc *crtc)
+{
+ EVDI_CHECKPT();
+}
+
+static void evdi_crtc_atomic_flush(
+ struct drm_crtc *crtc,
+ __always_unused struct drm_crtc_state *old_state)
+{
+ struct drm_crtc_state *state = crtc->state;
+ struct evdi_device *evdi = crtc->dev->dev_private;
+ unsigned long flags;
+
+ if (state->event) {
+ spin_lock_irqsave(&crtc->dev->event_lock, flags);
+ drm_crtc_send_vblank_event(crtc, state->event);
+ state->event = NULL;
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+ }
+ if (state->mode_changed && state->active)
+ evdi_painter_mode_changed_notify(evdi, &state->adjusted_mode);
+
+ if (state->active_changed)
+ evdi_painter_dpms_notify(evdi,
+ state->active ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF);
+
+ evdi_painter_send_update_ready_if_needed(evdi);
+}
+
+static void evdi_crtc_mark_full_screen_dirty(struct evdi_device *evdi,
+ struct drm_crtc *crtc)
+{
+ if (crtc && crtc->primary && crtc->primary->fb) {
+ struct drm_clip_rect rect = {
+ 0,
+ 0,
+ crtc->primary->fb->width,
+ crtc->primary->fb->height
+ };
+
+ evdi_painter_mark_dirty(evdi, &rect);
+ evdi_painter_send_update_ready_if_needed(evdi);
+ }
+}
+
+static int evdi_crtc_cursor_set(struct drm_crtc *crtc,
+ struct drm_file *file,
+ uint32_t handle,
+ uint32_t width,
+ uint32_t height,
+ int32_t hot_x,
+ int32_t hot_y)
+{
+ struct drm_device *dev = crtc->dev;
+ struct evdi_device *evdi = dev->dev_private;
+ struct drm_gem_object *obj = NULL;
+ struct evdi_gem_object *eobj = NULL;
+ /*
+ * evdi_crtc_cursor_set is callback function using
+ * deprecated cursor entry point.
+ * There is no info about underlaying pixel format.
+ * Hence we are assuming that it is in ARGB 32bpp format.
+ * This format it the only one supported in cursor composition
+ * function.
+ * This format is also enforced during framebuffer creation.
+ *
+ * Proper format will be available when driver start support
+ * universal planes for cursor.
+ */
+ uint32_t format = DRM_FORMAT_ARGB8888;
+ uint32_t stride = 4 * width;
+
+ EVDI_CHECKPT();
+ if (handle) {
+ mutex_lock(&dev->struct_mutex);
+ obj = drm_gem_object_lookup(file, handle);
+ if (obj)
+ eobj = to_evdi_bo(obj);
+ else
+ EVDI_ERROR("Failed to lookup gem object.\n");
+ mutex_unlock(&dev->struct_mutex);
+ }
+
+ evdi_cursor_set(evdi->cursor,
+ eobj, width, height, hot_x, hot_y,
+ format, stride);
+ drm_gem_object_unreference_unlocked(obj);
+
+ if (evdi_enable_cursor_blending)
+ evdi_crtc_mark_full_screen_dirty(evdi, crtc);
+ else
+ evdi_painter_send_cursor_set(evdi->painter, evdi->cursor);
+ return 0;
+}
+
+static int evdi_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+{
+ struct drm_device *dev = crtc->dev;
+ struct evdi_device *evdi = dev->dev_private;
+
+ evdi_cursor_move(evdi->cursor, x, y);
+
+ if (evdi_enable_cursor_blending)
+ evdi_crtc_mark_full_screen_dirty(evdi, crtc);
+ else
+ evdi_painter_send_cursor_move(evdi->painter, evdi->cursor);
+ return 0;
+}
+
+static struct drm_crtc_helper_funcs evdi_helper_funcs = {
+ .atomic_flush = evdi_crtc_atomic_flush,
+
+ .dpms = evdi_crtc_dpms,
+ .commit = evdi_crtc_commit,
+};
+
+
+static const struct drm_crtc_funcs evdi_crtc_funcs = {
+ .reset = drm_atomic_helper_crtc_reset,
+ .destroy = evdi_crtc_destroy,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+
+ .cursor_set2 = evdi_crtc_cursor_set,
+ .cursor_move = evdi_crtc_cursor_move,
+};
+
+static void evdi_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ if (plane && plane->state && plane->state->fb &&
+ plane->dev && plane->dev->dev_private) {
+ struct drm_plane_state *state = plane->state;
+ struct drm_framebuffer *fb = state->fb;
+ struct evdi_framebuffer *efb = to_evdi_fb(fb);
+ struct evdi_device *evdi = plane->dev->dev_private;
+
+ const struct drm_clip_rect rect = {
+ 0, 0, fb->width, fb->height
+ };
+
+ evdi_painter_mark_dirty(evdi, &rect);
+
+ if (state->fb != old_state->fb ||
+ evdi_painter_needs_full_modeset(evdi)) {
+ evdi_painter_set_new_scanout_buffer(evdi, efb);
+ evdi_painter_commit_scanout_buffer(evdi);
+ }
+ }
+}
+
+static void evdi_cursor_atomic_get_rect(struct drm_clip_rect *rect,
+ struct drm_plane_state *state)
+{
+ rect->x1 = (state->crtc_x < 0) ? 0 : state->crtc_x;
+ rect->y1 = (state->crtc_y < 0) ? 0 : state->crtc_y;
+ rect->x2 = state->crtc_x + state->crtc_w;
+ rect->y2 = state->crtc_y + state->crtc_h;
+}
+
+static void evdi_cursor_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ if (plane && plane->state && plane->dev && plane->dev->dev_private) {
+ struct drm_plane_state *state = plane->state;
+ struct evdi_device *evdi = plane->dev->dev_private;
+ struct drm_framebuffer *fb = state->fb;
+ struct evdi_framebuffer *efb = to_evdi_fb(fb);
+
+ struct drm_clip_rect old_rect;
+ struct drm_clip_rect rect;
+ bool cursor_changed = false;
+ bool cursor_position_changed = false;
+ int32_t cursor_position_x = 0;
+ int32_t cursor_position_y = 0;
+
+ mutex_lock(&plane->dev->struct_mutex);
+
+ evdi_cursor_position(evdi->cursor, &cursor_position_x,
+ &cursor_position_y);
+ evdi_cursor_move(evdi->cursor, state->crtc_x, state->crtc_y);
+ cursor_position_changed = cursor_position_x != state->crtc_x ||
+ cursor_position_y != state->crtc_y;
+
+ if (fb != old_state->fb) {
+ if (fb != NULL) {
+ uint32_t stride = 4 * fb->width;
+
+ evdi_cursor_set(evdi->cursor,
+ efb->obj,
+ fb->width,
+ fb->height,
+ 0,
+ 0,
+ fb->format->format,
+ stride);
+ }
+
+ evdi_cursor_enable(evdi->cursor, fb != NULL);
+ cursor_changed = true;
+ }
+
+ mutex_unlock(&plane->dev->struct_mutex);
+
+ if (evdi_enable_cursor_blending) {
+ evdi_cursor_atomic_get_rect(&old_rect, old_state);
+ evdi_cursor_atomic_get_rect(&rect, state);
+
+ evdi_painter_mark_dirty(evdi, &old_rect);
+ evdi_painter_mark_dirty(evdi, &rect);
+ return;
+ }
+ if (cursor_changed)
+ evdi_painter_send_cursor_set(evdi->painter,
+ evdi->cursor);
+ if (cursor_position_changed)
+ evdi_painter_send_cursor_move(evdi->painter,
+ evdi->cursor);
+ }
+}
+
+static const struct drm_plane_helper_funcs evdi_plane_helper_funcs = {
+ .atomic_update = evdi_plane_atomic_update
+};
+
+static const struct drm_plane_helper_funcs evdi_cursor_helper_funcs = {
+ .atomic_update = evdi_cursor_atomic_update
+};
+
+static const struct drm_plane_funcs evdi_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = drm_plane_cleanup,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static const uint32_t formats[] = {
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+};
+
+static struct drm_plane *evdi_create_plane(
+ struct drm_device *dev,
+ enum drm_plane_type type,
+ const struct drm_plane_helper_funcs *helper_funcs)
+{
+ struct drm_plane *plane;
+ int ret;
+
+ plane = kzalloc(sizeof(*plane), GFP_KERNEL);
+ if (plane == NULL) {
+ EVDI_ERROR("Failed to allocate primary plane\n");
+ return NULL;
+ }
+ plane->format_default = true;
+
+ ret = drm_universal_plane_init(dev,
+ plane,
+ 0xFF,
+ &evdi_plane_funcs,
+ formats,
+ ARRAY_SIZE(formats),
+ NULL,
+ type, NULL);
+ if (ret) {
+ EVDI_ERROR("Failed to initialize primary plane\n");
+ kfree(plane);
+ return NULL;
+ }
+
+ drm_plane_helper_add(plane, helper_funcs);
+
+ return plane;
+}
+
+static int evdi_crtc_init(struct drm_device *dev)
+{
+ struct drm_crtc *crtc = NULL;
+ struct drm_plane *primary = NULL;
+ int status = 0;
+
+ EVDI_CHECKPT();
+ crtc = kzalloc(sizeof(struct drm_crtc), GFP_KERNEL);
+ if (crtc == NULL)
+ return -ENOMEM;
+
+ primary = evdi_create_plane(dev, DRM_PLANE_TYPE_PRIMARY,
+ &evdi_plane_helper_funcs);
+ status = drm_crtc_init_with_planes(dev, crtc, primary, NULL,
+ &evdi_crtc_funcs, NULL);
+
+ EVDI_INFO("drm_crtc_init: %d p%p\n", status, primary);
+ drm_crtc_helper_add(crtc, &evdi_helper_funcs);
+
+ return 0;
+}
+
+static int evdi_atomic_check(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state = NULL;
+ int i;
+ struct evdi_device *evdi = dev->dev_private;
+
+
+ if (evdi_painter_needs_full_modeset(evdi)) {
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ crtc_state->active_changed = true;
+ crtc_state->mode_changed = true;
+ }
+ }
+
+ return drm_atomic_helper_check(dev, state);
+}
+
+
+static const struct drm_mode_config_funcs evdi_mode_funcs = {
+ .fb_create = evdi_fb_user_fb_create,
+ .output_poll_changed = NULL,
+ .atomic_commit = drm_atomic_helper_commit,
+ .atomic_check = evdi_atomic_check
+};
+
+void evdi_modeset_init(struct drm_device *dev)
+{
+ struct drm_encoder *encoder;
+
+ EVDI_CHECKPT();
+ drm_mode_config_init(dev);
+
+ dev->mode_config.min_width = 64;
+ dev->mode_config.min_height = 64;
+
+ dev->mode_config.max_width = 3840;
+ dev->mode_config.max_height = 2160;
+
+ dev->mode_config.prefer_shadow = 0;
+ dev->mode_config.preferred_depth = 24;
+
+ dev->mode_config.funcs = &evdi_mode_funcs;
+
+ drm_dev_set_unique(dev, dev_name(dev->dev));
+ evdi_crtc_init(dev);
+
+ encoder = evdi_encoder_init(dev);
+
+ evdi_connector_init(dev, encoder);
+
+ drm_mode_config_reset(dev);
+}
+
+void evdi_modeset_cleanup(struct drm_device *dev)
+{
+ EVDI_CHECKPT();
+ drm_mode_config_cleanup(dev);
+}
diff --git a/drivers/gpu/drm/evdi/evdi_painter.c b/drivers/gpu/drm/evdi/evdi_painter.c
new file mode 100644
index 0000000..09421fd
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_painter.c
@@ -0,0 +1,859 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2013 - 2017 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_edid.h>
+#include <uapi/drm/evdi_drm.h>
+#include "evdi_drv.h"
+#include "evdi_cursor.h"
+#include <linux/mutex.h>
+#include <linux/compiler.h>
+
+struct evdi_event_cursor_set_pending {
+ struct drm_pending_event base;
+ struct drm_evdi_event_cursor_set cursor_set;
+};
+
+struct evdi_event_cursor_move_pending {
+ struct drm_pending_event base;
+ struct drm_evdi_event_cursor_move cursor_move;
+};
+
+struct evdi_event_update_ready_pending {
+ struct drm_pending_event base;
+ struct drm_evdi_event_update_ready update_ready;
+};
+
+struct evdi_event_dpms_pending {
+ struct drm_pending_event base;
+ struct drm_evdi_event_dpms dpms;
+};
+
+struct evdi_event_mode_changed_pending {
+ struct drm_pending_event base;
+ struct drm_evdi_event_mode_changed mode_changed;
+};
+
+struct evdi_event_crtc_state_pending {
+ struct drm_pending_event base;
+ struct drm_evdi_event_crtc_state crtc_state;
+};
+
+#define MAX_DIRTS 16
+#define EDID_EXT_BLOCK_SIZE 128
+#define MAX_EDID_SIZE (255 * EDID_EXT_BLOCK_SIZE + sizeof(struct edid))
+
+struct evdi_painter {
+ bool is_connected;
+ struct edid *edid;
+ unsigned int edid_length;
+
+ struct mutex lock;
+ struct mutex new_scanout_fb_lock;
+ struct drm_clip_rect dirty_rects[MAX_DIRTS];
+ int num_dirts;
+ struct evdi_framebuffer *new_scanout_fb;
+ struct evdi_framebuffer *scanout_fb;
+
+ struct drm_file *drm_filp;
+
+ bool was_update_requested;
+ bool needs_full_modeset;
+};
+
+static void expand_rect(struct drm_clip_rect *a, const struct drm_clip_rect *b)
+{
+ a->x1 = min(a->x1, b->x1);
+ a->y1 = min(a->y1, b->y1);
+ a->x2 = max(a->x2, b->x2);
+ a->y2 = max(a->y2, b->y2);
+}
+
+static int rect_area(const struct drm_clip_rect *r)
+{
+ return (r->x2 - r->x1) * (r->y2 - r->y1);
+}
+
+static void merge_dirty_rects(struct drm_clip_rect *rects, int *count)
+{
+ int a, b;
+
+ for (a = 0; a < *count - 1; ++a) {
+ for (b = a + 1; b < *count;) {
+ /* collapse to bounding rect if it is fewer pixels */
+ const int area_a = rect_area(&rects[a]);
+ const int area_b = rect_area(&rects[b]);
+ struct drm_clip_rect bounding_rect = rects[a];
+
+ expand_rect(&bounding_rect, &rects[b]);
+
+ if (rect_area(&bounding_rect) <= area_a + area_b) {
+ rects[a] = bounding_rect;
+ rects[b] = rects[*count - 1];
+ /* repass */
+ b = a + 1;
+ --*count;
+ } else {
+ ++b;
+ }
+ }
+ }
+}
+
+static void collapse_dirty_rects(struct drm_clip_rect *rects, int *count)
+{
+ int i;
+
+ EVDI_CHECKPT();
+ EVDI_WARN("Not enough space for clip rects! Rects will be collapsed");
+
+ for (i = 1; i < *count; ++i)
+ expand_rect(&rects[0], &rects[i]);
+
+ *count = 1;
+}
+
+static int copy_primary_pixels(struct evdi_framebuffer *ufb,
+ char __user *buffer,
+ int buf_byte_stride,
+ int num_rects, struct drm_clip_rect *rects,
+ int const max_x,
+ int const max_y)
+{
+ struct drm_framebuffer *fb = &ufb->base;
+ struct drm_clip_rect *r;
+
+ EVDI_CHECKPT();
+
+ for (r = rects; r != rects + num_rects; ++r) {
+ const int byte_offset = r->x1 * 4;
+ const int byte_span = (r->x2 - r->x1) * 4;
+ const int src_offset = fb->pitches[0] * r->y1 + byte_offset;
+ const char *src = (char *)ufb->obj->vmapping + src_offset;
+ const int dst_offset = buf_byte_stride * r->y1 + byte_offset;
+ char __user *dst = buffer + dst_offset;
+ int y = r->y2 - r->y1;
+
+ /* rect size may correspond to previous resolution */
+ if (max_x < r->x2 || max_y < r->y2) {
+ EVDI_WARN("Rect size beyond expected dimensions\n");
+ return -EFAULT;
+ }
+
+ EVDI_VERBOSE("copy rect %d,%d-%d,%d\n", r->x1, r->y1, r->x2,
+ r->y2);
+
+ for (; y > 0; --y) {
+ if (copy_to_user(dst, src, byte_span))
+ return -EFAULT;
+
+ src += fb->pitches[0];
+ dst += buf_byte_stride;
+ }
+ }
+
+ return 0;
+}
+
+static void copy_cursor_pixels(struct evdi_framebuffer *efb,
+ char __user *buffer,
+ int buf_byte_stride,
+ struct evdi_cursor *cursor)
+{
+ if (evdi_enable_cursor_blending) {
+ evdi_cursor_lock(cursor);
+ if (evdi_cursor_compose_and_copy(cursor,
+ efb,
+ buffer,
+ buf_byte_stride))
+ EVDI_ERROR("Failed to blend cursor\n");
+
+ evdi_cursor_unlock(cursor);
+ }
+}
+
+#define painter_lock(painter) \
+ do { \
+ EVDI_VERBOSE("Painter lock\n"); \
+ mutex_lock(&painter->lock); \
+ } while (0)
+
+#define painter_unlock(painter) \
+ do { \
+ EVDI_VERBOSE("Painter unlock\n"); \
+ mutex_unlock(&painter->lock); \
+ } while (0)
+
+bool evdi_painter_is_connected(struct evdi_device *evdi)
+{
+ if (evdi && evdi->painter)
+ return evdi->painter->is_connected;
+ return false;
+}
+
+u8 *evdi_painter_get_edid_copy(struct evdi_device *evdi)
+{
+ u8 *block = NULL;
+
+ EVDI_CHECKPT();
+
+ painter_lock(evdi->painter);
+ if (evdi_painter_is_connected(evdi) &&
+ evdi->painter->edid &&
+ evdi->painter->edid_length) {
+ block = kmalloc(evdi->painter->edid_length, GFP_KERNEL);
+ if (block) {
+ memcpy(block,
+ evdi->painter->edid,
+ evdi->painter->edid_length);
+ EVDI_DEBUG("(dev=%d) %02x %02x %02x\n", evdi->dev_index,
+ block[0], block[1], block[2]);
+ }
+ }
+ painter_unlock(evdi->painter);
+ return block;
+}
+
+static void evdi_painter_send_event(struct drm_file *drm_filp,
+ struct list_head *event_link)
+{
+ list_add_tail(event_link, &drm_filp->event_list);
+ wake_up_interruptible(&drm_filp->event_wait);
+}
+
+static void evdi_painter_send_update_ready(struct evdi_painter *painter)
+{
+ struct evdi_event_update_ready_pending *event;
+
+ if (painter->drm_filp) {
+ event = kzalloc(sizeof(*event), GFP_KERNEL);
+ event->update_ready.base.type = DRM_EVDI_EVENT_UPDATE_READY;
+ event->update_ready.base.length = sizeof(event->update_ready);
+ event->base.event = &event->update_ready.base;
+ event->base.file_priv = painter->drm_filp;
+ evdi_painter_send_event(painter->drm_filp, &event->base.link);
+ } else {
+ EVDI_WARN("Painter is not connected!");
+ }
+}
+
+static uint32_t evdi_painter_get_gem_handle(struct evdi_painter *painter,
+ struct evdi_gem_object *obj)
+{
+ uint32_t handle = 0;
+
+ if (!obj)
+ return 0;
+
+ handle = evdi_gem_object_handle_lookup(painter->drm_filp, &obj->base);
+
+ if (handle)
+ return handle;
+
+ if (drm_gem_handle_create(painter->drm_filp,
+ &obj->base, &handle)) {
+ EVDI_ERROR("Failed to create gem handle for %p\n",
+ painter->drm_filp);
+ }
+
+ return handle;
+}
+
+void evdi_painter_send_cursor_set(struct evdi_painter *painter,
+ struct evdi_cursor *cursor)
+{
+ struct evdi_event_cursor_set_pending *event;
+ struct evdi_gem_object *eobj = NULL;
+
+ if (painter->drm_filp) {
+ event = kzalloc(sizeof(*event), GFP_KERNEL);
+ event->cursor_set.base.type = DRM_EVDI_EVENT_CURSOR_SET;
+ event->cursor_set.base.length =
+ sizeof(event->cursor_set);
+
+ evdi_cursor_lock(cursor);
+ event->cursor_set.enabled = evdi_cursor_enabled(cursor);
+ evdi_cursor_hotpoint(cursor,
+ &event->cursor_set.hot_x,
+ &event->cursor_set.hot_y);
+ evdi_cursor_size(cursor,
+ &event->cursor_set.width,
+ &event->cursor_set.height);
+ evdi_cursor_format(cursor,
+ &event->cursor_set.pixel_format);
+ evdi_cursor_stride(cursor,
+ &event->cursor_set.stride);
+ eobj = evdi_cursor_gem(cursor);
+ event->cursor_set.buffer_handle =
+ evdi_painter_get_gem_handle(painter, eobj);
+ if (eobj)
+ event->cursor_set.buffer_length = eobj->base.size;
+ if (!event->cursor_set.buffer_handle) {
+ event->cursor_set.enabled = false;
+ event->cursor_set.buffer_length = 0;
+ }
+ evdi_cursor_unlock(cursor);
+
+ event->base.event = &event->cursor_set.base;
+ event->base.file_priv = painter->drm_filp;
+ evdi_painter_send_event(painter->drm_filp, &event->base.link);
+ } else {
+ EVDI_WARN("Painter is not connected!");
+ }
+}
+
+void evdi_painter_send_cursor_move(struct evdi_painter *painter,
+ struct evdi_cursor *cursor)
+{
+ struct evdi_event_cursor_move_pending *event;
+
+ if (painter->drm_filp) {
+ event = kzalloc(sizeof(*event), GFP_KERNEL);
+ event->cursor_move.base.type = DRM_EVDI_EVENT_CURSOR_MOVE;
+ event->cursor_move.base.length = sizeof(event->cursor_move);
+
+ evdi_cursor_lock(cursor);
+ evdi_cursor_position(
+ cursor,
+ &event->cursor_move.x,
+ &event->cursor_move.y);
+ evdi_cursor_unlock(cursor);
+
+ event->base.event = &event->cursor_move.base;
+ event->base.file_priv = painter->drm_filp;
+ evdi_painter_send_event(painter->drm_filp, &event->base.link);
+ } else {
+ EVDI_WARN("Painter is not connected!");
+ }
+}
+
+static void evdi_painter_send_dpms(struct evdi_painter *painter, int mode)
+{
+ struct evdi_event_dpms_pending *event;
+
+ if (painter->drm_filp) {
+ event = kzalloc(sizeof(*event), GFP_KERNEL);
+ event->dpms.base.type = DRM_EVDI_EVENT_DPMS;
+ event->dpms.base.length = sizeof(event->dpms);
+ event->dpms.mode = mode;
+ event->base.event = &event->dpms.base;
+ event->base.file_priv = painter->drm_filp;
+ evdi_painter_send_event(painter->drm_filp, &event->base.link);
+ } else {
+ EVDI_WARN("Painter is not connected!");
+ }
+}
+
+static void evdi_painter_send_crtc_state(struct evdi_painter *painter,
+ int state)
+{
+ struct evdi_event_crtc_state_pending *event;
+
+ if (painter->drm_filp) {
+ event = kzalloc(sizeof(*event), GFP_KERNEL);
+ event->crtc_state.base.type = DRM_EVDI_EVENT_CRTC_STATE;
+ event->crtc_state.base.length = sizeof(event->crtc_state);
+ event->crtc_state.state = state;
+ event->base.event = &event->crtc_state.base;
+ event->base.file_priv = painter->drm_filp;
+ evdi_painter_send_event(painter->drm_filp, &event->base.link);
+ } else {
+ EVDI_WARN("Painter is not connected!");
+ }
+}
+
+static void evdi_painter_send_mode_changed(
+ struct evdi_painter *painter,
+ struct drm_display_mode *current_mode,
+ int32_t bits_per_pixel,
+ uint32_t pixel_format)
+{
+ struct evdi_event_mode_changed_pending *event;
+
+ if (painter->drm_filp) {
+ event = kzalloc(sizeof(*event), GFP_KERNEL);
+ event->mode_changed.base.type = DRM_EVDI_EVENT_MODE_CHANGED;
+ event->mode_changed.base.length = sizeof(event->mode_changed);
+
+ event->mode_changed.hdisplay = current_mode->hdisplay;
+ event->mode_changed.vdisplay = current_mode->vdisplay;
+ event->mode_changed.vrefresh =
+ drm_mode_vrefresh(current_mode);
+ event->mode_changed.bits_per_pixel = bits_per_pixel;
+ event->mode_changed.pixel_format = pixel_format;
+
+ event->base.event = &event->mode_changed.base;
+ event->base.file_priv = painter->drm_filp;
+ evdi_painter_send_event(painter->drm_filp, &event->base.link);
+ } else {
+ EVDI_WARN("Painter is not connected!");
+ }
+}
+
+void evdi_painter_mark_dirty(struct evdi_device *evdi,
+ const struct drm_clip_rect *dirty_rect)
+{
+ struct drm_clip_rect rect;
+ struct evdi_framebuffer *efb = NULL;
+ struct evdi_painter *painter = evdi->painter;
+
+ painter_lock(evdi->painter);
+ efb = evdi->painter->scanout_fb;
+ if (!efb) {
+ EVDI_WARN("(dev=%d) Skip clip rect. Scanout buffer not set.\n",
+ evdi->dev_index);
+ goto unlock;
+ }
+
+ rect = evdi_framebuffer_sanitize_rect(efb, dirty_rect);
+
+ EVDI_VERBOSE("(dev=%d) %d,%d-%d,%d\n", evdi->dev_index, rect.x1,
+ rect.y1, rect.x2, rect.y2);
+
+ if (painter->num_dirts == MAX_DIRTS)
+ merge_dirty_rects(&painter->dirty_rects[0],
+ &painter->num_dirts);
+
+ if (painter->num_dirts == MAX_DIRTS)
+ collapse_dirty_rects(&painter->dirty_rects[0],
+ &painter->num_dirts);
+
+ memcpy(&painter->dirty_rects[painter->num_dirts], &rect, sizeof(rect));
+ painter->num_dirts++;
+
+unlock:
+ painter_unlock(evdi->painter);
+}
+
+void evdi_painter_send_update_ready_if_needed(struct evdi_device *evdi)
+{
+ struct evdi_painter *painter = evdi->painter;
+
+ painter_lock(evdi->painter);
+ if (painter->was_update_requested) {
+ evdi_painter_send_update_ready(painter);
+ painter->was_update_requested = false;
+ }
+ painter_unlock(evdi->painter);
+}
+
+void evdi_painter_dpms_notify(struct evdi_device *evdi, int mode)
+{
+ struct evdi_painter *painter = evdi->painter;
+
+ if (painter) {
+ EVDI_DEBUG("(dev=%d) Notifying dpms mode: %d\n",
+ evdi->dev_index, mode);
+ evdi_painter_send_dpms(painter, mode);
+ } else {
+ EVDI_WARN("Painter does not exist!");
+ }
+}
+
+void evdi_painter_crtc_state_notify(struct evdi_device *evdi, int state)
+{
+ struct evdi_painter *painter = evdi->painter;
+
+ if (painter) {
+ EVDI_DEBUG("(dev=%d) Notifying crtc state: %d\n",
+ evdi->dev_index, state);
+ evdi_painter_send_crtc_state(painter, state);
+ } else {
+ EVDI_WARN("Painter does not exist!");
+ }
+}
+
+void evdi_painter_mode_changed_notify(struct evdi_device *evdi,
+ struct drm_display_mode *new_mode)
+{
+ struct evdi_painter *painter = evdi->painter;
+ struct drm_framebuffer *fb = &painter->scanout_fb->base;
+ int bits_per_pixel;
+ uint32_t pixel_format;
+
+ if (fb == NULL)
+ return;
+
+ bits_per_pixel = fb->format->cpp[0];
+ pixel_format = fb->format->format;
+
+ EVDI_DEBUG("(dev=%d) Notifying mode changed: %dx%d@%d; bpp %d; ",
+ evdi->dev_index, new_mode->hdisplay, new_mode->vdisplay,
+ drm_mode_vrefresh(new_mode), bits_per_pixel);
+ EVDI_DEBUG("pixel format %d\n", pixel_format);
+
+ evdi_painter_send_mode_changed(painter,
+ new_mode,
+ bits_per_pixel,
+ pixel_format);
+ if (painter)
+ painter->needs_full_modeset = false;
+}
+
+static int
+evdi_painter_connect(struct evdi_device *evdi,
+ void const __user *edid_data, unsigned int edid_length,
+ uint32_t sku_area_limit,
+ struct drm_file *file, int dev_index)
+{
+ struct evdi_painter *painter = evdi->painter;
+ struct edid *new_edid = NULL;
+ int expected_edid_size = 0;
+
+ EVDI_CHECKPT();
+
+ if (edid_length < sizeof(struct edid)) {
+ EVDI_ERROR("Edid length too small\n");
+ return -EINVAL;
+ }
+
+ if (edid_length > MAX_EDID_SIZE) {
+ EVDI_ERROR("Edid length too large\n");
+ return -EINVAL;
+ }
+
+ new_edid = kzalloc(edid_length, GFP_KERNEL);
+ if (!new_edid)
+ return -ENOMEM;
+
+ if (copy_from_user(new_edid, edid_data, edid_length)) {
+ EVDI_ERROR("(dev=%d) Failed to read edid\n", dev_index);
+ kfree(new_edid);
+ return -EFAULT;
+ }
+
+ expected_edid_size = sizeof(struct edid) +
+ new_edid->extensions * EDID_EXT_BLOCK_SIZE;
+ if (expected_edid_size != edid_length) {
+ EVDI_ERROR("Wrong edid size. Expected %d but is %d\n",
+ expected_edid_size, edid_length);
+ kfree(new_edid);
+ return -EINVAL;
+ }
+
+ if (painter->drm_filp)
+ EVDI_WARN("(dev=%d) Double connect - replacing %p with %p\n",
+ dev_index, painter->drm_filp, file);
+
+ painter_lock(painter);
+
+ evdi->dev_index = dev_index;
+ evdi->sku_area_limit = sku_area_limit;
+ painter->drm_filp = file;
+ kfree(painter->edid);
+ painter->edid_length = edid_length;
+ painter->edid = new_edid;
+ painter->is_connected = true;
+ painter->needs_full_modeset = true;
+
+ painter_unlock(painter);
+
+ EVDI_DEBUG("(dev=%d) Connected with %p\n", evdi->dev_index,
+ painter->drm_filp);
+
+ drm_helper_hpd_irq_event(evdi->ddev);
+
+
+ return 0;
+}
+
+static int evdi_painter_disconnect(struct evdi_device *evdi,
+ struct drm_file *file)
+{
+ struct evdi_painter *painter = evdi->painter;
+
+ EVDI_CHECKPT();
+
+ painter_lock(painter);
+
+ if (file != painter->drm_filp) {
+ EVDI_WARN
+ ("(dev=%d) An unknown connection to %p tries to close us",
+ evdi->dev_index, file);
+ EVDI_WARN(" - ignoring\n");
+
+ painter_unlock(painter);
+ return -EFAULT;
+ }
+
+ evdi_painter_set_new_scanout_buffer(evdi, NULL);
+
+ if (painter->scanout_fb) {
+ drm_framebuffer_unreference(&painter->scanout_fb->base);
+ painter->scanout_fb = NULL;
+ }
+
+ painter->is_connected = false;
+
+ EVDI_DEBUG("(dev=%d) Disconnected from %p\n", evdi->dev_index,
+ painter->drm_filp);
+
+ evdi_cursor_enable(evdi->cursor, false);
+
+ painter->drm_filp = NULL;
+
+ painter->was_update_requested = false;
+
+ painter_unlock(painter);
+
+ drm_helper_hpd_irq_event(evdi->ddev);
+ return 0;
+}
+
+void evdi_painter_close(struct evdi_device *evdi, struct drm_file *file)
+{
+ EVDI_CHECKPT();
+
+ if (evdi->painter)
+ evdi_painter_disconnect(evdi, file);
+ else
+ EVDI_WARN("Painter does not exist!");
+}
+
+int evdi_painter_connect_ioctl(struct drm_device *drm_dev, void *data,
+ struct drm_file *file)
+{
+ struct evdi_device *evdi = drm_dev->dev_private;
+ struct evdi_painter *painter = evdi->painter;
+ struct drm_evdi_connect *cmd = data;
+ int ret;
+
+ EVDI_CHECKPT();
+ if (painter) {
+ if (cmd->connected)
+ ret = evdi_painter_connect(evdi,
+ cmd->edid,
+ cmd->edid_length,
+ cmd->sku_area_limit,
+ file,
+ cmd->dev_index);
+ else
+ ret = evdi_painter_disconnect(evdi, file);
+
+ return ret;
+ }
+ EVDI_WARN("Painter does not exist!");
+ return -ENODEV;
+}
+
+int evdi_painter_grabpix_ioctl(struct drm_device *drm_dev, void *data,
+ __always_unused struct drm_file *file)
+{
+ struct evdi_device *evdi = drm_dev->dev_private;
+ struct evdi_painter *painter = evdi->painter;
+ struct drm_evdi_grabpix *cmd = data;
+ struct drm_framebuffer *fb = NULL;
+ struct evdi_framebuffer *efb = NULL;
+ int err = 0;
+
+ EVDI_CHECKPT();
+
+ if (!painter)
+ return -ENODEV;
+
+ painter_lock(painter);
+
+ efb = painter->scanout_fb;
+
+ if (!efb) {
+ EVDI_ERROR("Scanout buffer not set\n");
+ err = -EAGAIN;
+ goto unlock;
+ }
+
+ if (painter->was_update_requested) {
+ EVDI_WARN("(dev=%d) Update ready not sent,",
+ evdi->dev_index);
+ EVDI_WARN(" but pixels are grabbed.\n");
+ }
+
+ fb = &efb->base;
+ if (!efb->obj->vmapping) {
+ if (evdi_gem_vmap(efb->obj) == -ENOMEM) {
+ EVDI_ERROR("Failed to map scanout buffer\n");
+ err = -EFAULT;
+ goto unlock;
+ }
+ if (!efb->obj->vmapping) {
+ EVDI_ERROR("Inexistent vmapping\n");
+ err = -EFAULT;
+ goto unlock;
+ }
+ }
+
+ if (cmd->buf_width != fb->width ||
+ cmd->buf_height != fb->height) {
+ EVDI_ERROR("Invalid buffer dimension\n");
+ err = -EINVAL;
+ goto unlock;
+ }
+
+ if (cmd->num_rects < 1) {
+ EVDI_ERROR("No space for clip rects\n");
+ err = -EINVAL;
+ goto unlock;
+ }
+
+ if (cmd->mode == EVDI_GRABPIX_MODE_DIRTY) {
+ if (painter->num_dirts < 0) {
+ err = -EAGAIN;
+ goto unlock;
+ }
+ merge_dirty_rects(&painter->dirty_rects[0],
+ &painter->num_dirts);
+ if (painter->num_dirts > cmd->num_rects)
+ collapse_dirty_rects(&painter->dirty_rects[0],
+ &painter->num_dirts);
+
+ cmd->num_rects = painter->num_dirts;
+
+ if (copy_to_user(cmd->rects, painter->dirty_rects,
+ cmd->num_rects * sizeof(cmd->rects[0])))
+ err = -EFAULT;
+ if (err == 0)
+ err = copy_primary_pixels(efb,
+ cmd->buffer,
+ cmd->buf_byte_stride,
+ painter->num_dirts,
+ painter->dirty_rects,
+ cmd->buf_width,
+ cmd->buf_height);
+ if (err == 0)
+ copy_cursor_pixels(efb,
+ cmd->buffer,
+ cmd->buf_byte_stride,
+ evdi->cursor);
+
+ painter->num_dirts = 0;
+ }
+unlock:
+ painter_unlock(painter);
+
+ return err;
+}
+
+int evdi_painter_request_update_ioctl(struct drm_device *drm_dev,
+ __always_unused void *data,
+ __always_unused struct drm_file *file)
+{
+ struct evdi_device *evdi = drm_dev->dev_private;
+ struct evdi_painter *painter = evdi->painter;
+ int result = 0;
+
+ if (painter) {
+ painter_lock(painter);
+
+ if (painter->was_update_requested) {
+ EVDI_WARN
+ ("(dev=%d) Update was already requested - ignoring\n",
+ evdi->dev_index);
+ } else {
+ if (painter->num_dirts > 0)
+ result = 1;
+ else
+ painter->was_update_requested = true;
+ }
+
+ painter_unlock(painter);
+
+ return result;
+ } else {
+ return -ENODEV;
+ }
+}
+
+int evdi_painter_init(struct evdi_device *dev)
+{
+ EVDI_CHECKPT();
+ dev->painter = kzalloc(sizeof(*dev->painter), GFP_KERNEL);
+ if (dev->painter) {
+ mutex_init(&dev->painter->lock);
+ mutex_init(&dev->painter->new_scanout_fb_lock);
+ dev->painter->edid = NULL;
+ dev->painter->edid_length = 0;
+ dev->painter->needs_full_modeset = true;
+ return 0;
+ }
+ return -ENOMEM;
+}
+
+void evdi_painter_cleanup(struct evdi_device *evdi)
+{
+ struct evdi_painter *painter = evdi->painter;
+
+ EVDI_CHECKPT();
+ if (painter) {
+ painter_lock(painter);
+ kfree(painter->edid);
+ painter->edid_length = 0;
+ painter->edid = 0;
+ painter_unlock(painter);
+ } else {
+ EVDI_WARN("Painter does not exist\n");
+ }
+}
+
+/*
+ * This can be called from multiple threads so we need to lock during
+ * *new_scanout_fb* assignment.
+ * It is called from *evdi_crtc_page_flip* which must return immediately.
+ * If we lock here whole painter object it will interfere with grab_pics
+ * ioctl (which can take some time).
+ * Because of that we lock only on the *new_scanout_fb*.
+ */
+void evdi_painter_set_new_scanout_buffer(struct evdi_device *evdi,
+ struct evdi_framebuffer *newfb)
+{
+ struct evdi_painter *painter = evdi->painter;
+ struct evdi_framebuffer *oldfb = NULL;
+
+ if (newfb)
+ drm_framebuffer_reference(&newfb->base);
+
+ mutex_lock(&painter->new_scanout_fb_lock);
+ oldfb = painter->new_scanout_fb;
+ painter->new_scanout_fb = newfb;
+ mutex_unlock(&painter->new_scanout_fb_lock);
+
+ if (oldfb)
+ drm_framebuffer_unreference(&oldfb->base);
+}
+
+void evdi_painter_commit_scanout_buffer(struct evdi_device *evdi)
+{
+ struct evdi_painter *painter = evdi->painter;
+ struct evdi_framebuffer *newfb = NULL;
+ struct evdi_framebuffer *oldfb = NULL;
+
+ painter_lock(painter);
+ mutex_lock(&painter->new_scanout_fb_lock);
+
+ newfb = painter->new_scanout_fb;
+
+ if (newfb)
+ drm_framebuffer_reference(&newfb->base);
+
+ oldfb = painter->scanout_fb;
+ painter->scanout_fb = newfb;
+
+ mutex_unlock(&painter->new_scanout_fb_lock);
+ painter_unlock(painter);
+
+ if (oldfb)
+ drm_framebuffer_unreference(&oldfb->base);
+}
+
+bool evdi_painter_needs_full_modeset(struct evdi_device *evdi)
+{
+ struct evdi_painter *painter = evdi->painter;
+
+ if (painter)
+ return painter->needs_full_modeset;
+ return false;
+}
diff --git a/drivers/gpu/drm/evdi/evdi_stats.c b/drivers/gpu/drm/evdi/evdi_stats.c
new file mode 100644
index 0000000..bd226f1
--- /dev/null
+++ b/drivers/gpu/drm/evdi/evdi_stats.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015 - 2016 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include "evdi_drv.h"
+
+static ssize_t frame_count_show(struct device *dev,
+ __always_unused struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_minor *drm_minor = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = drm_minor->dev;
+ struct evdi_device *evdi = drm_dev->dev_private;
+
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ atomic_read(&evdi->frame_count));
+}
+
+static struct device_attribute evdi_device_attributes[] = {
+ __ATTR_RO(frame_count),
+};
+
+void evdi_stats_init(struct evdi_device *evdi)
+{
+ int i, retval;
+
+ DRM_INFO("evdi: %s\n", __func__);
+ atomic_set(&evdi->frame_count, 0);
+ for (i = 0; i < ARRAY_SIZE(evdi_device_attributes); i++) {
+ retval =
+ device_create_file(evdi->ddev->primary->kdev,
+ &evdi_device_attributes[i]);
+ if (retval)
+ DRM_ERROR("evdi: device_create_file failed %d\n",
+ retval);
+ }
+}
+
+void evdi_stats_cleanup(struct evdi_device *evdi)
+{
+ int i;
+
+ DRM_INFO("evdi: %s\n", __func__);
+
+ for (i = 0; i < ARRAY_SIZE(evdi_device_attributes); i++)
+ device_remove_file(evdi->ddev->primary->kdev,
+ &evdi_device_attributes[i]);
+}
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
index 3518167..8516e005 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
@@ -223,9 +223,10 @@
return tt;
}
-static int hibmc_ttm_tt_populate(struct ttm_tt *ttm)
+static int hibmc_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
static void hibmc_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -344,6 +345,7 @@
int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (bo->pin_count) {
@@ -356,7 +358,7 @@
hibmc_ttm_placement(bo, pl_flag);
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -368,6 +370,7 @@
int hibmc_bo_unpin(struct hibmc_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
@@ -380,7 +383,7 @@
for (i = 0; i < bo->placement.num_placement ; i++)
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret) {
DRM_ERROR("validate failed for unpin: %d\n", ret);
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eacc5ab..f9e953c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1167,15 +1167,18 @@
int count = gen8_pte_count(start, length);
if (pt == vm->scratch_pt) {
+ pd->used_pdes++;
+
pt = alloc_pt(vm);
- if (IS_ERR(pt))
+ if (IS_ERR(pt)) {
+ pd->used_pdes--;
goto unwind;
+ }
if (count < GEN8_PTES || intel_vgpu_active(vm->i915))
gen8_initialize_pt(vm, pt);
gen8_ppgtt_set_pde(vm, pd, pt, pde);
- pd->used_pdes++;
GEM_BUG_ON(pd->used_pdes > I915_PDES);
}
@@ -1199,13 +1202,16 @@
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
if (pd == vm->scratch_pd) {
+ pdp->used_pdpes++;
+
pd = alloc_pd(vm);
- if (IS_ERR(pd))
+ if (IS_ERR(pd)) {
+ pdp->used_pdpes--;
goto unwind;
+ }
gen8_initialize_pd(vm, pd);
gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
- pdp->used_pdpes++;
GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b0dd05c..78ee602 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2485,12 +2485,17 @@
#define _3D_CHICKEN _MMIO(0x2084)
#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
#define _3D_CHICKEN2 _MMIO(0x208c)
+
+#define FF_SLICE_CHICKEN _MMIO(0x2088)
+#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
+
/* Disables pipelining of read flushes past the SF-WIZ interface.
* Required on all Ironlake steppings according to the B-Spec, but the
* particular danger of not doing so is not specified.
*/
# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
#define _3D_CHICKEN3 _MMIO(0x2090)
+#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6de9d35..b4a3217 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1322,11 +1322,21 @@
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
batch = gen8_emit_flush_coherentl3_wa(engine, batch);
+ *batch++ = MI_LOAD_REGISTER_IMM(3);
+
/* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
- *batch++ = MI_LOAD_REGISTER_IMM(1);
*batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
*batch++ = _MASKED_BIT_DISABLE(
GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
+
+ /* BSpec: 11391 */
+ *batch++ = i915_mmio_reg_offset(FF_SLICE_CHICKEN);
+ *batch++ = _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
+
+ /* BSpec: 11299 */
+ *batch++ = i915_mmio_reg_offset(_3D_CHICKEN3);
+ *batch++ = _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);
+
*batch++ = MI_NOOP;
/* WaClearSlmSpaceAtContextSwitch:kbl */
diff --git a/drivers/gpu/drm/mgag200/mgag200_ttm.c b/drivers/gpu/drm/mgag200/mgag200_ttm.c
index 3e7e1cd..c97009b 100644
--- a/drivers/gpu/drm/mgag200/mgag200_ttm.c
+++ b/drivers/gpu/drm/mgag200/mgag200_ttm.c
@@ -216,9 +216,10 @@
return tt;
}
-static int mgag200_ttm_tt_populate(struct ttm_tt *ttm)
+static int mgag200_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
static void mgag200_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -237,7 +238,6 @@
.verify_access = mgag200_bo_verify_access,
.io_mem_reserve = &mgag200_ttm_io_mem_reserve,
.io_mem_free = &mgag200_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
int mgag200_mm_init(struct mga_device *mdev)
@@ -354,6 +354,7 @@
int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (bo->pin_count) {
@@ -366,7 +367,7 @@
mgag200_ttm_placement(bo, pl_flag);
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -378,6 +379,7 @@
int mgag200_bo_unpin(struct mgag200_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i;
if (!bo->pin_count) {
DRM_ERROR("unpin bad %p\n", bo);
@@ -389,11 +391,12 @@
for (i = 0; i < bo->placement.num_placement ; i++)
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
- return ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ return ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
}
int mgag200_bo_push_sysram(struct mgag200_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
DRM_ERROR("unpin bad %p\n", bo);
@@ -410,7 +413,7 @@
for (i = 0; i < bo->placement.num_placement ; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret) {
DRM_ERROR("pushing to VRAM failed\n");
return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index e427f80..eb7a4bf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -486,10 +486,10 @@
nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
bool no_wait_gpu)
{
+ struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
int ret;
- ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
- interruptible, no_wait_gpu);
+ ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
if (ret)
return ret;
@@ -1129,6 +1129,7 @@
nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
{
+ struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
struct ttm_place placement_memtype = {
.fpfn = 0,
.lpfn = 0,
@@ -1143,11 +1144,11 @@
tmp_reg = *new_reg;
tmp_reg.mm_node = NULL;
- ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu);
+ ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
if (ret)
return ret;
- ret = ttm_tt_bind(bo->ttm, &tmp_reg);
+ ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx);
if (ret)
goto out;
@@ -1155,7 +1156,7 @@
if (ret)
goto out;
- ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg);
+ ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
out:
ttm_bo_mem_put(bo, &tmp_reg);
return ret;
@@ -1165,6 +1166,7 @@
nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
{
+ struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
struct ttm_place placement_memtype = {
.fpfn = 0,
.lpfn = 0,
@@ -1179,11 +1181,11 @@
tmp_reg = *new_reg;
tmp_reg.mm_node = NULL;
- ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu);
+ ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
if (ret)
return ret;
- ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg);
+ ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
if (ret)
goto out;
@@ -1255,8 +1257,9 @@
}
static int
-nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
- bool no_wait_gpu, struct ttm_mem_reg *new_reg)
+nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_reg)
{
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
struct nouveau_bo *nvbo = nouveau_bo(bo);
@@ -1264,7 +1267,7 @@
struct nouveau_drm_tile *new_tile = NULL;
int ret = 0;
- ret = ttm_bo_wait(bo, intr, no_wait_gpu);
+ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (ret)
return ret;
@@ -1288,22 +1291,25 @@
/* Hardware assisted copy. */
if (drm->ttm.move) {
if (new_reg->mem_type == TTM_PL_SYSTEM)
- ret = nouveau_bo_move_flipd(bo, evict, intr,
- no_wait_gpu, new_reg);
+ ret = nouveau_bo_move_flipd(bo, evict,
+ ctx->interruptible,
+ ctx->no_wait_gpu, new_reg);
else if (old_reg->mem_type == TTM_PL_SYSTEM)
- ret = nouveau_bo_move_flips(bo, evict, intr,
- no_wait_gpu, new_reg);
+ ret = nouveau_bo_move_flips(bo, evict,
+ ctx->interruptible,
+ ctx->no_wait_gpu, new_reg);
else
- ret = nouveau_bo_move_m2mf(bo, evict, intr,
- no_wait_gpu, new_reg);
+ ret = nouveau_bo_move_m2mf(bo, evict,
+ ctx->interruptible,
+ ctx->no_wait_gpu, new_reg);
if (!ret)
goto out;
}
/* Fallback to software copy. */
- ret = ttm_bo_wait(bo, intr, no_wait_gpu);
+ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (ret == 0)
- ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg);
+ ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
out:
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
@@ -1441,7 +1447,7 @@
}
static int
-nouveau_ttm_tt_populate(struct ttm_tt *ttm)
+nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
struct ttm_dma_tt *ttm_dma = (void *)ttm;
struct nouveau_drm *drm;
@@ -1470,17 +1476,17 @@
#if IS_ENABLED(CONFIG_AGP)
if (drm->agp.bridge) {
- return ttm_agp_tt_populate(ttm);
+ return ttm_agp_tt_populate(ttm, ctx);
}
#endif
#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
if (swiotlb_nr_tbl()) {
- return ttm_dma_populate((void *)ttm, dev->dev);
+ return ttm_dma_populate((void *)ttm, dev->dev, ctx);
}
#endif
- r = ttm_pool_populate(ttm);
+ r = ttm_pool_populate(ttm, ctx);
if (r) {
return r;
}
@@ -1574,7 +1580,6 @@
.fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
.io_mem_reserve = &nouveau_ttm_io_mem_reserve,
.io_mem_free = &nouveau_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
struct nvkm_vma *
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 2170534..dedd58f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -349,7 +349,7 @@
list_del(&nvbo->entry);
nvbo->reserved_by = NULL;
- ttm_bo_unreserve_ticket(&nvbo->bo, &op->ticket);
+ ttm_bo_unreserve(&nvbo->bo);
drm_gem_object_unreference_unlocked(&nvbo->gem);
}
}
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index 9a9214a..573bab2 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -630,7 +630,7 @@
struct qxl_cursor_cmd *cmd;
struct qxl_cursor *cursor;
struct drm_gem_object *obj;
- struct qxl_bo *cursor_bo = NULL, *user_bo = NULL;
+ struct qxl_bo *cursor_bo = NULL, *user_bo = NULL, *old_cursor_bo = NULL;
int ret;
void *user_ptr;
int size = 64*64*4;
@@ -684,7 +684,7 @@
cursor_bo, 0);
cmd->type = QXL_CURSOR_SET;
- qxl_bo_unref(&qcrtc->cursor_bo);
+ old_cursor_bo = qcrtc->cursor_bo;
qcrtc->cursor_bo = cursor_bo;
cursor_bo = NULL;
} else {
@@ -704,6 +704,9 @@
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
qxl_release_fence_buffer_objects(release);
+ if (old_cursor_bo)
+ qxl_bo_unref(&old_cursor_bo);
+
qxl_bo_unref(&cursor_bo);
return;
diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c
index 31effed..e8c0b10 100644
--- a/drivers/gpu/drm/qxl/qxl_ioctl.c
+++ b/drivers/gpu/drm/qxl/qxl_ioctl.c
@@ -309,6 +309,7 @@
int ret;
struct drm_gem_object *gobj = NULL;
struct qxl_bo *qobj = NULL;
+ struct ttm_operation_ctx ctx = { true, false };
if (update_area->left >= update_area->right ||
update_area->top >= update_area->bottom)
@@ -326,8 +327,7 @@
if (!qobj->pin_count) {
qxl_ttm_placement_from_domain(qobj, qobj->type, false);
- ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
- true, false);
+ ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
if (unlikely(ret))
goto out;
}
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index 0a67ddf..f6b80fe 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -223,6 +223,7 @@
static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
struct drm_device *ddev = bo->gem_base.dev;
int r;
@@ -233,7 +234,7 @@
return 0;
}
qxl_ttm_placement_from_domain(bo, domain, true);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (likely(r == 0)) {
bo->pin_count = 1;
if (gpu_addr != NULL)
@@ -246,6 +247,7 @@
static int __qxl_bo_unpin(struct qxl_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
struct drm_device *ddev = bo->gem_base.dev;
int r, i;
@@ -258,7 +260,7 @@
return 0;
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (unlikely(r != 0))
dev_err(ddev->dev, "%p validate failed for unpin\n", bo);
return r;
diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c
index e6ec845..17c5565 100644
--- a/drivers/gpu/drm/qxl/qxl_release.c
+++ b/drivers/gpu/drm/qxl/qxl_release.c
@@ -231,12 +231,12 @@
static int qxl_release_validate_bo(struct qxl_bo *bo)
{
+ struct ttm_operation_ctx ctx = { true, false };
int ret;
if (!bo->pin_count) {
qxl_ttm_placement_from_domain(bo, bo->type, false);
- ret = ttm_bo_validate(&bo->tbo, &bo->placement,
- true, false);
+ ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (ret)
return ret;
}
@@ -469,7 +469,7 @@
reservation_object_add_shared_fence(bo->resv, &release->base);
ttm_bo_add_to_lru(bo);
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
}
spin_unlock(&glob->lru_lock);
ww_acquire_fini(&release->ticket);
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 7ecf8a4..54fa1ec 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -294,14 +294,15 @@
.destroy = &qxl_ttm_backend_destroy,
};
-static int qxl_ttm_tt_populate(struct ttm_tt *ttm)
+static int qxl_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
int r;
if (ttm->state != tt_unpopulated)
return 0;
- r = ttm_pool_populate(ttm);
+ r = ttm_pool_populate(ttm, ctx);
if (r)
return r;
@@ -344,15 +345,14 @@
new_mem->mm_node = NULL;
}
-static int qxl_bo_move(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu,
+static int qxl_bo_move(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem)
{
struct ttm_mem_reg *old_mem = &bo->mem;
int ret;
- ret = ttm_bo_wait(bo, interruptible, no_wait_gpu);
+ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (ret)
return ret;
@@ -361,8 +361,7 @@
qxl_move_null(bo, new_mem);
return 0;
}
- return ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu,
- new_mem);
+ return ttm_bo_move_memcpy(bo, ctx, new_mem);
}
static void qxl_bo_move_notify(struct ttm_buffer_object *bo,
@@ -393,7 +392,6 @@
.verify_access = &qxl_verify_access,
.io_mem_reserve = &qxl_ttm_io_mem_reserve,
.io_mem_free = &qxl_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
.move_notify = &qxl_bo_move_notify,
};
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index ac467b8..2ff2a2d 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -283,6 +283,7 @@
int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct radeon_device *rdev = dev->dev_private;
struct drm_radeon_gem_userptr *args = data;
struct drm_gem_object *gobj;
@@ -341,7 +342,7 @@
}
radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
radeon_bo_unreserve(bo);
up_read(¤t->mm->mmap_sem);
if (r)
diff --git a/drivers/gpu/drm/radeon/radeon_mn.c b/drivers/gpu/drm/radeon/radeon_mn.c
index 1d62288..abd2497 100644
--- a/drivers/gpu/drm/radeon/radeon_mn.c
+++ b/drivers/gpu/drm/radeon/radeon_mn.c
@@ -124,6 +124,7 @@
unsigned long end)
{
struct radeon_mn *rmn = container_of(mn, struct radeon_mn, mn);
+ struct ttm_operation_ctx ctx = { false, false };
struct interval_tree_node *it;
/* notification is exclusive, but interval is inclusive */
@@ -157,7 +158,7 @@
DRM_ERROR("(%ld) failed to wait for user bo\n", r);
radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r)
DRM_ERROR("(%ld) failed to validate user bo\n", r);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index b19a54d..5b6aecc 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -332,6 +332,7 @@
int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int r, i;
if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
@@ -374,7 +375,7 @@
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
}
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (likely(r == 0)) {
bo->pin_count = 1;
if (gpu_addr != NULL)
@@ -396,6 +397,7 @@
int radeon_bo_unpin(struct radeon_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int r, i;
if (!bo->pin_count) {
@@ -409,7 +411,7 @@
bo->placements[i].lpfn = 0;
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
}
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (likely(r == 0)) {
if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
bo->rdev->vram_pin_size -= radeon_bo_size(bo);
@@ -534,6 +536,7 @@
struct ww_acquire_ctx *ticket,
struct list_head *head, int ring)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct radeon_bo_list *lobj;
struct list_head duplicates;
int r;
@@ -575,7 +578,7 @@
radeon_uvd_force_into_uvd_segment(bo, allowed);
initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
initial_bytes_moved;
@@ -795,6 +798,7 @@
int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
struct radeon_device *rdev;
struct radeon_bo *rbo;
unsigned long offset, size, lpfn;
@@ -826,10 +830,10 @@
(!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
rbo->placements[i].lpfn = lpfn;
}
- r = ttm_bo_validate(bo, &rbo->placement, false, false);
+ r = ttm_bo_validate(bo, &rbo->placement, &ctx);
if (unlikely(r == -ENOMEM)) {
radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
- return ttm_bo_validate(bo, &rbo->placement, false, false);
+ return ttm_bo_validate(bo, &rbo->placement, &ctx);
} else if (unlikely(r != 0)) {
return r;
}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 8032da5..742d26f 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -311,6 +311,7 @@
bool no_wait_gpu,
struct ttm_mem_reg *new_mem)
{
+ struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
struct radeon_device *rdev;
struct ttm_mem_reg *old_mem = &bo->mem;
struct ttm_mem_reg tmp_mem;
@@ -328,8 +329,7 @@
placements.fpfn = 0;
placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
- interruptible, no_wait_gpu);
+ r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
if (unlikely(r)) {
return r;
}
@@ -339,7 +339,7 @@
goto out_cleanup;
}
- r = ttm_tt_bind(bo->ttm, &tmp_mem);
+ r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx);
if (unlikely(r)) {
goto out_cleanup;
}
@@ -347,7 +347,7 @@
if (unlikely(r)) {
goto out_cleanup;
}
- r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
+ r = ttm_bo_move_ttm(bo, &ctx, new_mem);
out_cleanup:
ttm_bo_mem_put(bo, &tmp_mem);
return r;
@@ -358,6 +358,7 @@
bool no_wait_gpu,
struct ttm_mem_reg *new_mem)
{
+ struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
struct radeon_device *rdev;
struct ttm_mem_reg *old_mem = &bo->mem;
struct ttm_mem_reg tmp_mem;
@@ -375,12 +376,11 @@
placements.fpfn = 0;
placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
- interruptible, no_wait_gpu);
+ r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
if (unlikely(r)) {
return r;
}
- r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
+ r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem);
if (unlikely(r)) {
goto out_cleanup;
}
@@ -393,17 +393,16 @@
return r;
}
-static int radeon_bo_move(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu,
- struct ttm_mem_reg *new_mem)
+static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_mem)
{
struct radeon_device *rdev;
struct radeon_bo *rbo;
struct ttm_mem_reg *old_mem = &bo->mem;
int r;
- r = ttm_bo_wait(bo, interruptible, no_wait_gpu);
+ r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (r)
return r;
@@ -433,19 +432,20 @@
if (old_mem->mem_type == TTM_PL_VRAM &&
new_mem->mem_type == TTM_PL_SYSTEM) {
- r = radeon_move_vram_ram(bo, evict, interruptible,
- no_wait_gpu, new_mem);
+ r = radeon_move_vram_ram(bo, evict, ctx->interruptible,
+ ctx->no_wait_gpu, new_mem);
} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
new_mem->mem_type == TTM_PL_VRAM) {
- r = radeon_move_ram_vram(bo, evict, interruptible,
- no_wait_gpu, new_mem);
+ r = radeon_move_ram_vram(bo, evict, ctx->interruptible,
+ ctx->no_wait_gpu, new_mem);
} else {
- r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
+ r = radeon_move_blit(bo, evict, ctx->no_wait_gpu,
+ new_mem, old_mem);
}
if (r) {
memcpy:
- r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
+ r = ttm_bo_move_memcpy(bo, ctx, new_mem);
if (r) {
return r;
}
@@ -721,7 +721,8 @@
return (struct radeon_ttm_tt *)ttm;
}
-static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
+static int radeon_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
struct radeon_device *rdev;
@@ -750,17 +751,17 @@
rdev = radeon_get_rdev(ttm->bdev);
#if IS_ENABLED(CONFIG_AGP)
if (rdev->flags & RADEON_IS_AGP) {
- return ttm_agp_tt_populate(ttm);
+ return ttm_agp_tt_populate(ttm, ctx);
}
#endif
#ifdef CONFIG_SWIOTLB
if (swiotlb_nr_tbl()) {
- return ttm_dma_populate(>t->ttm, rdev->dev);
+ return ttm_dma_populate(>t->ttm, rdev->dev, ctx);
}
#endif
- return ttm_populate_and_map_pages(rdev->dev, >t->ttm);
+ return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx);
}
static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -844,7 +845,6 @@
.fault_reserve_notify = &radeon_bo_fault_reserve_notify,
.io_mem_reserve = &radeon_ttm_io_mem_reserve,
.io_mem_free = &radeon_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
int radeon_ttm_init(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index e5c0e63..7f1a9c7 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -387,6 +387,7 @@
static int radeon_vm_clear_bo(struct radeon_device *rdev,
struct radeon_bo *bo)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct radeon_ib ib;
unsigned entries;
uint64_t addr;
@@ -396,7 +397,7 @@
if (r)
return r;
- r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r)
goto error_unreserve;
diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile
new file mode 100644
index 0000000..bd0377c
--- /dev/null
+++ b/drivers/gpu/drm/scheduler/Makefile
@@ -0,0 +1,26 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+ccflags-y := -Iinclude/drm
+gpu-sched-y := gpu_scheduler.o sched_fence.o
+
+obj-$(CONFIG_DRM_SCHED) += gpu-sched.o
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/scheduler/gpu_scheduler.c
similarity index 60%
rename from drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
rename to drivers/gpu/drm/scheduler/gpu_scheduler.c
index 1089ab8..4b11dcd 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
@@ -19,37 +19,36 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
- *
*/
+
#include <linux/kthread.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <uapi/linux/sched/types.h>
#include <drm/drmP.h>
-#include "gpu_scheduler.h"
-
-#include "spsc_queue.h"
+#include <drm/gpu_scheduler.h>
+#include <drm/spsc_queue.h>
#define CREATE_TRACE_POINTS
-#include "gpu_sched_trace.h"
+#include <drm/gpu_scheduler_trace.h>
-#define to_amd_sched_job(sched_job) \
- container_of((sched_job), struct amd_sched_job, queue_node)
+#define to_drm_sched_job(sched_job) \
+ container_of((sched_job), struct drm_sched_job, queue_node)
-static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity);
-static void amd_sched_wakeup(struct amd_gpu_scheduler *sched);
-static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb);
+static bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
+static void drm_sched_wakeup(struct drm_gpu_scheduler *sched);
+static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb);
/* Initialize a given run queue struct */
-static void amd_sched_rq_init(struct amd_sched_rq *rq)
+static void drm_sched_rq_init(struct drm_sched_rq *rq)
{
spin_lock_init(&rq->lock);
INIT_LIST_HEAD(&rq->entities);
rq->current_entity = NULL;
}
-static void amd_sched_rq_add_entity(struct amd_sched_rq *rq,
- struct amd_sched_entity *entity)
+static void drm_sched_rq_add_entity(struct drm_sched_rq *rq,
+ struct drm_sched_entity *entity)
{
if (!list_empty(&entity->list))
return;
@@ -58,8 +57,8 @@
spin_unlock(&rq->lock);
}
-static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq,
- struct amd_sched_entity *entity)
+static void drm_sched_rq_remove_entity(struct drm_sched_rq *rq,
+ struct drm_sched_entity *entity)
{
if (list_empty(&entity->list))
return;
@@ -77,17 +76,17 @@
*
* Try to find a ready entity, returns NULL if none found.
*/
-static struct amd_sched_entity *
-amd_sched_rq_select_entity(struct amd_sched_rq *rq)
+static struct drm_sched_entity *
+drm_sched_rq_select_entity(struct drm_sched_rq *rq)
{
- struct amd_sched_entity *entity;
+ struct drm_sched_entity *entity;
spin_lock(&rq->lock);
entity = rq->current_entity;
if (entity) {
list_for_each_entry_continue(entity, &rq->entities, list) {
- if (amd_sched_entity_is_ready(entity)) {
+ if (drm_sched_entity_is_ready(entity)) {
rq->current_entity = entity;
spin_unlock(&rq->lock);
return entity;
@@ -97,7 +96,7 @@
list_for_each_entry(entity, &rq->entities, list) {
- if (amd_sched_entity_is_ready(entity)) {
+ if (drm_sched_entity_is_ready(entity)) {
rq->current_entity = entity;
spin_unlock(&rq->lock);
return entity;
@@ -116,22 +115,22 @@
* Init a context entity used by scheduler when submit to HW ring.
*
* @sched The pointer to the scheduler
- * @entity The pointer to a valid amd_sched_entity
+ * @entity The pointer to a valid drm_sched_entity
* @rq The run queue this entity belongs
* @kernel If this is an entity for the kernel
* @jobs The max number of jobs in the job queue
*
* return 0 if succeed. negative error code on failure
*/
-int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity,
- struct amd_sched_rq *rq,
+int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity,
+ struct drm_sched_rq *rq,
uint32_t jobs, atomic_t *guilty)
{
if (!(sched && entity && rq))
return -EINVAL;
- memset(entity, 0, sizeof(struct amd_sched_entity));
+ memset(entity, 0, sizeof(struct drm_sched_entity));
INIT_LIST_HEAD(&entity->list);
entity->rq = rq;
entity->sched = sched;
@@ -146,6 +145,7 @@
return 0;
}
+EXPORT_SYMBOL(drm_sched_entity_init);
/**
* Query if entity is initialized
@@ -155,8 +155,8 @@
*
* return true if entity is initialized, false otherwise
*/
-static bool amd_sched_entity_is_initialized(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity)
+static bool drm_sched_entity_is_initialized(struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity)
{
return entity->sched == sched &&
entity->rq != NULL;
@@ -169,7 +169,7 @@
*
* Return true if entity don't has any unscheduled jobs.
*/
-static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity)
+static bool drm_sched_entity_is_idle(struct drm_sched_entity *entity)
{
rmb();
if (spsc_queue_peek(&entity->job_queue) == NULL)
@@ -185,7 +185,7 @@
*
* Return true if entity could provide a job.
*/
-static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
+static bool drm_sched_entity_is_ready(struct drm_sched_entity *entity)
{
if (spsc_queue_peek(&entity->job_queue) == NULL)
return false;
@@ -204,12 +204,12 @@
*
* Cleanup and free the allocated resources.
*/
-void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity)
+void drm_sched_entity_fini(struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity)
{
int r;
- if (!amd_sched_entity_is_initialized(sched, entity))
+ if (!drm_sched_entity_is_initialized(sched, entity))
return;
/**
* The client will not queue more IBs during this fini, consume existing
@@ -219,46 +219,55 @@
r = -ERESTARTSYS;
else
r = wait_event_killable(sched->job_scheduled,
- amd_sched_entity_is_idle(entity));
- amd_sched_entity_set_rq(entity, NULL);
+ drm_sched_entity_is_idle(entity));
+ drm_sched_entity_set_rq(entity, NULL);
if (r) {
- struct amd_sched_job *job;
+ struct drm_sched_job *job;
/* Park the kernel for a moment to make sure it isn't processing
* our enity.
*/
kthread_park(sched->thread);
kthread_unpark(sched->thread);
- while ((job = to_amd_sched_job(spsc_queue_pop(&entity->job_queue)))) {
- struct amd_sched_fence *s_fence = job->s_fence;
- amd_sched_fence_scheduled(s_fence);
+ if (entity->dependency) {
+ dma_fence_remove_callback(entity->dependency,
+ &entity->cb);
+ dma_fence_put(entity->dependency);
+ entity->dependency = NULL;
+ }
+
+ while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_queue)))) {
+ struct drm_sched_fence *s_fence = job->s_fence;
+ drm_sched_fence_scheduled(s_fence);
dma_fence_set_error(&s_fence->finished, -ESRCH);
- amd_sched_fence_finished(s_fence);
+ drm_sched_fence_finished(s_fence);
+ WARN_ON(s_fence->parent);
dma_fence_put(&s_fence->finished);
sched->ops->free_job(job);
}
}
}
+EXPORT_SYMBOL(drm_sched_entity_fini);
-static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb)
+static void drm_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb)
{
- struct amd_sched_entity *entity =
- container_of(cb, struct amd_sched_entity, cb);
+ struct drm_sched_entity *entity =
+ container_of(cb, struct drm_sched_entity, cb);
entity->dependency = NULL;
dma_fence_put(f);
- amd_sched_wakeup(entity->sched);
+ drm_sched_wakeup(entity->sched);
}
-static void amd_sched_entity_clear_dep(struct dma_fence *f, struct dma_fence_cb *cb)
+static void drm_sched_entity_clear_dep(struct dma_fence *f, struct dma_fence_cb *cb)
{
- struct amd_sched_entity *entity =
- container_of(cb, struct amd_sched_entity, cb);
+ struct drm_sched_entity *entity =
+ container_of(cb, struct drm_sched_entity, cb);
entity->dependency = NULL;
dma_fence_put(f);
}
-void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
- struct amd_sched_rq *rq)
+void drm_sched_entity_set_rq(struct drm_sched_entity *entity,
+ struct drm_sched_rq *rq)
{
if (entity->rq == rq)
return;
@@ -266,37 +275,39 @@
spin_lock(&entity->rq_lock);
if (entity->rq)
- amd_sched_rq_remove_entity(entity->rq, entity);
+ drm_sched_rq_remove_entity(entity->rq, entity);
entity->rq = rq;
if (rq)
- amd_sched_rq_add_entity(rq, entity);
+ drm_sched_rq_add_entity(rq, entity);
spin_unlock(&entity->rq_lock);
}
+EXPORT_SYMBOL(drm_sched_entity_set_rq);
-bool amd_sched_dependency_optimized(struct dma_fence* fence,
- struct amd_sched_entity *entity)
+bool drm_sched_dependency_optimized(struct dma_fence* fence,
+ struct drm_sched_entity *entity)
{
- struct amd_gpu_scheduler *sched = entity->sched;
- struct amd_sched_fence *s_fence;
+ struct drm_gpu_scheduler *sched = entity->sched;
+ struct drm_sched_fence *s_fence;
if (!fence || dma_fence_is_signaled(fence))
return false;
if (fence->context == entity->fence_context)
return true;
- s_fence = to_amd_sched_fence(fence);
+ s_fence = to_drm_sched_fence(fence);
if (s_fence && s_fence->sched == sched)
return true;
return false;
}
+EXPORT_SYMBOL(drm_sched_dependency_optimized);
-static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
+static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity)
{
- struct amd_gpu_scheduler *sched = entity->sched;
+ struct drm_gpu_scheduler *sched = entity->sched;
struct dma_fence * fence = entity->dependency;
- struct amd_sched_fence *s_fence;
+ struct drm_sched_fence *s_fence;
if (fence->context == entity->fence_context) {
/* We can ignore fences from ourself */
@@ -304,7 +315,7 @@
return false;
}
- s_fence = to_amd_sched_fence(fence);
+ s_fence = to_drm_sched_fence(fence);
if (s_fence && s_fence->sched == sched) {
/*
@@ -315,7 +326,7 @@
dma_fence_put(entity->dependency);
entity->dependency = fence;
if (!dma_fence_add_callback(fence, &entity->cb,
- amd_sched_entity_clear_dep))
+ drm_sched_entity_clear_dep))
return true;
/* Ignore it when it is already scheduled */
@@ -324,27 +335,31 @@
}
if (!dma_fence_add_callback(entity->dependency, &entity->cb,
- amd_sched_entity_wakeup))
+ drm_sched_entity_wakeup))
return true;
dma_fence_put(entity->dependency);
return false;
}
-static struct amd_sched_job *
-amd_sched_entity_pop_job(struct amd_sched_entity *entity)
+static struct drm_sched_job *
+drm_sched_entity_pop_job(struct drm_sched_entity *entity)
{
- struct amd_gpu_scheduler *sched = entity->sched;
- struct amd_sched_job *sched_job = to_amd_sched_job(
+ struct drm_gpu_scheduler *sched = entity->sched;
+ struct drm_sched_job *sched_job = to_drm_sched_job(
spsc_queue_peek(&entity->job_queue));
if (!sched_job)
return NULL;
while ((entity->dependency = sched->ops->dependency(sched_job, entity)))
- if (amd_sched_entity_add_dependency_cb(entity))
+ if (drm_sched_entity_add_dependency_cb(entity))
return NULL;
+ /* skip jobs from entity that marked guilty */
+ if (entity->guilty && atomic_read(entity->guilty))
+ dma_fence_set_error(&sched_job->s_fence->finished, -ECANCELED);
+
spsc_queue_pop(&entity->job_queue);
return sched_job;
}
@@ -356,13 +371,13 @@
*
* Returns 0 for success, negative error code otherwise.
*/
-void amd_sched_entity_push_job(struct amd_sched_job *sched_job,
- struct amd_sched_entity *entity)
+void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
+ struct drm_sched_entity *entity)
{
- struct amd_gpu_scheduler *sched = sched_job->sched;
+ struct drm_gpu_scheduler *sched = sched_job->sched;
bool first = false;
- trace_amd_sched_job(sched_job, entity);
+ trace_drm_sched_job(sched_job, entity);
spin_lock(&entity->queue_lock);
first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
@@ -373,25 +388,26 @@
if (first) {
/* Add the entity to the run queue */
spin_lock(&entity->rq_lock);
- amd_sched_rq_add_entity(entity->rq, entity);
+ drm_sched_rq_add_entity(entity->rq, entity);
spin_unlock(&entity->rq_lock);
- amd_sched_wakeup(sched);
+ drm_sched_wakeup(sched);
}
}
+EXPORT_SYMBOL(drm_sched_entity_push_job);
/* job_finish is called after hw fence signaled
*/
-static void amd_sched_job_finish(struct work_struct *work)
+static void drm_sched_job_finish(struct work_struct *work)
{
- struct amd_sched_job *s_job = container_of(work, struct amd_sched_job,
+ struct drm_sched_job *s_job = container_of(work, struct drm_sched_job,
finish_work);
- struct amd_gpu_scheduler *sched = s_job->sched;
+ struct drm_gpu_scheduler *sched = s_job->sched;
/* remove job from ring_mirror_list */
spin_lock(&sched->job_list_lock);
list_del_init(&s_job->node);
if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
- struct amd_sched_job *next;
+ struct drm_sched_job *next;
spin_unlock(&sched->job_list_lock);
cancel_delayed_work_sync(&s_job->work_tdr);
@@ -399,7 +415,7 @@
/* queue TDR for next job */
next = list_first_entry_or_null(&sched->ring_mirror_list,
- struct amd_sched_job, node);
+ struct drm_sched_job, node);
if (next)
schedule_delayed_work(&next->work_tdr, sched->timeout);
@@ -409,50 +425,42 @@
sched->ops->free_job(s_job);
}
-static void amd_sched_job_finish_cb(struct dma_fence *f,
+static void drm_sched_job_finish_cb(struct dma_fence *f,
struct dma_fence_cb *cb)
{
- struct amd_sched_job *job = container_of(cb, struct amd_sched_job,
+ struct drm_sched_job *job = container_of(cb, struct drm_sched_job,
finish_cb);
schedule_work(&job->finish_work);
}
-static void amd_sched_job_begin(struct amd_sched_job *s_job)
+static void drm_sched_job_begin(struct drm_sched_job *s_job)
{
- struct amd_gpu_scheduler *sched = s_job->sched;
+ struct drm_gpu_scheduler *sched = s_job->sched;
dma_fence_add_callback(&s_job->s_fence->finished, &s_job->finish_cb,
- amd_sched_job_finish_cb);
+ drm_sched_job_finish_cb);
spin_lock(&sched->job_list_lock);
list_add_tail(&s_job->node, &sched->ring_mirror_list);
if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
list_first_entry_or_null(&sched->ring_mirror_list,
- struct amd_sched_job, node) == s_job)
+ struct drm_sched_job, node) == s_job)
schedule_delayed_work(&s_job->work_tdr, sched->timeout);
spin_unlock(&sched->job_list_lock);
}
-static void amd_sched_job_timedout(struct work_struct *work)
+static void drm_sched_job_timedout(struct work_struct *work)
{
- struct amd_sched_job *job = container_of(work, struct amd_sched_job,
+ struct drm_sched_job *job = container_of(work, struct drm_sched_job,
work_tdr.work);
job->sched->ops->timedout_job(job);
}
-static void amd_sched_set_guilty(struct amd_sched_job *s_job,
- struct amd_sched_entity *s_entity)
+void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
{
- if (atomic_inc_return(&s_job->karma) > s_job->sched->hang_limit)
- if (s_entity->guilty)
- atomic_set(s_entity->guilty, 1);
-}
-
-void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad)
-{
- struct amd_sched_job *s_job;
- struct amd_sched_entity *entity, *tmp;
+ struct drm_sched_job *s_job;
+ struct drm_sched_entity *entity, *tmp;
int i;;
spin_lock(&sched->job_list_lock);
@@ -467,50 +475,56 @@
}
spin_unlock(&sched->job_list_lock);
- if (bad) {
- bool found = false;
-
- for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++ ) {
- struct amd_sched_rq *rq = &sched->sched_rq[i];
+ if (bad && bad->s_priority != DRM_SCHED_PRIORITY_KERNEL) {
+ atomic_inc(&bad->karma);
+ /* don't increase @bad's karma if it's from KERNEL RQ,
+ * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs)
+ * corrupt but keep in mind that kernel jobs always considered good.
+ */
+ for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_KERNEL; i++ ) {
+ struct drm_sched_rq *rq = &sched->sched_rq[i];
spin_lock(&rq->lock);
list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
if (bad->s_fence->scheduled.context == entity->fence_context) {
- found = true;
- amd_sched_set_guilty(bad, entity);
+ if (atomic_read(&bad->karma) > bad->sched->hang_limit)
+ if (entity->guilty)
+ atomic_set(entity->guilty, 1);
break;
}
}
spin_unlock(&rq->lock);
- if (found)
+ if (&entity->list != &rq->entities)
break;
}
}
}
+EXPORT_SYMBOL(drm_sched_hw_job_reset);
-void amd_sched_job_kickout(struct amd_sched_job *s_job)
+void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
{
- struct amd_gpu_scheduler *sched = s_job->sched;
-
- spin_lock(&sched->job_list_lock);
- list_del_init(&s_job->node);
- spin_unlock(&sched->job_list_lock);
-}
-
-void amd_sched_job_recovery(struct amd_gpu_scheduler *sched)
-{
- struct amd_sched_job *s_job, *tmp;
+ struct drm_sched_job *s_job, *tmp;
+ bool found_guilty = false;
int r;
spin_lock(&sched->job_list_lock);
s_job = list_first_entry_or_null(&sched->ring_mirror_list,
- struct amd_sched_job, node);
+ struct drm_sched_job, node);
if (s_job && sched->timeout != MAX_SCHEDULE_TIMEOUT)
schedule_delayed_work(&s_job->work_tdr, sched->timeout);
list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
- struct amd_sched_fence *s_fence = s_job->s_fence;
+ struct drm_sched_fence *s_fence = s_job->s_fence;
struct dma_fence *fence;
+ uint64_t guilty_context;
+
+ if (!found_guilty && atomic_read(&s_job->karma) > sched->hang_limit) {
+ found_guilty = true;
+ guilty_context = s_job->s_fence->scheduled.context;
+ }
+
+ if (found_guilty && s_job->s_fence->scheduled.context == guilty_context)
+ dma_fence_set_error(&s_fence->finished, -ECANCELED);
spin_unlock(&sched->job_list_lock);
fence = sched->ops->run_job(s_job);
@@ -518,46 +532,47 @@
if (fence) {
s_fence->parent = dma_fence_get(fence);
r = dma_fence_add_callback(fence, &s_fence->cb,
- amd_sched_process_job);
+ drm_sched_process_job);
if (r == -ENOENT)
- amd_sched_process_job(fence, &s_fence->cb);
+ drm_sched_process_job(fence, &s_fence->cb);
else if (r)
DRM_ERROR("fence add callback failed (%d)\n",
r);
dma_fence_put(fence);
} else {
- DRM_ERROR("Failed to run job!\n");
- amd_sched_process_job(NULL, &s_fence->cb);
+ drm_sched_process_job(NULL, &s_fence->cb);
}
spin_lock(&sched->job_list_lock);
}
spin_unlock(&sched->job_list_lock);
}
+EXPORT_SYMBOL(drm_sched_job_recovery);
/* init a sched_job with basic field */
-int amd_sched_job_init(struct amd_sched_job *job,
- struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity,
+int drm_sched_job_init(struct drm_sched_job *job,
+ struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity,
void *owner)
{
job->sched = sched;
job->s_priority = entity->rq - sched->sched_rq;
- job->s_fence = amd_sched_fence_create(entity, owner);
+ job->s_fence = drm_sched_fence_create(entity, owner);
if (!job->s_fence)
return -ENOMEM;
job->id = atomic64_inc_return(&sched->job_id_count);
- INIT_WORK(&job->finish_work, amd_sched_job_finish);
+ INIT_WORK(&job->finish_work, drm_sched_job_finish);
INIT_LIST_HEAD(&job->node);
- INIT_DELAYED_WORK(&job->work_tdr, amd_sched_job_timedout);
+ INIT_DELAYED_WORK(&job->work_tdr, drm_sched_job_timedout);
return 0;
}
+EXPORT_SYMBOL(drm_sched_job_init);
/**
* Return ture if we can push more jobs to the hw.
*/
-static bool amd_sched_ready(struct amd_gpu_scheduler *sched)
+static bool drm_sched_ready(struct drm_gpu_scheduler *sched)
{
return atomic_read(&sched->hw_rq_count) <
sched->hw_submission_limit;
@@ -566,27 +581,27 @@
/**
* Wake up the scheduler when it is ready
*/
-static void amd_sched_wakeup(struct amd_gpu_scheduler *sched)
+static void drm_sched_wakeup(struct drm_gpu_scheduler *sched)
{
- if (amd_sched_ready(sched))
+ if (drm_sched_ready(sched))
wake_up_interruptible(&sched->wake_up_worker);
}
/**
* Select next entity to process
*/
-static struct amd_sched_entity *
-amd_sched_select_entity(struct amd_gpu_scheduler *sched)
+static struct drm_sched_entity *
+drm_sched_select_entity(struct drm_gpu_scheduler *sched)
{
- struct amd_sched_entity *entity;
+ struct drm_sched_entity *entity;
int i;
- if (!amd_sched_ready(sched))
+ if (!drm_sched_ready(sched))
return NULL;
/* Kernel run queue has higher priority than normal run queue*/
- for (i = AMD_SCHED_PRIORITY_MAX - 1; i >= AMD_SCHED_PRIORITY_MIN; i--) {
- entity = amd_sched_rq_select_entity(&sched->sched_rq[i]);
+ for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
+ entity = drm_sched_rq_select_entity(&sched->sched_rq[i]);
if (entity)
break;
}
@@ -594,22 +609,22 @@
return entity;
}
-static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb)
+static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb)
{
- struct amd_sched_fence *s_fence =
- container_of(cb, struct amd_sched_fence, cb);
- struct amd_gpu_scheduler *sched = s_fence->sched;
+ struct drm_sched_fence *s_fence =
+ container_of(cb, struct drm_sched_fence, cb);
+ struct drm_gpu_scheduler *sched = s_fence->sched;
dma_fence_get(&s_fence->finished);
atomic_dec(&sched->hw_rq_count);
- amd_sched_fence_finished(s_fence);
+ drm_sched_fence_finished(s_fence);
- trace_amd_sched_process_job(s_fence);
+ trace_drm_sched_process_job(s_fence);
dma_fence_put(&s_fence->finished);
wake_up_interruptible(&sched->wake_up_worker);
}
-static bool amd_sched_blocked(struct amd_gpu_scheduler *sched)
+static bool drm_sched_blocked(struct drm_gpu_scheduler *sched)
{
if (kthread_should_park()) {
kthread_parkme();
@@ -619,53 +634,52 @@
return false;
}
-static int amd_sched_main(void *param)
+static int drm_sched_main(void *param)
{
struct sched_param sparam = {.sched_priority = 1};
- struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param;
+ struct drm_gpu_scheduler *sched = (struct drm_gpu_scheduler *)param;
int r;
sched_setscheduler(current, SCHED_FIFO, &sparam);
while (!kthread_should_stop()) {
- struct amd_sched_entity *entity = NULL;
- struct amd_sched_fence *s_fence;
- struct amd_sched_job *sched_job;
+ struct drm_sched_entity *entity = NULL;
+ struct drm_sched_fence *s_fence;
+ struct drm_sched_job *sched_job;
struct dma_fence *fence;
wait_event_interruptible(sched->wake_up_worker,
- (!amd_sched_blocked(sched) &&
- (entity = amd_sched_select_entity(sched))) ||
+ (!drm_sched_blocked(sched) &&
+ (entity = drm_sched_select_entity(sched))) ||
kthread_should_stop());
if (!entity)
continue;
- sched_job = amd_sched_entity_pop_job(entity);
+ sched_job = drm_sched_entity_pop_job(entity);
if (!sched_job)
continue;
s_fence = sched_job->s_fence;
atomic_inc(&sched->hw_rq_count);
- amd_sched_job_begin(sched_job);
+ drm_sched_job_begin(sched_job);
fence = sched->ops->run_job(sched_job);
- amd_sched_fence_scheduled(s_fence);
+ drm_sched_fence_scheduled(s_fence);
if (fence) {
s_fence->parent = dma_fence_get(fence);
r = dma_fence_add_callback(fence, &s_fence->cb,
- amd_sched_process_job);
+ drm_sched_process_job);
if (r == -ENOENT)
- amd_sched_process_job(fence, &s_fence->cb);
+ drm_sched_process_job(fence, &s_fence->cb);
else if (r)
DRM_ERROR("fence add callback failed (%d)\n",
r);
dma_fence_put(fence);
} else {
- DRM_ERROR("Failed to run job!\n");
- amd_sched_process_job(NULL, &s_fence->cb);
+ drm_sched_process_job(NULL, &s_fence->cb);
}
wake_up(&sched->job_scheduled);
@@ -683,8 +697,8 @@
*
* Return 0 on success, otherwise error code.
*/
-int amd_sched_init(struct amd_gpu_scheduler *sched,
- const struct amd_sched_backend_ops *ops,
+int drm_sched_init(struct drm_gpu_scheduler *sched,
+ const struct drm_sched_backend_ops *ops,
unsigned hw_submission,
unsigned hang_limit,
long timeout,
@@ -696,8 +710,8 @@
sched->name = name;
sched->timeout = timeout;
sched->hang_limit = hang_limit;
- for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++)
- amd_sched_rq_init(&sched->sched_rq[i]);
+ for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_MAX; i++)
+ drm_sched_rq_init(&sched->sched_rq[i]);
init_waitqueue_head(&sched->wake_up_worker);
init_waitqueue_head(&sched->job_scheduled);
@@ -707,7 +721,7 @@
atomic64_set(&sched->job_id_count, 0);
/* Each scheduler will run on a seperate kernel thread */
- sched->thread = kthread_run(amd_sched_main, sched, sched->name);
+ sched->thread = kthread_run(drm_sched_main, sched, sched->name);
if (IS_ERR(sched->thread)) {
DRM_ERROR("Failed to create scheduler for %s.\n", name);
return PTR_ERR(sched->thread);
@@ -715,14 +729,16 @@
return 0;
}
+EXPORT_SYMBOL(drm_sched_init);
/**
* Destroy a gpu scheduler
*
* @sched The pointer to the scheduler
*/
-void amd_sched_fini(struct amd_gpu_scheduler *sched)
+void drm_sched_fini(struct drm_gpu_scheduler *sched)
{
if (sched->thread)
kthread_stop(sched->thread);
}
+EXPORT_SYMBOL(drm_sched_fini);
diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c
new file mode 100644
index 0000000..69aab086
--- /dev/null
+++ b/drivers/gpu/drm/scheduler/sched_fence.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/kthread.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <drm/drmP.h>
+#include <drm/gpu_scheduler.h>
+
+static struct kmem_cache *sched_fence_slab;
+
+static int __init drm_sched_fence_slab_init(void)
+{
+ sched_fence_slab = kmem_cache_create(
+ "drm_sched_fence", sizeof(struct drm_sched_fence), 0,
+ SLAB_HWCACHE_ALIGN, NULL);
+ if (!sched_fence_slab)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void __exit drm_sched_fence_slab_fini(void)
+{
+ rcu_barrier();
+ kmem_cache_destroy(sched_fence_slab);
+}
+
+void drm_sched_fence_scheduled(struct drm_sched_fence *fence)
+{
+ int ret = dma_fence_signal(&fence->scheduled);
+
+ if (!ret)
+ DMA_FENCE_TRACE(&fence->scheduled,
+ "signaled from irq context\n");
+ else
+ DMA_FENCE_TRACE(&fence->scheduled,
+ "was already signaled\n");
+}
+
+void drm_sched_fence_finished(struct drm_sched_fence *fence)
+{
+ int ret = dma_fence_signal(&fence->finished);
+
+ if (!ret)
+ DMA_FENCE_TRACE(&fence->finished,
+ "signaled from irq context\n");
+ else
+ DMA_FENCE_TRACE(&fence->finished,
+ "was already signaled\n");
+}
+
+static const char *drm_sched_fence_get_driver_name(struct dma_fence *fence)
+{
+ return "drm_sched";
+}
+
+static const char *drm_sched_fence_get_timeline_name(struct dma_fence *f)
+{
+ struct drm_sched_fence *fence = to_drm_sched_fence(f);
+ return (const char *)fence->sched->name;
+}
+
+static bool drm_sched_fence_enable_signaling(struct dma_fence *f)
+{
+ return true;
+}
+
+/**
+ * amd_sched_fence_free - free up the fence memory
+ *
+ * @rcu: RCU callback head
+ *
+ * Free up the fence memory after the RCU grace period.
+ */
+static void drm_sched_fence_free(struct rcu_head *rcu)
+{
+ struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
+ struct drm_sched_fence *fence = to_drm_sched_fence(f);
+
+ dma_fence_put(fence->parent);
+ kmem_cache_free(sched_fence_slab, fence);
+}
+
+/**
+ * amd_sched_fence_release_scheduled - callback that fence can be freed
+ *
+ * @fence: fence
+ *
+ * This function is called when the reference count becomes zero.
+ * It just RCU schedules freeing up the fence.
+ */
+static void drm_sched_fence_release_scheduled(struct dma_fence *f)
+{
+ struct drm_sched_fence *fence = to_drm_sched_fence(f);
+
+ call_rcu(&fence->finished.rcu, drm_sched_fence_free);
+}
+
+/**
+ * amd_sched_fence_release_finished - drop extra reference
+ *
+ * @f: fence
+ *
+ * Drop the extra reference from the scheduled fence to the base fence.
+ */
+static void drm_sched_fence_release_finished(struct dma_fence *f)
+{
+ struct drm_sched_fence *fence = to_drm_sched_fence(f);
+
+ dma_fence_put(&fence->scheduled);
+}
+
+const struct dma_fence_ops drm_sched_fence_ops_scheduled = {
+ .get_driver_name = drm_sched_fence_get_driver_name,
+ .get_timeline_name = drm_sched_fence_get_timeline_name,
+ .enable_signaling = drm_sched_fence_enable_signaling,
+ .signaled = NULL,
+ .wait = dma_fence_default_wait,
+ .release = drm_sched_fence_release_scheduled,
+};
+
+const struct dma_fence_ops drm_sched_fence_ops_finished = {
+ .get_driver_name = drm_sched_fence_get_driver_name,
+ .get_timeline_name = drm_sched_fence_get_timeline_name,
+ .enable_signaling = drm_sched_fence_enable_signaling,
+ .signaled = NULL,
+ .wait = dma_fence_default_wait,
+ .release = drm_sched_fence_release_finished,
+};
+
+struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f)
+{
+ if (f->ops == &drm_sched_fence_ops_scheduled)
+ return container_of(f, struct drm_sched_fence, scheduled);
+
+ if (f->ops == &drm_sched_fence_ops_finished)
+ return container_of(f, struct drm_sched_fence, finished);
+
+ return NULL;
+}
+EXPORT_SYMBOL(to_drm_sched_fence);
+
+struct drm_sched_fence *drm_sched_fence_create(struct drm_sched_entity *entity,
+ void *owner)
+{
+ struct drm_sched_fence *fence = NULL;
+ unsigned seq;
+
+ fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL);
+ if (fence == NULL)
+ return NULL;
+
+ fence->owner = owner;
+ fence->sched = entity->sched;
+ spin_lock_init(&fence->lock);
+
+ seq = atomic_inc_return(&entity->fence_seq);
+ dma_fence_init(&fence->scheduled, &drm_sched_fence_ops_scheduled,
+ &fence->lock, entity->fence_context, seq);
+ dma_fence_init(&fence->finished, &drm_sched_fence_ops_finished,
+ &fence->lock, entity->fence_context + 1, seq);
+
+ return fence;
+}
+
+module_init(drm_sched_fence_slab_init);
+module_exit(drm_sched_fence_slab_fini);
+
+MODULE_DESCRIPTION("DRM GPU scheduler");
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 0598b4c..b61819d 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -155,8 +155,7 @@
order = __ffs(tegra->domain->pgsize_bitmap);
init_iova_domain(&tegra->carveout.domain, 1UL << order,
- carveout_start >> order,
- carveout_end >> order);
+ carveout_start >> order);
tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
diff --git a/drivers/gpu/drm/tinydrm/core/tinydrm-core.c b/drivers/gpu/drm/tinydrm/core/tinydrm-core.c
index 1a8a57c..4c661627 100644
--- a/drivers/gpu/drm/tinydrm/core/tinydrm-core.c
+++ b/drivers/gpu/drm/tinydrm/core/tinydrm-core.c
@@ -10,6 +10,7 @@
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/tinydrm/tinydrm.h>
#include <linux/device.h>
@@ -36,23 +37,6 @@
*/
/**
- * tinydrm_lastclose - DRM lastclose helper
- * @drm: DRM device
- *
- * This function ensures that fbdev is restored when drm_lastclose() is called
- * on the last drm_release(). Drivers can use this as their
- * &drm_driver->lastclose callback.
- */
-void tinydrm_lastclose(struct drm_device *drm)
-{
- struct tinydrm_device *tdev = drm->dev_private;
-
- DRM_DEBUG_KMS("\n");
- drm_fbdev_cma_restore_mode(tdev->fbdev_cma);
-}
-EXPORT_SYMBOL(tinydrm_lastclose);
-
-/**
* tinydrm_gem_cma_prime_import_sg_table - Produce a CMA GEM object from
* another driver's scatter/gather table of pinned pages
* @drm: DRM device to import into
@@ -214,35 +198,24 @@
static int tinydrm_register(struct tinydrm_device *tdev)
{
struct drm_device *drm = tdev->drm;
- int bpp = drm->mode_config.preferred_depth;
- struct drm_fbdev_cma *fbdev;
int ret;
ret = drm_dev_register(tdev->drm, 0);
if (ret)
return ret;
- fbdev = drm_fbdev_cma_init_with_funcs(drm, bpp ? bpp : 32,
- drm->mode_config.num_connector,
- tdev->fb_funcs);
- if (IS_ERR(fbdev))
- DRM_ERROR("Failed to initialize fbdev: %ld\n", PTR_ERR(fbdev));
- else
- tdev->fbdev_cma = fbdev;
+ ret = drm_fb_cma_fbdev_init_with_funcs(drm, 0, 0, tdev->fb_funcs);
+ if (ret)
+ DRM_ERROR("Failed to initialize fbdev: %d\n", ret);
return 0;
}
static void tinydrm_unregister(struct tinydrm_device *tdev)
{
- struct drm_fbdev_cma *fbdev_cma = tdev->fbdev_cma;
-
drm_atomic_helper_shutdown(tdev->drm);
- /* don't restore fbdev in lastclose, keep pipeline disabled */
- tdev->fbdev_cma = NULL;
+ drm_fb_cma_fbdev_fini(tdev->drm);
drm_dev_unregister(tdev->drm);
- if (fbdev_cma)
- drm_fbdev_cma_fini(fbdev_cma);
}
static void devm_tinydrm_register_release(void *data)
@@ -292,71 +265,4 @@
}
EXPORT_SYMBOL(tinydrm_shutdown);
-/**
- * tinydrm_suspend - Suspend tinydrm
- * @tdev: tinydrm device
- *
- * Used in driver PM operations to suspend tinydrm.
- * Suspends fbdev and DRM.
- * Resume with tinydrm_resume().
- *
- * Returns:
- * Zero on success, negative error code on failure.
- */
-int tinydrm_suspend(struct tinydrm_device *tdev)
-{
- struct drm_atomic_state *state;
-
- if (tdev->suspend_state) {
- DRM_ERROR("Failed to suspend: state already set\n");
- return -EINVAL;
- }
-
- drm_fbdev_cma_set_suspend_unlocked(tdev->fbdev_cma, 1);
- state = drm_atomic_helper_suspend(tdev->drm);
- if (IS_ERR(state)) {
- drm_fbdev_cma_set_suspend_unlocked(tdev->fbdev_cma, 0);
- return PTR_ERR(state);
- }
-
- tdev->suspend_state = state;
-
- return 0;
-}
-EXPORT_SYMBOL(tinydrm_suspend);
-
-/**
- * tinydrm_resume - Resume tinydrm
- * @tdev: tinydrm device
- *
- * Used in driver PM operations to resume tinydrm.
- * Suspend with tinydrm_suspend().
- *
- * Returns:
- * Zero on success, negative error code on failure.
- */
-int tinydrm_resume(struct tinydrm_device *tdev)
-{
- struct drm_atomic_state *state = tdev->suspend_state;
- int ret;
-
- if (!state) {
- DRM_ERROR("Failed to resume: state is not set\n");
- return -EINVAL;
- }
-
- tdev->suspend_state = NULL;
-
- ret = drm_atomic_helper_resume(tdev->drm, state);
- if (ret) {
- DRM_ERROR("Error resuming state: %d\n", ret);
- return ret;
- }
-
- drm_fbdev_cma_set_suspend_unlocked(tdev->fbdev_cma, 0);
-
- return 0;
-}
-EXPORT_SYMBOL(tinydrm_resume);
-
MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/tinydrm/mi0283qt.c b/drivers/gpu/drm/tinydrm/mi0283qt.c
index 7e5bb7d..ab41d136 100644
--- a/drivers/gpu/drm/tinydrm/mi0283qt.c
+++ b/drivers/gpu/drm/tinydrm/mi0283qt.c
@@ -9,6 +9,8 @@
* (at your option) any later version.
*/
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_modeset_helper.h>
#include <drm/tinydrm/ili9341.h>
#include <drm/tinydrm/mipi-dbi.h>
#include <drm/tinydrm/tinydrm-helpers.h>
@@ -139,7 +141,7 @@
DRIVER_ATOMIC,
.fops = &mi0283qt_fops,
TINYDRM_GEM_DRIVER_OPS,
- .lastclose = tinydrm_lastclose,
+ .lastclose = drm_fb_helper_lastclose,
.debugfs_init = mipi_dbi_debugfs_init,
.name = "mi0283qt",
.desc = "Multi-Inno MI0283QT",
@@ -243,7 +245,7 @@
struct mipi_dbi *mipi = dev_get_drvdata(dev);
int ret;
- ret = tinydrm_suspend(&mipi->tinydrm);
+ ret = drm_mode_config_helper_suspend(mipi->tinydrm.drm);
if (ret)
return ret;
@@ -261,7 +263,9 @@
if (ret)
return ret;
- return tinydrm_resume(&mipi->tinydrm);
+ drm_mode_config_helper_resume(mipi->tinydrm.drm);
+
+ return 0;
}
static const struct dev_pm_ops mi0283qt_pm_ops = {
diff --git a/drivers/gpu/drm/tinydrm/mipi-dbi.c b/drivers/gpu/drm/tinydrm/mipi-dbi.c
index d379b26..18cd72a 100644
--- a/drivers/gpu/drm/tinydrm/mipi-dbi.c
+++ b/drivers/gpu/drm/tinydrm/mipi-dbi.c
@@ -154,8 +154,18 @@
}
EXPORT_SYMBOL(mipi_dbi_command_buf);
-static int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
- struct drm_clip_rect *clip, bool swap)
+/**
+ * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
+ * @dst: The destination buffer
+ * @fb: The source framebuffer
+ * @clip: Clipping rectangle of the area to be copied
+ * @swap: When true, swap MSB/LSB of 16-bit values
+ *
+ * Returns:
+ * Zero on success, negative error code on failure.
+ */
+int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
+ struct drm_clip_rect *clip, bool swap)
{
struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
@@ -192,6 +202,7 @@
DMA_FROM_DEVICE);
return ret;
}
+EXPORT_SYMBOL(mipi_dbi_buf_copy);
static int mipi_dbi_fb_dirty(struct drm_framebuffer *fb,
struct drm_file *file_priv,
@@ -444,18 +455,23 @@
#if IS_ENABLED(CONFIG_SPI)
-/*
+/**
+ * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
+ * @spi: SPI device
+ * @len: The transfer buffer length.
+ *
* Many controllers have a max speed of 10MHz, but can be pushed way beyond
* that. Increase reliability by running pixel data at max speed and the rest
* at 10MHz, preventing transfer glitches from messing up the init settings.
*/
-static u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
+u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
{
if (len > 64)
return 0; /* use default */
return min_t(u32, 10000000, spi->max_speed_hz);
}
+EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
/*
* MIPI DBI Type C Option 1
diff --git a/drivers/gpu/drm/tinydrm/st7586.c b/drivers/gpu/drm/tinydrm/st7586.c
index 72eab2d..0009110 100644
--- a/drivers/gpu/drm/tinydrm/st7586.c
+++ b/drivers/gpu/drm/tinydrm/st7586.c
@@ -17,6 +17,7 @@
#include <linux/spi/spi.h>
#include <video/mipi_display.h>
+#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/tinydrm/mipi-dbi.h>
#include <drm/tinydrm/tinydrm-helpers.h>
@@ -320,7 +321,7 @@
DRIVER_ATOMIC,
.fops = &st7586_fops,
TINYDRM_GEM_DRIVER_OPS,
- .lastclose = tinydrm_lastclose,
+ .lastclose = drm_fb_helper_lastclose,
.debugfs_init = mipi_dbi_debugfs_init,
.name = "st7586",
.desc = "Sitronix ST7586",
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c
index 028ab60..3e795a0 100644
--- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -133,12 +133,12 @@
}
EXPORT_SYMBOL(ttm_agp_tt_create);
-int ttm_agp_tt_populate(struct ttm_tt *ttm)
+int ttm_agp_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
if (ttm->state != tt_unpopulated)
return 0;
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
EXPORT_SYMBOL(ttm_agp_tt_populate);
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 68eed68..2fef09a5 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -42,11 +42,6 @@
#include <linux/atomic.h>
#include <linux/reservation.h>
-#define TTM_ASSERT_LOCKED(param)
-#define TTM_DEBUG(fmt, arg...)
-#define TTM_BO_HASH_ORDER 13
-
-static int ttm_bo_swapout(struct ttm_mem_shrink *shrink);
static void ttm_bo_global_kobj_release(struct kobject *kobj);
static struct attribute ttm_bo_count = {
@@ -165,7 +160,7 @@
struct ttm_bo_device *bdev = bo->bdev;
struct ttm_mem_type_manager *man;
- lockdep_assert_held(&bo->resv->lock.base);
+ reservation_object_assert_held(bo->resv);
if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
@@ -217,7 +212,7 @@
void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo)
{
- lockdep_assert_held(&bo->resv->lock.base);
+ reservation_object_assert_held(bo->resv);
ttm_bo_del_from_lru(bo);
ttm_bo_add_to_lru(bo);
@@ -234,7 +229,7 @@
int ret = 0;
uint32_t page_flags = 0;
- TTM_ASSERT_LOCKED(&bo->mutex);
+ reservation_object_assert_held(bo->resv);
bo->ttm = NULL;
if (bdev->need_dma32)
@@ -270,9 +265,8 @@
}
static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo,
- struct ttm_mem_reg *mem,
- bool evict, bool interruptible,
- bool no_wait_gpu)
+ struct ttm_mem_reg *mem, bool evict,
+ struct ttm_operation_ctx *ctx)
{
struct ttm_bo_device *bdev = bo->bdev;
bool old_is_pci = ttm_mem_reg_is_pci(bdev, &bo->mem);
@@ -307,7 +301,7 @@
goto out_err;
if (mem->mem_type != TTM_PL_SYSTEM) {
- ret = ttm_tt_bind(bo->ttm, mem);
+ ret = ttm_tt_bind(bo->ttm, mem, ctx);
if (ret)
goto out_err;
}
@@ -326,12 +320,11 @@
if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) &&
!(new_man->flags & TTM_MEMTYPE_FLAG_FIXED))
- ret = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, mem);
+ ret = ttm_bo_move_ttm(bo, ctx, mem);
else if (bdev->driver->move)
- ret = bdev->driver->move(bo, evict, interruptible,
- no_wait_gpu, mem);
+ ret = bdev->driver->move(bo, evict, ctx, mem);
else
- ret = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, mem);
+ ret = ttm_bo_move_memcpy(bo, ctx, mem);
if (ret) {
if (bdev->driver->move_notify) {
@@ -356,13 +349,13 @@
bo->evicted = false;
}
- if (bo->mem.mm_node) {
+ if (bo->mem.mm_node)
bo->offset = (bo->mem.start << PAGE_SHIFT) +
bdev->man[bo->mem.mem_type].gpu_offset;
- bo->cur_placement = bo->mem.placement;
- } else
+ else
bo->offset = 0;
+ ctx->bytes_moved += bo->num_pages << PAGE_SHIFT;
return 0;
out_err:
@@ -391,8 +384,6 @@
ttm_tt_destroy(bo->ttm);
bo->ttm = NULL;
ttm_bo_mem_put(bo, &bo->mem);
-
- ww_mutex_unlock (&bo->resv->lock);
}
static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo)
@@ -449,7 +440,7 @@
}
spin_lock(&glob->lru_lock);
- ret = __ttm_bo_reserve(bo, false, true, NULL);
+ ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY;
if (!ret) {
if (reservation_object_test_signaled_rcu(&bo->ttm_resv, true)) {
ttm_bo_del_from_lru(bo);
@@ -458,6 +449,7 @@
reservation_object_unlock(&bo->ttm_resv);
ttm_bo_cleanup_memtype_use(bo);
+ reservation_object_unlock(bo->resv);
return;
}
@@ -473,7 +465,7 @@
ttm_bo_add_to_lru(bo);
}
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
}
if (bo->resv != &bo->ttm_resv)
reservation_object_unlock(&bo->ttm_resv);
@@ -488,20 +480,21 @@
}
/**
- * function ttm_bo_cleanup_refs_and_unlock
+ * function ttm_bo_cleanup_refs
* If bo idle, remove from delayed- and lru lists, and unref.
* If not idle, do nothing.
*
* Must be called with lru_lock and reservation held, this function
- * will drop both before returning.
+ * will drop the lru lock and optionally the reservation lock before returning.
*
* @interruptible Any sleeps should occur interruptibly.
* @no_wait_gpu Never wait for gpu. Return -EBUSY instead.
+ * @unlock_resv Unlock the reservation lock as well.
*/
-static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo,
- bool interruptible,
- bool no_wait_gpu)
+static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo,
+ bool interruptible, bool no_wait_gpu,
+ bool unlock_resv)
{
struct ttm_bo_global *glob = bo->glob;
struct reservation_object *resv;
@@ -519,7 +512,9 @@
if (ret && !no_wait_gpu) {
long lret;
- ww_mutex_unlock(&bo->resv->lock);
+
+ if (unlock_resv)
+ reservation_object_unlock(bo->resv);
spin_unlock(&glob->lru_lock);
lret = reservation_object_wait_timeout_rcu(resv, true,
@@ -532,24 +527,24 @@
return -EBUSY;
spin_lock(&glob->lru_lock);
- ret = __ttm_bo_reserve(bo, false, true, NULL);
-
- /*
- * We raced, and lost, someone else holds the reservation now,
- * and is probably busy in ttm_bo_cleanup_memtype_use.
- *
- * Even if it's not the case, because we finished waiting any
- * delayed destruction would succeed, so just return success
- * here.
- */
- if (ret) {
+ if (unlock_resv && !reservation_object_trylock(bo->resv)) {
+ /*
+ * We raced, and lost, someone else holds the reservation now,
+ * and is probably busy in ttm_bo_cleanup_memtype_use.
+ *
+ * Even if it's not the case, because we finished waiting any
+ * delayed destruction would succeed, so just return success
+ * here.
+ */
spin_unlock(&glob->lru_lock);
return 0;
}
+ ret = 0;
}
if (ret || unlikely(list_empty(&bo->ddestroy))) {
- __ttm_bo_unreserve(bo);
+ if (unlock_resv)
+ reservation_object_unlock(bo->resv);
spin_unlock(&glob->lru_lock);
return ret;
}
@@ -561,6 +556,9 @@
spin_unlock(&glob->lru_lock);
ttm_bo_cleanup_memtype_use(bo);
+ if (unlock_resv)
+ reservation_object_unlock(bo->resv);
+
return 0;
}
@@ -568,60 +566,44 @@
* Traverse the delayed list, and call ttm_bo_cleanup_refs on all
* encountered buffers.
*/
-
-static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
+static bool ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
{
struct ttm_bo_global *glob = bdev->glob;
- struct ttm_buffer_object *entry = NULL;
- int ret = 0;
+ struct list_head removed;
+ bool empty;
+
+ INIT_LIST_HEAD(&removed);
spin_lock(&glob->lru_lock);
- if (list_empty(&bdev->ddestroy))
- goto out_unlock;
+ while (!list_empty(&bdev->ddestroy)) {
+ struct ttm_buffer_object *bo;
- entry = list_first_entry(&bdev->ddestroy,
- struct ttm_buffer_object, ddestroy);
- kref_get(&entry->list_kref);
+ bo = list_first_entry(&bdev->ddestroy, struct ttm_buffer_object,
+ ddestroy);
+ kref_get(&bo->list_kref);
+ list_move_tail(&bo->ddestroy, &removed);
- for (;;) {
- struct ttm_buffer_object *nentry = NULL;
-
- if (entry->ddestroy.next != &bdev->ddestroy) {
- nentry = list_first_entry(&entry->ddestroy,
- struct ttm_buffer_object, ddestroy);
- kref_get(&nentry->list_kref);
- }
-
- ret = __ttm_bo_reserve(entry, false, true, NULL);
- if (remove_all && ret) {
+ if (remove_all || bo->resv != &bo->ttm_resv) {
spin_unlock(&glob->lru_lock);
- ret = __ttm_bo_reserve(entry, false, false, NULL);
+ reservation_object_lock(bo->resv, NULL);
+
spin_lock(&glob->lru_lock);
+ ttm_bo_cleanup_refs(bo, false, !remove_all, true);
+
+ } else if (reservation_object_trylock(bo->resv)) {
+ ttm_bo_cleanup_refs(bo, false, !remove_all, true);
+ } else {
+ spin_unlock(&glob->lru_lock);
}
- if (!ret)
- ret = ttm_bo_cleanup_refs_and_unlock(entry, false,
- !remove_all);
- else
- spin_unlock(&glob->lru_lock);
-
- kref_put(&entry->list_kref, ttm_bo_release_list);
- entry = nentry;
-
- if (ret || !entry)
- goto out;
-
+ kref_put(&bo->list_kref, ttm_bo_release_list);
spin_lock(&glob->lru_lock);
- if (list_empty(&entry->ddestroy))
- break;
}
-
-out_unlock:
+ list_splice_tail(&removed, &bdev->ddestroy);
+ empty = list_empty(&bdev->ddestroy);
spin_unlock(&glob->lru_lock);
-out:
- if (entry)
- kref_put(&entry->list_kref, ttm_bo_release_list);
- return ret;
+
+ return empty;
}
static void ttm_bo_delayed_workqueue(struct work_struct *work)
@@ -629,7 +611,7 @@
struct ttm_bo_device *bdev =
container_of(work, struct ttm_bo_device, wq.work);
- if (ttm_bo_delayed_delete(bdev, false)) {
+ if (!ttm_bo_delayed_delete(bdev, false)) {
schedule_delayed_work(&bdev->wq,
((HZ / 100) < 1) ? 1 : HZ / 100);
}
@@ -673,15 +655,15 @@
}
EXPORT_SYMBOL(ttm_bo_unlock_delayed_workqueue);
-static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible,
- bool no_wait_gpu)
+static int ttm_bo_evict(struct ttm_buffer_object *bo,
+ struct ttm_operation_ctx *ctx)
{
struct ttm_bo_device *bdev = bo->bdev;
struct ttm_mem_reg evict_mem;
struct ttm_placement placement;
int ret = 0;
- lockdep_assert_held(&bo->resv->lock.base);
+ reservation_object_assert_held(bo->resv);
evict_mem = bo->mem;
evict_mem.mm_node = NULL;
@@ -691,8 +673,7 @@
placement.num_placement = 0;
placement.num_busy_placement = 0;
bdev->driver->evict_flags(bo, &placement);
- ret = ttm_bo_mem_space(bo, &placement, &evict_mem, interruptible,
- no_wait_gpu);
+ ret = ttm_bo_mem_space(bo, &placement, &evict_mem, ctx);
if (ret) {
if (ret != -ERESTARTSYS) {
pr_err("Failed to find memory space for buffer 0x%p eviction\n",
@@ -702,8 +683,7 @@
goto out;
}
- ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, interruptible,
- no_wait_gpu);
+ ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, ctx);
if (unlikely(ret)) {
if (ret != -ERESTARTSYS)
pr_err("Buffer eviction failed\n");
@@ -729,49 +709,78 @@
}
EXPORT_SYMBOL(ttm_bo_eviction_valuable);
+/**
+ * Check the target bo is allowable to be evicted or swapout, including cases:
+ *
+ * a. if share same reservation object with ctx->resv, have assumption
+ * reservation objects should already be locked, so not lock again and
+ * return true directly when either the opreation allow_reserved_eviction
+ * or the target bo already is in delayed free list;
+ *
+ * b. Otherwise, trylock it.
+ */
+static bool ttm_bo_evict_swapout_allowable(struct ttm_buffer_object *bo,
+ struct ttm_operation_ctx *ctx, bool *locked)
+{
+ bool ret = false;
+
+ *locked = false;
+ if (bo->resv == ctx->resv) {
+ reservation_object_assert_held(bo->resv);
+ if (ctx->allow_reserved_eviction || !list_empty(&bo->ddestroy))
+ ret = true;
+ } else {
+ *locked = reservation_object_trylock(bo->resv);
+ ret = *locked;
+ }
+
+ return ret;
+}
+
static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
- uint32_t mem_type,
- const struct ttm_place *place,
- bool interruptible,
- bool no_wait_gpu)
+ uint32_t mem_type,
+ const struct ttm_place *place,
+ struct ttm_operation_ctx *ctx)
{
struct ttm_bo_global *glob = bdev->glob;
struct ttm_mem_type_manager *man = &bdev->man[mem_type];
- struct ttm_buffer_object *bo;
- int ret = -EBUSY;
+ struct ttm_buffer_object *bo = NULL;
+ bool locked = false;
unsigned i;
+ int ret;
spin_lock(&glob->lru_lock);
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
list_for_each_entry(bo, &man->lru[i], lru) {
- ret = __ttm_bo_reserve(bo, false, true, NULL);
- if (ret)
+ if (!ttm_bo_evict_swapout_allowable(bo, ctx, &locked))
continue;
if (place && !bdev->driver->eviction_valuable(bo,
place)) {
- __ttm_bo_unreserve(bo);
- ret = -EBUSY;
+ if (locked)
+ reservation_object_unlock(bo->resv);
continue;
}
-
break;
}
- if (!ret)
+ /* If the inner loop terminated early, we have our candidate */
+ if (&bo->lru != &man->lru[i])
break;
+
+ bo = NULL;
}
- if (ret) {
+ if (!bo) {
spin_unlock(&glob->lru_lock);
- return ret;
+ return -EBUSY;
}
kref_get(&bo->list_kref);
if (!list_empty(&bo->ddestroy)) {
- ret = ttm_bo_cleanup_refs_and_unlock(bo, interruptible,
- no_wait_gpu);
+ ret = ttm_bo_cleanup_refs(bo, ctx->interruptible,
+ ctx->no_wait_gpu, locked);
kref_put(&bo->list_kref, ttm_bo_release_list);
return ret;
}
@@ -779,10 +788,14 @@
ttm_bo_del_from_lru(bo);
spin_unlock(&glob->lru_lock);
- BUG_ON(ret != 0);
-
- ret = ttm_bo_evict(bo, interruptible, no_wait_gpu);
- ttm_bo_unreserve(bo);
+ ret = ttm_bo_evict(bo, ctx);
+ if (locked) {
+ ttm_bo_unreserve(bo);
+ } else {
+ spin_lock(&glob->lru_lock);
+ ttm_bo_add_to_lru(bo);
+ spin_unlock(&glob->lru_lock);
+ }
kref_put(&bo->list_kref, ttm_bo_release_list);
return ret;
@@ -833,8 +846,7 @@
uint32_t mem_type,
const struct ttm_place *place,
struct ttm_mem_reg *mem,
- bool interruptible,
- bool no_wait_gpu)
+ struct ttm_operation_ctx *ctx)
{
struct ttm_bo_device *bdev = bo->bdev;
struct ttm_mem_type_manager *man = &bdev->man[mem_type];
@@ -846,8 +858,7 @@
return ret;
if (mem->mm_node)
break;
- ret = ttm_mem_evict_first(bdev, mem_type, place,
- interruptible, no_wait_gpu);
+ ret = ttm_mem_evict_first(bdev, mem_type, place, ctx);
if (unlikely(ret != 0))
return ret;
} while (1);
@@ -910,8 +921,7 @@
int ttm_bo_mem_space(struct ttm_buffer_object *bo,
struct ttm_placement *placement,
struct ttm_mem_reg *mem,
- bool interruptible,
- bool no_wait_gpu)
+ struct ttm_operation_ctx *ctx)
{
struct ttm_bo_device *bdev = bo->bdev;
struct ttm_mem_type_manager *man;
@@ -1005,8 +1015,7 @@
return 0;
}
- ret = ttm_bo_mem_force_space(bo, mem_type, place, mem,
- interruptible, no_wait_gpu);
+ ret = ttm_bo_mem_force_space(bo, mem_type, place, mem, ctx);
if (ret == 0 && mem->mm_node) {
mem->placement = cur_flags;
return 0;
@@ -1025,14 +1034,13 @@
EXPORT_SYMBOL(ttm_bo_mem_space);
static int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
- struct ttm_placement *placement,
- bool interruptible,
- bool no_wait_gpu)
+ struct ttm_placement *placement,
+ struct ttm_operation_ctx *ctx)
{
int ret = 0;
struct ttm_mem_reg mem;
- lockdep_assert_held(&bo->resv->lock.base);
+ reservation_object_assert_held(bo->resv);
mem.num_pages = bo->num_pages;
mem.size = mem.num_pages << PAGE_SHIFT;
@@ -1042,12 +1050,10 @@
/*
* Determine where to move the buffer.
*/
- ret = ttm_bo_mem_space(bo, placement, &mem,
- interruptible, no_wait_gpu);
+ ret = ttm_bo_mem_space(bo, placement, &mem, ctx);
if (ret)
goto out_unlock;
- ret = ttm_bo_handle_move_mem(bo, &mem, false,
- interruptible, no_wait_gpu);
+ ret = ttm_bo_handle_move_mem(bo, &mem, false, ctx);
out_unlock:
if (ret && mem.mm_node)
ttm_bo_mem_put(bo, &mem);
@@ -1098,20 +1104,18 @@
EXPORT_SYMBOL(ttm_bo_mem_compat);
int ttm_bo_validate(struct ttm_buffer_object *bo,
- struct ttm_placement *placement,
- bool interruptible,
- bool no_wait_gpu)
+ struct ttm_placement *placement,
+ struct ttm_operation_ctx *ctx)
{
int ret;
uint32_t new_flags;
- lockdep_assert_held(&bo->resv->lock.base);
+ reservation_object_assert_held(bo->resv);
/*
* Check whether we need to move buffer.
*/
if (!ttm_bo_mem_compat(placement, &bo->mem, &new_flags)) {
- ret = ttm_bo_move_buffer(bo, placement, interruptible,
- no_wait_gpu);
+ ret = ttm_bo_move_buffer(bo, placement, ctx);
if (ret)
return ret;
} else {
@@ -1140,7 +1144,7 @@
enum ttm_bo_type type,
struct ttm_placement *placement,
uint32_t page_alignment,
- bool interruptible,
+ struct ttm_operation_ctx *ctx,
struct file *persistent_swap_storage,
size_t acc_size,
struct sg_table *sg,
@@ -1152,7 +1156,7 @@
struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
bool locked;
- ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
+ ret = ttm_mem_global_alloc(mem_glob, acc_size, ctx);
if (ret) {
pr_err("Out of kernel memory\n");
if (destroy)
@@ -1200,7 +1204,7 @@
bo->sg = sg;
if (resv) {
bo->resv = resv;
- lockdep_assert_held(&bo->resv->lock.base);
+ reservation_object_assert_held(bo->resv);
} else {
bo->resv = &bo->ttm_resv;
}
@@ -1222,12 +1226,12 @@
* since otherwise lockdep will be angered in radeon.
*/
if (!resv) {
- locked = ww_mutex_trylock(&bo->resv->lock);
+ locked = reservation_object_trylock(bo->resv);
WARN_ON(!locked);
}
if (likely(!ret))
- ret = ttm_bo_validate(bo, placement, interruptible, false);
+ ret = ttm_bo_validate(bo, placement, ctx);
if (unlikely(ret)) {
if (!resv)
@@ -1260,10 +1264,11 @@
struct reservation_object *resv,
void (*destroy) (struct ttm_buffer_object *))
{
+ struct ttm_operation_ctx ctx = { interruptible, false };
int ret;
ret = ttm_bo_init_reserved(bdev, bo, size, type, placement,
- page_alignment, interruptible,
+ page_alignment, &ctx,
persistent_swap_storage, acc_size,
sg, resv, destroy);
if (ret)
@@ -1335,6 +1340,7 @@
static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev,
unsigned mem_type)
{
+ struct ttm_operation_ctx ctx = { false, false };
struct ttm_mem_type_manager *man = &bdev->man[mem_type];
struct ttm_bo_global *glob = bdev->glob;
struct dma_fence *fence;
@@ -1349,7 +1355,7 @@
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
while (!list_empty(&man->lru[i])) {
spin_unlock(&glob->lru_lock);
- ret = ttm_mem_evict_first(bdev, mem_type, NULL, false, false);
+ ret = ttm_mem_evict_first(bdev, mem_type, NULL, &ctx);
if (ret)
return ret;
spin_lock(&glob->lru_lock);
@@ -1470,7 +1476,6 @@
struct ttm_bo_global *glob =
container_of(kobj, struct ttm_bo_global, kobj);
- ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink);
__free_page(glob->dummy_read_page);
kfree(glob);
}
@@ -1495,6 +1500,7 @@
mutex_init(&glob->device_list_mutex);
spin_lock_init(&glob->lru_lock);
glob->mem_glob = bo_ref->mem_glob;
+ glob->mem_glob->bo_glob = glob;
glob->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32);
if (unlikely(glob->dummy_read_page == NULL)) {
@@ -1505,14 +1511,6 @@
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
INIT_LIST_HEAD(&glob->swap_lru[i]);
INIT_LIST_HEAD(&glob->device_list);
-
- ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout);
- ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink);
- if (unlikely(ret != 0)) {
- pr_err("Could not register buffer object swapout\n");
- goto out_no_shrink;
- }
-
atomic_set(&glob->bo_count, 0);
ret = kobject_init_and_add(
@@ -1520,8 +1518,6 @@
if (unlikely(ret != 0))
kobject_put(&glob->kobj);
return ret;
-out_no_shrink:
- __free_page(glob->dummy_read_page);
out_no_drp:
kfree(glob);
return ret;
@@ -1555,16 +1551,13 @@
cancel_delayed_work_sync(&bdev->wq);
- while (ttm_bo_delayed_delete(bdev, true))
- ;
+ if (ttm_bo_delayed_delete(bdev, true))
+ pr_debug("Delayed destroy list was clean\n");
spin_lock(&glob->lru_lock);
- if (list_empty(&bdev->ddestroy))
- TTM_DEBUG("Delayed destroy list was clean\n");
-
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
if (list_empty(&bdev->man[0].lru[0]))
- TTM_DEBUG("Swap list %d was clean\n", i);
+ pr_debug("Swap list %d was clean\n", i);
spin_unlock(&glob->lru_lock);
drm_vma_offset_manager_destroy(&bdev->vma_manager);
@@ -1707,21 +1700,20 @@
* A buffer object shrink method that tries to swap out the first
* buffer object on the bo_global::swap_lru list.
*/
-
-static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
+int ttm_bo_swapout(struct ttm_bo_global *glob, struct ttm_operation_ctx *ctx)
{
- struct ttm_bo_global *glob =
- container_of(shrink, struct ttm_bo_global, shrink);
struct ttm_buffer_object *bo;
int ret = -EBUSY;
+ bool locked;
unsigned i;
spin_lock(&glob->lru_lock);
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
list_for_each_entry(bo, &glob->swap_lru[i], swap) {
- ret = __ttm_bo_reserve(bo, false, true, NULL);
- if (!ret)
+ if (ttm_bo_evict_swapout_allowable(bo, ctx, &locked)) {
+ ret = 0;
break;
+ }
}
if (!ret)
break;
@@ -1735,7 +1727,7 @@
kref_get(&bo->list_kref);
if (!list_empty(&bo->ddestroy)) {
- ret = ttm_bo_cleanup_refs_and_unlock(bo, false, false);
+ ret = ttm_bo_cleanup_refs(bo, false, false, locked);
kref_put(&bo->list_kref, ttm_bo_release_list);
return ret;
}
@@ -1749,6 +1741,7 @@
if (bo->mem.mem_type != TTM_PL_SYSTEM ||
bo->ttm->caching_state != tt_cached) {
+ struct ttm_operation_ctx ctx = { false, false };
struct ttm_mem_reg evict_mem;
evict_mem = bo->mem;
@@ -1756,8 +1749,7 @@
evict_mem.placement = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED;
evict_mem.mem_type = TTM_PL_SYSTEM;
- ret = ttm_bo_handle_move_mem(bo, &evict_mem, true,
- false, false);
+ ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, &ctx);
if (unlikely(ret != 0))
goto out;
}
@@ -1788,15 +1780,21 @@
* Unreserve without putting on LRU to avoid swapping out an
* already swapped buffer.
*/
-
- __ttm_bo_unreserve(bo);
+ if (locked)
+ reservation_object_unlock(bo->resv);
kref_put(&bo->list_kref, ttm_bo_release_list);
return ret;
}
+EXPORT_SYMBOL(ttm_bo_swapout);
void ttm_bo_swapout_all(struct ttm_bo_device *bdev)
{
- while (ttm_bo_swapout(&bdev->glob->shrink) == 0)
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
+
+ while (ttm_bo_swapout(bdev->glob, &ctx) == 0)
;
}
EXPORT_SYMBOL(ttm_bo_swapout_all);
@@ -1823,10 +1821,12 @@
return -ERESTARTSYS;
if (!ww_mutex_is_locked(&bo->resv->lock))
goto out_unlock;
- ret = __ttm_bo_reserve(bo, true, false, NULL);
+ ret = reservation_object_lock_interruptible(bo->resv, NULL);
+ if (ret == -EINTR)
+ ret = -ERESTARTSYS;
if (unlikely(ret != 0))
goto out_unlock;
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
out_unlock:
mutex_unlock(&bo->wu_mutex);
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index e7a519f..153de1b 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -45,7 +45,7 @@
}
int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait_gpu,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem)
{
struct ttm_tt *ttm = bo->ttm;
@@ -53,7 +53,7 @@
int ret;
if (old_mem->mem_type != TTM_PL_SYSTEM) {
- ret = ttm_bo_wait(bo, interruptible, no_wait_gpu);
+ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
@@ -73,7 +73,7 @@
return ret;
if (new_mem->mem_type != TTM_PL_SYSTEM) {
- ret = ttm_tt_bind(ttm, new_mem);
+ ret = ttm_tt_bind(ttm, new_mem, ctx);
if (unlikely(ret != 0))
return ret;
}
@@ -329,7 +329,7 @@
}
int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait_gpu,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem)
{
struct ttm_bo_device *bdev = bo->bdev;
@@ -345,7 +345,7 @@
unsigned long add = 0;
int dir;
- ret = ttm_bo_wait(bo, interruptible, no_wait_gpu);
+ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (ret)
return ret;
@@ -376,7 +376,7 @@
* TTM might be null for moves within the same region.
*/
if (ttm && ttm->state == tt_unpopulated) {
- ret = ttm->bdev->driver->ttm_tt_populate(ttm);
+ ret = ttm->bdev->driver->ttm_tt_populate(ttm, ctx);
if (ret)
goto out1;
}
@@ -485,7 +485,7 @@
fbo->acc_size = 0;
fbo->resv = &fbo->ttm_resv;
reservation_object_init(fbo->resv);
- ret = ww_mutex_trylock(&fbo->resv->lock);
+ ret = reservation_object_trylock(fbo->resv);
WARN_ON(!ret);
*new_obj = fbo;
@@ -545,14 +545,19 @@
unsigned long num_pages,
struct ttm_bo_kmap_obj *map)
{
- struct ttm_mem_reg *mem = &bo->mem; pgprot_t prot;
+ struct ttm_mem_reg *mem = &bo->mem;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
struct ttm_tt *ttm = bo->ttm;
+ pgprot_t prot;
int ret;
BUG_ON(!ttm);
if (ttm->state == tt_unpopulated) {
- ret = ttm->bdev->driver->ttm_tt_populate(ttm);
+ ret = ttm->bdev->driver->ttm_tt_populate(ttm, &ctx);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 092c749..48237ff 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -92,6 +92,18 @@
return ret;
}
+static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo,
+ unsigned long page_offset)
+{
+ struct ttm_bo_device *bdev = bo->bdev;
+
+ if (bdev->driver->io_mem_pfn)
+ return bdev->driver->io_mem_pfn(bo, page_offset);
+
+ return ((bo->mem.bus.base + bo->mem.bus.offset) >> PAGE_SHIFT)
+ + page_offset;
+}
+
static int ttm_bo_vm_fault(struct vm_fault *vmf)
{
struct vm_area_struct *vma = vmf->vma;
@@ -215,12 +227,17 @@
cvma.vm_page_prot = ttm_io_prot(bo->mem.placement,
cvma.vm_page_prot);
} else {
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
+
ttm = bo->ttm;
cvma.vm_page_prot = ttm_io_prot(bo->mem.placement,
cvma.vm_page_prot);
/* Allocate all page at once, most common usage */
- if (ttm->bdev->driver->ttm_tt_populate(ttm)) {
+ if (ttm->bdev->driver->ttm_tt_populate(ttm, &ctx)) {
retval = VM_FAULT_OOM;
goto out_io_unlock;
}
@@ -234,7 +251,7 @@
if (bo->mem.bus.is_iomem) {
/* Iomem should not be marked encrypted */
cvma.vm_page_prot = pgprot_decrypted(cvma.vm_page_prot);
- pfn = bdev->driver->io_mem_pfn(bo, page_offset);
+ pfn = ttm_bo_io_mem_pfn(bo, page_offset);
} else {
page = ttm->pages[page_offset];
if (unlikely(!page && i == 0)) {
@@ -403,14 +420,6 @@
return bo;
}
-unsigned long ttm_bo_default_io_mem_pfn(struct ttm_buffer_object *bo,
- unsigned long page_offset)
-{
- return ((bo->mem.bus.base + bo->mem.bus.offset) >> PAGE_SHIFT)
- + page_offset;
-}
-EXPORT_SYMBOL(ttm_bo_default_io_mem_pfn);
-
int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma,
struct ttm_bo_device *bdev)
{
diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
index 5e1bcab..373ced0 100644
--- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c
+++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
@@ -38,7 +38,7 @@
list_for_each_entry_continue_reverse(entry, list, head) {
struct ttm_buffer_object *bo = entry->bo;
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
}
}
@@ -69,7 +69,7 @@
struct ttm_buffer_object *bo = entry->bo;
ttm_bo_add_to_lru(bo);
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
}
spin_unlock(&glob->lru_lock);
@@ -112,7 +112,7 @@
ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket);
if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) {
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
ret = -EBUSY;
@@ -203,7 +203,7 @@
else
reservation_object_add_excl_fence(bo->resv, fence);
ttm_bo_add_to_lru(bo);
- __ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
}
spin_unlock(&glob->lru_lock);
if (ticket)
diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index e9637499..aa0c381 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -211,35 +211,33 @@
*/
static void ttm_shrink(struct ttm_mem_global *glob, bool from_wq,
- uint64_t extra)
+ uint64_t extra, struct ttm_operation_ctx *ctx)
{
int ret;
- struct ttm_mem_shrink *shrink;
spin_lock(&glob->lock);
- if (glob->shrink == NULL)
- goto out;
while (ttm_zones_above_swap_target(glob, from_wq, extra)) {
- shrink = glob->shrink;
spin_unlock(&glob->lock);
- ret = shrink->do_shrink(shrink);
+ ret = ttm_bo_swapout(glob->bo_glob, ctx);
spin_lock(&glob->lock);
if (unlikely(ret != 0))
- goto out;
+ break;
}
-out:
+
spin_unlock(&glob->lock);
}
-
-
static void ttm_shrink_work(struct work_struct *work)
{
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
struct ttm_mem_global *glob =
container_of(work, struct ttm_mem_global, work);
- ttm_shrink(glob, true, 0ULL);
+ ttm_shrink(glob, true, 0ULL, &ctx);
}
static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob,
@@ -514,7 +512,7 @@
static int ttm_mem_global_alloc_zone(struct ttm_mem_global *glob,
struct ttm_mem_zone *single_zone,
uint64_t memory,
- bool no_wait, bool interruptible)
+ struct ttm_operation_ctx *ctx)
{
int count = TTM_MEMORY_ALLOC_RETRIES;
@@ -522,33 +520,32 @@
single_zone,
memory, true)
!= 0)) {
- if (no_wait)
+ if (ctx->no_wait_gpu)
return -ENOMEM;
if (unlikely(count-- == 0))
return -ENOMEM;
- ttm_shrink(glob, false, memory + (memory >> 2) + 16);
+ ttm_shrink(glob, false, memory + (memory >> 2) + 16, ctx);
}
return 0;
}
int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
- bool no_wait, bool interruptible)
+ struct ttm_operation_ctx *ctx)
{
/**
* Normal allocations of kernel memory are registered in
* all zones.
*/
- return ttm_mem_global_alloc_zone(glob, NULL, memory, no_wait,
- interruptible);
+ return ttm_mem_global_alloc_zone(glob, NULL, memory, ctx);
}
EXPORT_SYMBOL(ttm_mem_global_alloc);
int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
- struct page *page, uint64_t size)
+ struct page *page, uint64_t size,
+ struct ttm_operation_ctx *ctx)
{
-
struct ttm_mem_zone *zone = NULL;
/**
@@ -563,7 +560,7 @@
if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
zone = glob->zone_kernel;
#endif
- return ttm_mem_global_alloc_zone(glob, zone, size, false, false);
+ return ttm_mem_global_alloc_zone(glob, zone, size, ctx);
}
void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page,
diff --git a/drivers/gpu/drm/ttm/ttm_object.c b/drivers/gpu/drm/ttm/ttm_object.c
index 26a7ad0..1aa2baa 100644
--- a/drivers/gpu/drm/ttm/ttm_object.c
+++ b/drivers/gpu/drm/ttm/ttm_object.c
@@ -325,6 +325,10 @@
struct ttm_ref_object *ref;
struct drm_hash_item *hash;
struct ttm_mem_global *mem_glob = tfile->tdev->mem_glob;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
int ret = -EINVAL;
if (base->tfile != tfile && !base->shareable)
@@ -350,7 +354,7 @@
return -EPERM;
ret = ttm_mem_global_alloc(mem_glob, sizeof(*ref),
- false, false);
+ &ctx);
if (unlikely(ret != 0))
return ret;
ref = kmalloc(sizeof(*ref), GFP_KERNEL);
@@ -686,7 +690,10 @@
dma_buf = prime->dma_buf;
if (!dma_buf || !get_dma_buf_unless_doomed(dma_buf)) {
DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
-
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
exp_info.ops = &tdev->ops;
exp_info.size = prime->size;
exp_info.flags = flags;
@@ -696,7 +703,7 @@
* Need to create a new dma_buf, with memory accounting.
*/
ret = ttm_mem_global_alloc(tdev->mem_glob, tdev->dma_buf_size,
- false, true);
+ &ctx);
if (unlikely(ret != 0)) {
mutex_unlock(&prime->mutex);
goto out_unref;
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 5d252fb..2b12c55a 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -477,12 +477,12 @@
return count;
}
-static void ttm_pool_mm_shrink_init(struct ttm_pool_manager *manager)
+static int ttm_pool_mm_shrink_init(struct ttm_pool_manager *manager)
{
manager->mm_shrink.count_objects = ttm_pool_shrink_count;
manager->mm_shrink.scan_objects = ttm_pool_shrink_scan;
manager->mm_shrink.seeks = 1;
- register_shrinker(&manager->mm_shrink);
+ return register_shrinker(&manager->mm_shrink);
}
static void ttm_pool_mm_shrink_fini(struct ttm_pool_manager *manager)
@@ -1034,15 +1034,18 @@
ret = kobject_init_and_add(&_manager->kobj, &ttm_pool_kobj_type,
&glob->kobj, "pool");
- if (unlikely(ret != 0)) {
- kobject_put(&_manager->kobj);
- _manager = NULL;
- return ret;
- }
+ if (unlikely(ret != 0))
+ goto error;
- ttm_pool_mm_shrink_init(_manager);
-
+ ret = ttm_pool_mm_shrink_init(_manager);
+ if (unlikely(ret != 0))
+ goto error;
return 0;
+
+error:
+ kobject_put(&_manager->kobj);
+ _manager = NULL;
+ return ret;
}
void ttm_page_alloc_fini(void)
@@ -1060,7 +1063,7 @@
_manager = NULL;
}
-int ttm_pool_populate(struct ttm_tt *ttm)
+int ttm_pool_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
unsigned i;
@@ -1072,15 +1075,17 @@
ret = ttm_get_pages(ttm->pages, ttm->num_pages, ttm->page_flags,
ttm->caching_state);
if (unlikely(ret != 0)) {
- ttm_pool_unpopulate(ttm);
+ ttm_put_pages(ttm->pages, ttm->num_pages, ttm->page_flags,
+ ttm->caching_state);
return ret;
}
for (i = 0; i < ttm->num_pages; ++i) {
ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
- PAGE_SIZE);
+ PAGE_SIZE, ctx);
if (unlikely(ret != 0)) {
- ttm_pool_unpopulate(ttm);
+ ttm_put_pages(ttm->pages, ttm->num_pages,
+ ttm->page_flags, ttm->caching_state);
return -ENOMEM;
}
}
@@ -1115,12 +1120,13 @@
}
EXPORT_SYMBOL(ttm_pool_unpopulate);
-int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
+int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt,
+ struct ttm_operation_ctx *ctx)
{
unsigned i, j;
int r;
- r = ttm_pool_populate(&tt->ttm);
+ r = ttm_pool_populate(&tt->ttm, ctx);
if (r)
return r;
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 6b2627f..a880515 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -61,6 +61,7 @@
#define SMALL_ALLOCATION 4
#define FREE_ALL_PAGES (~0U)
#define VADDR_FLAG_HUGE_POOL 1UL
+#define VADDR_FLAG_UPDATED_COUNT 2UL
enum pool_type {
IS_UNDEFINED = 0,
@@ -333,14 +334,18 @@
static struct dma_page *__ttm_dma_alloc_page(struct dma_pool *pool)
{
struct dma_page *d_page;
+ unsigned long attrs = 0;
void *vaddr;
d_page = kmalloc(sizeof(struct dma_page), GFP_KERNEL);
if (!d_page)
return NULL;
- vaddr = dma_alloc_coherent(pool->dev, pool->size, &d_page->dma,
- pool->gfp_flags);
+ if (pool->type & IS_HUGE)
+ attrs = DMA_ATTR_NO_WARN;
+
+ vaddr = dma_alloc_attrs(pool->dev, pool->size, &d_page->dma,
+ pool->gfp_flags, attrs);
if (vaddr) {
if (is_vmalloc_addr(vaddr))
d_page->p = vmalloc_to_page(vaddr);
@@ -870,18 +875,18 @@
}
/*
- * @return count of pages still required to fulfill the request.
* The populate list is actually a stack (not that is matters as TTM
* allocates one page at a time.
+ * return dma_page pointer if success, otherwise NULL.
*/
-static int ttm_dma_pool_get_pages(struct dma_pool *pool,
+static struct dma_page *ttm_dma_pool_get_pages(struct dma_pool *pool,
struct ttm_dma_tt *ttm_dma,
unsigned index)
{
- struct dma_page *d_page;
+ struct dma_page *d_page = NULL;
struct ttm_tt *ttm = &ttm_dma->ttm;
unsigned long irq_flags;
- int count, r = -ENOMEM;
+ int count;
spin_lock_irqsave(&pool->lock, irq_flags);
count = ttm_dma_page_pool_fill_locked(pool, &irq_flags);
@@ -890,12 +895,11 @@
ttm->pages[index] = d_page->p;
ttm_dma->dma_address[index] = d_page->dma;
list_move_tail(&d_page->page_list, &ttm_dma->pages_list);
- r = 0;
pool->npages_in_use += 1;
pool->npages_free -= 1;
}
spin_unlock_irqrestore(&pool->lock, irq_flags);
- return r;
+ return d_page;
}
static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt *ttm_dma, bool huge)
@@ -923,12 +927,14 @@
* On success pages list will hold count number of correctly
* cached pages. On failure will hold the negative return value (-ENOMEM, etc).
*/
-int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev)
+int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev,
+ struct ttm_operation_ctx *ctx)
{
struct ttm_tt *ttm = &ttm_dma->ttm;
struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
unsigned long num_pages = ttm->num_pages;
struct dma_pool *pool;
+ struct dma_page *d_page;
enum pool_type type;
unsigned i;
int ret;
@@ -957,17 +963,18 @@
while (num_pages >= HPAGE_PMD_NR) {
unsigned j;
- ret = ttm_dma_pool_get_pages(pool, ttm_dma, i);
- if (ret != 0)
+ d_page = ttm_dma_pool_get_pages(pool, ttm_dma, i);
+ if (!d_page)
break;
ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
- pool->size);
+ pool->size, ctx);
if (unlikely(ret != 0)) {
ttm_dma_unpopulate(ttm_dma, dev);
return -ENOMEM;
}
+ d_page->vaddr |= VADDR_FLAG_UPDATED_COUNT;
for (j = i + 1; j < (i + HPAGE_PMD_NR); ++j) {
ttm->pages[j] = ttm->pages[j - 1] + 1;
ttm_dma->dma_address[j] = ttm_dma->dma_address[j - 1] +
@@ -991,19 +998,20 @@
}
while (num_pages) {
- ret = ttm_dma_pool_get_pages(pool, ttm_dma, i);
- if (ret != 0) {
+ d_page = ttm_dma_pool_get_pages(pool, ttm_dma, i);
+ if (!d_page) {
ttm_dma_unpopulate(ttm_dma, dev);
return -ENOMEM;
}
ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
- pool->size);
+ pool->size, ctx);
if (unlikely(ret != 0)) {
ttm_dma_unpopulate(ttm_dma, dev);
return -ENOMEM;
}
+ d_page->vaddr |= VADDR_FLAG_UPDATED_COUNT;
++i;
--num_pages;
}
@@ -1044,8 +1052,11 @@
continue;
count++;
- ttm_mem_global_free_page(ttm->glob->mem_glob,
- d_page->p, pool->size);
+ if (d_page->vaddr & VADDR_FLAG_UPDATED_COUNT) {
+ ttm_mem_global_free_page(ttm->glob->mem_glob,
+ d_page->p, pool->size);
+ d_page->vaddr &= ~VADDR_FLAG_UPDATED_COUNT;
+ }
ttm_dma_page_put(pool, d_page);
}
@@ -1065,9 +1076,19 @@
/* make sure pages array match list and count number of pages */
count = 0;
- list_for_each_entry(d_page, &ttm_dma->pages_list, page_list) {
+ list_for_each_entry_safe(d_page, next, &ttm_dma->pages_list,
+ page_list) {
ttm->pages[count] = d_page->p;
count++;
+
+ if (d_page->vaddr & VADDR_FLAG_UPDATED_COUNT) {
+ ttm_mem_global_free_page(ttm->glob->mem_glob,
+ d_page->p, pool->size);
+ d_page->vaddr &= ~VADDR_FLAG_UPDATED_COUNT;
+ }
+
+ if (is_cached)
+ ttm_dma_page_put(pool, d_page);
}
spin_lock_irqsave(&pool->lock, irq_flags);
@@ -1087,19 +1108,6 @@
}
spin_unlock_irqrestore(&pool->lock, irq_flags);
- if (is_cached) {
- list_for_each_entry_safe(d_page, next, &ttm_dma->pages_list, page_list) {
- ttm_mem_global_free_page(ttm->glob->mem_glob,
- d_page->p, pool->size);
- ttm_dma_page_put(pool, d_page);
- }
- } else {
- for (i = 0; i < count; i++) {
- ttm_mem_global_free_page(ttm->glob->mem_glob,
- ttm->pages[i], pool->size);
- }
- }
-
INIT_LIST_HEAD(&ttm_dma->pages_list);
for (i = 0; i < ttm->num_pages; i++) {
ttm->pages[i] = NULL;
@@ -1177,12 +1185,12 @@
return count;
}
-static void ttm_dma_pool_mm_shrink_init(struct ttm_pool_manager *manager)
+static int ttm_dma_pool_mm_shrink_init(struct ttm_pool_manager *manager)
{
manager->mm_shrink.count_objects = ttm_dma_pool_shrink_count;
manager->mm_shrink.scan_objects = &ttm_dma_pool_shrink_scan;
manager->mm_shrink.seeks = 1;
- register_shrinker(&manager->mm_shrink);
+ return register_shrinker(&manager->mm_shrink);
}
static void ttm_dma_pool_mm_shrink_fini(struct ttm_pool_manager *manager)
@@ -1192,7 +1200,7 @@
int ttm_dma_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages)
{
- int ret = -ENOMEM;
+ int ret;
WARN_ON(_manager);
@@ -1200,7 +1208,7 @@
_manager = kzalloc(sizeof(*_manager), GFP_KERNEL);
if (!_manager)
- goto err;
+ return -ENOMEM;
mutex_init(&_manager->lock);
INIT_LIST_HEAD(&_manager->pools);
@@ -1212,13 +1220,17 @@
/* This takes care of auto-freeing the _manager */
ret = kobject_init_and_add(&_manager->kobj, &ttm_pool_kobj_type,
&glob->kobj, "dma_pool");
- if (unlikely(ret != 0)) {
- kobject_put(&_manager->kobj);
- goto err;
- }
- ttm_dma_pool_mm_shrink_init(_manager);
+ if (unlikely(ret != 0))
+ goto error;
+
+ ret = ttm_dma_pool_mm_shrink_init(_manager);
+ if (unlikely(ret != 0))
+ goto error;
return 0;
-err:
+
+error:
+ kobject_put(&_manager->kobj);
+ _manager = NULL;
return ret;
}
@@ -1244,15 +1256,12 @@
{
struct device_pools *p;
struct dma_pool *pool = NULL;
- char *h[] = {"pool", "refills", "pages freed", "inuse", "available",
- "name", "virt", "busaddr"};
if (!_manager) {
seq_printf(m, "No pool allocator running.\n");
return 0;
}
- seq_printf(m, "%13s %12s %13s %8s %8s %8s\n",
- h[0], h[1], h[2], h[3], h[4], h[5]);
+ seq_printf(m, " pool refills pages freed inuse available name\n");
mutex_lock(&_manager->lock);
list_for_each_entry(p, &_manager->pools, pools) {
struct device *dev = p->dev;
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 8ebc8d3..5a046a3 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -261,7 +261,8 @@
}
}
-int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
+int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem,
+ struct ttm_operation_ctx *ctx)
{
int ret = 0;
@@ -271,7 +272,7 @@
if (ttm->state == tt_bound)
return 0;
- ret = ttm->bdev->driver->ttm_tt_populate(ttm);
+ ret = ttm->bdev->driver->ttm_tt_populate(ttm, ctx);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
index 2ebdc6d..d558319 100644
--- a/drivers/gpu/drm/udl/udl_fb.c
+++ b/drivers/gpu/drm/udl/udl_fb.c
@@ -137,7 +137,10 @@
if (cmd > (char *) urb->transfer_buffer) {
/* Send partial buffer remaining before exiting */
- int len = cmd - (char *) urb->transfer_buffer;
+ int len;
+ if (cmd < (char *) urb->transfer_buffer + urb->transfer_buffer_length)
+ *cmd++ = 0xAF;
+ len = cmd - (char *) urb->transfer_buffer;
ret = udl_submit_urb(dev, urb, len);
bytes_sent += len;
} else
diff --git a/drivers/gpu/drm/udl/udl_transfer.c b/drivers/gpu/drm/udl/udl_transfer.c
index 0c87b1ac6b..b992644c1 100644
--- a/drivers/gpu/drm/udl/udl_transfer.c
+++ b/drivers/gpu/drm/udl/udl_transfer.c
@@ -153,11 +153,11 @@
raw_pixels_count_byte = cmd++; /* we'll know this later */
raw_pixel_start = pixel;
- cmd_pixel_end = pixel + (min(MAX_CMD_PIXELS + 1,
- min((int)(pixel_end - pixel) / bpp,
- (int)(cmd_buffer_end - cmd) / 2))) * bpp;
+ cmd_pixel_end = pixel + min3(MAX_CMD_PIXELS + 1UL,
+ (unsigned long)(pixel_end - pixel) / bpp,
+ (unsigned long)(cmd_buffer_end - 1 - cmd) / 2) * bpp;
- prefetch_range((void *) pixel, (cmd_pixel_end - pixel) * bpp);
+ prefetch_range((void *) pixel, cmd_pixel_end - pixel);
pixel_val16 = get_pixel_val16(pixel, bpp);
while (pixel < cmd_pixel_end) {
@@ -193,6 +193,9 @@
if (pixel > raw_pixel_start) {
/* finalize last RAW span */
*raw_pixels_count_byte = ((pixel-raw_pixel_start) / bpp) & 0xFF;
+ } else {
+ /* undo unused byte */
+ cmd--;
}
*cmd_pixels_count_byte = ((pixel - cmd_pixel_start) / bpp) & 0xFF;
diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
index 8540b44..02d3358 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
@@ -56,6 +56,7 @@
static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
struct list_head *head)
{
+ struct ttm_operation_ctx ctx = { false, false };
struct ttm_validate_buffer *buf;
struct ttm_buffer_object *bo;
struct virtio_gpu_object *qobj;
@@ -68,7 +69,7 @@
list_for_each_entry(buf, head, head) {
bo = buf->bo;
qobj = container_of(bo, struct virtio_gpu_object, tbo);
- ret = ttm_bo_validate(bo, &qobj->placement, false, false);
+ ret = ttm_bo_validate(bo, &qobj->placement, &ctx);
if (ret) {
ttm_eu_backoff_reservation(ticket, head);
return ret;
@@ -355,6 +356,7 @@
struct virtio_gpu_device *vgdev = dev->dev_private;
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
struct drm_virtgpu_3d_transfer_from_host *args = data;
+ struct ttm_operation_ctx ctx = { true, false };
struct drm_gem_object *gobj = NULL;
struct virtio_gpu_object *qobj = NULL;
struct virtio_gpu_fence *fence;
@@ -375,8 +377,7 @@
if (ret)
goto out;
- ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
- true, false);
+ ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
if (unlikely(ret))
goto out_unres;
@@ -402,6 +403,7 @@
struct virtio_gpu_device *vgdev = dev->dev_private;
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
struct drm_virtgpu_3d_transfer_to_host *args = data;
+ struct ttm_operation_ctx ctx = { true, false };
struct drm_gem_object *gobj = NULL;
struct virtio_gpu_object *qobj = NULL;
struct virtio_gpu_fence *fence;
@@ -419,8 +421,7 @@
if (ret)
goto out;
- ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
- true, false);
+ ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
if (unlikely(ret))
goto out_unres;
diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c
index 6f66b73..0b90cdb 100644
--- a/drivers/gpu/drm/virtio/virtgpu_object.c
+++ b/drivers/gpu/drm/virtio/virtgpu_object.c
@@ -124,13 +124,17 @@
int ret;
struct page **pages = bo->tbo.ttm->pages;
int nr_pages = bo->tbo.num_pages;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
/* wtf swapping */
if (bo->pages)
return 0;
if (bo->tbo.ttm->state == tt_unpopulated)
- bo->tbo.ttm->bdev->driver->ttm_tt_populate(bo->tbo.ttm);
+ bo->tbo.ttm->bdev->driver->ttm_tt_populate(bo->tbo.ttm, &ctx);
bo->pages = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
if (!bo->pages)
goto out;
diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c
index cd389c5..36655b7 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ttm.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c
@@ -324,12 +324,13 @@
.destroy = &virtio_gpu_ttm_backend_destroy,
};
-static int virtio_gpu_ttm_tt_populate(struct ttm_tt *ttm)
+static int virtio_gpu_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
if (ttm->state != tt_unpopulated)
return 0;
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
static void virtio_gpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -369,14 +370,13 @@
new_mem->mm_node = NULL;
}
-static int virtio_gpu_bo_move(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu,
+static int virtio_gpu_bo_move(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem)
{
int ret;
- ret = ttm_bo_wait(bo, interruptible, no_wait_gpu);
+ ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
if (ret)
return ret;
@@ -431,7 +431,6 @@
.verify_access = &virtio_gpu_verify_access,
.io_mem_reserve = &virtio_gpu_ttm_io_mem_reserve,
.io_mem_free = &virtio_gpu_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
.move_notify = &virtio_gpu_bo_move_notify,
.swap_notify = &virtio_gpu_bo_swap_notify,
};
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c b/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
index 9c42e96..55d32ae 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
@@ -1202,10 +1202,14 @@
vmw_binding_state_alloc(struct vmw_private *dev_priv)
{
struct vmw_ctx_binding_state *cbs;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
int ret;
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), sizeof(*cbs),
- false, false);
+ &ctx);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
index c705632..22231bc9 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
@@ -394,6 +394,10 @@
struct vmw_private *dev_priv = vmw_tt->dev_priv;
struct ttm_mem_global *glob = vmw_mem_glob(dev_priv);
struct vmw_sg_table *vsgt = &vmw_tt->vsgt;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
struct vmw_piter iter;
dma_addr_t old;
int ret = 0;
@@ -417,8 +421,7 @@
sgt_size = ttm_round_pot(sizeof(struct sg_table));
}
vmw_tt->sg_alloc_size = sgt_size + sgl_size * vsgt->num_pages;
- ret = ttm_mem_global_alloc(glob, vmw_tt->sg_alloc_size, false,
- true);
+ ret = ttm_mem_global_alloc(glob, vmw_tt->sg_alloc_size, &ctx);
if (unlikely(ret != 0))
return ret;
@@ -632,7 +635,7 @@
}
-static int vmw_ttm_populate(struct ttm_tt *ttm)
+static int vmw_ttm_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
struct vmw_ttm_tt *vmw_tt =
container_of(ttm, struct vmw_ttm_tt, dma_ttm.ttm);
@@ -646,15 +649,16 @@
if (dev_priv->map_mode == vmw_dma_alloc_coherent) {
size_t size =
ttm_round_pot(ttm->num_pages * sizeof(dma_addr_t));
- ret = ttm_mem_global_alloc(glob, size, false, true);
+ ret = ttm_mem_global_alloc(glob, size, ctx);
if (unlikely(ret != 0))
return ret;
- ret = ttm_dma_populate(&vmw_tt->dma_ttm, dev_priv->dev->dev);
+ ret = ttm_dma_populate(&vmw_tt->dma_ttm, dev_priv->dev->dev,
+ ctx);
if (unlikely(ret != 0))
ttm_mem_global_free(glob, size);
} else
- ret = ttm_pool_populate(ttm);
+ ret = ttm_pool_populate(ttm, ctx);
return ret;
}
@@ -859,5 +863,4 @@
.fault_reserve_notify = &vmw_ttm_fault_reserve_notify,
.io_mem_reserve = &vmw_ttm_io_mem_reserve,
.io_mem_free = &vmw_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
index 4212b3e67..3767ac3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
@@ -746,6 +746,10 @@
struct vmw_resource *tmp;
struct drm_vmw_context_arg *arg = (struct drm_vmw_context_arg *)data;
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
+ struct ttm_operation_ctx ttm_opt_ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
int ret;
if (!dev_priv->has_dx && dx) {
@@ -768,7 +772,7 @@
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
vmw_user_context_size,
- false, true);
+ &ttm_opt_ctx);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for context"
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
index d87861b..cbf54ea 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
@@ -387,6 +387,7 @@
*/
static int vmw_cotable_resize(struct vmw_resource *res, size_t new_size)
{
+ struct ttm_operation_ctx ctx = { false, false };
struct vmw_private *dev_priv = res->dev_priv;
struct vmw_cotable *vcotbl = vmw_cotable(res);
struct vmw_dma_buffer *buf, *old_buf = res->backup;
@@ -455,7 +456,7 @@
}
/* Unpin new buffer, and switch backup buffers. */
- ret = ttm_bo_validate(bo, &vmw_mob_placement, false, false);
+ ret = ttm_bo_validate(bo, &vmw_mob_placement, &ctx);
if (unlikely(ret != 0)) {
DRM_ERROR("Failed validating new COTable backup buffer.\n");
goto out_wait;
@@ -572,6 +573,10 @@
u32 type)
{
struct vmw_cotable *vcotbl;
+ struct ttm_operation_ctx ttm_opt_ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
int ret;
u32 num_entries;
@@ -579,7 +584,7 @@
cotable_acc_size = ttm_round_pot(sizeof(struct vmw_cotable));
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
- cotable_acc_size, false, true);
+ cotable_acc_size, &ttm_opt_ctx);
if (unlikely(ret))
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c
index 0cd8890..d45d2caf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c
@@ -47,6 +47,7 @@
struct ttm_placement *placement,
bool interruptible)
{
+ struct ttm_operation_ctx ctx = {interruptible, false };
struct ttm_buffer_object *bo = &buf->base;
int ret;
uint32_t new_flags;
@@ -65,7 +66,7 @@
ret = ttm_bo_mem_compat(placement, &bo->mem,
&new_flags) == true ? 0 : -EINVAL;
else
- ret = ttm_bo_validate(bo, placement, interruptible, false);
+ ret = ttm_bo_validate(bo, placement, &ctx);
if (!ret)
vmw_bo_pin_reserved(buf, true);
@@ -95,6 +96,7 @@
struct vmw_dma_buffer *buf,
bool interruptible)
{
+ struct ttm_operation_ctx ctx = {interruptible, false };
struct ttm_buffer_object *bo = &buf->base;
int ret;
uint32_t new_flags;
@@ -115,12 +117,11 @@
goto out_unreserve;
}
- ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, interruptible,
- false);
+ ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, &ctx);
if (likely(ret == 0) || ret == -ERESTARTSYS)
goto out_unreserve;
- ret = ttm_bo_validate(bo, &vmw_vram_placement, interruptible, false);
+ ret = ttm_bo_validate(bo, &vmw_vram_placement, &ctx);
out_unreserve:
if (!ret)
@@ -170,6 +171,7 @@
struct vmw_dma_buffer *buf,
bool interruptible)
{
+ struct ttm_operation_ctx ctx = {interruptible, false };
struct ttm_buffer_object *bo = &buf->base;
struct ttm_placement placement;
struct ttm_place place;
@@ -200,14 +202,16 @@
if (bo->mem.mem_type == TTM_PL_VRAM &&
bo->mem.start < bo->num_pages &&
bo->mem.start > 0 &&
- buf->pin_count == 0)
- (void) ttm_bo_validate(bo, &vmw_sys_placement, false, false);
+ buf->pin_count == 0) {
+ ctx.interruptible = false;
+ (void) ttm_bo_validate(bo, &vmw_sys_placement, &ctx);
+ }
if (buf->pin_count > 0)
ret = ttm_bo_mem_compat(&placement, &bo->mem,
&new_flags) == true ? 0 : -EINVAL;
else
- ret = ttm_bo_validate(bo, &placement, interruptible, false);
+ ret = ttm_bo_validate(bo, &placement, &ctx);
/* For some reason we didn't end up at the start of vram */
WARN_ON(ret == 0 && bo->offset != 0);
@@ -286,6 +290,7 @@
*/
void vmw_bo_pin_reserved(struct vmw_dma_buffer *vbo, bool pin)
{
+ struct ttm_operation_ctx ctx = { false, true };
struct ttm_place pl;
struct ttm_placement placement;
struct ttm_buffer_object *bo = &vbo->base;
@@ -314,7 +319,7 @@
placement.num_placement = 1;
placement.placement = &pl;
- ret = ttm_bo_validate(bo, &placement, false, true);
+ ret = ttm_bo_validate(bo, &placement, &ctx);
BUG_ON(ret != 0 || bo->mem.mem_type != old_mem_type);
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 87e8af5..c9d5cc2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -3703,14 +3703,14 @@
{
struct vmw_dma_buffer *vbo = container_of(bo, struct vmw_dma_buffer,
base);
+ struct ttm_operation_ctx ctx = { interruptible, true };
int ret;
if (vbo->pin_count > 0)
return 0;
if (validate_as_mob)
- return ttm_bo_validate(bo, &vmw_mob_placement, interruptible,
- false);
+ return ttm_bo_validate(bo, &vmw_mob_placement, &ctx);
/**
* Put BO in VRAM if there is space, otherwise as a GMR.
@@ -3719,8 +3719,7 @@
* used as a GMR, this will return -ENOMEM.
*/
- ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, interruptible,
- false);
+ ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, &ctx);
if (likely(ret == 0 || ret == -ERESTARTSYS))
return ret;
@@ -3729,7 +3728,7 @@
* previous contents.
*/
- ret = ttm_bo_validate(bo, &vmw_vram_placement, interruptible, false);
+ ret = ttm_bo_validate(bo, &vmw_vram_placement, &ctx);
return ret;
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
index d6b1c50..6c5c75c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
@@ -588,6 +588,10 @@
struct vmw_user_fence *ufence;
struct vmw_fence_obj *tmp;
struct ttm_mem_global *mem_glob = vmw_mem_glob(fman->dev_priv);
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
int ret;
/*
@@ -596,7 +600,7 @@
*/
ret = ttm_mem_global_alloc(mem_glob, fman->user_fence_size,
- false, false);
+ &ctx);
if (unlikely(ret != 0))
return ret;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
index b17f08f..736ca47 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
@@ -240,6 +240,10 @@
unsigned long offset;
unsigned long bo_size;
struct vmw_otable *otables = batch->otables;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
SVGAOTableType i;
int ret;
@@ -264,7 +268,7 @@
ret = ttm_bo_reserve(batch->otable_bo, false, true, NULL);
BUG_ON(ret != 0);
- ret = vmw_bo_driver.ttm_tt_populate(batch->otable_bo->ttm);
+ ret = vmw_bo_driver.ttm_tt_populate(batch->otable_bo->ttm, &ctx);
if (unlikely(ret != 0))
goto out_unreserve;
ret = vmw_bo_map_dma(batch->otable_bo);
@@ -430,6 +434,11 @@
struct vmw_mob *mob)
{
int ret;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
+
BUG_ON(mob->pt_bo != NULL);
ret = ttm_bo_create(&dev_priv->bdev, mob->num_pages * PAGE_SIZE,
@@ -442,7 +451,7 @@
ret = ttm_bo_reserve(mob->pt_bo, false, true, NULL);
BUG_ON(ret != 0);
- ret = vmw_bo_driver.ttm_tt_populate(mob->pt_bo->ttm);
+ ret = vmw_bo_driver.ttm_tt_populate(mob->pt_bo->ttm, &ctx);
if (unlikely(ret != 0))
goto out_unreserve;
ret = vmw_bo_map_dma(mob->pt_bo);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index a96f90f..200904f 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -968,6 +968,7 @@
bool interruptible,
struct ttm_validate_buffer *val_buf)
{
+ struct ttm_operation_ctx ctx = { true, false };
struct list_head val_list;
bool backup_dirty = false;
int ret;
@@ -992,7 +993,7 @@
backup_dirty = res->backup_dirty;
ret = ttm_bo_validate(&res->backup->base,
res->func->backup_placement,
- true, false);
+ &ctx);
if (unlikely(ret != 0))
goto out_no_validate;
@@ -1446,6 +1447,7 @@
*/
int vmw_resource_pin(struct vmw_resource *res, bool interruptible)
{
+ struct ttm_operation_ctx ctx = { interruptible, false };
struct vmw_private *dev_priv = res->dev_priv;
int ret;
@@ -1466,7 +1468,7 @@
ret = ttm_bo_validate
(&vbo->base,
res->func->backup_placement,
- interruptible, false);
+ &ctx);
if (ret) {
ttm_bo_unreserve(&vbo->base);
goto out_no_validate;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
index 9b832f1..73b8e9a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
@@ -607,6 +607,10 @@
struct vmw_dx_shader *shader;
struct vmw_resource *res;
struct vmw_private *dev_priv = ctx->dev_priv;
+ struct ttm_operation_ctx ttm_opt_ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
int ret;
if (!vmw_shader_dx_size)
@@ -616,7 +620,7 @@
return -EINVAL;
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), vmw_shader_dx_size,
- false, true);
+ &ttm_opt_ctx);
if (ret) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for shader "
@@ -730,6 +734,10 @@
{
struct vmw_user_shader *ushader;
struct vmw_resource *res, *tmp;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
int ret;
/*
@@ -742,7 +750,7 @@
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
vmw_user_shader_size,
- false, true);
+ &ctx);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for shader "
@@ -800,6 +808,10 @@
{
struct vmw_shader *shader;
struct vmw_resource *res;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
int ret;
/*
@@ -812,7 +824,7 @@
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
vmw_shader_size,
- false, true);
+ &ctx);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for shader "
@@ -970,6 +982,7 @@
size_t size,
struct list_head *list)
{
+ struct ttm_operation_ctx ctx = { false, true };
struct vmw_dma_buffer *buf;
struct ttm_bo_kmap_obj map;
bool is_iomem;
@@ -1005,7 +1018,7 @@
WARN_ON(is_iomem);
ttm_bo_kunmap(&map);
- ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, false, true);
+ ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, &ctx);
WARN_ON(ret != 0);
ttm_bo_unreserve(&buf->base);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c
index 051d3b3..a0cb310 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c
@@ -149,6 +149,10 @@
struct vmw_resource *res;
struct vmw_resource *tmp;
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
size_t alloc_size;
size_t account_size;
int ret;
@@ -162,7 +166,7 @@
return ret;
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), account_size,
- false, true);
+ &ctx);
ttm_read_unlock(&dev_priv->reservation_sem);
if (ret) {
if (ret != -ERESTARTSYS)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_so.c b/drivers/gpu/drm/vmwgfx/vmwgfx_so.c
index 5a73eeb..d3573c3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_so.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_so.c
@@ -329,6 +329,10 @@
struct vmw_private *dev_priv = ctx->dev_priv;
struct vmw_resource *res;
struct vmw_view *view;
+ struct ttm_operation_ctx ttm_opt_ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
size_t size;
int ret;
@@ -345,7 +349,7 @@
size = offsetof(struct vmw_view, cmd) + cmd_size;
- ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), size, false, true);
+ ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), size, &ttm_opt_ctx);
if (ret) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for view"
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
index a552e4e..a7910c8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
@@ -700,6 +700,10 @@
struct drm_vmw_surface_create_req *req = &arg->req;
struct drm_vmw_surface_arg *rep = &arg->rep;
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
int ret;
int i, j;
uint32_t cur_bo_offset;
@@ -741,7 +745,7 @@
return ret;
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
- size, false, true);
+ size, &ctx);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for surface"
@@ -1479,6 +1483,10 @@
{
struct vmw_private *dev_priv = vmw_priv(dev);
struct vmw_user_surface *user_srf;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false
+ };
struct vmw_surface *srf;
int ret;
u32 num_layers;
@@ -1525,7 +1533,7 @@
return ret;
ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv),
- user_accounting_size, false, true);
+ user_accounting_size, &ctx);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
DRM_ERROR("Out of graphics memory for surface"
diff --git a/drivers/gpu/drm/zte/zx_drm_drv.c b/drivers/gpu/drm/zte/zx_drm_drv.c
index e8b8266..6f4205e8 100644
--- a/drivers/gpu/drm/zte/zx_drm_drv.c
+++ b/drivers/gpu/drm/zte/zx_drm_drv.c
@@ -29,37 +29,19 @@
#include "zx_drm_drv.h"
#include "zx_vou.h"
-struct zx_drm_private {
- struct drm_fbdev_cma *fbdev;
-};
-
-static void zx_drm_fb_output_poll_changed(struct drm_device *drm)
-{
- struct zx_drm_private *priv = drm->dev_private;
-
- drm_fbdev_cma_hotplug_event(priv->fbdev);
-}
-
static const struct drm_mode_config_funcs zx_drm_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
- .output_poll_changed = zx_drm_fb_output_poll_changed,
+ .output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
-static void zx_drm_lastclose(struct drm_device *drm)
-{
- struct zx_drm_private *priv = drm->dev_private;
-
- drm_fbdev_cma_restore_mode(priv->fbdev);
-}
-
DEFINE_DRM_GEM_CMA_FOPS(zx_drm_fops);
static struct drm_driver zx_drm_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
DRIVER_ATOMIC,
- .lastclose = zx_drm_lastclose,
+ .lastclose = drm_fb_helper_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = drm_gem_cma_dumb_create,
@@ -83,18 +65,12 @@
static int zx_drm_bind(struct device *dev)
{
struct drm_device *drm;
- struct zx_drm_private *priv;
int ret;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
drm = drm_dev_alloc(&zx_drm_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
- drm->dev_private = priv;
dev_set_drvdata(dev, drm);
drm_mode_config_init(drm);
@@ -125,12 +101,9 @@
drm_mode_config_reset(drm);
drm_kms_helper_poll_init(drm);
- priv->fbdev = drm_fbdev_cma_init(drm, 32,
- drm->mode_config.num_connector);
- if (IS_ERR(priv->fbdev)) {
- ret = PTR_ERR(priv->fbdev);
+ ret = drm_fb_cma_fbdev_init(drm, 32, 0);
+ if (ret) {
DRM_DEV_ERROR(dev, "failed to init cma fbdev: %d\n", ret);
- priv->fbdev = NULL;
goto out_poll_fini;
}
@@ -141,10 +114,7 @@
return 0;
out_fbdev_fini:
- if (priv->fbdev) {
- drm_fbdev_cma_fini(priv->fbdev);
- priv->fbdev = NULL;
- }
+ drm_fb_cma_fbdev_fini(drm);
out_poll_fini:
drm_kms_helper_poll_fini(drm);
drm_mode_config_cleanup(drm);
@@ -152,7 +122,6 @@
component_unbind_all(dev, drm);
out_unregister:
dev_set_drvdata(dev, NULL);
- drm->dev_private = NULL;
drm_dev_unref(drm);
return ret;
}
@@ -160,18 +129,13 @@
static void zx_drm_unbind(struct device *dev)
{
struct drm_device *drm = dev_get_drvdata(dev);
- struct zx_drm_private *priv = drm->dev_private;
drm_dev_unregister(drm);
- if (priv->fbdev) {
- drm_fbdev_cma_fini(priv->fbdev);
- priv->fbdev = NULL;
- }
+ drm_fb_cma_fbdev_fini(drm);
drm_kms_helper_poll_fini(drm);
drm_mode_config_cleanup(drm);
component_unbind_all(dev, drm);
dev_set_drvdata(dev, NULL);
- drm->dev_private = NULL;
drm_dev_unref(drm);
}
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 773d633..bf67c3a 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -239,8 +239,7 @@
order = __ffs(host->domain->pgsize_bitmap);
init_iova_domain(&host->iova, 1UL << order,
- geometry->aperture_start >> order,
- geometry->aperture_end >> order);
+ geometry->aperture_start >> order);
host->iova_end = geometry->aperture_end;
}
diff --git a/drivers/hid/hid-debug.c b/drivers/hid/hid-debug.c
index 5271db5..ae8c8e6 100644
--- a/drivers/hid/hid-debug.c
+++ b/drivers/hid/hid-debug.c
@@ -1154,6 +1154,8 @@
goto out;
if (list->tail > list->head) {
len = list->tail - list->head;
+ if (len > count)
+ len = count;
if (copy_to_user(buffer + ret, &list->hid_debug_buf[list->head], len)) {
ret = -EFAULT;
@@ -1163,6 +1165,8 @@
list->head += len;
} else {
len = HID_DEBUG_BUFSIZE - list->head;
+ if (len > count)
+ len = count;
if (copy_to_user(buffer, &list->hid_debug_buf[list->head], len)) {
ret = -EFAULT;
@@ -1170,7 +1174,9 @@
}
list->head = 0;
ret += len;
- goto copy_rest;
+ count -= len;
+ if (count > 0)
+ goto copy_rest;
}
}
diff --git a/drivers/hid/i2c-hid/i2c-hid.c b/drivers/hid/i2c-hid/i2c-hid.c
index f63e752..b6e428c 100644
--- a/drivers/hid/i2c-hid/i2c-hid.c
+++ b/drivers/hid/i2c-hid/i2c-hid.c
@@ -476,7 +476,7 @@
return;
}
- if ((ret_size > size) || (ret_size <= 2)) {
+ if ((ret_size > size) || (ret_size < 2)) {
dev_err(&ihid->client->dev, "%s: incomplete report (%d/%d)\n",
__func__, size, ret_size);
return;
diff --git a/drivers/hid/usbhid/hiddev.c b/drivers/hid/usbhid/hiddev.c
index 7d749b1..cf307bd 100644
--- a/drivers/hid/usbhid/hiddev.c
+++ b/drivers/hid/usbhid/hiddev.c
@@ -36,6 +36,7 @@
#include <linux/hiddev.h>
#include <linux/compat.h>
#include <linux/vmalloc.h>
+#include <linux/nospec.h>
#include "usbhid.h"
#ifdef CONFIG_USB_DYNAMIC_MINORS
@@ -469,10 +470,14 @@
if (uref->field_index >= report->maxfield)
goto inval;
+ uref->field_index = array_index_nospec(uref->field_index,
+ report->maxfield);
field = report->field[uref->field_index];
if (uref->usage_index >= field->maxusage)
goto inval;
+ uref->usage_index = array_index_nospec(uref->usage_index,
+ field->maxusage);
uref->usage_code = field->usage[uref->usage_index].hid;
@@ -499,6 +504,8 @@
if (uref->field_index >= report->maxfield)
goto inval;
+ uref->field_index = array_index_nospec(uref->field_index,
+ report->maxfield);
field = report->field[uref->field_index];
@@ -753,6 +760,8 @@
if (finfo.field_index >= report->maxfield)
break;
+ finfo.field_index = array_index_nospec(finfo.field_index,
+ report->maxfield);
field = report->field[finfo.field_index];
memset(&finfo, 0, sizeof(finfo));
@@ -797,6 +806,8 @@
if (cinfo.index >= hid->maxcollection)
break;
+ cinfo.index = array_index_nospec(cinfo.index,
+ hid->maxcollection);
cinfo.type = hid->collection[cinfo.index].type;
cinfo.usage = hid->collection[cinfo.index].usage;
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 60292d2..ec2d11af6 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -547,6 +547,14 @@
{
u32 cnfg;
+ /*
+ * NACK interrupt is generated before the I2C controller generates
+ * the STOP condition on the bus. So wait for 2 clock periods
+ * before disabling the controller so that the STOP condition has
+ * been delivered properly.
+ */
+ udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
+
cnfg = i2c_readl(i2c_dev, I2C_CNFG);
if (cnfg & I2C_CNFG_PACKET_MODE_EN)
i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
@@ -708,15 +716,6 @@
if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
return 0;
- /*
- * NACK interrupt is generated before the I2C controller generates
- * the STOP condition on the bus. So wait for 2 clock periods
- * before resetting the controller so that the STOP condition has
- * been delivered properly.
- */
- if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
- udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
-
tegra_i2c_init(i2c_dev);
if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
if (msg->flags & I2C_M_IGNORE_NAK)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 731a793..f5d9025 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -61,10 +61,13 @@
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/moduleparam.h>
+#include <linux/suspend.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/mwait.h>
#include <asm/msr.h>
+#include <asm/pmc_core.h>
+#include <asm/intel_pmc_ipc.h>
#define INTEL_IDLE_VERSION "0.4.1"
@@ -93,12 +96,29 @@
bool disable_promotion_to_c1e;
};
+/*
+ * The limit for the exponential backoff for the freeze duration. At this point,
+ * power impact is far from measurable. It's about 3uW based on scaling from
+ * waking up 10 times a second.
+ */
+#define MAX_SLP_S0_SECONDS 1000
+#define SLP_S0_EXP_BASE 10
+
+static bool slp_s0_check;
+static unsigned int slp_s0_seconds;
+
+static DEFINE_SPINLOCK(slp_s0_check_lock);
+static unsigned int slp_s0_num_cpus;
+static bool slp_s0_check_inprogress;
+
static const struct idle_cpu *icpu;
static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
static int intel_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
-static void intel_idle_s2idle(struct cpuidle_device *dev,
+static int intel_idle_s2idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
+static int intel_idle_s2idle_and_check(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index);
static struct cpuidle_state *cpuidle_state_table;
/*
@@ -597,7 +617,7 @@
.exit_latency = 2,
.target_residency = 2,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C1E",
.desc = "MWAIT 0x01",
@@ -605,7 +625,7 @@
.exit_latency = 10,
.target_residency = 20,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C3",
.desc = "MWAIT 0x10",
@@ -613,7 +633,7 @@
.exit_latency = 70,
.target_residency = 100,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C6",
.desc = "MWAIT 0x20",
@@ -621,7 +641,7 @@
.exit_latency = 85,
.target_residency = 200,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C7s",
.desc = "MWAIT 0x33",
@@ -629,7 +649,7 @@
.exit_latency = 124,
.target_residency = 800,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C8",
.desc = "MWAIT 0x40",
@@ -637,7 +657,7 @@
.exit_latency = 200,
.target_residency = 800,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C9",
.desc = "MWAIT 0x50",
@@ -645,7 +665,7 @@
.exit_latency = 480,
.target_residency = 5000,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C10",
.desc = "MWAIT 0x60",
@@ -653,7 +673,7 @@
.exit_latency = 890,
.target_residency = 5000,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.enter = NULL }
};
@@ -816,7 +836,7 @@
.exit_latency = 2,
.target_residency = 2,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C1E",
.desc = "MWAIT 0x01",
@@ -824,7 +844,7 @@
.exit_latency = 10,
.target_residency = 20,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C6",
.desc = "MWAIT 0x20",
@@ -832,7 +852,7 @@
.exit_latency = 133,
.target_residency = 133,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C7s",
.desc = "MWAIT 0x31",
@@ -840,7 +860,7 @@
.exit_latency = 155,
.target_residency = 155,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C8",
.desc = "MWAIT 0x40",
@@ -848,7 +868,7 @@
.exit_latency = 1000,
.target_residency = 1000,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C9",
.desc = "MWAIT 0x50",
@@ -856,7 +876,7 @@
.exit_latency = 2000,
.target_residency = 2000,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.name = "C10",
.desc = "MWAIT 0x60",
@@ -864,7 +884,7 @@
.exit_latency = 10000,
.target_residency = 10000,
.enter = &intel_idle,
- .enter_s2idle = intel_idle_s2idle, },
+ .enter_s2idle = intel_idle_s2idle_and_check, },
{
.enter = NULL }
};
@@ -940,16 +960,127 @@
* @dev: cpuidle_device
* @drv: cpuidle driver
* @index: state index
+ *
+ * @return 0 for success, no failure state
*/
-static void intel_idle_s2idle(struct cpuidle_device *dev,
+static int intel_idle_s2idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
unsigned long ecx = 1; /* break on interrupt flag */
unsigned long eax = flg2MWAIT(drv->states[index].flags);
mwait_idle_with_hints(eax, ecx);
+
+ return 0;
}
+static int get_slpS0_count(u64* slp_s0_count)
+{
+ switch (boot_cpu_data.x86_model) {
+
+ case INTEL_FAM6_ATOM_GEMINI_LAKE:
+ return intel_pmc_s0ix_counter_read(slp_s0_count);
+ default:
+ return intel_pmc_slp_s0_counter_read((u32*)slp_s0_count);
+ }
+}
+
+static int check_slp_s0(u64 slp_s0_saved_count)
+{
+ u64 slp_s0_new_count;
+
+ if (get_slpS0_count(&slp_s0_new_count)) {
+ pr_warn("After s2idle attempt: Unable to read SLP S0 residency counter\n");
+ return -EIO;
+ }
+
+ if (slp_s0_saved_count == slp_s0_new_count) {
+ pr_warn("CPU did not enter SLP S0 for suspend-to-idle.\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * intel_idle_s2idle_and_check - enters suspend-to-idle and validates the power
+ * state
+ *
+ * This function enters suspend-to-idle with intel_idle_freeze, but also sets up
+ * a timer to check that S0ix (low power state for suspend-to-idle on Intel
+ * CPUs) is properly entered.
+ *
+ * @dev: cpuidle_device
+ * @drv: cpuidle_driver
+ * @index: state index
+ * @return 0 for success, -EERROR if S0ix was not entered.
+ */
+static int intel_idle_s2idle_and_check(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ bool check_on_this_cpu = false;
+ u64 slp_s0_saved_count;
+ unsigned long flags;
+ int cpu = smp_processor_id();
+ int ret;
+
+ /* The last CPU to freeze sets up checking SLP S0 assertion. */
+ spin_lock_irqsave(&slp_s0_check_lock, flags);
+ slp_s0_num_cpus++;
+
+ if (slp_s0_seconds &&
+ slp_s0_num_cpus == num_online_cpus() &&
+ !slp_s0_check_inprogress &&
+ !get_slpS0_count(&slp_s0_saved_count)) {
+ ret = tick_set_freeze_event(cpu, ktime_set(slp_s0_seconds, 0));
+ if (ret < 0) {
+ spin_unlock_irqrestore(&slp_s0_check_lock, flags);
+ goto out;
+ }
+
+ /*
+ * Make sure check_slp_s0 isn't scheduled on another CPU if it
+ * were to leave freeze and enter it again before this CPU
+ * leaves freeze.
+ */
+ slp_s0_check_inprogress = true;
+ check_on_this_cpu = true;
+ }
+ spin_unlock_irqrestore(&slp_s0_check_lock, flags);
+
+ ret = intel_idle_s2idle(dev, drv, index);
+ if (ret < 0)
+ goto out;
+
+ if (check_on_this_cpu && tick_clear_freeze_event(cpu))
+ ret = check_slp_s0(slp_s0_saved_count);
+
+out:
+ spin_lock_irqsave(&slp_s0_check_lock, flags);
+ if (check_on_this_cpu) {
+ slp_s0_check_inprogress = false;
+ slp_s0_seconds = min_t(unsigned int,
+ SLP_S0_EXP_BASE * slp_s0_seconds,
+ MAX_SLP_S0_SECONDS);
+ }
+ slp_s0_num_cpus--;
+ spin_unlock_irqrestore(&slp_s0_check_lock, flags);
+ return ret;
+}
+
+static int slp_s0_check_prepare(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ if (action == PM_SUSPEND_PREPARE)
+ slp_s0_seconds = slp_s0_check ? 1 : 0;
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block intel_slp_s0_check_nb = {
+ .notifier_call = slp_s0_check_prepare,
+};
+
static void __setup_broadcast_timer(bool on)
{
if (on)
@@ -1454,6 +1585,13 @@
goto init_driver_fail;
}
+ retval = register_pm_notifier(&intel_slp_s0_check_nb);
+ if (retval) {
+ free_percpu(intel_idle_cpuidle_devices);
+ cpuidle_unregister_driver(&intel_idle_driver);
+ goto pm_nb_fail;
+ }
+
if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
@@ -1469,6 +1607,8 @@
hp_setup_fail:
intel_idle_cpuidle_devices_uninit();
+ unregister_pm_notifier(&intel_slp_s0_check_nb);
+pm_nb_fail:
cpuidle_unregister_driver(&intel_idle_driver);
init_driver_fail:
free_percpu(intel_idle_cpuidle_devices);
@@ -1484,3 +1624,4 @@
* is the easiest way (currently) to continue doing that.
*/
module_param(max_cstate, int, 0444);
+module_param(slp_s0_check, bool, 0644);
diff --git a/drivers/iio/accel/sca3000.c b/drivers/iio/accel/sca3000.c
index 39ab210..565f7d8d 100644
--- a/drivers/iio/accel/sca3000.c
+++ b/drivers/iio/accel/sca3000.c
@@ -1277,7 +1277,7 @@
{
struct iio_buffer *buffer;
- buffer = iio_kfifo_allocate();
+ buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
if (!buffer)
return -ENOMEM;
@@ -1287,11 +1287,6 @@
return 0;
}
-static void sca3000_unconfigure_ring(struct iio_dev *indio_dev)
-{
- iio_kfifo_free(indio_dev->buffer);
-}
-
static inline
int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
{
@@ -1547,8 +1542,6 @@
if (spi->irq)
free_irq(spi->irq, indio_dev);
- sca3000_unconfigure_ring(indio_dev);
-
return 0;
}
diff --git a/drivers/iio/adc/ad7791.c b/drivers/iio/adc/ad7791.c
index 34e353c..677f812 100644
--- a/drivers/iio/adc/ad7791.c
+++ b/drivers/iio/adc/ad7791.c
@@ -244,58 +244,9 @@
return -EINVAL;
}
-static const char * const ad7791_sample_freq_avail[] = {
- [AD7791_FILTER_RATE_120] = "120",
- [AD7791_FILTER_RATE_100] = "100",
- [AD7791_FILTER_RATE_33_3] = "33.3",
- [AD7791_FILTER_RATE_20] = "20",
- [AD7791_FILTER_RATE_16_6] = "16.6",
- [AD7791_FILTER_RATE_16_7] = "16.7",
- [AD7791_FILTER_RATE_13_3] = "13.3",
- [AD7791_FILTER_RATE_9_5] = "9.5",
-};
-
-static ssize_t ad7791_read_frequency(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct iio_dev *indio_dev = dev_to_iio_dev(dev);
- struct ad7791_state *st = iio_priv(indio_dev);
- unsigned int rate = st->filter & AD7791_FILTER_RATE_MASK;
-
- return sprintf(buf, "%s\n", ad7791_sample_freq_avail[rate]);
-}
-
-static ssize_t ad7791_write_frequency(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t len)
-{
- struct iio_dev *indio_dev = dev_to_iio_dev(dev);
- struct ad7791_state *st = iio_priv(indio_dev);
- int i, ret;
-
- i = sysfs_match_string(ad7791_sample_freq_avail, buf);
- if (i < 0)
- return i;
-
- ret = iio_device_claim_direct_mode(indio_dev);
- if (ret)
- return ret;
- st->filter &= ~AD7791_FILTER_RATE_MASK;
- st->filter |= i;
- ad_sd_write_reg(&st->sd, AD7791_REG_FILTER, sizeof(st->filter),
- st->filter);
- iio_device_release_direct_mode(indio_dev);
-
- return len;
-}
-
-static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
- ad7791_read_frequency,
- ad7791_write_frequency);
-
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("120 100 33.3 20 16.7 16.6 13.3 9.5");
static struct attribute *ad7791_attributes[] = {
- &iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig
index 7507cc6..27b3c39 100644
--- a/drivers/infiniband/Kconfig
+++ b/drivers/infiniband/Kconfig
@@ -34,6 +34,18 @@
libibverbs, libibcm and a hardware driver library from
<http://www.openfabrics.org/git/>.
+config INFINIBAND_USER_ACCESS_UCM
+ bool "Userspace CM (UCM, DEPRECATED)"
+ depends on BROKEN
+ depends on INFINIBAND_USER_ACCESS
+ help
+ The UCM module has known security flaws, which no one is
+ interested to fix. The user-space part of this code was
+ dropped from the upstream a long time ago.
+
+ This option is DEPRECATED and planned to be removed.
+
+
config INFINIBAND_EXP_USER_ACCESS
bool "Allow experimental support for Infiniband ABI"
depends on INFINIBAND_USER_ACCESS
diff --git a/drivers/infiniband/core/Makefile b/drivers/infiniband/core/Makefile
index 9c0a2b5..991c252 100644
--- a/drivers/infiniband/core/Makefile
+++ b/drivers/infiniband/core/Makefile
@@ -5,8 +5,8 @@
obj-$(CONFIG_INFINIBAND) += ib_core.o ib_cm.o iw_cm.o \
$(infiniband-y)
obj-$(CONFIG_INFINIBAND_USER_MAD) += ib_umad.o
-obj-$(CONFIG_INFINIBAND_USER_ACCESS) += ib_uverbs.o ib_ucm.o \
- $(user_access-y)
+obj-$(CONFIG_INFINIBAND_USER_ACCESS) += ib_uverbs.o $(user_access-y)
+obj-$(CONFIG_INFINIBAND_USER_ACCESS_UCM) += ib_ucm.o $(user_access-y)
ib_core-y := packer.o ud_header.o verbs.o cq.o rw.o sysfs.o \
device.o fmr_pool.o cache.o netlink.o \
diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
index 2b6c9b5..d76455e 100644
--- a/drivers/infiniband/core/umem.c
+++ b/drivers/infiniband/core/umem.c
@@ -119,16 +119,7 @@
umem->length = size;
umem->address = addr;
umem->page_shift = PAGE_SHIFT;
- /*
- * We ask for writable memory if any of the following
- * access flags are set. "Local write" and "remote write"
- * obviously require write access. "Remote atomic" can do
- * things like fetch and add, which will modify memory, and
- * "MW bind" can change permissions by binding a window.
- */
- umem->writable = !!(access &
- (IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE |
- IB_ACCESS_REMOTE_ATOMIC | IB_ACCESS_MW_BIND));
+ umem->writable = ib_access_writable(access);
if (access & IB_ACCESS_ON_DEMAND) {
ret = ib_umem_odp_get(context, umem, access);
diff --git a/drivers/infiniband/hw/cxgb4/mem.c b/drivers/infiniband/hw/cxgb4/mem.c
index c2fba76..b5784cb 100644
--- a/drivers/infiniband/hw/cxgb4/mem.c
+++ b/drivers/infiniband/hw/cxgb4/mem.c
@@ -720,7 +720,7 @@
{
struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
- if (unlikely(mhp->mpl_len == mhp->max_mpl_len))
+ if (unlikely(mhp->mpl_len == mhp->attr.pbl_size))
return -ENOMEM;
mhp->mpl[mhp->mpl_len++] = addr;
diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c
index 2595622..33cf173 100644
--- a/drivers/infiniband/hw/hfi1/chip.c
+++ b/drivers/infiniband/hw/hfi1/chip.c
@@ -6829,7 +6829,7 @@
}
rcvmask = HFI1_RCVCTRL_CTXT_ENB;
/* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
- rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ?
+ rcvmask |= rcd->rcvhdrtail_kvaddr ?
HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
hfi1_rcvctrl(dd, rcvmask, rcd);
hfi1_rcd_put(rcd);
@@ -8341,7 +8341,7 @@
u32 tail;
int present;
- if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
+ if (!rcd->rcvhdrtail_kvaddr)
present = (rcd->seq_cnt ==
rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
else /* is RDMA rtail */
@@ -11813,7 +11813,7 @@
/* reset the tail and hdr addresses, and sequence count */
write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
rcd->rcvhdrq_dma);
- if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
+ if (rcd->rcvhdrtail_kvaddr)
write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
rcd->rcvhdrqtailaddr_dma);
rcd->seq_cnt = 1;
@@ -11893,7 +11893,7 @@
rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
- if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma)
+ if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && rcd->rcvhdrtail_kvaddr)
rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
/* See comment on RcvCtxtCtrl.TailUpd above */
diff --git a/drivers/infiniband/hw/hfi1/debugfs.c b/drivers/infiniband/hw/hfi1/debugfs.c
index 36ae1fd..f661b38 100644
--- a/drivers/infiniband/hw/hfi1/debugfs.c
+++ b/drivers/infiniband/hw/hfi1/debugfs.c
@@ -1179,7 +1179,8 @@
static void fault_exit_opcode_debugfs(struct hfi1_ibdev *ibd)
{
- debugfs_remove_recursive(ibd->fault_opcode->dir);
+ if (ibd->fault_opcode)
+ debugfs_remove_recursive(ibd->fault_opcode->dir);
kfree(ibd->fault_opcode);
ibd->fault_opcode = NULL;
}
@@ -1207,6 +1208,7 @@
&ibd->fault_opcode->attr);
if (IS_ERR(ibd->fault_opcode->dir)) {
kfree(ibd->fault_opcode);
+ ibd->fault_opcode = NULL;
return -ENOENT;
}
@@ -1230,7 +1232,8 @@
static void fault_exit_packet_debugfs(struct hfi1_ibdev *ibd)
{
- debugfs_remove_recursive(ibd->fault_packet->dir);
+ if (ibd->fault_packet)
+ debugfs_remove_recursive(ibd->fault_packet->dir);
kfree(ibd->fault_packet);
ibd->fault_packet = NULL;
}
@@ -1256,6 +1259,7 @@
&ibd->fault_opcode->attr);
if (IS_ERR(ibd->fault_packet->dir)) {
kfree(ibd->fault_packet);
+ ibd->fault_packet = NULL;
return -ENOENT;
}
diff --git a/drivers/infiniband/hw/hfi1/file_ops.c b/drivers/infiniband/hw/hfi1/file_ops.c
index ee2253d..9abc5a9 100644
--- a/drivers/infiniband/hw/hfi1/file_ops.c
+++ b/drivers/infiniband/hw/hfi1/file_ops.c
@@ -622,7 +622,7 @@
ret = -EINVAL;
goto done;
}
- if (flags & VM_WRITE) {
+ if ((flags & VM_WRITE) || !uctxt->rcvhdrtail_kvaddr) {
ret = -EPERM;
goto done;
}
@@ -807,8 +807,8 @@
* checks to default and disable the send context.
*/
if (uctxt->sc) {
- set_pio_integrity(uctxt->sc);
sc_disable(uctxt->sc);
+ set_pio_integrity(uctxt->sc);
}
hfi1_free_ctxt_rcv_groups(uctxt);
diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h
index ccc7b9b..13a7bcaa 100644
--- a/drivers/infiniband/hw/hfi1/hfi.h
+++ b/drivers/infiniband/hw/hfi1/hfi.h
@@ -1851,6 +1851,7 @@
#define HFI1_HAS_SDMA_TIMEOUT 0x8
#define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
#define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
+#define HFI1_SHUTDOWN 0x100 /* device is shutting down */
/* IB dword length mask in PBC (lower 11 bits); same for all chips */
#define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
diff --git a/drivers/infiniband/hw/hfi1/init.c b/drivers/infiniband/hw/hfi1/init.c
index 918dbd3..ee5cbdf 100644
--- a/drivers/infiniband/hw/hfi1/init.c
+++ b/drivers/infiniband/hw/hfi1/init.c
@@ -1029,6 +1029,10 @@
unsigned pidx;
int i;
+ if (dd->flags & HFI1_SHUTDOWN)
+ return;
+ dd->flags |= HFI1_SHUTDOWN;
+
for (pidx = 0; pidx < dd->num_pports; ++pidx) {
ppd = dd->pport + pidx;
@@ -1353,6 +1357,7 @@
static void remove_one(struct pci_dev *);
static int init_one(struct pci_dev *, const struct pci_device_id *);
+static void shutdown_one(struct pci_dev *);
#define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
#define PFX DRIVER_NAME ": "
@@ -1369,6 +1374,7 @@
.name = DRIVER_NAME,
.probe = init_one,
.remove = remove_one,
+ .shutdown = shutdown_one,
.id_table = hfi1_pci_tbl,
.err_handler = &hfi1_pci_err_handler,
};
@@ -1780,6 +1786,13 @@
postinit_cleanup(dd);
}
+static void shutdown_one(struct pci_dev *pdev)
+{
+ struct hfi1_devdata *dd = pci_get_drvdata(pdev);
+
+ shutdown_device(dd);
+}
+
/**
* hfi1_create_rcvhdrq - create a receive header queue
* @dd: the hfi1_ib device
@@ -1795,7 +1808,6 @@
u64 reg;
if (!rcd->rcvhdrq) {
- dma_addr_t dma_hdrqtail;
gfp_t gfp_flags;
/*
@@ -1821,13 +1833,13 @@
goto bail;
}
- if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) {
+ if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ||
+ HFI1_CAP_UGET_MASK(rcd->flags, DMA_RTAIL)) {
rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent(
- &dd->pcidev->dev, PAGE_SIZE, &dma_hdrqtail,
- gfp_flags);
+ &dd->pcidev->dev, PAGE_SIZE,
+ &rcd->rcvhdrqtailaddr_dma, gfp_flags);
if (!rcd->rcvhdrtail_kvaddr)
goto bail_free;
- rcd->rcvhdrqtailaddr_dma = dma_hdrqtail;
}
rcd->rcvhdrq_size = amt;
diff --git a/drivers/infiniband/hw/hfi1/pio.c b/drivers/infiniband/hw/hfi1/pio.c
index 7108a4b..a95ac624 100644
--- a/drivers/infiniband/hw/hfi1/pio.c
+++ b/drivers/infiniband/hw/hfi1/pio.c
@@ -50,8 +50,6 @@
#include "qp.h"
#include "trace.h"
-#define SC_CTXT_PACKET_EGRESS_TIMEOUT 350 /* in chip cycles */
-
#define SC(name) SEND_CTXT_##name
/*
* Send Context functions
@@ -977,15 +975,40 @@
}
/* return SendEgressCtxtStatus.PacketOccupancy */
-#define packet_occupancy(r) \
- (((r) & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)\
- >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT)
+static u64 packet_occupancy(u64 reg)
+{
+ return (reg &
+ SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)
+ >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT;
+}
/* is egress halted on the context? */
-#define egress_halted(r) \
- ((r) & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK)
+static bool egress_halted(u64 reg)
+{
+ return !!(reg & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK);
+}
-/* wait for packet egress, optionally pause for credit return */
+/* is the send context halted? */
+static bool is_sc_halted(struct hfi1_devdata *dd, u32 hw_context)
+{
+ return !!(read_kctxt_csr(dd, hw_context, SC(STATUS)) &
+ SC(STATUS_CTXT_HALTED_SMASK));
+}
+
+/**
+ * sc_wait_for_packet_egress
+ * @sc: valid send context
+ * @pause: wait for credit return
+ *
+ * Wait for packet egress, optionally pause for credit return
+ *
+ * Egress halt and Context halt are not necessarily the same thing, so
+ * check for both.
+ *
+ * NOTE: The context halt bit may not be set immediately. Because of this,
+ * it is necessary to check the SW SFC_HALTED bit (set in the IRQ) and the HW
+ * context bit to determine if the context is halted.
+ */
static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
{
struct hfi1_devdata *dd = sc->dd;
@@ -997,8 +1020,9 @@
reg_prev = reg;
reg = read_csr(dd, sc->hw_context * 8 +
SEND_EGRESS_CTXT_STATUS);
- /* done if egress is stopped */
- if (egress_halted(reg))
+ /* done if any halt bits, SW or HW are set */
+ if (sc->flags & SCF_HALTED ||
+ is_sc_halted(dd, sc->hw_context) || egress_halted(reg))
break;
reg = packet_occupancy(reg);
if (reg == 0)
diff --git a/drivers/infiniband/hw/hfi1/rc.c b/drivers/infiniband/hw/hfi1/rc.c
index 84c6a6f..818bac1 100644
--- a/drivers/infiniband/hw/hfi1/rc.c
+++ b/drivers/infiniband/hw/hfi1/rc.c
@@ -273,7 +273,7 @@
lockdep_assert_held(&qp->s_lock);
ps->s_txreq = get_txreq(ps->dev, qp);
- if (IS_ERR(ps->s_txreq))
+ if (!ps->s_txreq)
goto bail_no_tx;
ps->s_txreq->phdr.hdr.hdr_type = priv->hdr_type;
diff --git a/drivers/infiniband/hw/hfi1/uc.c b/drivers/infiniband/hw/hfi1/uc.c
index 0b64617..92e033f 100644
--- a/drivers/infiniband/hw/hfi1/uc.c
+++ b/drivers/infiniband/hw/hfi1/uc.c
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2015, 2016 Intel Corporation.
+ * Copyright(c) 2015 - 2018 Intel Corporation.
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
@@ -72,7 +72,7 @@
int middle = 0;
ps->s_txreq = get_txreq(ps->dev, qp);
- if (IS_ERR(ps->s_txreq))
+ if (!ps->s_txreq)
goto bail_no_tx;
if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_SEND_OK)) {
diff --git a/drivers/infiniband/hw/hfi1/ud.c b/drivers/infiniband/hw/hfi1/ud.c
index 38c7d9c..37abd15 100644
--- a/drivers/infiniband/hw/hfi1/ud.c
+++ b/drivers/infiniband/hw/hfi1/ud.c
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2015, 2016 Intel Corporation.
+ * Copyright(c) 2015 - 2018 Intel Corporation.
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
@@ -479,7 +479,7 @@
u32 lid;
ps->s_txreq = get_txreq(ps->dev, qp);
- if (IS_ERR(ps->s_txreq))
+ if (!ps->s_txreq)
goto bail_no_tx;
if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_NEXT_SEND_OK)) {
diff --git a/drivers/infiniband/hw/hfi1/verbs_txreq.c b/drivers/infiniband/hw/hfi1/verbs_txreq.c
index 873e48e..c4ab2d5 100644
--- a/drivers/infiniband/hw/hfi1/verbs_txreq.c
+++ b/drivers/infiniband/hw/hfi1/verbs_txreq.c
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2016 - 2017 Intel Corporation.
+ * Copyright(c) 2016 - 2018 Intel Corporation.
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
@@ -94,7 +94,7 @@
struct rvt_qp *qp)
__must_hold(&qp->s_lock)
{
- struct verbs_txreq *tx = ERR_PTR(-EBUSY);
+ struct verbs_txreq *tx = NULL;
write_seqlock(&dev->txwait_lock);
if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
diff --git a/drivers/infiniband/hw/hfi1/verbs_txreq.h b/drivers/infiniband/hw/hfi1/verbs_txreq.h
index 76216f2..22fc5dd 100644
--- a/drivers/infiniband/hw/hfi1/verbs_txreq.h
+++ b/drivers/infiniband/hw/hfi1/verbs_txreq.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2016 Intel Corporation.
+ * Copyright(c) 2016 - 2018 Intel Corporation.
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
@@ -83,7 +83,7 @@
if (unlikely(!tx)) {
/* call slow path to get the lock */
tx = __get_txreq(dev, qp);
- if (IS_ERR(tx))
+ if (!tx)
return tx;
}
tx->qp = qp;
diff --git a/drivers/infiniband/hw/mlx4/mad.c b/drivers/infiniband/hw/mlx4/mad.c
index 0793a21..d604b3d 100644
--- a/drivers/infiniband/hw/mlx4/mad.c
+++ b/drivers/infiniband/hw/mlx4/mad.c
@@ -1934,7 +1934,6 @@
"buf:%lld\n", wc.wr_id);
break;
default:
- BUG_ON(1);
break;
}
} else {
diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c
index e80a7f7..1587ced 100644
--- a/drivers/infiniband/hw/mlx4/mr.c
+++ b/drivers/infiniband/hw/mlx4/mr.c
@@ -131,6 +131,40 @@
return err;
}
+static struct ib_umem *mlx4_get_umem_mr(struct ib_ucontext *context, u64 start,
+ u64 length, u64 virt_addr,
+ int access_flags)
+{
+ /*
+ * Force registering the memory as writable if the underlying pages
+ * are writable. This is so rereg can change the access permissions
+ * from readable to writable without having to run through ib_umem_get
+ * again
+ */
+ if (!ib_access_writable(access_flags)) {
+ struct vm_area_struct *vma;
+
+ down_read(¤t->mm->mmap_sem);
+ /*
+ * FIXME: Ideally this would iterate over all the vmas that
+ * cover the memory, but for now it requires a single vma to
+ * entirely cover the MR to support RO mappings.
+ */
+ vma = find_vma(current->mm, start);
+ if (vma && vma->vm_end >= start + length &&
+ vma->vm_start <= start) {
+ if (vma->vm_flags & VM_WRITE)
+ access_flags |= IB_ACCESS_LOCAL_WRITE;
+ } else {
+ access_flags |= IB_ACCESS_LOCAL_WRITE;
+ }
+
+ up_read(¤t->mm->mmap_sem);
+ }
+
+ return ib_umem_get(context, start, length, access_flags, 0);
+}
+
struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
u64 virt_addr, int access_flags,
struct ib_udata *udata)
@@ -145,10 +179,8 @@
if (!mr)
return ERR_PTR(-ENOMEM);
- /* Force registering the memory as writable. */
- /* Used for memory re-registeration. HCA protects the access */
- mr->umem = ib_umem_get(pd->uobject->context, start, length,
- access_flags | IB_ACCESS_LOCAL_WRITE, 0);
+ mr->umem = mlx4_get_umem_mr(pd->uobject->context, start, length,
+ virt_addr, access_flags);
if (IS_ERR(mr->umem)) {
err = PTR_ERR(mr->umem);
goto err_free;
@@ -215,6 +247,9 @@
}
if (flags & IB_MR_REREG_ACCESS) {
+ if (ib_access_writable(mr_access_flags) && !mmr->umem->writable)
+ return -EPERM;
+
err = mlx4_mr_hw_change_access(dev->dev, *pmpt_entry,
convert_access(mr_access_flags));
@@ -228,10 +263,9 @@
mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr);
ib_umem_release(mmr->umem);
- mmr->umem = ib_umem_get(mr->uobject->context, start, length,
- mr_access_flags |
- IB_ACCESS_LOCAL_WRITE,
- 0);
+ mmr->umem =
+ mlx4_get_umem_mr(mr->uobject->context, start, length,
+ virt_addr, mr_access_flags);
if (IS_ERR(mmr->umem)) {
err = PTR_ERR(mmr->umem);
/* Prevent mlx4_ib_dereg_mr from free'ing invalid pointer */
diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c
index d804880..be6612f 100644
--- a/drivers/infiniband/hw/mlx5/cq.c
+++ b/drivers/infiniband/hw/mlx5/cq.c
@@ -646,7 +646,7 @@
}
static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
- struct ib_wc *wc)
+ struct ib_wc *wc, bool is_fatal_err)
{
struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
struct mlx5_ib_wc *soft_wc, *next;
@@ -659,6 +659,10 @@
mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
cq->mcq.cqn);
+ if (unlikely(is_fatal_err)) {
+ soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
+ soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
+ }
wc[npolled++] = soft_wc->wc;
list_del(&soft_wc->list);
kfree(soft_wc);
@@ -679,12 +683,17 @@
spin_lock_irqsave(&cq->lock, flags);
if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
- mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
+ /* make sure no soft wqe's are waiting */
+ if (unlikely(!list_empty(&cq->wc_list)))
+ soft_polled = poll_soft_wc(cq, num_entries, wc, true);
+
+ mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
+ wc + soft_polled, &npolled);
goto out;
}
if (unlikely(!list_empty(&cq->wc_list)))
- soft_polled = poll_soft_wc(cq, num_entries, wc);
+ soft_polled = poll_soft_wc(cq, num_entries, wc, false);
for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
diff --git a/drivers/infiniband/hw/qib/qib.h b/drivers/infiniband/hw/qib/qib.h
index f9e1c696..1dda4a2 100644
--- a/drivers/infiniband/hw/qib/qib.h
+++ b/drivers/infiniband/hw/qib/qib.h
@@ -1250,6 +1250,7 @@
#define QIB_BADINTR 0x8000 /* severe interrupt problems */
#define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
#define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
+#define QIB_SHUTDOWN 0x40000 /* device is shutting down */
/*
* values for ppd->lflags (_ib_port_ related flags)
@@ -1448,8 +1449,7 @@
/*
* dma_addr wrappers - all 0's invalid for hw
*/
-dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
- size_t, int);
+int qib_map_page(struct pci_dev *d, struct page *p, dma_addr_t *daddr);
const char *qib_get_unit_name(int unit);
const char *qib_get_card_name(struct rvt_dev_info *rdi);
struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi);
diff --git a/drivers/infiniband/hw/qib/qib_file_ops.c b/drivers/infiniband/hw/qib/qib_file_ops.c
index 9396c18..40efc91 100644
--- a/drivers/infiniband/hw/qib/qib_file_ops.c
+++ b/drivers/infiniband/hw/qib/qib_file_ops.c
@@ -364,6 +364,8 @@
goto done;
}
for (i = 0; i < cnt; i++, vaddr += PAGE_SIZE) {
+ dma_addr_t daddr;
+
for (; ntids--; tid++) {
if (tid == tidcnt)
tid = 0;
@@ -380,12 +382,14 @@
ret = -ENOMEM;
break;
}
+ ret = qib_map_page(dd->pcidev, pagep[i], &daddr);
+ if (ret)
+ break;
+
tidlist[i] = tid + tidoff;
/* we "know" system pages and TID pages are same size */
dd->pageshadow[ctxttid + tid] = pagep[i];
- dd->physshadow[ctxttid + tid] =
- qib_map_page(dd->pcidev, pagep[i], 0, PAGE_SIZE,
- PCI_DMA_FROMDEVICE);
+ dd->physshadow[ctxttid + tid] = daddr;
/*
* don't need atomic or it's overhead
*/
diff --git a/drivers/infiniband/hw/qib/qib_init.c b/drivers/infiniband/hw/qib/qib_init.c
index c5a4c65..7ba7d21 100644
--- a/drivers/infiniband/hw/qib/qib_init.c
+++ b/drivers/infiniband/hw/qib/qib_init.c
@@ -850,6 +850,10 @@
struct qib_pportdata *ppd;
unsigned pidx;
+ if (dd->flags & QIB_SHUTDOWN)
+ return;
+ dd->flags |= QIB_SHUTDOWN;
+
for (pidx = 0; pidx < dd->num_pports; ++pidx) {
ppd = dd->pport + pidx;
@@ -1189,6 +1193,7 @@
static void qib_remove_one(struct pci_dev *);
static int qib_init_one(struct pci_dev *, const struct pci_device_id *);
+static void qib_shutdown_one(struct pci_dev *);
#define DRIVER_LOAD_MSG "Intel " QIB_DRV_NAME " loaded: "
#define PFX QIB_DRV_NAME ": "
@@ -1206,6 +1211,7 @@
.name = QIB_DRV_NAME,
.probe = qib_init_one,
.remove = qib_remove_one,
+ .shutdown = qib_shutdown_one,
.id_table = qib_pci_tbl,
.err_handler = &qib_pci_err_handler,
};
@@ -1556,6 +1562,13 @@
qib_postinit_cleanup(dd);
}
+static void qib_shutdown_one(struct pci_dev *pdev)
+{
+ struct qib_devdata *dd = pci_get_drvdata(pdev);
+
+ qib_shutdown_device(dd);
+}
+
/**
* qib_create_rcvhdrq - create a receive header queue
* @dd: the qlogic_ib device
diff --git a/drivers/infiniband/hw/qib/qib_user_pages.c b/drivers/infiniband/hw/qib/qib_user_pages.c
index ce83ba9..16543d5 100644
--- a/drivers/infiniband/hw/qib/qib_user_pages.c
+++ b/drivers/infiniband/hw/qib/qib_user_pages.c
@@ -99,23 +99,27 @@
*
* I'm sure we won't be so lucky with other iommu's, so FIXME.
*/
-dma_addr_t qib_map_page(struct pci_dev *hwdev, struct page *page,
- unsigned long offset, size_t size, int direction)
+int qib_map_page(struct pci_dev *hwdev, struct page *page, dma_addr_t *daddr)
{
dma_addr_t phys;
- phys = pci_map_page(hwdev, page, offset, size, direction);
+ phys = pci_map_page(hwdev, page, 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
+ if (pci_dma_mapping_error(hwdev, phys))
+ return -ENOMEM;
- if (phys == 0) {
- pci_unmap_page(hwdev, phys, size, direction);
- phys = pci_map_page(hwdev, page, offset, size, direction);
+ if (!phys) {
+ pci_unmap_page(hwdev, phys, PAGE_SIZE, PCI_DMA_FROMDEVICE);
+ phys = pci_map_page(hwdev, page, 0, PAGE_SIZE,
+ PCI_DMA_FROMDEVICE);
+ if (pci_dma_mapping_error(hwdev, phys))
+ return -ENOMEM;
/*
* FIXME: If we get 0 again, we should keep this page,
* map another, then free the 0 page.
*/
}
-
- return phys;
+ *daddr = phys;
+ return 0;
}
/**
diff --git a/drivers/infiniband/sw/rdmavt/cq.c b/drivers/infiniband/sw/rdmavt/cq.c
index 88fa4d4..76a86f8 100644
--- a/drivers/infiniband/sw/rdmavt/cq.c
+++ b/drivers/infiniband/sw/rdmavt/cq.c
@@ -121,17 +121,20 @@
if (cq->notify == IB_CQ_NEXT_COMP ||
(cq->notify == IB_CQ_SOLICITED &&
(solicited || entry->status != IB_WC_SUCCESS))) {
+ struct kthread_worker *worker;
+
/*
* This will cause send_complete() to be called in
* another thread.
*/
- spin_lock(&cq->rdi->n_cqs_lock);
- if (likely(cq->rdi->worker)) {
+ rcu_read_lock();
+ worker = rcu_dereference(cq->rdi->worker);
+ if (likely(worker)) {
cq->notify = RVT_CQ_NONE;
cq->triggered++;
- kthread_queue_work(cq->rdi->worker, &cq->comptask);
+ kthread_queue_work(worker, &cq->comptask);
}
- spin_unlock(&cq->rdi->n_cqs_lock);
+ rcu_read_unlock();
}
spin_unlock_irqrestore(&cq->lock, flags);
@@ -513,7 +516,7 @@
int cpu;
struct kthread_worker *worker;
- if (rdi->worker)
+ if (rcu_access_pointer(rdi->worker))
return 0;
spin_lock_init(&rdi->n_cqs_lock);
@@ -525,7 +528,7 @@
return PTR_ERR(worker);
set_user_nice(worker->task, MIN_NICE);
- rdi->worker = worker;
+ RCU_INIT_POINTER(rdi->worker, worker);
return 0;
}
@@ -537,15 +540,19 @@
{
struct kthread_worker *worker;
- /* block future queuing from send_complete() */
- spin_lock_irq(&rdi->n_cqs_lock);
- worker = rdi->worker;
+ if (!rcu_access_pointer(rdi->worker))
+ return;
+
+ spin_lock(&rdi->n_cqs_lock);
+ worker = rcu_dereference_protected(rdi->worker,
+ lockdep_is_held(&rdi->n_cqs_lock));
if (!worker) {
- spin_unlock_irq(&rdi->n_cqs_lock);
+ spin_unlock(&rdi->n_cqs_lock);
return;
}
- rdi->worker = NULL;
- spin_unlock_irq(&rdi->n_cqs_lock);
+ RCU_INIT_POINTER(rdi->worker, NULL);
+ spin_unlock(&rdi->n_cqs_lock);
+ synchronize_rcu();
kthread_destroy_worker(worker);
}
diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c
index e770c17c..ee3f630 100644
--- a/drivers/infiniband/ulp/isert/ib_isert.c
+++ b/drivers/infiniband/ulp/isert/ib_isert.c
@@ -885,15 +885,9 @@
}
static void
-isert_create_send_desc(struct isert_conn *isert_conn,
- struct isert_cmd *isert_cmd,
- struct iser_tx_desc *tx_desc)
+__isert_create_send_desc(struct isert_device *device,
+ struct iser_tx_desc *tx_desc)
{
- struct isert_device *device = isert_conn->device;
- struct ib_device *ib_dev = device->ib_device;
-
- ib_dma_sync_single_for_cpu(ib_dev, tx_desc->dma_addr,
- ISER_HEADERS_LEN, DMA_TO_DEVICE);
memset(&tx_desc->iser_header, 0, sizeof(struct iser_ctrl));
tx_desc->iser_header.flags = ISCSI_CTRL;
@@ -906,6 +900,20 @@
}
}
+static void
+isert_create_send_desc(struct isert_conn *isert_conn,
+ struct isert_cmd *isert_cmd,
+ struct iser_tx_desc *tx_desc)
+{
+ struct isert_device *device = isert_conn->device;
+ struct ib_device *ib_dev = device->ib_device;
+
+ ib_dma_sync_single_for_cpu(ib_dev, tx_desc->dma_addr,
+ ISER_HEADERS_LEN, DMA_TO_DEVICE);
+
+ __isert_create_send_desc(device, tx_desc);
+}
+
static int
isert_init_tx_hdrs(struct isert_conn *isert_conn,
struct iser_tx_desc *tx_desc)
@@ -993,7 +1001,7 @@
struct iser_tx_desc *tx_desc = &isert_conn->login_tx_desc;
int ret;
- isert_create_send_desc(isert_conn, NULL, tx_desc);
+ __isert_create_send_desc(device, tx_desc);
memcpy(&tx_desc->iscsi_header, &login->rsp[0],
sizeof(struct iscsi_hdr));
@@ -2108,7 +2116,7 @@
sig_attrs->check_mask =
(se_cmd->prot_checks & TARGET_DIF_CHECK_GUARD ? 0xc0 : 0) |
- (se_cmd->prot_checks & TARGET_DIF_CHECK_REFTAG ? 0x30 : 0) |
+ (se_cmd->prot_checks & TARGET_DIF_CHECK_APPTAG ? 0x30 : 0) |
(se_cmd->prot_checks & TARGET_DIF_CHECK_REFTAG ? 0x0f : 0);
return 0;
}
diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c
index 466cef9..53f775c 100644
--- a/drivers/input/joystick/xpad.c
+++ b/drivers/input/joystick/xpad.c
@@ -126,7 +126,7 @@
u8 mapping;
u8 xtype;
} xpad_device[] = {
- { 0x0079, 0x18d4, "GPD Win 2 Controller", 0, XTYPE_XBOX360 },
+ { 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 },
{ 0x044f, 0x0f00, "Thrustmaster Wheel", 0, XTYPE_XBOX },
{ 0x044f, 0x0f03, "Thrustmaster Wheel", 0, XTYPE_XBOX },
{ 0x044f, 0x0f07, "Thrustmaster, Inc. Controller", 0, XTYPE_XBOX },
diff --git a/drivers/input/mouse/elan_i2c.h b/drivers/input/mouse/elan_i2c.h
index 599544c..243e0fa 100644
--- a/drivers/input/mouse/elan_i2c.h
+++ b/drivers/input/mouse/elan_i2c.h
@@ -27,6 +27,8 @@
#define ETP_DISABLE_POWER 0x0001
#define ETP_PRESSURE_OFFSET 25
+#define ETP_CALIBRATE_MAX_LEN 3
+
/* IAP Firmware handling */
#define ETP_PRODUCT_ID_FORMAT_STRING "%d.0"
#define ETP_FW_NAME "elan_i2c_" ETP_PRODUCT_ID_FORMAT_STRING ".bin"
diff --git a/drivers/input/mouse/elan_i2c_core.c b/drivers/input/mouse/elan_i2c_core.c
index 902cf16..ec2401b 100644
--- a/drivers/input/mouse/elan_i2c_core.c
+++ b/drivers/input/mouse/elan_i2c_core.c
@@ -678,7 +678,7 @@
int tries = 20;
int retval;
int error;
- u8 val[3];
+ u8 val[ETP_CALIBRATE_MAX_LEN];
retval = mutex_lock_interruptible(&data->sysfs_mutex);
if (retval)
@@ -1333,6 +1333,7 @@
{ "ELAN060C", 0 },
{ "ELAN0611", 0 },
{ "ELAN0612", 0 },
+ { "ELAN0618", 0 },
{ "ELAN1000", 0 },
{ }
};
diff --git a/drivers/input/mouse/elan_i2c_smbus.c b/drivers/input/mouse/elan_i2c_smbus.c
index cfcb325..c060d27 100644
--- a/drivers/input/mouse/elan_i2c_smbus.c
+++ b/drivers/input/mouse/elan_i2c_smbus.c
@@ -56,7 +56,7 @@
static int elan_smbus_initialize(struct i2c_client *client)
{
u8 check[ETP_SMBUS_HELLOPACKET_LEN] = { 0x55, 0x55, 0x55, 0x55, 0x55 };
- u8 values[ETP_SMBUS_HELLOPACKET_LEN] = { 0, 0, 0, 0, 0 };
+ u8 values[I2C_SMBUS_BLOCK_MAX] = {0};
int len, error;
/* Get hello packet */
@@ -117,12 +117,16 @@
static int elan_smbus_calibrate_result(struct i2c_client *client, u8 *val)
{
int error;
+ u8 buf[I2C_SMBUS_BLOCK_MAX] = {0};
+
+ BUILD_BUG_ON(ETP_CALIBRATE_MAX_LEN > sizeof(buf));
error = i2c_smbus_read_block_data(client,
- ETP_SMBUS_CALIBRATE_QUERY, val);
+ ETP_SMBUS_CALIBRATE_QUERY, buf);
if (error < 0)
return error;
+ memcpy(val, buf, ETP_CALIBRATE_MAX_LEN);
return 0;
}
@@ -472,6 +476,8 @@
{
int len;
+ BUILD_BUG_ON(I2C_SMBUS_BLOCK_MAX > ETP_SMBUS_REPORT_LEN);
+
len = i2c_smbus_read_block_data(client,
ETP_SMBUS_PACKET_QUERY,
&report[ETP_SMBUS_REPORT_OFFSET]);
diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c
index a4aaa74..a250f43 100644
--- a/drivers/input/mouse/elantech.c
+++ b/drivers/input/mouse/elantech.c
@@ -804,7 +804,7 @@
else if (ic_version == 7 && etd->samples[1] == 0x2A)
sanity_check = ((packet[3] & 0x1c) == 0x10);
else
- sanity_check = ((packet[0] & 0x0c) == 0x04 &&
+ sanity_check = ((packet[0] & 0x08) == 0x00 &&
(packet[3] & 0x1c) == 0x10);
if (!sanity_check)
@@ -1177,6 +1177,12 @@
{ }
};
+static const char * const middle_button_pnp_ids[] = {
+ "LEN2131", /* ThinkPad P52 w/ NFC */
+ "LEN2132", /* ThinkPad P52 */
+ NULL
+};
+
/*
* Set the appropriate event bits for the input subsystem
*/
@@ -1196,7 +1202,8 @@
__clear_bit(EV_REL, dev->evbit);
__set_bit(BTN_LEFT, dev->keybit);
- if (dmi_check_system(elantech_dmi_has_middle_button))
+ if (dmi_check_system(elantech_dmi_has_middle_button) ||
+ psmouse_matches_pnp_id(psmouse, middle_button_pnp_ids))
__set_bit(BTN_MIDDLE, dev->keybit);
__set_bit(BTN_RIGHT, dev->keybit);
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index f3a2134..32e9139 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -23,7 +23,7 @@
config IOMMU_IO_PGTABLE_LPAE
bool "ARMv7/v8 Long Descriptor Format"
select IOMMU_IO_PGTABLE
- depends on HAS_DMA && (ARM || ARM64 || (COMPILE_TEST && !GENERIC_ATOMIC64))
+ depends on ARM || ARM64 || (COMPILE_TEST && !GENERIC_ATOMIC64)
help
Enable support for the ARM long descriptor pagetable format.
This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page
@@ -42,7 +42,7 @@
config IOMMU_IO_PGTABLE_ARMV7S
bool "ARMv7/v8 Short Descriptor Format"
select IOMMU_IO_PGTABLE
- depends on HAS_DMA && (ARM || ARM64 || COMPILE_TEST)
+ depends on ARM || ARM64 || COMPILE_TEST
help
Enable support for the ARM Short-descriptor pagetable format.
This supports 32-bit virtual and physical addresses mapped using
@@ -374,7 +374,6 @@
# Note: iommu drivers cannot (yet?) be built as modules
bool "Qualcomm IOMMU Support"
depends on ARCH_QCOM || (COMPILE_TEST && !GENERIC_ATOMIC64)
- depends on HAS_DMA
select IOMMU_API
select IOMMU_IO_PGTABLE_LPAE
select ARM_DMA_USE_IOMMU
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 4a6e052..27fbd71 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -63,7 +63,6 @@
/* IO virtual address start page frame number */
#define IOVA_START_PFN (1)
#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
-#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
/* Reserved IOVA ranges */
#define MSI_RANGE_START (0xfee00000)
@@ -1549,10 +1548,11 @@
if (dma_mask > DMA_BIT_MASK(32))
pfn = alloc_iova_fast(&dma_dom->iovad, pages,
- IOVA_PFN(DMA_BIT_MASK(32)));
+ IOVA_PFN(DMA_BIT_MASK(32)), false);
if (!pfn)
- pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
+ pfn = alloc_iova_fast(&dma_dom->iovad, pages,
+ IOVA_PFN(dma_mask), true);
return (pfn << PAGE_SHIFT);
}
@@ -1790,8 +1790,7 @@
if (!dma_dom->domain.pt_root)
goto free_dma_dom;
- init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
- IOVA_START_PFN, DMA_32BIT_PFN);
+ init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
goto free_dma_dom;
@@ -2698,8 +2697,7 @@
struct pci_dev *pdev = NULL;
struct iova *val;
- init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
- IOVA_START_PFN, DMA_32BIT_PFN);
+ init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
&reserved_rbtree_key);
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 78912ca..a92fd59 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -413,15 +413,6 @@
#define MSI_IOVA_BASE 0x8000000
#define MSI_IOVA_LENGTH 0x100000
-/* Until ACPICA headers cover IORT rev. C */
-#ifndef ACPI_IORT_SMMU_HISILICON_HI161X
-#define ACPI_IORT_SMMU_HISILICON_HI161X 0x1
-#endif
-
-#ifndef ACPI_IORT_SMMU_V3_CAVIUM_CN99XX
-#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2
-#endif
-
static bool disable_bypass;
module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
@@ -2684,7 +2675,7 @@
case ACPI_IORT_SMMU_V3_CAVIUM_CN99XX:
smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY;
break;
- case ACPI_IORT_SMMU_HISILICON_HI161X:
+ case ACPI_IORT_SMMU_V3_HISILICON_HI161X:
smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH;
break;
}
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 970e089..ca3559e 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -122,14 +122,6 @@
QCOM_SMMUV2,
};
-/* Until ACPICA headers cover IORT rev. C */
-#ifndef ACPI_IORT_SMMU_CORELINK_MMU401
-#define ACPI_IORT_SMMU_CORELINK_MMU401 0x4
-#endif
-#ifndef ACPI_IORT_SMMU_CAVIUM_THUNDERX
-#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x5
-#endif
-
struct arm_smmu_s2cr {
struct iommu_group *group;
int count;
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 9d1cebe..25914d3 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -292,18 +292,7 @@
/* ...then finally give it a kicking to make sure it fits */
base_pfn = max_t(unsigned long, base_pfn,
domain->geometry.aperture_start >> order);
- end_pfn = min_t(unsigned long, end_pfn,
- domain->geometry.aperture_end >> order);
}
- /*
- * PCI devices may have larger DMA masks, but still prefer allocating
- * within a 32-bit mask to avoid DAC addressing. Such limitations don't
- * apply to the typical platform device, so for those we may as well
- * leave the cache limit at the top of their range to save an rb_last()
- * traversal on every allocation.
- */
- if (dev && dev_is_pci(dev))
- end_pfn &= DMA_BIT_MASK(32) >> order;
/* start_pfn is always nonzero for an already-initialised domain */
if (iovad->start_pfn) {
@@ -312,16 +301,11 @@
pr_warn("Incompatible range for DMA domain\n");
return -EFAULT;
}
- /*
- * If we have devices with different DMA masks, move the free
- * area cache limit down for the benefit of the smaller one.
- */
- iovad->dma_32bit_pfn = min(end_pfn + 1, iovad->dma_32bit_pfn);
return 0;
}
- init_iova_domain(iovad, 1UL << order, base_pfn, end_pfn);
+ init_iova_domain(iovad, 1UL << order, base_pfn);
if (!dev)
return 0;
@@ -386,10 +370,12 @@
/* Try to get PCI devices a SAC address */
if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
- iova = alloc_iova_fast(iovad, iova_len, DMA_BIT_MASK(32) >> shift);
+ iova = alloc_iova_fast(iovad, iova_len,
+ DMA_BIT_MASK(32) >> shift, false);
if (!iova)
- iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift);
+ iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
+ true);
return (dma_addr_t)iova << shift;
}
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index e8414bc..deafe58b7 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -82,8 +82,6 @@
#define IOVA_START_PFN (1)
#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
-#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
-#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
/* page table handling */
#define LEVEL_STRIDE (9)
@@ -1877,8 +1875,7 @@
struct iova *iova;
int i;
- init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
- DMA_32BIT_PFN);
+ init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN);
lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
&reserved_rbtree_key);
@@ -1937,8 +1934,7 @@
unsigned long sagaw;
int err;
- init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
- DMA_32BIT_PFN);
+ init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN);
err = init_iova_flush_queue(&domain->iovad,
iommu_flush_iova, iova_entry_free);
@@ -3474,11 +3470,12 @@
* from higher range
*/
iova_pfn = alloc_iova_fast(&domain->iovad, nrpages,
- IOVA_PFN(DMA_BIT_MASK(32)));
+ IOVA_PFN(DMA_BIT_MASK(32)), false);
if (iova_pfn)
return iova_pfn;
}
- iova_pfn = alloc_iova_fast(&domain->iovad, nrpages, IOVA_PFN(dma_mask));
+ iova_pfn = alloc_iova_fast(&domain->iovad, nrpages,
+ IOVA_PFN(dma_mask), true);
if (unlikely(!iova_pfn)) {
pr_err("Allocating %ld-page iova for %s failed",
nrpages, dev_name(dev));
@@ -4898,8 +4895,7 @@
{
int adjust_width;
- init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
- DMA_32BIT_PFN);
+ init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN);
domain_reserve_special_ranges(domain);
/* calculate AGAW */
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index c89ec72..e3d73f5 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -903,8 +903,7 @@
/* Full unmap */
iova = 0;
- i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
- while (i != BITS_PER_LONG) {
+ for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
size = 1UL << i;
if (ops->unmap(ops, iova, size) != size)
@@ -921,8 +920,6 @@
return __FAIL(ops);
iova += SZ_16M;
- i++;
- i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
}
free_io_pgtable_ops(ops);
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 8faaaa04..010a254 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -21,6 +21,7 @@
#define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
#include <linux/atomic.h>
+#include <linux/bitops.h>
#include <linux/iommu.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
@@ -32,7 +33,7 @@
#include "io-pgtable.h"
-#define ARM_LPAE_MAX_ADDR_BITS 48
+#define ARM_LPAE_MAX_ADDR_BITS 52
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
#define ARM_LPAE_MAX_LEVELS 4
@@ -86,6 +87,8 @@
#define ARM_LPAE_PTE_TYPE_TABLE 3
#define ARM_LPAE_PTE_TYPE_PAGE 3
+#define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
+
#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
#define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
#define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
@@ -159,6 +162,7 @@
#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
+#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
@@ -170,9 +174,7 @@
#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
/* IOPTE accessors */
-#define iopte_deref(pte,d) \
- (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \
- & ~(ARM_LPAE_GRANULE(d) - 1ULL)))
+#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
#define iopte_type(pte,l) \
(((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
@@ -184,12 +186,6 @@
(iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
(iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
-#define iopte_to_pfn(pte,d) \
- (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift)
-
-#define pfn_to_iopte(pfn,d) \
- (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1))
-
struct arm_lpae_io_pgtable {
struct io_pgtable iop;
@@ -203,6 +199,27 @@
typedef u64 arm_lpae_iopte;
+static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
+ struct arm_lpae_io_pgtable *data)
+{
+ arm_lpae_iopte pte = paddr;
+
+ /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
+ return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
+}
+
+static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
+ struct arm_lpae_io_pgtable *data)
+{
+ u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
+
+ if (data->pg_shift < 16)
+ return paddr;
+
+ /* Rotate the packed high-order bits back to the top */
+ return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
+}
+
static bool selftest_running = false;
static dma_addr_t __arm_lpae_dma_addr(void *pages)
@@ -214,12 +231,17 @@
struct io_pgtable_cfg *cfg)
{
struct device *dev = cfg->iommu_dev;
+ int order = get_order(size);
+ struct page *p;
dma_addr_t dma;
- void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO);
+ void *pages;
- if (!pages)
+ VM_BUG_ON((gfp & __GFP_HIGHMEM));
+ p = alloc_pages_node(dev_to_node(dev), gfp | __GFP_ZERO, order);
+ if (!p)
return NULL;
+ pages = page_address(p);
if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA)) {
dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
if (dma_mapping_error(dev, dma))
@@ -239,7 +261,7 @@
dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
out_free:
- free_pages_exact(pages, size);
+ __free_pages(p, order);
return NULL;
}
@@ -249,7 +271,7 @@
if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
size, DMA_TO_DEVICE);
- free_pages_exact(pages, size);
+ free_pages((unsigned long)pages, get_order(size));
}
static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep,
@@ -287,7 +309,7 @@
pte |= ARM_LPAE_PTE_TYPE_BLOCK;
pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
- pte |= pfn_to_iopte(paddr >> data->pg_shift, data);
+ pte |= paddr_to_iopte(paddr, data);
__arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
}
@@ -528,7 +550,7 @@
if (size == split_sz)
unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
- blk_paddr = iopte_to_pfn(blk_pte, data) << data->pg_shift;
+ blk_paddr = iopte_to_paddr(blk_pte, data);
pte = iopte_prot(blk_pte);
for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
@@ -652,12 +674,13 @@
found_translation:
iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
- return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova;
+ return iopte_to_paddr(pte, data) | iova;
}
static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
{
- unsigned long granule;
+ unsigned long granule, page_sizes;
+ unsigned int max_addr_bits = 48;
/*
* We need to restrict the supported page sizes to match the
@@ -677,17 +700,24 @@
switch (granule) {
case SZ_4K:
- cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
+ page_sizes = (SZ_4K | SZ_2M | SZ_1G);
break;
case SZ_16K:
- cfg->pgsize_bitmap &= (SZ_16K | SZ_32M);
+ page_sizes = (SZ_16K | SZ_32M);
break;
case SZ_64K:
- cfg->pgsize_bitmap &= (SZ_64K | SZ_512M);
+ max_addr_bits = 52;
+ page_sizes = (SZ_64K | SZ_512M);
+ if (cfg->oas > 48)
+ page_sizes |= 1ULL << 42; /* 4TB */
break;
default:
- cfg->pgsize_bitmap = 0;
+ page_sizes = 0;
}
+
+ cfg->pgsize_bitmap &= page_sizes;
+ cfg->ias = min(cfg->ias, max_addr_bits);
+ cfg->oas = min(cfg->oas, max_addr_bits);
}
static struct arm_lpae_io_pgtable *
@@ -784,6 +814,9 @@
case 48:
reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
break;
+ case 52:
+ reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_IPS_SHIFT);
+ break;
default:
goto out_free_data;
}
@@ -891,6 +924,9 @@
case 48:
reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
break;
+ case 52:
+ reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT);
+ break;
default:
goto out_free_data;
}
@@ -1089,8 +1125,7 @@
/* Full unmap */
iova = 0;
- j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
- while (j != BITS_PER_LONG) {
+ for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
size = 1UL << j;
if (ops->unmap(ops, iova, size) != size)
@@ -1107,8 +1142,6 @@
return __FAIL(ops, i);
iova += SZ_1G;
- j++;
- j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
}
free_io_pgtable_ops(ops);
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index d2aa2320..63b3756 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -116,9 +116,11 @@
static int __init iommu_set_def_domain_type(char *str)
{
bool pt;
+ int ret;
- if (!str || strtobool(str, &pt))
- return -EINVAL;
+ ret = kstrtobool(str, &pt);
+ if (ret)
+ return ret;
iommu_def_domain_type = pt ? IOMMU_DOMAIN_IDENTITY : IOMMU_DOMAIN_DMA;
return 0;
@@ -322,7 +324,6 @@
/**
* iommu_group_alloc - Allocate a new group
- * @name: Optional name to associate with group, visible in sysfs
*
* This function is called by an iommu driver to allocate a new iommu
* group. The iommu group represents the minimum granularity of the iommu.
diff --git a/drivers/iommu/iova.c b/drivers/iommu/iova.c
index b309000..466aaa8 100644
--- a/drivers/iommu/iova.c
+++ b/drivers/iommu/iova.c
@@ -24,6 +24,9 @@
#include <linux/bitops.h>
#include <linux/cpu.h>
+/* The anchor node sits above the top of the usable address space */
+#define IOVA_ANCHOR ~0UL
+
static bool iova_rcache_insert(struct iova_domain *iovad,
unsigned long pfn,
unsigned long size);
@@ -37,7 +40,7 @@
void
init_iova_domain(struct iova_domain *iovad, unsigned long granule,
- unsigned long start_pfn, unsigned long pfn_32bit)
+ unsigned long start_pfn)
{
/*
* IOVA granularity will normally be equal to the smallest
@@ -48,12 +51,16 @@
spin_lock_init(&iovad->iova_rbtree_lock);
iovad->rbroot = RB_ROOT;
- iovad->cached32_node = NULL;
+ iovad->cached_node = &iovad->anchor.node;
+ iovad->cached32_node = &iovad->anchor.node;
iovad->granule = granule;
iovad->start_pfn = start_pfn;
- iovad->dma_32bit_pfn = pfn_32bit + 1;
+ iovad->dma_32bit_pfn = 1UL << (32 - iova_shift(iovad));
iovad->flush_cb = NULL;
iovad->fq = NULL;
+ iovad->anchor.pfn_lo = iovad->anchor.pfn_hi = IOVA_ANCHOR;
+ rb_link_node(&iovad->anchor.node, NULL, &iovad->rbroot.rb_node);
+ rb_insert_color(&iovad->anchor.node, &iovad->rbroot);
init_iova_rcaches(iovad);
}
EXPORT_SYMBOL_GPL(init_iova_domain);
@@ -108,50 +115,36 @@
EXPORT_SYMBOL_GPL(init_iova_flush_queue);
static struct rb_node *
-__get_cached_rbnode(struct iova_domain *iovad, unsigned long *limit_pfn)
+__get_cached_rbnode(struct iova_domain *iovad, unsigned long limit_pfn)
{
- if ((*limit_pfn > iovad->dma_32bit_pfn) ||
- (iovad->cached32_node == NULL))
- return rb_last(&iovad->rbroot);
- else {
- struct rb_node *prev_node = rb_prev(iovad->cached32_node);
- struct iova *curr_iova =
- rb_entry(iovad->cached32_node, struct iova, node);
- *limit_pfn = curr_iova->pfn_lo;
- return prev_node;
- }
+ if (limit_pfn <= iovad->dma_32bit_pfn)
+ return iovad->cached32_node;
+
+ return iovad->cached_node;
}
static void
-__cached_rbnode_insert_update(struct iova_domain *iovad,
- unsigned long limit_pfn, struct iova *new)
+__cached_rbnode_insert_update(struct iova_domain *iovad, struct iova *new)
{
- if (limit_pfn != iovad->dma_32bit_pfn)
- return;
- iovad->cached32_node = &new->node;
+ if (new->pfn_hi < iovad->dma_32bit_pfn)
+ iovad->cached32_node = &new->node;
+ else
+ iovad->cached_node = &new->node;
}
static void
__cached_rbnode_delete_update(struct iova_domain *iovad, struct iova *free)
{
struct iova *cached_iova;
- struct rb_node *curr;
- if (!iovad->cached32_node)
- return;
- curr = iovad->cached32_node;
- cached_iova = rb_entry(curr, struct iova, node);
+ cached_iova = rb_entry(iovad->cached32_node, struct iova, node);
+ if (free->pfn_hi < iovad->dma_32bit_pfn &&
+ free->pfn_lo >= cached_iova->pfn_lo)
+ iovad->cached32_node = rb_next(&free->node);
- if (free->pfn_lo >= cached_iova->pfn_lo) {
- struct rb_node *node = rb_next(&free->node);
- struct iova *iova = rb_entry(node, struct iova, node);
-
- /* only cache if it's below 32bit pfn */
- if (node && iova->pfn_lo < iovad->dma_32bit_pfn)
- iovad->cached32_node = node;
- else
- iovad->cached32_node = NULL;
- }
+ cached_iova = rb_entry(iovad->cached_node, struct iova, node);
+ if (free->pfn_lo >= cached_iova->pfn_lo)
+ iovad->cached_node = rb_next(&free->node);
}
/* Insert the iova into domain rbtree by holding writer lock */
@@ -182,63 +175,43 @@
rb_insert_color(&iova->node, root);
}
-/*
- * Computes the padding size required, to make the start address
- * naturally aligned on the power-of-two order of its size
- */
-static unsigned int
-iova_get_pad_size(unsigned int size, unsigned int limit_pfn)
-{
- return (limit_pfn - size) & (__roundup_pow_of_two(size) - 1);
-}
-
static int __alloc_and_insert_iova_range(struct iova_domain *iovad,
unsigned long size, unsigned long limit_pfn,
struct iova *new, bool size_aligned)
{
- struct rb_node *prev, *curr = NULL;
+ struct rb_node *curr, *prev;
+ struct iova *curr_iova;
unsigned long flags;
- unsigned long saved_pfn;
- unsigned int pad_size = 0;
+ unsigned long new_pfn;
+ unsigned long align_mask = ~0UL;
+
+ if (size_aligned)
+ align_mask <<= fls_long(size - 1);
/* Walk the tree backwards */
spin_lock_irqsave(&iovad->iova_rbtree_lock, flags);
- saved_pfn = limit_pfn;
- curr = __get_cached_rbnode(iovad, &limit_pfn);
- prev = curr;
- while (curr) {
- struct iova *curr_iova = rb_entry(curr, struct iova, node);
-
- if (limit_pfn <= curr_iova->pfn_lo) {
- goto move_left;
- } else if (limit_pfn > curr_iova->pfn_hi) {
- if (size_aligned)
- pad_size = iova_get_pad_size(size, limit_pfn);
- if ((curr_iova->pfn_hi + size + pad_size) < limit_pfn)
- break; /* found a free slot */
- }
- limit_pfn = curr_iova->pfn_lo;
-move_left:
+ curr = __get_cached_rbnode(iovad, limit_pfn);
+ curr_iova = rb_entry(curr, struct iova, node);
+ do {
+ limit_pfn = min(limit_pfn, curr_iova->pfn_lo);
+ new_pfn = (limit_pfn - size) & align_mask;
prev = curr;
curr = rb_prev(curr);
- }
+ curr_iova = rb_entry(curr, struct iova, node);
+ } while (curr && new_pfn <= curr_iova->pfn_hi);
- if (!curr) {
- if (size_aligned)
- pad_size = iova_get_pad_size(size, limit_pfn);
- if ((iovad->start_pfn + size + pad_size) > limit_pfn) {
- spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags);
- return -ENOMEM;
- }
+ if (limit_pfn < size || new_pfn < iovad->start_pfn) {
+ spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags);
+ return -ENOMEM;
}
/* pfn_lo will point to size aligned address if size_aligned is set */
- new->pfn_lo = limit_pfn - (size + pad_size);
+ new->pfn_lo = new_pfn;
new->pfn_hi = new->pfn_lo + size - 1;
/* If we have 'prev', it's a valid place to start the insertion. */
iova_insert_rbtree(&iovad->rbroot, new, prev);
- __cached_rbnode_insert_update(iovad, saved_pfn, new);
+ __cached_rbnode_insert_update(iovad, new);
spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags);
@@ -258,7 +231,8 @@
void free_iova_mem(struct iova *iova)
{
- kmem_cache_free(iova_cache, iova);
+ if (iova->pfn_lo != IOVA_ANCHOR)
+ kmem_cache_free(iova_cache, iova);
}
EXPORT_SYMBOL(free_iova_mem);
@@ -342,15 +316,12 @@
while (node) {
struct iova *iova = rb_entry(node, struct iova, node);
- /* If pfn falls within iova's range, return iova */
- if ((pfn >= iova->pfn_lo) && (pfn <= iova->pfn_hi)) {
- return iova;
- }
-
if (pfn < iova->pfn_lo)
node = node->rb_left;
- else if (pfn > iova->pfn_lo)
+ else if (pfn > iova->pfn_hi)
node = node->rb_right;
+ else
+ return iova; /* pfn falls within iova's range */
}
return NULL;
@@ -424,18 +395,19 @@
* @iovad: - iova domain in question
* @size: - size of page frames to allocate
* @limit_pfn: - max limit address
+ * @flush_rcache: - set to flush rcache on regular allocation failure
* This function tries to satisfy an iova allocation from the rcache,
- * and falls back to regular allocation on failure.
+ * and falls back to regular allocation on failure. If regular allocation
+ * fails too and the flush_rcache flag is set then the rcache will be flushed.
*/
unsigned long
alloc_iova_fast(struct iova_domain *iovad, unsigned long size,
- unsigned long limit_pfn)
+ unsigned long limit_pfn, bool flush_rcache)
{
- bool flushed_rcache = false;
unsigned long iova_pfn;
struct iova *new_iova;
- iova_pfn = iova_rcache_get(iovad, size, limit_pfn);
+ iova_pfn = iova_rcache_get(iovad, size, limit_pfn + 1);
if (iova_pfn)
return iova_pfn;
@@ -444,11 +416,11 @@
if (!new_iova) {
unsigned int cpu;
- if (flushed_rcache)
+ if (!flush_rcache)
return 0;
/* Try replenishing IOVAs by flushing rcache. */
- flushed_rcache = true;
+ flush_rcache = false;
for_each_online_cpu(cpu)
free_cpu_cached_iovas(cpu, iovad);
goto retry;
@@ -610,21 +582,12 @@
*/
void put_iova_domain(struct iova_domain *iovad)
{
- struct rb_node *node;
- unsigned long flags;
+ struct iova *iova, *tmp;
free_iova_flush_queue(iovad);
free_iova_rcaches(iovad);
- spin_lock_irqsave(&iovad->iova_rbtree_lock, flags);
- node = rb_first(&iovad->rbroot);
- while (node) {
- struct iova *iova = rb_entry(node, struct iova, node);
-
- rb_erase(node, &iovad->rbroot);
+ rbtree_postorder_for_each_entry_safe(iova, tmp, &iovad->rbroot, node)
free_iova_mem(iova);
- node = rb_first(&iovad->rbroot);
- }
- spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags);
}
EXPORT_SYMBOL_GPL(put_iova_domain);
@@ -693,6 +656,10 @@
struct iova *iova;
unsigned int overlap = 0;
+ /* Don't allow nonsensical pfns */
+ if (WARN_ON((pfn_hi | pfn_lo) > (ULLONG_MAX >> iova_shift(iovad))))
+ return NULL;
+
spin_lock_irqsave(&iovad->iova_rbtree_lock, flags);
for (node = rb_first(&iovad->rbroot); node; node = rb_next(node)) {
if (__is_range_overlap(node, pfn_lo, pfn_hi)) {
@@ -736,6 +703,9 @@
struct iova *iova = rb_entry(node, struct iova, node);
struct iova *new_iova;
+ if (iova->pfn_lo == IOVA_ANCHOR)
+ continue;
+
new_iova = reserve_iova(to, iova->pfn_lo, iova->pfn_hi);
if (!new_iova)
printk(KERN_ERR "Reserve iova range %lx@%lx failed\n",
@@ -853,12 +823,21 @@
static unsigned long iova_magazine_pop(struct iova_magazine *mag,
unsigned long limit_pfn)
{
+ int i;
+ unsigned long pfn;
+
BUG_ON(iova_magazine_empty(mag));
- if (mag->pfns[mag->size - 1] >= limit_pfn)
- return 0;
+ /* Only fall back to the rbtree if we have no suitable pfns at all */
+ for (i = mag->size - 1; mag->pfns[i] > limit_pfn; i--)
+ if (i == 0)
+ return 0;
- return mag->pfns[--mag->size];
+ /* Swap it to pop it */
+ pfn = mag->pfns[i];
+ mag->pfns[i] = mag->pfns[--mag->size];
+
+ return pfn;
}
static void iova_magazine_push(struct iova_magazine *mag, unsigned long pfn)
@@ -1009,27 +988,7 @@
if (log_size >= IOVA_RANGE_CACHE_MAX_SIZE)
return 0;
- return __iova_rcache_get(&iovad->rcaches[log_size], limit_pfn);
-}
-
-/*
- * Free a cpu's rcache.
- */
-static void free_cpu_iova_rcache(unsigned int cpu, struct iova_domain *iovad,
- struct iova_rcache *rcache)
-{
- struct iova_cpu_rcache *cpu_rcache = per_cpu_ptr(rcache->cpu_rcaches, cpu);
- unsigned long flags;
-
- spin_lock_irqsave(&cpu_rcache->lock, flags);
-
- iova_magazine_free_pfns(cpu_rcache->loaded, iovad);
- iova_magazine_free(cpu_rcache->loaded);
-
- iova_magazine_free_pfns(cpu_rcache->prev, iovad);
- iova_magazine_free(cpu_rcache->prev);
-
- spin_unlock_irqrestore(&cpu_rcache->lock, flags);
+ return __iova_rcache_get(&iovad->rcaches[log_size], limit_pfn - size);
}
/*
@@ -1038,21 +997,20 @@
static void free_iova_rcaches(struct iova_domain *iovad)
{
struct iova_rcache *rcache;
- unsigned long flags;
+ struct iova_cpu_rcache *cpu_rcache;
unsigned int cpu;
int i, j;
for (i = 0; i < IOVA_RANGE_CACHE_MAX_SIZE; ++i) {
rcache = &iovad->rcaches[i];
- for_each_possible_cpu(cpu)
- free_cpu_iova_rcache(cpu, iovad, rcache);
- spin_lock_irqsave(&rcache->lock, flags);
- free_percpu(rcache->cpu_rcaches);
- for (j = 0; j < rcache->depot_size; ++j) {
- iova_magazine_free_pfns(rcache->depot[j], iovad);
- iova_magazine_free(rcache->depot[j]);
+ for_each_possible_cpu(cpu) {
+ cpu_rcache = per_cpu_ptr(rcache->cpu_rcaches, cpu);
+ iova_magazine_free(cpu_rcache->loaded);
+ iova_magazine_free(cpu_rcache->prev);
}
- spin_unlock_irqrestore(&rcache->lock, flags);
+ free_percpu(rcache->cpu_rcaches);
+ for (j = 0; j < rcache->depot_size; ++j)
+ iova_magazine_free(rcache->depot[j]);
}
}
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index e2ea4ab..c564443 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2225,7 +2225,14 @@
cpu_mask = cpumask_of_node(its_dev->its->numa_node);
/* Bind the LPI to the first possible CPU */
- cpu = cpumask_first(cpu_mask);
+ cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
+ if (cpu >= nr_cpu_ids) {
+ if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
+ return;
+
+ cpu = cpumask_first(cpu_online_mask);
+ }
+
its_dev->event_map.col_map[event] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c
index 33834db..38a2ac2 100644
--- a/drivers/md/dm-raid.c
+++ b/drivers/md/dm-raid.c
@@ -3637,8 +3637,11 @@
{
struct raid_set *rs = ti->private;
- if (!test_and_set_bit(RT_FLAG_RS_SUSPENDED, &rs->runtime_flags))
+ if (!test_and_set_bit(RT_FLAG_RS_SUSPENDED, &rs->runtime_flags)) {
+ mddev_lock_nointr(&rs->md);
mddev_suspend(&rs->md);
+ mddev_unlock(&rs->md);
+ }
rs->md.ro = 1;
}
@@ -3898,8 +3901,11 @@
if (!(rs->ctr_flags & RESUME_STAY_FROZEN_FLAGS))
clear_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
- if (test_and_clear_bit(RT_FLAG_RS_SUSPENDED, &rs->runtime_flags))
+ if (test_and_clear_bit(RT_FLAG_RS_SUSPENDED, &rs->runtime_flags)) {
+ mddev_lock_nointr(mddev);
mddev_resume(mddev);
+ mddev_unlock(mddev);
+ }
}
static struct target_type raid_target = {
diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c
index b0f68b6..e79144c 100644
--- a/drivers/md/dm-table.c
+++ b/drivers/md/dm-table.c
@@ -548,14 +548,14 @@
* On the other hand, dm-switch needs to process bulk data using messages and
* excessive use of GFP_NOIO could cause trouble.
*/
-static char **realloc_argv(unsigned *array_size, char **old_argv)
+static char **realloc_argv(unsigned *size, char **old_argv)
{
char **argv;
unsigned new_size;
gfp_t gfp;
- if (*array_size) {
- new_size = *array_size * 2;
+ if (*size) {
+ new_size = *size * 2;
gfp = GFP_KERNEL;
} else {
new_size = 8;
@@ -563,8 +563,8 @@
}
argv = kmalloc(new_size * sizeof(*argv), gfp);
if (argv) {
- memcpy(argv, old_argv, *array_size * sizeof(*argv));
- *array_size = new_size;
+ memcpy(argv, old_argv, *size * sizeof(*argv));
+ *size = new_size;
}
kfree(old_argv);
@@ -884,9 +884,7 @@
static int device_supports_dax(struct dm_target *ti, struct dm_dev *dev,
sector_t start, sector_t len, void *data)
{
- struct request_queue *q = bdev_get_queue(dev->bdev);
-
- return q && blk_queue_dax(q);
+ return bdev_dax_supported(dev->bdev, PAGE_SIZE);
}
static bool dm_table_supports_dax(struct dm_table *t)
@@ -1842,6 +1840,11 @@
}
blk_queue_write_cache(q, wc, fua);
+ if (dm_table_supports_dax(t))
+ queue_flag_set_unlocked(QUEUE_FLAG_DAX, q);
+ else
+ queue_flag_clear_unlocked(QUEUE_FLAG_DAX, q);
+
if (dm_table_supports_dax_write_cache(t))
dax_write_cache(t->md->dax_dev, true);
diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c
index 02e42ba..72ae5dc 100644
--- a/drivers/md/dm-thin.c
+++ b/drivers/md/dm-thin.c
@@ -1380,6 +1380,8 @@
static void set_pool_mode(struct pool *pool, enum pool_mode new_mode);
+static void requeue_bios(struct pool *pool);
+
static void check_for_space(struct pool *pool)
{
int r;
@@ -1392,8 +1394,10 @@
if (r)
return;
- if (nr_free)
+ if (nr_free) {
set_pool_mode(pool, PM_WRITE);
+ requeue_bios(pool);
+ }
}
/*
@@ -1470,7 +1474,10 @@
r = dm_pool_alloc_data_block(pool->pmd, result);
if (r) {
- metadata_operation_failed(pool, "dm_pool_alloc_data_block", r);
+ if (r == -ENOSPC)
+ set_pool_mode(pool, PM_OUT_OF_DATA_SPACE);
+ else
+ metadata_operation_failed(pool, "dm_pool_alloc_data_block", r);
return r;
}
diff --git a/drivers/md/dm-zoned-target.c b/drivers/md/dm-zoned-target.c
index 6d7bda6..ba6b0a9 100644
--- a/drivers/md/dm-zoned-target.c
+++ b/drivers/md/dm-zoned-target.c
@@ -788,7 +788,7 @@
/* Chunk BIO work */
mutex_init(&dmz->chunk_lock);
- INIT_RADIX_TREE(&dmz->chunk_rxtree, GFP_KERNEL);
+ INIT_RADIX_TREE(&dmz->chunk_rxtree, GFP_NOIO);
dmz->chunk_wq = alloc_workqueue("dmz_cwq_%s", WQ_MEM_RECLAIM | WQ_UNBOUND,
0, dev->name);
if (!dmz->chunk_wq) {
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index 1dfc855a..24ec6e0 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -961,8 +961,7 @@
if (len < 1)
goto out;
nr_pages = min(len, nr_pages);
- if (ti->type->direct_access)
- ret = ti->type->direct_access(ti, pgoff, nr_pages, kaddr, pfn);
+ ret = ti->type->direct_access(ti, pgoff, nr_pages, kaddr, pfn);
out:
dm_put_live_table(md, srcu_idx);
@@ -2050,9 +2049,6 @@
*/
bioset_free(md->queue->bio_split);
md->queue->bio_split = NULL;
-
- if (type == DM_TYPE_DAX_BIO_BASED)
- queue_flag_set_unlocked(QUEUE_FLAG_DAX, md->queue);
break;
case DM_TYPE_NONE:
WARN_ON_ONCE(true);
diff --git a/drivers/md/md-cluster.c b/drivers/md/md-cluster.c
index 03082e1..72ce0bc 100644
--- a/drivers/md/md-cluster.c
+++ b/drivers/md/md-cluster.c
@@ -442,10 +442,11 @@
static void remove_suspend_info(struct mddev *mddev, int slot)
{
struct md_cluster_info *cinfo = mddev->cluster_info;
+ mddev->pers->quiesce(mddev, 1);
spin_lock_irq(&cinfo->suspend_lock);
__remove_suspend_info(cinfo, slot);
spin_unlock_irq(&cinfo->suspend_lock);
- mddev->pers->quiesce(mddev, 2);
+ mddev->pers->quiesce(mddev, 0);
}
@@ -492,13 +493,12 @@
s->lo = lo;
s->hi = hi;
mddev->pers->quiesce(mddev, 1);
- mddev->pers->quiesce(mddev, 0);
spin_lock_irq(&cinfo->suspend_lock);
/* Remove existing entry (if exists) before adding */
__remove_suspend_info(cinfo, slot);
list_add(&s->list, &cinfo->suspend_list);
spin_unlock_irq(&cinfo->suspend_lock);
- mddev->pers->quiesce(mddev, 2);
+ mddev->pers->quiesce(mddev, 0);
}
static void process_add_new_disk(struct mddev *mddev, struct cluster_msg *cmsg)
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 24e64b0..11a67ea 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -266,16 +266,31 @@
* call has finished, the bio has been linked into some internal structure
* and so is visible to ->quiesce(), so we don't need the refcount any more.
*/
+static bool is_suspended(struct mddev *mddev, struct bio *bio)
+{
+ if (mddev->suspended)
+ return true;
+ if (bio_data_dir(bio) != WRITE)
+ return false;
+ if (mddev->suspend_lo >= mddev->suspend_hi)
+ return false;
+ if (bio->bi_iter.bi_sector >= mddev->suspend_hi)
+ return false;
+ if (bio_end_sector(bio) < mddev->suspend_lo)
+ return false;
+ return true;
+}
+
void md_handle_request(struct mddev *mddev, struct bio *bio)
{
check_suspended:
rcu_read_lock();
- if (mddev->suspended) {
+ if (is_suspended(mddev, bio)) {
DEFINE_WAIT(__wait);
for (;;) {
prepare_to_wait(&mddev->sb_wait, &__wait,
TASK_UNINTERRUPTIBLE);
- if (!mddev->suspended)
+ if (!is_suspended(mddev, bio))
break;
rcu_read_unlock();
schedule();
@@ -344,12 +359,17 @@
void mddev_suspend(struct mddev *mddev)
{
WARN_ON_ONCE(mddev->thread && current == mddev->thread->tsk);
+ lockdep_assert_held(&mddev->reconfig_mutex);
if (mddev->suspended++)
return;
synchronize_rcu();
wake_up(&mddev->sb_wait);
+ set_bit(MD_ALLOW_SB_UPDATE, &mddev->flags);
+ smp_mb__after_atomic();
wait_event(mddev->sb_wait, atomic_read(&mddev->active_io) == 0);
mddev->pers->quiesce(mddev, 1);
+ clear_bit_unlock(MD_ALLOW_SB_UPDATE, &mddev->flags);
+ wait_event(mddev->sb_wait, !test_bit(MD_UPDATING_SB, &mddev->flags));
del_timer_sync(&mddev->safemode_timer);
}
@@ -357,6 +377,7 @@
void mddev_resume(struct mddev *mddev)
{
+ lockdep_assert_held(&mddev->reconfig_mutex);
if (--mddev->suspended)
return;
wake_up(&mddev->sb_wait);
@@ -663,6 +684,7 @@
*/
spin_lock(&pers_lock);
md_wakeup_thread(mddev->thread);
+ wake_up(&mddev->sb_wait);
spin_unlock(&pers_lock);
}
EXPORT_SYMBOL_GPL(mddev_unlock);
@@ -2823,7 +2845,8 @@
err = 0;
}
} else if (cmd_match(buf, "re-add")) {
- if (test_bit(Faulty, &rdev->flags) && (rdev->raid_disk == -1)) {
+ if (test_bit(Faulty, &rdev->flags) && (rdev->raid_disk == -1) &&
+ rdev->saved_raid_disk >= 0) {
/* clear_bit is performed _after_ all the devices
* have their local Faulty bit cleared. If any writes
* happen in the meantime in the local node, they
@@ -4827,7 +4850,7 @@
static ssize_t
suspend_lo_store(struct mddev *mddev, const char *buf, size_t len)
{
- unsigned long long old, new;
+ unsigned long long new;
int err;
err = kstrtoull(buf, 10, &new);
@@ -4843,16 +4866,10 @@
if (mddev->pers == NULL ||
mddev->pers->quiesce == NULL)
goto unlock;
- old = mddev->suspend_lo;
+ mddev_suspend(mddev);
mddev->suspend_lo = new;
- if (new >= old)
- /* Shrinking suspended region */
- mddev->pers->quiesce(mddev, 2);
- else {
- /* Expanding suspended region - need to wait */
- mddev->pers->quiesce(mddev, 1);
- mddev->pers->quiesce(mddev, 0);
- }
+ mddev_resume(mddev);
+
err = 0;
unlock:
mddev_unlock(mddev);
@@ -4870,7 +4887,7 @@
static ssize_t
suspend_hi_store(struct mddev *mddev, const char *buf, size_t len)
{
- unsigned long long old, new;
+ unsigned long long new;
int err;
err = kstrtoull(buf, 10, &new);
@@ -4883,19 +4900,13 @@
if (err)
return err;
err = -EINVAL;
- if (mddev->pers == NULL ||
- mddev->pers->quiesce == NULL)
+ if (mddev->pers == NULL)
goto unlock;
- old = mddev->suspend_hi;
+
+ mddev_suspend(mddev);
mddev->suspend_hi = new;
- if (new <= old)
- /* Shrinking suspended region */
- mddev->pers->quiesce(mddev, 2);
- else {
- /* Expanding suspended region - need to wait */
- mddev->pers->quiesce(mddev, 1);
- mddev->pers->quiesce(mddev, 0);
- }
+ mddev_resume(mddev);
+
err = 0;
unlock:
mddev_unlock(mddev);
@@ -6641,22 +6652,26 @@
return -ENOENT; /* cannot remove what isn't there */
err = 0;
if (mddev->pers) {
- mddev->pers->quiesce(mddev, 1);
if (fd >= 0) {
struct bitmap *bitmap;
bitmap = bitmap_create(mddev, -1);
+ mddev_suspend(mddev);
if (!IS_ERR(bitmap)) {
mddev->bitmap = bitmap;
err = bitmap_load(mddev);
} else
err = PTR_ERR(bitmap);
- }
- if (fd < 0 || err) {
+ if (err) {
+ bitmap_destroy(mddev);
+ fd = -1;
+ }
+ mddev_resume(mddev);
+ } else if (fd < 0) {
+ mddev_suspend(mddev);
bitmap_destroy(mddev);
- fd = -1; /* make sure to put the file */
+ mddev_resume(mddev);
}
- mddev->pers->quiesce(mddev, 0);
}
if (fd < 0) {
struct file *f = mddev->bitmap_info.file;
@@ -6940,8 +6955,8 @@
mddev->bitmap_info.default_offset;
mddev->bitmap_info.space =
mddev->bitmap_info.default_space;
- mddev->pers->quiesce(mddev, 1);
bitmap = bitmap_create(mddev, -1);
+ mddev_suspend(mddev);
if (!IS_ERR(bitmap)) {
mddev->bitmap = bitmap;
rv = bitmap_load(mddev);
@@ -6949,7 +6964,7 @@
rv = PTR_ERR(bitmap);
if (rv)
bitmap_destroy(mddev);
- mddev->pers->quiesce(mddev, 0);
+ mddev_resume(mddev);
} else {
/* remove the bitmap */
if (!mddev->bitmap) {
@@ -6972,9 +6987,9 @@
mddev->bitmap_info.nodes = 0;
md_cluster_ops->leave(mddev);
}
- mddev->pers->quiesce(mddev, 1);
+ mddev_suspend(mddev);
bitmap_destroy(mddev);
- mddev->pers->quiesce(mddev, 0);
+ mddev_resume(mddev);
mddev->bitmap_info.offset = 0;
}
}
@@ -8594,6 +8609,7 @@
if (mddev->pers->hot_remove_disk(
mddev, rdev) == 0) {
sysfs_unlink_rdev(mddev, rdev);
+ rdev->saved_raid_disk = rdev->raid_disk;
rdev->raid_disk = -1;
removed++;
}
@@ -8856,6 +8872,16 @@
unlock:
wake_up(&mddev->sb_wait);
mddev_unlock(mddev);
+ } else if (test_bit(MD_ALLOW_SB_UPDATE, &mddev->flags) && mddev->sb_flags) {
+ /* Write superblock - thread that called mddev_suspend()
+ * holds reconfig_mutex for us.
+ */
+ set_bit(MD_UPDATING_SB, &mddev->flags);
+ smp_mb__after_atomic();
+ if (test_bit(MD_ALLOW_SB_UPDATE, &mddev->flags))
+ md_update_sb(mddev, 0);
+ clear_bit_unlock(MD_UPDATING_SB, &mddev->flags);
+ wake_up(&mddev->sb_wait);
}
}
EXPORT_SYMBOL(md_check_recovery);
diff --git a/drivers/md/md.h b/drivers/md/md.h
index 9b0a896..11696ab 100644
--- a/drivers/md/md.h
+++ b/drivers/md/md.h
@@ -237,6 +237,12 @@
*/
MD_HAS_PPL, /* The raid array has PPL feature set */
MD_HAS_MULTIPLE_PPLS, /* The raid array has multiple PPLs feature set */
+ MD_ALLOW_SB_UPDATE, /* md_check_recovery is allowed to update
+ * the metadata without taking reconfig_mutex.
+ */
+ MD_UPDATING_SB, /* md_check_recovery is updating the metadata
+ * without explicitly holding reconfig_mutex.
+ */
};
enum mddev_sb_flags {
@@ -540,12 +546,11 @@
int (*check_reshape) (struct mddev *mddev);
int (*start_reshape) (struct mddev *mddev);
void (*finish_reshape) (struct mddev *mddev);
- /* quiesce moves between quiescence states
- * 0 - fully active
- * 1 - no new requests allowed
- * others - reserved
+ /* quiesce suspends or resumes internal processing.
+ * 1 - stop new actions and wait for action io to complete
+ * 0 - return to normal behaviour
*/
- void (*quiesce) (struct mddev *mddev, int state);
+ void (*quiesce) (struct mddev *mddev, int quiesce);
/* takeover is used to transition an array from one
* personality to another. The new personality must be able
* to handle the data in the current layout.
diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c
index 5a00fc11..5ecba9e 100644
--- a/drivers/md/raid0.c
+++ b/drivers/md/raid0.c
@@ -768,7 +768,7 @@
return ERR_PTR(-EINVAL);
}
-static void raid0_quiesce(struct mddev *mddev, int state)
+static void raid0_quiesce(struct mddev *mddev, int quiesce)
{
}
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index e4e01d3..029ecba 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -1298,11 +1298,9 @@
*/
- if ((bio_end_sector(bio) > mddev->suspend_lo &&
- bio->bi_iter.bi_sector < mddev->suspend_hi) ||
- (mddev_is_clustered(mddev) &&
+ if (mddev_is_clustered(mddev) &&
md_cluster_ops->area_resyncing(mddev, WRITE,
- bio->bi_iter.bi_sector, bio_end_sector(bio)))) {
+ bio->bi_iter.bi_sector, bio_end_sector(bio))) {
/*
* As the suspend_* range is controlled by userspace, we want
@@ -1313,12 +1311,10 @@
sigset_t full, old;
prepare_to_wait(&conf->wait_barrier,
&w, TASK_INTERRUPTIBLE);
- if ((bio_end_sector(bio) <= mddev->suspend_lo ||
- bio->bi_iter.bi_sector >= mddev->suspend_hi) &&
- (!mddev_is_clustered(mddev) ||
- !md_cluster_ops->area_resyncing(mddev, WRITE,
+ if (!mddev_is_clustered(mddev) ||
+ !md_cluster_ops->area_resyncing(mddev, WRITE,
bio->bi_iter.bi_sector,
- bio_end_sector(bio))))
+ bio_end_sector(bio)))
break;
sigfillset(&full);
sigprocmask(SIG_BLOCK, &full, &old);
@@ -3280,21 +3276,14 @@
return 0;
}
-static void raid1_quiesce(struct mddev *mddev, int state)
+static void raid1_quiesce(struct mddev *mddev, int quiesce)
{
struct r1conf *conf = mddev->private;
- switch(state) {
- case 2: /* wake for suspend */
- wake_up(&conf->wait_barrier);
- break;
- case 1:
+ if (quiesce)
freeze_array(conf, 0);
- break;
- case 0:
+ else
unfreeze_array(conf);
- break;
- }
}
static void *raid1_takeover(struct mddev *mddev)
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 5fb31ef..b20c23f 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -3838,18 +3838,14 @@
kfree(conf);
}
-static void raid10_quiesce(struct mddev *mddev, int state)
+static void raid10_quiesce(struct mddev *mddev, int quiesce)
{
struct r10conf *conf = mddev->private;
- switch(state) {
- case 1:
+ if (quiesce)
raise_barrier(conf, 0);
- break;
- case 0:
+ else
lower_barrier(conf);
- break;
- }
}
static int raid10_resize(struct mddev *mddev, sector_t sectors)
diff --git a/drivers/md/raid5-cache.c b/drivers/md/raid5-cache.c
index 9a34072..0d535b4 100644
--- a/drivers/md/raid5-cache.c
+++ b/drivers/md/raid5-cache.c
@@ -693,6 +693,8 @@
struct r5l_log *log = container_of(work, struct r5l_log,
disable_writeback_work);
struct mddev *mddev = log->rdev->mddev;
+ struct r5conf *conf = mddev->private;
+ int locked = 0;
if (log->r5c_journal_mode == R5C_JOURNAL_MODE_WRITE_THROUGH)
return;
@@ -701,11 +703,15 @@
/* wait superblock change before suspend */
wait_event(mddev->sb_wait,
- !test_bit(MD_SB_CHANGE_PENDING, &mddev->sb_flags));
-
- mddev_suspend(mddev);
- log->r5c_journal_mode = R5C_JOURNAL_MODE_WRITE_THROUGH;
- mddev_resume(mddev);
+ conf->log == NULL ||
+ (!test_bit(MD_SB_CHANGE_PENDING, &mddev->sb_flags) &&
+ (locked = mddev_trylock(mddev))));
+ if (locked) {
+ mddev_suspend(mddev);
+ log->r5c_journal_mode = R5C_JOURNAL_MODE_WRITE_THROUGH;
+ mddev_resume(mddev);
+ mddev_unlock(mddev);
+ }
}
static void r5l_submit_current_io(struct r5l_log *log)
@@ -1583,21 +1589,21 @@
md_wakeup_thread(log->reclaim_thread);
}
-void r5l_quiesce(struct r5l_log *log, int state)
+void r5l_quiesce(struct r5l_log *log, int quiesce)
{
struct mddev *mddev;
- if (!log || state == 2)
+ if (!log)
return;
- if (state == 0)
- kthread_unpark(log->reclaim_thread->tsk);
- else if (state == 1) {
+
+ if (quiesce) {
/* make sure r5l_write_super_and_discard_space exits */
mddev = log->rdev->mddev;
wake_up(&mddev->sb_wait);
kthread_park(log->reclaim_thread->tsk);
r5l_wake_reclaim(log, MaxSector);
r5l_do_reclaim(log);
- }
+ } else
+ kthread_unpark(log->reclaim_thread->tsk);
}
bool r5l_log_disk_error(struct r5conf *conf)
@@ -3161,6 +3167,8 @@
conf->log = NULL;
synchronize_rcu();
+ /* Ensure disable_writeback_work wakes up and exits */
+ wake_up(&conf->mddev->sb_wait);
flush_work(&log->disable_writeback_work);
md_unregister_thread(&log->reclaim_thread);
mempool_destroy(log->meta_pool);
diff --git a/drivers/md/raid5-log.h b/drivers/md/raid5-log.h
index 7f9ad5f..284578b 100644
--- a/drivers/md/raid5-log.h
+++ b/drivers/md/raid5-log.h
@@ -9,7 +9,7 @@
extern void r5l_flush_stripe_to_raid(struct r5l_log *log);
extern void r5l_stripe_write_finished(struct stripe_head *sh);
extern int r5l_handle_flush_request(struct r5l_log *log, struct bio *bio);
-extern void r5l_quiesce(struct r5l_log *log, int state);
+extern void r5l_quiesce(struct r5l_log *log, int quiesce);
extern bool r5l_log_disk_error(struct r5conf *conf);
extern bool r5c_is_writeback(struct r5l_log *log);
extern int
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index de1ef62..07ca2fd 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -5686,28 +5686,6 @@
goto retry;
}
- if (rw == WRITE &&
- logical_sector >= mddev->suspend_lo &&
- logical_sector < mddev->suspend_hi) {
- raid5_release_stripe(sh);
- /* As the suspend_* range is controlled by
- * userspace, we want an interruptible
- * wait.
- */
- prepare_to_wait(&conf->wait_for_overlap,
- &w, TASK_INTERRUPTIBLE);
- if (logical_sector >= mddev->suspend_lo &&
- logical_sector < mddev->suspend_hi) {
- sigset_t full, old;
- sigfillset(&full);
- sigprocmask(SIG_BLOCK, &full, &old);
- schedule();
- sigprocmask(SIG_SETMASK, &old, NULL);
- do_prepare = true;
- }
- goto retry;
- }
-
if (test_bit(STRIPE_EXPANDING, &sh->state) ||
!add_stripe_bio(sh, bi, dd_idx, rw, previous)) {
/* Stripe is busy expanding or
@@ -8025,16 +8003,12 @@
}
}
-static void raid5_quiesce(struct mddev *mddev, int state)
+static void raid5_quiesce(struct mddev *mddev, int quiesce)
{
struct r5conf *conf = mddev->private;
- switch(state) {
- case 2: /* resume for a suspend */
- wake_up(&conf->wait_for_overlap);
- break;
-
- case 1: /* stop all writes */
+ if (quiesce) {
+ /* stop all writes */
lock_all_device_hash_locks_irq(conf);
/* '2' tells resync/reshape to pause so that all
* active stripes can drain
@@ -8050,17 +8024,15 @@
unlock_all_device_hash_locks_irq(conf);
/* allow reshape to continue */
wake_up(&conf->wait_for_overlap);
- break;
-
- case 0: /* re-enable writes */
+ } else {
+ /* re-enable writes */
lock_all_device_hash_locks_irq(conf);
conf->quiesce = 0;
wake_up(&conf->wait_for_quiescent);
wake_up(&conf->wait_for_overlap);
unlock_all_device_hash_locks_irq(conf);
- break;
}
- r5l_quiesce(conf->log, state);
+ r5l_quiesce(conf->log, quiesce);
}
static void *raid45_takeover_raid0(struct mddev *mddev, int level)
diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c
index 33d844f..f7d4ec3 100644
--- a/drivers/media/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb-core/dvb_frontend.c
@@ -275,8 +275,20 @@
wake_up_interruptible (&events->wait_queue);
}
+static int dvb_frontend_test_event(struct dvb_frontend_private *fepriv,
+ struct dvb_fe_events *events)
+{
+ int ret;
+
+ up(&fepriv->sem);
+ ret = events->eventw != events->eventr;
+ down(&fepriv->sem);
+
+ return ret;
+}
+
static int dvb_frontend_get_event(struct dvb_frontend *fe,
- struct dvb_frontend_event *event, int flags)
+ struct dvb_frontend_event *event, int flags)
{
struct dvb_frontend_private *fepriv = fe->frontend_priv;
struct dvb_fe_events *events = &fepriv->events;
@@ -294,13 +306,8 @@
if (flags & O_NONBLOCK)
return -EWOULDBLOCK;
- up(&fepriv->sem);
-
- ret = wait_event_interruptible (events->wait_queue,
- events->eventw != events->eventr);
-
- if (down_interruptible (&fepriv->sem))
- return -ERESTARTSYS;
+ ret = wait_event_interruptible(events->wait_queue,
+ dvb_frontend_test_event(fepriv, events));
if (ret < 0)
return ret;
diff --git a/drivers/media/i2c/cx25840/cx25840-core.c b/drivers/media/i2c/cx25840/cx25840-core.c
index 39f51daa..c5642813 100644
--- a/drivers/media/i2c/cx25840/cx25840-core.c
+++ b/drivers/media/i2c/cx25840/cx25840-core.c
@@ -463,8 +463,13 @@
{
DEFINE_WAIT(wait);
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
+ u32 clk_freq = 0;
struct workqueue_struct *q;
+ /* cx23885 sets hostdata to clk_freq pointer */
+ if (v4l2_get_subdev_hostdata(&state->sd))
+ clk_freq = *((u32 *)v4l2_get_subdev_hostdata(&state->sd));
+
/*
* Come out of digital power down
* The CX23888, at least, needs this, otherwise registers aside from
@@ -500,8 +505,13 @@
* 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
* 572.73 MHz before post divide
*/
- /* HVR1850 or 50MHz xtal */
- cx25840_write(client, 0x2, 0x71);
+ if (clk_freq == 25000000) {
+ /* 888/ImpactVCBe or 25Mhz xtal */
+ ; /* nothing to do */
+ } else {
+ /* HVR1850 or 50MHz xtal */
+ cx25840_write(client, 0x2, 0x71);
+ }
cx25840_write4(client, 0x11c, 0x01d1744c);
cx25840_write4(client, 0x118, 0x00000416);
cx25840_write4(client, 0x404, 0x0010253e);
@@ -544,9 +554,15 @@
/* HVR1850 */
switch (state->id) {
case CX23888_AV:
- /* 888/HVR1250 specific */
- cx25840_write4(client, 0x10c, 0x13333333);
- cx25840_write4(client, 0x108, 0x00000515);
+ if (clk_freq == 25000000) {
+ /* 888/ImpactVCBe or 25MHz xtal */
+ cx25840_write4(client, 0x10c, 0x01b6db7b);
+ cx25840_write4(client, 0x108, 0x00000512);
+ } else {
+ /* 888/HVR1250 or 50MHz xtal */
+ cx25840_write4(client, 0x10c, 0x13333333);
+ cx25840_write4(client, 0x108, 0x00000515);
+ }
break;
default:
cx25840_write4(client, 0x10c, 0x002be2c9);
@@ -576,7 +592,7 @@
* 368.64 MHz before post divide
* 122.88 MHz / 0xa = 12.288 MHz
*/
- /* HVR1850 or 50MHz xtal */
+ /* HVR1850 or 50MHz xtal or 25MHz xtal */
cx25840_write4(client, 0x114, 0x017dbf48);
cx25840_write4(client, 0x110, 0x000a030e);
break;
diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
index c2d3b8f0..93f69b3 100644
--- a/drivers/media/platform/vsp1/vsp1_video.c
+++ b/drivers/media/platform/vsp1/vsp1_video.c
@@ -849,9 +849,8 @@
return 0;
}
-static void vsp1_video_cleanup_pipeline(struct vsp1_pipeline *pipe)
+static void vsp1_video_release_buffers(struct vsp1_video *video)
{
- struct vsp1_video *video = pipe->output->video;
struct vsp1_vb2_buffer *buffer;
unsigned long flags;
@@ -861,12 +860,18 @@
vb2_buffer_done(&buffer->buf.vb2_buf, VB2_BUF_STATE_ERROR);
INIT_LIST_HEAD(&video->irqqueue);
spin_unlock_irqrestore(&video->irqlock, flags);
+}
+
+static void vsp1_video_cleanup_pipeline(struct vsp1_pipeline *pipe)
+{
+ lockdep_assert_held(&pipe->lock);
/* Release our partition table allocation */
- mutex_lock(&pipe->lock);
kfree(pipe->part_table);
pipe->part_table = NULL;
- mutex_unlock(&pipe->lock);
+
+ vsp1_dl_list_put(pipe->dl);
+ pipe->dl = NULL;
}
static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count)
@@ -881,8 +886,9 @@
if (pipe->stream_count == pipe->num_inputs) {
ret = vsp1_video_setup_pipeline(pipe);
if (ret < 0) {
- mutex_unlock(&pipe->lock);
+ vsp1_video_release_buffers(video);
vsp1_video_cleanup_pipeline(pipe);
+ mutex_unlock(&pipe->lock);
return ret;
}
@@ -932,13 +938,12 @@
if (ret == -ETIMEDOUT)
dev_err(video->vsp1->dev, "pipeline stop timeout\n");
- vsp1_dl_list_put(pipe->dl);
- pipe->dl = NULL;
+ vsp1_video_cleanup_pipeline(pipe);
}
mutex_unlock(&pipe->lock);
media_pipeline_stop(&video->video.entity);
- vsp1_video_cleanup_pipeline(pipe);
+ vsp1_video_release_buffers(video);
vsp1_video_pipeline_put(pipe);
}
diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c
index 7c572a6..2a1728e 100644
--- a/drivers/media/rc/ir-mce_kbd-decoder.c
+++ b/drivers/media/rc/ir-mce_kbd-decoder.c
@@ -130,6 +130,8 @@
for (i = 0; i < MCIR2_MASK_KEYS_START; i++)
input_report_key(mce_kbd->idev, kbd_keycodes[i], 0);
+
+ input_sync(mce_kbd->idev);
}
static enum mce_kbd_mode mce_kbd_mode(struct mce_kbd_dec *data)
diff --git a/drivers/media/usb/cx231xx/cx231xx-cards.c b/drivers/media/usb/cx231xx/cx231xx-cards.c
index 9b742d5..c30cb0f 100644
--- a/drivers/media/usb/cx231xx/cx231xx-cards.c
+++ b/drivers/media/usb/cx231xx/cx231xx-cards.c
@@ -918,6 +918,9 @@
.driver_info = CX231XX_BOARD_CNXT_RDE_250},
{USB_DEVICE(0x0572, 0x58A0),
.driver_info = CX231XX_BOARD_CNXT_RDU_250},
+ /* AverMedia DVD EZMaker 7 */
+ {USB_DEVICE(0x07ca, 0xc039),
+ .driver_info = CX231XX_BOARD_CNXT_VIDEO_GRABBER},
{USB_DEVICE(0x2040, 0xb110),
.driver_info = CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL},
{USB_DEVICE(0x2040, 0xb111),
diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
index 6730fd0..e159dfc 100644
--- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
+++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
@@ -871,7 +871,7 @@
get_user(kcontrols, &kp->controls))
return -EFAULT;
- if (!count)
+ if (!count || count > (U32_MAX/sizeof(*ucontrols)))
return 0;
if (get_user(p, &up->controls))
return -EFAULT;
diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c
index 4cc45a5..b96c70c69 100644
--- a/drivers/media/v4l2-core/videobuf2-core.c
+++ b/drivers/media/v4l2-core/videobuf2-core.c
@@ -1646,6 +1646,15 @@
for (i = 0; i < q->num_buffers; ++i) {
struct vb2_buffer *vb = q->bufs[i];
+ if (vb->state == VB2_BUF_STATE_PREPARED ||
+ vb->state == VB2_BUF_STATE_QUEUED) {
+ unsigned int plane;
+
+ for (plane = 0; plane < vb->num_planes; ++plane)
+ call_void_memop(vb, finish,
+ vb->planes[plane].mem_priv);
+ }
+
if (vb->state != VB2_BUF_STATE_DEQUEUED) {
vb->state = VB2_BUF_STATE_PREPARED;
call_void_vb_qop(vb, buf_finish, vb);
diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
index d1c46de..d9ae983 100644
--- a/drivers/mfd/intel-lpss-pci.c
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -124,6 +124,11 @@
.properties = apl_i2c_properties,
};
+static const struct intel_lpss_platform_info cnl_i2c_info = {
+ .clk_rate = 216000000,
+ .properties = spt_i2c_properties,
+};
+
static const struct pci_device_id intel_lpss_pci_ids[] = {
/* BXT A-Step */
{ PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
@@ -207,13 +212,13 @@
{ PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info },
- { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&spt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info },
- { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&spt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info },
/* SPT-H */
{ PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
@@ -240,10 +245,10 @@
{ PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info },
- { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&spt_i2c_info },
- { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&spt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&cnl_i2c_info },
+ { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&cnl_i2c_info },
{ }
};
MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
index 0e0ab9bb..40e8d9b 100644
--- a/drivers/mfd/intel-lpss.c
+++ b/drivers/mfd/intel-lpss.c
@@ -275,11 +275,11 @@
intel_lpss_deassert_reset(lpss);
+ intel_lpss_set_remap_addr(lpss);
+
if (!intel_lpss_has_idma(lpss))
return;
- intel_lpss_set_remap_addr(lpss);
-
/* Make sure that SPI multiblock DMA transfers are re-enabled */
if (lpss->type == LPSS_DEV_SPI)
writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c
index a8b6d6a..393a80b 100644
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -331,12 +331,20 @@
struct cxl_afu *afu = to_cxl_afu(device);
enum prefault_modes mode = -1;
- if (!strncmp(buf, "work_element_descriptor", 23))
- mode = CXL_PREFAULT_WED;
- if (!strncmp(buf, "all", 3))
- mode = CXL_PREFAULT_ALL;
if (!strncmp(buf, "none", 4))
mode = CXL_PREFAULT_NONE;
+ else {
+ if (!radix_enabled()) {
+
+ /* only allowed when not in radix mode */
+ if (!strncmp(buf, "work_element_descriptor", 23))
+ mode = CXL_PREFAULT_WED;
+ if (!strncmp(buf, "all", 3))
+ mode = CXL_PREFAULT_ALL;
+ } else {
+ dev_err(device, "Cannot prefault with radix enabled\n");
+ }
+ }
if (mode == -1)
return -EINVAL;
diff --git a/drivers/misc/ibmasm/ibmasmfs.c b/drivers/misc/ibmasm/ibmasmfs.c
index e05c324..fa84066 100644
--- a/drivers/misc/ibmasm/ibmasmfs.c
+++ b/drivers/misc/ibmasm/ibmasmfs.c
@@ -507,35 +507,14 @@
static ssize_t remote_settings_file_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
{
void __iomem *address = (void __iomem *)file->private_data;
- unsigned char *page;
- int retval;
int len = 0;
unsigned int value;
-
- if (*offset < 0)
- return -EINVAL;
- if (count == 0 || count > 1024)
- return 0;
- if (*offset != 0)
- return 0;
-
- page = (unsigned char *)__get_free_page(GFP_KERNEL);
- if (!page)
- return -ENOMEM;
+ char lbuf[20];
value = readl(address);
- len = sprintf(page, "%d\n", value);
+ len = snprintf(lbuf, sizeof(lbuf), "%d\n", value);
- if (copy_to_user(buf, page, len)) {
- retval = -EFAULT;
- goto exit;
- }
- *offset += len;
- retval = len;
-
-exit:
- free_page((unsigned long)page);
- return retval;
+ return simple_read_from_buffer(buf, count, offset, lbuf, len);
}
static ssize_t remote_settings_file_write(struct file *file, const char __user *ubuff, size_t count, loff_t *offset)
diff --git a/drivers/misc/mic/scif/scif_rma.c b/drivers/misc/mic/scif/scif_rma.c
index 329727e0..c824329 100644
--- a/drivers/misc/mic/scif/scif_rma.c
+++ b/drivers/misc/mic/scif/scif_rma.c
@@ -39,8 +39,7 @@
struct scif_endpt_rma_info *rma = &ep->rma_info;
mutex_init(&rma->rma_lock);
- init_iova_domain(&rma->iovad, PAGE_SIZE, SCIF_IOVA_START_PFN,
- SCIF_DMA_64BIT_PFN);
+ init_iova_domain(&rma->iovad, PAGE_SIZE, SCIF_IOVA_START_PFN);
spin_lock_init(&rma->tc_lock);
mutex_init(&rma->mmn_lock);
INIT_LIST_HEAD(&rma->reg_list);
diff --git a/drivers/misc/vmw_balloon.c b/drivers/misc/vmw_balloon.c
index efd7334..56c6f79 100644
--- a/drivers/misc/vmw_balloon.c
+++ b/drivers/misc/vmw_balloon.c
@@ -467,7 +467,7 @@
unsigned int num_pages, bool is_2m_pages, unsigned int *target)
{
unsigned long status;
- unsigned long pfn = page_to_pfn(b->page);
+ unsigned long pfn = PHYS_PFN(virt_to_phys(b->batch_page));
STATS_INC(b->stats.lock[is_2m_pages]);
@@ -515,7 +515,7 @@
unsigned int num_pages, bool is_2m_pages, unsigned int *target)
{
unsigned long status;
- unsigned long pfn = page_to_pfn(b->page);
+ unsigned long pfn = PHYS_PFN(virt_to_phys(b->batch_page));
STATS_INC(b->stats.unlock[is_2m_pages]);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index de31e20..6a2cbbb 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1089,8 +1089,8 @@
* It's used when HS400 mode is enabled.
*/
if (data->flags & MMC_DATA_WRITE &&
- !(host->timing != MMC_TIMING_MMC_HS400))
- return;
+ host->timing != MMC_TIMING_MMC_HS400)
+ goto disable;
if (data->flags & MMC_DATA_WRITE)
enable = SDMMC_CARD_WR_THR_EN;
@@ -1098,7 +1098,8 @@
enable = SDMMC_CARD_RD_THR_EN;
if (host->timing != MMC_TIMING_MMC_HS200 &&
- host->timing != MMC_TIMING_UHS_SDR104)
+ host->timing != MMC_TIMING_UHS_SDR104 &&
+ host->timing != MMC_TIMING_MMC_HS400)
goto disable;
blksz_depth = blksz / (1 << host->data_shift);
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 267f7ab..a2baa87 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -67,17 +67,23 @@
#define SDC_RESP2 0x48
#define SDC_RESP3 0x4c
#define SDC_BLK_NUM 0x50
+#define SDC_ADV_CFG0 0x64
#define EMMC_IOCON 0x7c
#define SDC_ACMD_RESP 0x80
+#define DMA_SA_H4BIT 0x8c
#define MSDC_DMA_SA 0x90
#define MSDC_DMA_CTRL 0x98
#define MSDC_DMA_CFG 0x9c
#define MSDC_PATCH_BIT 0xb0
#define MSDC_PATCH_BIT1 0xb4
+#define MSDC_PATCH_BIT2 0xb8
#define MSDC_PAD_TUNE 0xec
+#define MSDC_PAD_TUNE0 0xf0
#define PAD_DS_TUNE 0x188
#define PAD_CMD_TUNE 0x18c
#define EMMC50_CFG0 0x208
+#define EMMC50_CFG3 0x220
+#define SDC_FIFO_CFG 0x228
/*--------------------------------------------------------------------------*/
/* Register Mask */
@@ -95,6 +101,9 @@
#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
#define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
+#define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
+#define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
+#define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
/* MSDC_IOCON mask */
#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
@@ -183,6 +192,12 @@
#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
+/* SDC_ADV_CFG0 mask */
+#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
+
+/* DMA_SA_H4BIT mask */
+#define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
+
/* MSDC_DMA_CTRL mask */
#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
@@ -212,11 +227,23 @@
#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
+#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
+
+#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
+#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
+#define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
+#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
+#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
+#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
+
#define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
#define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
#define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
+#define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
+#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
+#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
@@ -228,6 +255,11 @@
#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
+#define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
+
+#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
+#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
+
#define REQ_CMD_EIO (0x1 << 0)
#define REQ_CMD_TMO (0x1 << 1)
#define REQ_DAT_ERR (0x1 << 2)
@@ -253,6 +285,8 @@
#define GPDMA_DESC_BDP (0x1 << 1)
#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
#define GPDMA_DESC_INT (0x1 << 16)
+#define GPDMA_DESC_NEXT_H4 (0xf << 24)
+#define GPDMA_DESC_PTR_H4 (0xf << 28)
u32 next;
u32 ptr;
u32 gpd_data_len;
@@ -269,6 +303,8 @@
#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
#define BDMA_DESC_BLKPAD (0x1 << 17)
#define BDMA_DESC_DWPAD (0x1 << 18)
+#define BDMA_DESC_NEXT_H4 (0xf << 24)
+#define BDMA_DESC_PTR_H4 (0xf << 28)
u32 next;
u32 ptr;
u32 bd_data_len;
@@ -290,9 +326,24 @@
u32 pad_tune;
u32 patch_bit0;
u32 patch_bit1;
+ u32 patch_bit2;
u32 pad_ds_tune;
u32 pad_cmd_tune;
u32 emmc50_cfg0;
+ u32 emmc50_cfg3;
+ u32 sdc_fifo_cfg;
+};
+
+struct mtk_mmc_compatible {
+ u8 clk_div_bits;
+ bool hs400_tune; /* only used for MT8173 */
+ u32 pad_tune_reg;
+ bool async_fifo;
+ bool data_tune;
+ bool busy_check;
+ bool stop_clk_fix;
+ bool enhance_rx;
+ bool support_64g;
};
struct msdc_tune_para {
@@ -309,6 +360,7 @@
struct msdc_host {
struct device *dev;
+ const struct mtk_mmc_compatible *dev_comp;
struct mmc_host *mmc; /* mmc structure */
int cmd_rsp;
@@ -334,11 +386,13 @@
struct clk *src_clk; /* msdc source clock */
struct clk *h_clk; /* msdc h_clk */
+ struct clk *src_clk_cg; /* msdc source clock control gate */
u32 mclk; /* mmc subsystem clock frequency */
u32 src_clk_freq; /* source clock frequency */
u32 sclk; /* SD/MS bus clock frequency */
unsigned char timing;
bool vqmmc_enabled;
+ u32 latch_ck;
u32 hs400_ds_delay;
u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
@@ -350,6 +404,76 @@
struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
};
+static const struct mtk_mmc_compatible mt8135_compat = {
+ .clk_div_bits = 8,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE,
+ .async_fifo = false,
+ .data_tune = false,
+ .busy_check = false,
+ .stop_clk_fix = false,
+ .enhance_rx = false,
+ .support_64g = false,
+};
+
+static const struct mtk_mmc_compatible mt8173_compat = {
+ .clk_div_bits = 8,
+ .hs400_tune = true,
+ .pad_tune_reg = MSDC_PAD_TUNE,
+ .async_fifo = false,
+ .data_tune = false,
+ .busy_check = false,
+ .stop_clk_fix = false,
+ .enhance_rx = false,
+ .support_64g = false,
+};
+
+static const struct mtk_mmc_compatible mt2701_compat = {
+ .clk_div_bits = 12,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = false,
+ .stop_clk_fix = false,
+ .enhance_rx = false,
+ .support_64g = false,
+};
+
+static const struct mtk_mmc_compatible mt2712_compat = {
+ .clk_div_bits = 12,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+ .enhance_rx = true,
+ .support_64g = true,
+};
+
+static const struct mtk_mmc_compatible mt7622_compat = {
+ .clk_div_bits = 12,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+ .enhance_rx = true,
+ .support_64g = false,
+};
+
+static const struct of_device_id msdc_of_ids[] = {
+ { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
+ { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
+ { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
+ { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
+ { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
+ {}
+};
+MODULE_DEVICE_TABLE(of, msdc_of_ids);
+
static void sdr_set_bits(void __iomem *reg, u32 bs)
{
u32 val = readl(reg);
@@ -447,7 +571,12 @@
/* init bd */
bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
bd[j].bd_info &= ~BDMA_DESC_DWPAD;
- bd[j].ptr = (u32)dma_address;
+ bd[j].ptr = lower_32_bits(dma_address);
+ if (host->dev_comp->support_64g) {
+ bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
+ bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
+ << 28;
+ }
bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
@@ -466,7 +595,10 @@
dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
- writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
+ if (host->dev_comp->support_64g)
+ sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
+ upper_32_bits(dma->gpd_addr) & 0xf);
+ writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
}
static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
@@ -509,7 +641,12 @@
timeout = (ns + clk_ns - 1) / clk_ns + clks;
/* in 1048576 sclk cycle unit */
timeout = (timeout + (0x1 << 20) - 1) >> 20;
- sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
+ if (host->dev_comp->clk_div_bits == 8)
+ sdr_get_field(host->base + MSDC_CFG,
+ MSDC_CFG_CKMOD, &mode);
+ else
+ sdr_get_field(host->base + MSDC_CFG,
+ MSDC_CFG_CKMOD_EXTRA, &mode);
/*DDR mode will double the clk cycles for data timeout */
timeout = mode >= 2 ? timeout * 2 : timeout;
timeout = timeout > 1 ? timeout - 1 : 0;
@@ -520,6 +657,7 @@
static void msdc_gate_clock(struct msdc_host *host)
{
+ clk_disable_unprepare(host->src_clk_cg);
clk_disable_unprepare(host->src_clk);
clk_disable_unprepare(host->h_clk);
}
@@ -528,6 +666,7 @@
{
clk_prepare_enable(host->h_clk);
clk_prepare_enable(host->src_clk);
+ clk_prepare_enable(host->src_clk_cg);
while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
cpu_relax();
}
@@ -538,6 +677,7 @@
u32 flags;
u32 div;
u32 sclk;
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
if (!hz) {
dev_dbg(host->dev, "set mclk to 0\n");
@@ -548,7 +688,11 @@
flags = readl(host->base + MSDC_INTEN);
sdr_clr_bits(host->base + MSDC_INTEN, flags);
- sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
+ if (host->dev_comp->clk_div_bits == 8)
+ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
+ else
+ sdr_clr_bits(host->base + MSDC_CFG,
+ MSDC_CFG_HS400_CK_MODE_EXTRA);
if (timing == MMC_TIMING_UHS_DDR50 ||
timing == MMC_TIMING_MMC_DDR52 ||
timing == MMC_TIMING_MMC_HS400) {
@@ -568,8 +712,12 @@
if (timing == MMC_TIMING_MMC_HS400 &&
hz >= (host->src_clk_freq >> 1)) {
- sdr_set_bits(host->base + MSDC_CFG,
- MSDC_CFG_HS400_CK_MODE);
+ if (host->dev_comp->clk_div_bits == 8)
+ sdr_set_bits(host->base + MSDC_CFG,
+ MSDC_CFG_HS400_CK_MODE);
+ else
+ sdr_set_bits(host->base + MSDC_CFG,
+ MSDC_CFG_HS400_CK_MODE_EXTRA);
sclk = host->src_clk_freq >> 1;
div = 0; /* div is ignore when bit18 is set */
}
@@ -587,11 +735,31 @@
sclk = (host->src_clk_freq >> 2) / div;
}
}
- sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
- (mode << 8) | div);
- sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
+ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
+ /*
+ * As src_clk/HCLK use the same bit to gate/ungate,
+ * So if want to only gate src_clk, need gate its parent(mux).
+ */
+ if (host->src_clk_cg)
+ clk_disable_unprepare(host->src_clk_cg);
+ else
+ clk_disable_unprepare(clk_get_parent(host->src_clk));
+ if (host->dev_comp->clk_div_bits == 8)
+ sdr_set_field(host->base + MSDC_CFG,
+ MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
+ (mode << 8) | div);
+ else
+ sdr_set_field(host->base + MSDC_CFG,
+ MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
+ (mode << 12) | div);
+ if (host->src_clk_cg)
+ clk_prepare_enable(host->src_clk_cg);
+ else
+ clk_prepare_enable(clk_get_parent(host->src_clk));
+
while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
cpu_relax();
+ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
host->sclk = sclk;
host->mclk = hz;
host->timing = timing;
@@ -605,15 +773,16 @@
*/
if (host->sclk <= 52000000) {
writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
- writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
+ writel(host->def_tune_para.pad_tune, host->base + tune_reg);
} else {
writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
- writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
+ writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
writel(host->saved_tune_para.pad_cmd_tune,
host->base + PAD_CMD_TUNE);
}
- if (timing == MMC_TIMING_MMC_HS400)
+ if (timing == MMC_TIMING_MMC_HS400 &&
+ host->dev_comp->hs400_tune)
sdr_set_field(host->base + PAD_CMD_TUNE,
MSDC_PAD_TUNE_CMDRRDLY,
host->hs400_cmd_int_delay);
@@ -1165,6 +1334,7 @@
static void msdc_init_hw(struct msdc_host *host)
{
u32 val;
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
/* Configure to MMC/SD mode, clock free running */
sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
@@ -1180,14 +1350,56 @@
val = readl(host->base + MSDC_INT);
writel(val, host->base + MSDC_INT);
- writel(0, host->base + MSDC_PAD_TUNE);
+ writel(0, host->base + tune_reg);
writel(0, host->base + MSDC_IOCON);
sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
writel(0x403c0046, host->base + MSDC_PATCH_BIT);
sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
- writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
+ if (host->dev_comp->stop_clk_fix) {
+ sdr_set_field(host->base + MSDC_PATCH_BIT1,
+ MSDC_PATCH_BIT1_STOP_DLY, 3);
+ sdr_clr_bits(host->base + SDC_FIFO_CFG,
+ SDC_FIFO_CFG_WRVALIDSEL);
+ sdr_clr_bits(host->base + SDC_FIFO_CFG,
+ SDC_FIFO_CFG_RDVALIDSEL);
+ }
+
+ if (host->dev_comp->busy_check)
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
+
+ if (host->dev_comp->async_fifo) {
+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
+ MSDC_PB2_RESPWAIT, 3);
+ if (host->dev_comp->enhance_rx) {
+ sdr_set_bits(host->base + SDC_ADV_CFG0,
+ SDC_RX_ENHANCE_EN);
+ } else {
+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
+ MSDC_PB2_RESPSTSENSEL, 2);
+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
+ MSDC_PB2_CRCSTSENSEL, 2);
+ }
+ /* use async fifo, then no need tune internal delay */
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
+ MSDC_PATCH_BIT2_CFGRESP);
+ sdr_set_bits(host->base + MSDC_PATCH_BIT2,
+ MSDC_PATCH_BIT2_CFGCRCSTS);
+ }
+
+ if (host->dev_comp->support_64g)
+ sdr_set_bits(host->base + MSDC_PATCH_BIT2,
+ MSDC_PB2_SUPPORT_64G);
+ if (host->dev_comp->data_tune) {
+ sdr_set_bits(host->base + tune_reg,
+ MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
+ } else {
+ /* choose clock tune */
+ sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
+ }
+
/* Configure to enable SDIO mode.
* it's must otherwise sdio cmd5 failed
*/
@@ -1200,7 +1412,9 @@
sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
- host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
+ host->def_tune_para.pad_tune = readl(host->base + tune_reg);
+ host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
+ host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
dev_dbg(host->dev, "init hardware done!");
}
@@ -1219,19 +1433,32 @@
{
struct mt_gpdma_desc *gpd = dma->gpd;
struct mt_bdma_desc *bd = dma->bd;
+ dma_addr_t dma_addr;
int i;
memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
+ dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
- gpd->ptr = (u32)dma->bd_addr; /* physical address */
/* gpd->next is must set for desc DMA
* That's why must alloc 2 gpd structure.
*/
- gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
+ gpd->next = lower_32_bits(dma_addr);
+ if (host->dev_comp->support_64g)
+ gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
+
+ dma_addr = dma->bd_addr;
+ gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
+ if (host->dev_comp->support_64g)
+ gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
+
memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
- for (i = 0; i < (MAX_BD_NUM - 1); i++)
- bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
+ for (i = 0; i < (MAX_BD_NUM - 1); i++) {
+ dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
+ bd[i].next = lower_32_bits(dma_addr);
+ if (host->dev_comp->support_64g)
+ bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
+ }
}
static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
@@ -1343,18 +1570,19 @@
struct msdc_delay_phase internal_delay_phase;
u8 final_delay, final_maxlen;
u32 internal_delay = 0;
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
int cmd_err;
int i, j;
if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
mmc->ios.timing == MMC_TIMING_UHS_SDR104)
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_CMDRRDLY,
host->hs200_cmd_int_delay);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_CMDRDLY, i);
/*
* Using the same parameters, it may sometimes pass the test,
@@ -1373,12 +1601,13 @@
}
final_rise_delay = get_best_delay(host, rise_delay);
/* if rising edge has enough margin, then do not scan falling edge */
- if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4)
+ if (final_rise_delay.maxlen >= 12 ||
+ (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
goto skip_fall;
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_CMDRDLY, i);
/*
* Using the same parameters, it may sometimes pass the test,
@@ -1403,20 +1632,20 @@
final_maxlen = final_fall_delay.maxlen;
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
final_fall_delay.final_phase);
final_delay = final_fall_delay.final_phase;
}
- if (host->hs200_cmd_int_delay)
+ if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
goto skip_internal;
for (i = 0; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_CMDRRDLY, i);
mmc_send_tuning(mmc, opcode, &cmd_err);
if (!cmd_err)
@@ -1424,7 +1653,7 @@
}
dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
internal_delay_phase = get_best_delay(host, internal_delay);
- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
internal_delay_phase.final_phase);
skip_internal:
dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
@@ -1486,12 +1715,15 @@
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
u8 final_delay, final_maxlen;
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
int i, ret;
+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
+ host->latch_ck);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_DATRRDLY, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
@@ -1506,7 +1738,7 @@
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_DATRRDLY, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
@@ -1519,14 +1751,14 @@
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_DATRRDLY,
final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- sdr_set_field(host->base + MSDC_PAD_TUNE,
+ sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_DATRRDLY,
final_fall_delay.final_phase);
final_delay = final_fall_delay.final_phase;
@@ -1540,8 +1772,10 @@
{
struct msdc_host *host = mmc_priv(mmc);
int ret;
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
- if (host->hs400_mode)
+ if (host->hs400_mode &&
+ host->dev_comp->hs400_tune)
ret = hs400_tune_response(mmc, opcode);
else
ret = msdc_tune_response(mmc, opcode);
@@ -1556,7 +1790,7 @@
}
host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
- host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
+ host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
return ret;
}
@@ -1567,6 +1801,11 @@
host->hs400_mode = true;
writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
+ /* hs400 mode must set it to 0 */
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
+ /* to improve read performance, set outstanding to 2 */
+ sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
+
return 0;
}
@@ -1596,6 +1835,9 @@
static void msdc_of_property_parse(struct platform_device *pdev,
struct msdc_host *host)
{
+ of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
+ &host->latch_ck);
+
of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
&host->hs400_ds_delay);
@@ -1617,12 +1859,17 @@
struct mmc_host *mmc;
struct msdc_host *host;
struct resource *res;
+ const struct of_device_id *of_id;
int ret;
if (!pdev->dev.of_node) {
dev_err(&pdev->dev, "No DT found\n");
return -EINVAL;
}
+
+ of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
+ if (!of_id)
+ return -EINVAL;
/* Allocate MMC host for this device */
mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
if (!mmc)
@@ -1641,7 +1888,7 @@
}
ret = mmc_regulator_get_supply(mmc);
- if (ret == -EPROBE_DEFER)
+ if (ret)
goto host_free;
host->src_clk = devm_clk_get(&pdev->dev, "source");
@@ -1656,6 +1903,11 @@
goto host_free;
}
+ /*source clock control gate is optional clock*/
+ host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
+ if (IS_ERR(host->src_clk_cg))
+ host->src_clk_cg = NULL;
+
host->irq = platform_get_irq(pdev, 0);
if (host->irq < 0) {
ret = -EINVAL;
@@ -1686,11 +1938,15 @@
msdc_of_property_parse(pdev, host);
host->dev = &pdev->dev;
+ host->dev_comp = of_id->data;
host->mmc = mmc;
host->src_clk_freq = clk_get_rate(host->src_clk);
/* Set host parameters to mmc */
mmc->ops = &mt_msdc_ops;
- mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
+ if (host->dev_comp->clk_div_bits == 8)
+ mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
+ else
+ mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
/* MMC core transfer sizes tunable parameters */
@@ -1699,7 +1955,10 @@
mmc->max_blk_size = 2048;
mmc->max_req_size = 512 * 1024;
mmc->max_blk_count = mmc->max_req_size / 512;
- host->dma_mask = DMA_BIT_MASK(32);
+ if (host->dev_comp->support_64g)
+ host->dma_mask = DMA_BIT_MASK(36);
+ else
+ host->dma_mask = DMA_BIT_MASK(32);
mmc_dev(mmc)->dma_mask = &host->dma_mask;
host->timeout_clks = 3 * 1048576;
@@ -1788,28 +2047,38 @@
#ifdef CONFIG_PM
static void msdc_save_reg(struct msdc_host *host)
{
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
+
host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
host->save_para.iocon = readl(host->base + MSDC_IOCON);
host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
- host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
+ host->save_para.pad_tune = readl(host->base + tune_reg);
host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
+ host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
+ host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
+ host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
}
static void msdc_restore_reg(struct msdc_host *host)
{
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
+
writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
writel(host->save_para.iocon, host->base + MSDC_IOCON);
writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
- writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
+ writel(host->save_para.pad_tune, host->base + tune_reg);
writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
+ writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
+ writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
+ writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
}
static int msdc_runtime_suspend(struct device *dev)
@@ -1839,12 +2108,6 @@
SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
};
-static const struct of_device_id msdc_of_ids[] = {
- { .compatible = "mediatek,mt8135-mmc", },
- {}
-};
-MODULE_DEVICE_TABLE(of, msdc_of_ids);
-
static struct platform_driver mt_msdc_driver = {
.probe = msdc_drv_probe,
.remove = msdc_drv_remove,
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 8b941f8..c81de2f 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -305,6 +305,15 @@
if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
val |= SDHCI_SUPPORT_HS400;
+
+ /*
+ * Do not advertise faster UHS modes if there are no
+ * pinctrl states for 100MHz/200MHz.
+ */
+ if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
+ IS_ERR_OR_NULL(imx_data->pins_200mhz))
+ val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
+ | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
}
}
@@ -1135,18 +1144,6 @@
ESDHC_PINCTRL_STATE_100MHZ);
imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
ESDHC_PINCTRL_STATE_200MHZ);
- if (IS_ERR(imx_data->pins_100mhz) ||
- IS_ERR(imx_data->pins_200mhz)) {
- dev_warn(mmc_dev(host->mmc),
- "could not get ultra high speed state, work on normal mode\n");
- /*
- * fall back to not supporting uhs by specifying no
- * 1.8v quirk
- */
- host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
- }
- } else {
- host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
}
/* call to generic mmc_of_parse to support additional capabilities */
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index bb11916..a0dc3e1 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -33,16 +33,11 @@
#define CORE_MCI_GENERICS 0x70
#define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
-#define CORE_HC_MODE 0x78
#define HC_MODE_EN 0x1
#define CORE_POWER 0x0
#define CORE_SW_RST BIT(7)
#define FF_CLK_SW_RST_DIS BIT(13)
-#define CORE_PWRCTL_STATUS 0xdc
-#define CORE_PWRCTL_MASK 0xe0
-#define CORE_PWRCTL_CLEAR 0xe4
-#define CORE_PWRCTL_CTL 0xe8
#define CORE_PWRCTL_BUS_OFF BIT(0)
#define CORE_PWRCTL_BUS_ON BIT(1)
#define CORE_PWRCTL_IO_LOW BIT(2)
@@ -63,17 +58,13 @@
#define CORE_CDR_EXT_EN BIT(19)
#define CORE_DLL_PDN BIT(29)
#define CORE_DLL_RST BIT(30)
-#define CORE_DLL_CONFIG 0x100
#define CORE_CMD_DAT_TRACK_SEL BIT(0)
-#define CORE_DLL_STATUS 0x108
-#define CORE_DLL_CONFIG_2 0x1b4
#define CORE_DDR_CAL_EN BIT(0)
#define CORE_FLL_CYCLE_CNT BIT(18)
#define CORE_DLL_CLOCK_DISABLE BIT(21)
-#define CORE_VENDOR_SPEC 0x10c
-#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
+#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
#define CORE_CLK_PWRSAVE BIT(1)
#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
@@ -111,17 +102,14 @@
#define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
#define CORE_CDC_SWITCH_RC_EN BIT(1)
-#define CORE_DDR_200_CFG 0x184
#define CORE_CDC_T4_DLY_SEL BIT(0)
#define CORE_CMDIN_RCLK_EN BIT(1)
#define CORE_START_CDC_TRAFFIC BIT(6)
-#define CORE_VENDOR_SPEC3 0x1b0
+
#define CORE_PWRSAVE_DLL BIT(3)
-#define CORE_DDR_CONFIG 0x1b8
#define DDR_CONFIG_POR_VAL 0x80040853
-#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
#define INVALID_TUNING_PHASE -1
#define SDHCI_MSM_MIN_CLOCK 400000
@@ -137,6 +125,117 @@
/* Timeout value to avoid infinite waiting for pwr_irq */
#define MSM_PWR_IRQ_TIMEOUT_MS 5000
+#define msm_host_readl(msm_host, host, offset) \
+ msm_host->var_ops->msm_readl_relaxed(host, offset)
+
+#define msm_host_writel(msm_host, val, host, offset) \
+ msm_host->var_ops->msm_writel_relaxed(val, host, offset)
+
+struct sdhci_msm_offset {
+ u32 core_hc_mode;
+ u32 core_mci_data_cnt;
+ u32 core_mci_status;
+ u32 core_mci_fifo_cnt;
+ u32 core_mci_version;
+ u32 core_generics;
+ u32 core_testbus_config;
+ u32 core_testbus_sel2_bit;
+ u32 core_testbus_ena;
+ u32 core_testbus_sel2;
+ u32 core_pwrctl_status;
+ u32 core_pwrctl_mask;
+ u32 core_pwrctl_clear;
+ u32 core_pwrctl_ctl;
+ u32 core_sdcc_debug_reg;
+ u32 core_dll_config;
+ u32 core_dll_status;
+ u32 core_vendor_spec;
+ u32 core_vendor_spec_adma_err_addr0;
+ u32 core_vendor_spec_adma_err_addr1;
+ u32 core_vendor_spec_func2;
+ u32 core_vendor_spec_capabilities0;
+ u32 core_ddr_200_cfg;
+ u32 core_vendor_spec3;
+ u32 core_dll_config_2;
+ u32 core_ddr_config;
+ u32 core_ddr_config_2;
+};
+
+static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
+ .core_mci_data_cnt = 0x35c,
+ .core_mci_status = 0x324,
+ .core_mci_fifo_cnt = 0x308,
+ .core_mci_version = 0x318,
+ .core_generics = 0x320,
+ .core_testbus_config = 0x32c,
+ .core_testbus_sel2_bit = 3,
+ .core_testbus_ena = (1 << 31),
+ .core_testbus_sel2 = (1 << 3),
+ .core_pwrctl_status = 0x240,
+ .core_pwrctl_mask = 0x244,
+ .core_pwrctl_clear = 0x248,
+ .core_pwrctl_ctl = 0x24c,
+ .core_sdcc_debug_reg = 0x358,
+ .core_dll_config = 0x200,
+ .core_dll_status = 0x208,
+ .core_vendor_spec = 0x20c,
+ .core_vendor_spec_adma_err_addr0 = 0x214,
+ .core_vendor_spec_adma_err_addr1 = 0x218,
+ .core_vendor_spec_func2 = 0x210,
+ .core_vendor_spec_capabilities0 = 0x21c,
+ .core_ddr_200_cfg = 0x224,
+ .core_vendor_spec3 = 0x250,
+ .core_dll_config_2 = 0x254,
+ .core_ddr_config = 0x258,
+ .core_ddr_config_2 = 0x25c,
+};
+
+static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
+ .core_hc_mode = 0x78,
+ .core_mci_data_cnt = 0x30,
+ .core_mci_status = 0x34,
+ .core_mci_fifo_cnt = 0x44,
+ .core_mci_version = 0x050,
+ .core_generics = 0x70,
+ .core_testbus_config = 0x0cc,
+ .core_testbus_sel2_bit = 4,
+ .core_testbus_ena = (1 << 3),
+ .core_testbus_sel2 = (1 << 4),
+ .core_pwrctl_status = 0xdc,
+ .core_pwrctl_mask = 0xe0,
+ .core_pwrctl_clear = 0xe4,
+ .core_pwrctl_ctl = 0xe8,
+ .core_sdcc_debug_reg = 0x124,
+ .core_dll_config = 0x100,
+ .core_dll_status = 0x108,
+ .core_vendor_spec = 0x10c,
+ .core_vendor_spec_adma_err_addr0 = 0x114,
+ .core_vendor_spec_adma_err_addr1 = 0x118,
+ .core_vendor_spec_func2 = 0x110,
+ .core_vendor_spec_capabilities0 = 0x11c,
+ .core_ddr_200_cfg = 0x184,
+ .core_vendor_spec3 = 0x1b0,
+ .core_dll_config_2 = 0x1b4,
+ .core_ddr_config = 0x1b8,
+ .core_ddr_config_2 = 0x1bc,
+};
+
+struct sdhci_msm_variant_ops {
+ u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
+ void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
+ u32 offset);
+};
+
+/*
+ * From V5, register spaces have changed. Wrap this info in a structure
+ * and choose the data_structure based on version info mentioned in DT.
+ */
+struct sdhci_msm_variant_info {
+ bool mci_removed;
+ const struct sdhci_msm_variant_ops *var_ops;
+ const struct sdhci_msm_offset *offset;
+};
+
struct sdhci_msm_host {
struct platform_device *pdev;
void __iomem *core_mem; /* MSM SDCC mapped address */
@@ -156,8 +255,53 @@
wait_queue_head_t pwr_irq_wait;
bool pwr_irq_flag;
u32 caps_0;
+ bool mci_removed;
+ const struct sdhci_msm_variant_ops *var_ops;
+ const struct sdhci_msm_offset *offset;
};
+static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+ return msm_host->offset;
+}
+
+/*
+ * APIs to read/write to vendor specific registers which were there in the
+ * core_mem region before MCI was removed.
+ */
+static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
+ u32 offset)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+ return readl_relaxed(msm_host->core_mem + offset);
+}
+
+static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
+ u32 offset)
+{
+ return readl_relaxed(host->ioaddr + offset);
+}
+
+static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
+ struct sdhci_host *host, u32 offset)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+ writel_relaxed(val, msm_host->core_mem + offset);
+}
+
+static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
+ struct sdhci_host *host, u32 offset)
+{
+ writel_relaxed(val, host->ioaddr + offset);
+}
+
static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
unsigned int clock)
{
@@ -205,10 +349,12 @@
u32 wait_cnt = 50;
u8 ck_out_en;
struct mmc_host *mmc = host->mmc;
+ const struct sdhci_msm_offset *msm_offset =
+ sdhci_priv_msm_offset(host);
/* Poll for CK_OUT_EN bit. max. poll time = 50us */
- ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
- CORE_CK_OUT_EN);
+ ck_out_en = !!(readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config) & CORE_CK_OUT_EN);
while (ck_out_en != poll) {
if (--wait_cnt == 0) {
@@ -218,8 +364,8 @@
}
udelay(1);
- ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
- CORE_CK_OUT_EN);
+ ck_out_en = !!(readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config) & CORE_CK_OUT_EN);
}
return 0;
@@ -235,16 +381,18 @@
unsigned long flags;
u32 config;
struct mmc_host *mmc = host->mmc;
+ const struct sdhci_msm_offset *msm_offset =
+ sdhci_priv_msm_offset(host);
if (phase > 0xf)
return -EINVAL;
spin_lock_irqsave(&host->lock, flags);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
rc = msm_dll_poll_ck_out_en(host, 0);
@@ -255,24 +403,24 @@
* Write the selected DLL clock output phase (0 ... 15)
* to CDR_SELEXT bit field of DLL_CONFIG register.
*/
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
config &= ~CDR_SELEXT_MASK;
config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
config |= CORE_CK_OUT_EN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
rc = msm_dll_poll_ck_out_en(host, 1);
if (rc)
goto err_out;
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
config |= CORE_CDR_EN;
config &= ~CORE_CDR_EXT_EN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
goto out;
err_out:
@@ -398,6 +546,8 @@
static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
{
u32 mclk_freq = 0, config;
+ const struct sdhci_msm_offset *msm_offset =
+ sdhci_priv_msm_offset(host);
/* Program the MCLK value to MCLK_FREQ bit field */
if (host->clock <= 112000000)
@@ -417,10 +567,10 @@
else if (host->clock <= 200000000)
mclk_freq = 7;
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
config &= ~CMUX_SHIFT_PHASE_MASK;
config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
}
/* Initialize the DLL (Programmable Delay Line) */
@@ -432,6 +582,8 @@
int wait_cnt = 50;
unsigned long flags;
u32 config;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
spin_lock_irqsave(&host->lock, flags);
@@ -440,34 +592,43 @@
* tuning is in progress. Keeping PWRSAVE ON may
* turn off the clock.
*/
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
config &= ~CORE_CLK_PWRSAVE;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
if (msm_host->use_14lpp_dll_reset) {
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config &= ~CORE_CK_OUT_EN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config_2);
config |= CORE_DLL_CLOCK_DISABLE;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config_2);
}
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_DLL_RST;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_DLL_PDN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
msm_cm_dll_set_freq(host);
if (msm_host->use_14lpp_dll_reset &&
!IS_ERR_OR_NULL(msm_host->xo_clk)) {
u32 mclk_freq = 0;
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config_2);
config &= CORE_FLL_CYCLE_CNT;
if (config)
mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
@@ -476,40 +637,52 @@
mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
clk_get_rate(msm_host->xo_clk));
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config_2);
config &= ~(0xFF << 10);
config |= mclk_freq << 10;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config_2);
/* wait for 5us before enabling DLL clock */
udelay(5);
}
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config &= ~CORE_DLL_RST;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config &= ~CORE_DLL_PDN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
if (msm_host->use_14lpp_dll_reset) {
msm_cm_dll_set_freq(host);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config_2);
config &= ~CORE_DLL_CLOCK_DISABLE;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config_2);
}
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_DLL_EN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_CK_OUT_EN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
- while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
+ while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
CORE_DLL_LOCK)) {
/* max. wait for 50us sec for LOCK bit to be set */
if (--wait_cnt == 0) {
@@ -530,19 +703,21 @@
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
u32 config;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
if (!msm_host->use_cdclp533) {
config = readl_relaxed(host->ioaddr +
- CORE_VENDOR_SPEC3);
+ msm_offset->core_vendor_spec3);
config &= ~CORE_PWRSAVE_DLL;
writel_relaxed(config, host->ioaddr +
- CORE_VENDOR_SPEC3);
+ msm_offset->core_vendor_spec3);
}
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
config &= ~CORE_HC_MCLK_SEL_MASK;
config |= CORE_HC_MCLK_SEL_DFLT;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
/*
* Disable HC_SELECT_IN to be able to use the UHS mode select
@@ -551,10 +726,10 @@
* Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
* in VENDOR_SPEC_FUNC
*/
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
config &= ~CORE_HC_SELECT_IN_EN;
config &= ~CORE_HC_SELECT_IN_MASK;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
/*
* Make sure above writes impacting free running MCLK are completed
@@ -570,32 +745,36 @@
struct mmc_ios ios = host->mmc->ios;
u32 config, dll_lock;
int rc;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
/* Select the divided clock (free running MCLK/2) */
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
config &= ~CORE_HC_MCLK_SEL_MASK;
config |= CORE_HC_MCLK_SEL_HS400;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
/*
* Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
* register
*/
if ((msm_host->tuning_done || ios.enhanced_strobe) &&
!msm_host->calibration_done) {
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_vendor_spec);
config |= CORE_HC_SELECT_IN_HS400;
config |= CORE_HC_SELECT_IN_EN;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_vendor_spec);
}
if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
/*
* Poll on DLL_LOCK or DDR_DLL_LOCK bits in
- * CORE_DLL_STATUS to be set. This should get set
+ * core_dll_status to be set. This should get set
* within 15 us at 200 MHz.
*/
rc = readl_relaxed_poll_timeout(host->ioaddr +
- CORE_DLL_STATUS,
+ msm_offset->core_dll_status,
dll_lock,
(dll_lock &
(CORE_DLL_LOCK |
@@ -647,6 +826,8 @@
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
u32 config, calib_done;
int ret;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
@@ -663,13 +844,13 @@
if (ret)
goto out;
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
config |= CORE_CMD_DAT_TRACK_SEL;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
config &= ~CORE_CDC_T4_DLY_SEL;
- writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
@@ -679,9 +860,9 @@
config |= CORE_CDC_SWITCH_RC_EN;
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
- config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
config &= ~CORE_START_CDC_TRAFFIC;
- writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
/* Perform CDC Register Initialization Sequence */
@@ -733,9 +914,9 @@
goto out;
}
- config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
config |= CORE_START_CDC_TRAFFIC;
- writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
out:
pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
__func__, ret);
@@ -747,32 +928,38 @@
struct mmc_host *mmc = host->mmc;
u32 dll_status, config;
int ret;
+ const struct sdhci_msm_offset *msm_offset =
+ sdhci_priv_msm_offset(host);
pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
/*
- * Currently the CORE_DDR_CONFIG register defaults to desired
+ * Currently the core_ddr_config register defaults to desired
* configuration on reset. Currently reprogramming the power on
* reset (POR) value in case it might have been modified by
* bootloaders. In the future, if this changes, then the desired
* values will need to be programmed appropriately.
*/
- writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
+ writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
+ msm_offset->core_ddr_config);
if (mmc->ios.enhanced_strobe) {
- config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_ddr_200_cfg);
config |= CORE_CMDIN_RCLK_EN;
- writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_ddr_200_cfg);
}
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
config |= CORE_DDR_CAL_EN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
- ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
- dll_status,
- (dll_status & CORE_DDR_DLL_LOCK),
- 10, 1000);
+ ret = readl_relaxed_poll_timeout(host->ioaddr +
+ msm_offset->core_dll_status,
+ dll_status,
+ (dll_status & CORE_DDR_DLL_LOCK),
+ 10, 1000);
if (ret == -ETIMEDOUT) {
pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
@@ -780,9 +967,9 @@
goto out;
}
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
config |= CORE_PWRSAVE_DLL;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
/*
* Drain writebuffer to ensure above DLL calibration
@@ -802,6 +989,8 @@
struct mmc_host *mmc = host->mmc;
int ret;
u32 config;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
@@ -819,9 +1008,11 @@
msm_host->saved_tuning_phase);
if (ret)
goto out;
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_CMD_DAT_TRACK_SEL;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
}
if (msm_host->use_cdclp533)
@@ -951,6 +1142,8 @@
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
u16 ctrl_2;
u32 config;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
@@ -991,13 +1184,17 @@
* DLL is not required for clock <= 100MHz
* Thus, make sure DLL it is disabled when not required
*/
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_DLL_RST;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config);
config |= CORE_DLL_PDN;
- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config);
/*
* The DLL needs to be restored and CDCLP533 recalibrated
@@ -1039,7 +1236,9 @@
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
bool done = false;
- u32 val;
+ u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
mmc_hostname(host->mmc), __func__, req_type,
@@ -1048,8 +1247,12 @@
/*
* The power interrupt will not be generated for signal voltage
* switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
+ * Since sdhci-msm-v5, this bit has been removed and SW must consider
+ * it as always set.
*/
- val = readl(msm_host->core_mem + CORE_MCI_GENERICS);
+ if (!msm_host->mci_removed)
+ val = msm_host_readl(msm_host, host,
+ msm_offset->core_generics);
if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
!(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
return;
@@ -1097,12 +1300,14 @@
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ const struct sdhci_msm_offset *msm_offset =
+ msm_host->offset;
pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
- mmc_hostname(host->mmc),
- readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),
- readl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),
- readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));
+ mmc_hostname(host->mmc),
+ msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
+ msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
+ msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
}
static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
@@ -1113,11 +1318,14 @@
int retry = 10;
u32 pwr_state = 0, io_level = 0;
u32 config;
+ const struct sdhci_msm_offset *msm_offset = msm_host->offset;
- irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
+ irq_status = msm_host_readl(msm_host, host,
+ msm_offset->core_pwrctl_status);
irq_status &= INT_MASK;
- writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
+ msm_host_writel(msm_host, irq_status, host,
+ msm_offset->core_pwrctl_clear);
/*
* There is a rare HW scenario where the first clear pulse could be
@@ -1126,8 +1334,8 @@
* sure status register is cleared. Otherwise, this will result in
* a spurious power IRQ resulting in system instability.
*/
- while (irq_status & readl_relaxed(msm_host->core_mem +
- CORE_PWRCTL_STATUS)) {
+ while (irq_status & msm_host_readl(msm_host, host,
+ msm_offset->core_pwrctl_status)) {
if (retry == 0) {
pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
mmc_hostname(host->mmc), irq_status);
@@ -1135,8 +1343,8 @@
WARN_ON(1);
break;
}
- writel_relaxed(irq_status,
- msm_host->core_mem + CORE_PWRCTL_CLEAR);
+ msm_host_writel(msm_host, irq_status, host,
+ msm_offset->core_pwrctl_clear);
retry--;
udelay(10);
}
@@ -1167,7 +1375,8 @@
* report back if it succeded or not to this register. The voltage
* switches are handled by the sdhci core, so just report success.
*/
- writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
+ msm_host_writel(msm_host, irq_ack, host,
+ msm_offset->core_pwrctl_ctl);
/*
* If we don't have info regarding the voltage levels supported by
@@ -1186,7 +1395,8 @@
* controllers with only 1.8V, we will set the IO PAD bit
* without waiting for a REQ_IO_LOW.
*/
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_vendor_spec);
new_config = config;
if ((io_level & REQ_IO_HIGH) &&
@@ -1197,8 +1407,8 @@
new_config |= CORE_IO_PAD_PWR_SWITCH;
if (config ^ new_config)
- writel_relaxed(new_config,
- host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(new_config, host->ioaddr +
+ msm_offset->core_vendor_spec);
}
if (pwr_state)
@@ -1359,6 +1569,7 @@
struct regulator *supply = mmc->supply.vqmmc;
u32 caps = 0, config;
struct sdhci_host *host = mmc_priv(mmc);
+ const struct sdhci_msm_offset *msm_offset = msm_host->offset;
if (!IS_ERR(mmc->supply.vqmmc)) {
if (regulator_is_supported_voltage(supply, 1700000, 1950000))
@@ -1378,7 +1589,8 @@
*/
u32 io_level = msm_host->curr_io_level;
- config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_vendor_spec);
config |= CORE_IO_PAD_PWR_SWITCH_EN;
if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
@@ -1386,14 +1598,38 @@
else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
config |= CORE_IO_PAD_PWR_SWITCH;
- writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ writel_relaxed(config,
+ host->ioaddr + msm_offset->core_vendor_spec);
}
msm_host->caps_0 |= caps;
pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
}
+static const struct sdhci_msm_variant_ops mci_var_ops = {
+ .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
+ .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
+};
+
+static const struct sdhci_msm_variant_ops v5_var_ops = {
+ .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
+ .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
+};
+
+static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
+ .mci_removed = false,
+ .var_ops = &mci_var_ops,
+ .offset = &sdhci_msm_mci_offset,
+};
+
+static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
+ .mci_removed = true,
+ .var_ops = &v5_var_ops,
+ .offset = &sdhci_msm_v5_offset,
+};
+
static const struct of_device_id sdhci_msm_dt_match[] = {
- { .compatible = "qcom,sdhci-msm-v4" },
+ {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
+ {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
{},
};
@@ -1412,7 +1648,6 @@
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
- SDHCI_QUIRK_NO_CARD_NO_RESET |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
@@ -1430,6 +1665,8 @@
u16 host_version, core_minor;
u32 core_version, config;
u8 core_major;
+ const struct sdhci_msm_offset *msm_offset;
+ const struct sdhci_msm_variant_info *var_info;
host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
if (IS_ERR(host))
@@ -1445,6 +1682,18 @@
if (ret)
goto pltfm_free;
+ /*
+ * Based on the compatible string, load the required msm host info from
+ * the data associated with the version info.
+ */
+ var_info = of_device_get_match_data(&pdev->dev);
+
+ msm_host->mci_removed = var_info->mci_removed;
+ msm_host->var_ops = var_info->var_ops;
+ msm_host->offset = var_info->offset;
+
+ msm_offset = msm_host->offset;
+
sdhci_get_of_property(pdev);
msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
@@ -1509,32 +1758,40 @@
dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
}
- core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
+ if (!msm_host->mci_removed) {
+ core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
+ core_memres);
- if (IS_ERR(msm_host->core_mem)) {
- dev_err(&pdev->dev, "Failed to remap registers\n");
- ret = PTR_ERR(msm_host->core_mem);
- goto clk_disable;
+ if (IS_ERR(msm_host->core_mem)) {
+ dev_err(&pdev->dev, "Failed to remap registers\n");
+ ret = PTR_ERR(msm_host->core_mem);
+ goto clk_disable;
+ }
}
/* Reset the vendor spec register to power on reset state */
writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
- host->ioaddr + CORE_VENDOR_SPEC);
+ host->ioaddr + msm_offset->core_vendor_spec);
- /* Set HC_MODE_EN bit in HC_MODE register */
- writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
-
- config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
- config |= FF_CLK_SW_RST_DIS;
- writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
+ if (!msm_host->mci_removed) {
+ /* Set HC_MODE_EN bit in HC_MODE register */
+ msm_host_writel(msm_host, HC_MODE_EN, host,
+ msm_offset->core_hc_mode);
+ config = msm_host_readl(msm_host, host,
+ msm_offset->core_hc_mode);
+ config |= FF_CLK_SW_RST_DIS;
+ msm_host_writel(msm_host, config, host,
+ msm_offset->core_hc_mode);
+ }
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
SDHCI_VENDOR_VER_SHIFT));
- core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
+ core_version = msm_host_readl(msm_host, host,
+ msm_offset->core_mci_version);
core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
CORE_VERSION_MAJOR_SHIFT;
core_minor = core_version & CORE_VERSION_MINOR_MASK;
@@ -1559,7 +1816,7 @@
config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
writel_relaxed(config, host->ioaddr +
- CORE_VENDOR_SPEC_CAPABILITIES0);
+ msm_offset->core_vendor_spec_capabilities0);
}
/*
@@ -1588,7 +1845,8 @@
sdhci_msm_init_pwr_irq_wait(msm_host);
/* Enable pwr irq interrupts */
- writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);
+ msm_host_writel(msm_host, INT_MASK, host,
+ msm_offset->core_pwrctl_mask);
ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
sdhci_msm_pwr_irq, IRQF_ONESHOT,
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index bc8a56e..1bde6ce 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -709,12 +709,15 @@
return sg_dma_address(host->data->sg);
}
-static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
+static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
+ bool *too_big)
{
u8 count;
struct mmc_data *data = cmd->data;
unsigned target_timeout, current_timeout;
+ *too_big = true;
+
/*
* If the host controller provides us with an incorrect timeout
* value, just skip the check and use 0xE. The hardware may take
@@ -768,9 +771,12 @@
}
if (count >= 0xF) {
- DBG("Too large timeout 0x%x requested for CMD%d!\n",
- count, cmd->opcode);
+ if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
+ DBG("Too large timeout 0x%x requested for CMD%d!\n",
+ count, cmd->opcode);
count = 0xE;
+ } else {
+ *too_big = false;
}
return count;
@@ -790,6 +796,16 @@
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
+static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
+{
+ if (enable)
+ host->ier |= SDHCI_INT_DATA_TIMEOUT;
+ else
+ host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+}
+
static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
@@ -797,7 +813,17 @@
if (host->ops->set_timeout) {
host->ops->set_timeout(host, cmd);
} else {
- count = sdhci_calc_timeout(host, cmd);
+ bool too_big = false;
+
+ count = sdhci_calc_timeout(host, cmd, &too_big);
+
+ if (too_big &&
+ host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
+ sdhci_set_data_timeout_irq(host, false);
+ } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
+ sdhci_set_data_timeout_irq(host, true);
+ }
+
sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
}
}
@@ -3390,7 +3416,7 @@
* available.
*/
ret = mmc_regulator_get_supply(mmc);
- if (ret == -EPROBE_DEFER)
+ if (ret)
return ret;
DBG("Version: 0x%08x | Present: 0x%08x\n",
@@ -3596,6 +3622,10 @@
mmc->max_busy_timeout /= host->timeout_clk;
}
+ if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
+ !host->ops->get_max_timeout_count)
+ mmc->max_busy_timeout = 0;
+
mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 1d7d61e..9129c99 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -437,6 +437,11 @@
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
/* Controller has CRC in 136 bit Command Response */
#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
+/*
+ * Disable HW timeout if the requested timeout is more than the maximum
+ * obtainable timeout.
+ */
+#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index d524a64..af3d207 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -42,7 +42,7 @@
#define AMD_BOOTLOC_BUG
#define FORCE_WORD_WRITE 0
-#define MAX_WORD_RETRIES 3
+#define MAX_RETRIES 3
#define SST49LF004B 0x0060
#define SST49LF040B 0x0050
@@ -1647,7 +1647,7 @@
map_write( map, CMD(0xF0), chip->start );
/* FIXME - should have reset delay before continuing */
- if (++retry_cnt <= MAX_WORD_RETRIES)
+ if (++retry_cnt <= MAX_RETRIES)
goto retry;
ret = -EIO;
@@ -1880,7 +1880,7 @@
if (time_after(jiffies, timeo) && !chip_ready(map, adr))
break;
- if (chip_ready(map, adr)) {
+ if (chip_good(map, adr, datum)) {
xip_enable(map, chip, adr);
goto op_done;
}
@@ -2106,7 +2106,7 @@
map_write(map, CMD(0xF0), chip->start);
/* FIXME - should have reset delay before continuing */
- if (++retry_cnt <= MAX_WORD_RETRIES)
+ if (++retry_cnt <= MAX_RETRIES)
goto retry;
ret = -EIO;
@@ -2241,6 +2241,7 @@
unsigned long int adr;
DECLARE_WAITQUEUE(wait, current);
int ret = 0;
+ int retry_cnt = 0;
adr = cfi->addr_unlock1;
@@ -2258,6 +2259,7 @@
ENABLE_VPP(map);
xip_disable(map, chip, adr);
+ retry:
cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
@@ -2294,12 +2296,13 @@
chip->erase_suspended = 0;
}
- if (chip_ready(map, adr))
+ if (chip_good(map, adr, map_word_ff(map)))
break;
if (time_after(jiffies, timeo)) {
printk(KERN_WARNING "MTD %s(): software timeout\n",
__func__ );
+ ret = -EIO;
break;
}
@@ -2307,12 +2310,15 @@
UDELAY(map, chip, adr, 1000000/HZ);
}
/* Did we succeed? */
- if (!chip_good(map, adr, map_word_ff(map))) {
+ if (ret) {
/* reset on all failures. */
map_write( map, CMD(0xF0), chip->start );
/* FIXME - should have reset delay before continuing */
- ret = -EIO;
+ if (++retry_cnt <= MAX_RETRIES) {
+ ret = 0;
+ goto retry;
+ }
}
chip->state = FL_READY;
@@ -2331,6 +2337,7 @@
unsigned long timeo = jiffies + HZ;
DECLARE_WAITQUEUE(wait, current);
int ret = 0;
+ int retry_cnt = 0;
adr += chip->start;
@@ -2348,6 +2355,7 @@
ENABLE_VPP(map);
xip_disable(map, chip, adr);
+ retry:
cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
@@ -2384,7 +2392,7 @@
chip->erase_suspended = 0;
}
- if (chip_ready(map, adr)) {
+ if (chip_good(map, adr, map_word_ff(map))) {
xip_enable(map, chip, adr);
break;
}
@@ -2393,6 +2401,7 @@
xip_enable(map, chip, adr);
printk(KERN_WARNING "MTD %s(): software timeout\n",
__func__ );
+ ret = -EIO;
break;
}
@@ -2400,12 +2409,15 @@
UDELAY(map, chip, adr, 1000000/HZ);
}
/* Did we succeed? */
- if (!chip_good(map, adr, map_word_ff(map))) {
+ if (ret) {
/* reset on all failures. */
map_write( map, CMD(0xF0), chip->start );
/* FIXME - should have reset delay before continuing */
- ret = -EIO;
+ if (++retry_cnt <= MAX_RETRIES) {
+ ret = 0;
+ goto retry;
+ }
}
chip->state = FL_READY;
@@ -2535,7 +2547,7 @@
struct ppb_lock {
struct flchip *chip;
- loff_t offset;
+ unsigned long adr;
int locked;
};
@@ -2553,8 +2565,9 @@
unsigned long timeo;
int ret;
+ adr += chip->start;
mutex_lock(&chip->mutex);
- ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
+ ret = get_chip(map, chip, adr, FL_LOCKING);
if (ret) {
mutex_unlock(&chip->mutex);
return ret;
@@ -2572,8 +2585,8 @@
if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
chip->state = FL_LOCKING;
- map_write(map, CMD(0xA0), chip->start + adr);
- map_write(map, CMD(0x00), chip->start + adr);
+ map_write(map, CMD(0xA0), adr);
+ map_write(map, CMD(0x00), adr);
} else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
/*
* Unlocking of one specific sector is not supported, so we
@@ -2611,7 +2624,7 @@
map_write(map, CMD(0x00), chip->start);
chip->state = FL_READY;
- put_chip(map, chip, adr + chip->start);
+ put_chip(map, chip, adr);
mutex_unlock(&chip->mutex);
return ret;
@@ -2668,9 +2681,9 @@
* sectors shall be unlocked, so lets keep their locking
* status at "unlocked" (locked=0) for the final re-locking.
*/
- if ((adr < ofs) || (adr >= (ofs + len))) {
+ if ((offset < ofs) || (offset >= (ofs + len))) {
sect[sectors].chip = &cfi->chips[chipnum];
- sect[sectors].offset = offset;
+ sect[sectors].adr = adr;
sect[sectors].locked = do_ppb_xxlock(
map, &cfi->chips[chipnum], adr, 0,
DO_XXLOCK_ONEBLOCK_GETLOCK);
@@ -2684,6 +2697,8 @@
i++;
if (adr >> cfi->chipshift) {
+ if (offset >= (ofs + len))
+ break;
adr = 0;
chipnum++;
@@ -2714,7 +2729,7 @@
*/
for (i = 0; i < sectors; i++) {
if (sect[i].locked)
- do_ppb_xxlock(map, sect[i].chip, sect[i].offset, 0,
+ do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
DO_XXLOCK_ONEBLOCK_LOCK);
}
diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 6def544..57b02c4b 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -81,6 +81,7 @@
config MTD_M25P80
tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
depends on SPI_MASTER && MTD_SPI_NOR
+ select SPI_MEM
help
This enables access to most modern SPI flash chips, used for
program and data storage. Series supported include Atmel AT26DF,
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 00eea6f..e84563d 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -24,12 +24,13 @@
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
#include <linux/spi/flash.h>
#include <linux/mtd/spi-nor.h>
#define MAX_CMD_SIZE 6
struct m25p {
- struct spi_device *spi;
+ struct spi_mem *spimem;
struct spi_nor spi_nor;
u8 command[MAX_CMD_SIZE];
};
@@ -37,97 +38,68 @@
static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
{
struct m25p *flash = nor->priv;
- struct spi_device *spi = flash->spi;
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(len, val, 1));
int ret;
- ret = spi_write_then_read(spi, &code, 1, val, len);
+ ret = spi_mem_exec_op(flash->spimem, &op);
if (ret < 0)
- dev_err(&spi->dev, "error %d reading %x\n", ret, code);
+ dev_err(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
+ code);
return ret;
}
-static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
-{
- /* opcode is in cmd[0] */
- cmd[1] = addr >> (nor->addr_width * 8 - 8);
- cmd[2] = addr >> (nor->addr_width * 8 - 16);
- cmd[3] = addr >> (nor->addr_width * 8 - 24);
- cmd[4] = addr >> (nor->addr_width * 8 - 32);
-}
-
-static int m25p_cmdsz(struct spi_nor *nor)
-{
- return 1 + nor->addr_width;
-}
-
static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
struct m25p *flash = nor->priv;
- struct spi_device *spi = flash->spi;
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(len, buf, 1));
- flash->command[0] = opcode;
- if (buf)
- memcpy(&flash->command[1], buf, len);
-
- return spi_write(spi, flash->command, len + 1);
+ return spi_mem_exec_op(flash->spimem, &op);
}
static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
const u_char *buf)
{
struct m25p *flash = nor->priv;
- struct spi_device *spi = flash->spi;
- unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;
- struct spi_transfer t[3] = {};
- struct spi_message m;
- int cmd_sz = m25p_cmdsz(nor);
- ssize_t ret;
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
+ SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
+ SPI_MEM_OP_DUMMY(0, 1),
+ SPI_MEM_OP_DATA_OUT(len, buf, 1));
+ size_t remaining = len;
+ int ret;
/* get transfer protocols. */
- inst_nbits = spi_nor_get_protocol_inst_nbits(nor->write_proto);
- addr_nbits = spi_nor_get_protocol_addr_nbits(nor->write_proto);
- data_nbits = spi_nor_get_protocol_data_nbits(nor->write_proto);
-
- spi_message_init(&m);
+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
+ op.dummy.buswidth = op.addr.buswidth;
+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
- cmd_sz = 1;
+ op.addr.nbytes = 0;
- flash->command[0] = nor->program_opcode;
- m25p_addr2cmd(nor, to, flash->command);
+ while (remaining) {
+ op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
+ ret = spi_mem_adjust_op_size(flash->spimem, &op);
+ if (ret)
+ return ret;
- t[0].tx_buf = flash->command;
- t[0].tx_nbits = inst_nbits;
- t[0].len = cmd_sz;
- spi_message_add_tail(&t[0], &m);
+ ret = spi_mem_exec_op(flash->spimem, &op);
+ if (ret)
+ return ret;
- /* split the op code and address bytes into two transfers if needed. */
- data_idx = 1;
- if (addr_nbits != inst_nbits) {
- t[0].len = 1;
-
- t[1].tx_buf = &flash->command[1];
- t[1].tx_nbits = addr_nbits;
- t[1].len = cmd_sz - 1;
- spi_message_add_tail(&t[1], &m);
-
- data_idx = 2;
+ op.addr.val += op.data.nbytes;
+ remaining -= op.data.nbytes;
+ op.data.buf.out += op.data.nbytes;
}
- t[data_idx].tx_buf = buf;
- t[data_idx].tx_nbits = data_nbits;
- t[data_idx].len = len;
- spi_message_add_tail(&t[data_idx], &m);
-
- ret = spi_sync(spi, &m);
- if (ret)
- return ret;
-
- ret = m.actual_length - cmd_sz;
- if (ret < 0)
- return -EIO;
- return ret;
+ return len;
}
/*
@@ -138,92 +110,39 @@
u_char *buf)
{
struct m25p *flash = nor->priv;
- struct spi_device *spi = flash->spi;
- unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;
- struct spi_transfer t[3];
- struct spi_message m;
- unsigned int dummy = nor->read_dummy;
- ssize_t ret;
- int cmd_sz;
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
+ SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
+ SPI_MEM_OP_DATA_IN(len, buf, 1));
+ size_t remaining = len;
+ int ret;
/* get transfer protocols. */
- inst_nbits = spi_nor_get_protocol_inst_nbits(nor->read_proto);
- addr_nbits = spi_nor_get_protocol_addr_nbits(nor->read_proto);
- data_nbits = spi_nor_get_protocol_data_nbits(nor->read_proto);
+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
+ op.dummy.buswidth = op.addr.buswidth;
+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
/* convert the dummy cycles to the number of bytes */
- dummy = (dummy * addr_nbits) / 8;
+ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
- if (spi_flash_read_supported(spi)) {
- struct spi_flash_read_message msg;
-
- memset(&msg, 0, sizeof(msg));
-
- msg.buf = buf;
- msg.from = from;
- msg.len = len;
- msg.read_opcode = nor->read_opcode;
- msg.addr_width = nor->addr_width;
- msg.dummy_bytes = dummy;
- msg.opcode_nbits = inst_nbits;
- msg.addr_nbits = addr_nbits;
- msg.data_nbits = data_nbits;
-
- ret = spi_flash_read(spi, &msg);
- if (ret < 0)
+ while (remaining) {
+ op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
+ ret = spi_mem_adjust_op_size(flash->spimem, &op);
+ if (ret)
return ret;
- return msg.retlen;
+
+ ret = spi_mem_exec_op(flash->spimem, &op);
+ if (ret)
+ return ret;
+
+ op.addr.val += op.data.nbytes;
+ remaining -= op.data.nbytes;
+ op.data.buf.in += op.data.nbytes;
}
- spi_message_init(&m);
- memset(t, 0, (sizeof t));
-
- flash->command[0] = nor->read_opcode;
- m25p_addr2cmd(nor, from, flash->command);
-
- t[0].tx_buf = flash->command;
- t[0].tx_nbits = inst_nbits;
- t[0].len = m25p_cmdsz(nor) + dummy;
- spi_message_add_tail(&t[0], &m);
-
- /*
- * Set all dummy/mode cycle bits to avoid sending some manufacturer
- * specific pattern, which might make the memory enter its Continuous
- * Read mode by mistake.
- * Based on the different mode cycle bit patterns listed and described
- * in the JESD216B specification, the 0xff value works for all memories
- * and all manufacturers.
- */
- cmd_sz = t[0].len;
- memset(flash->command + cmd_sz - dummy, 0xff, dummy);
-
- /* split the op code and address bytes into two transfers if needed. */
- data_idx = 1;
- if (addr_nbits != inst_nbits) {
- t[0].len = 1;
-
- t[1].tx_buf = &flash->command[1];
- t[1].tx_nbits = addr_nbits;
- t[1].len = cmd_sz - 1;
- spi_message_add_tail(&t[1], &m);
-
- data_idx = 2;
- }
-
- t[data_idx].rx_buf = buf;
- t[data_idx].rx_nbits = data_nbits;
- t[data_idx].len = min3(len, spi_max_transfer_size(spi),
- spi_max_message_size(spi) - cmd_sz);
- spi_message_add_tail(&t[data_idx], &m);
-
- ret = spi_sync(spi, &m);
- if (ret)
- return ret;
-
- ret = m.actual_length - cmd_sz;
- if (ret < 0)
- return -EIO;
- return ret;
+ return len;
}
/*
@@ -231,8 +150,9 @@
* matches what the READ command supports, at least until this driver
* understands FAST_READ (for clocks over 25 MHz).
*/
-static int m25p_probe(struct spi_device *spi)
+static int m25p_probe(struct spi_mem *spimem)
{
+ struct spi_device *spi = spimem->spi;
struct flash_platform_data *data;
struct m25p *flash;
struct spi_nor *nor;
@@ -244,9 +164,9 @@
char *flash_name;
int ret;
- data = dev_get_platdata(&spi->dev);
+ data = dev_get_platdata(&spimem->spi->dev);
- flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
+ flash = devm_kzalloc(&spimem->spi->dev, sizeof(*flash), GFP_KERNEL);
if (!flash)
return -ENOMEM;
@@ -258,12 +178,12 @@
nor->write_reg = m25p80_write_reg;
nor->read_reg = m25p80_read_reg;
- nor->dev = &spi->dev;
+ nor->dev = &spimem->spi->dev;
spi_nor_set_flash_node(nor, spi->dev.of_node);
nor->priv = flash;
- spi_set_drvdata(spi, flash);
- flash->spi = spi;
+ spi_mem_set_drvdata(spimem, flash);
+ flash->spimem = spimem;
if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
@@ -303,14 +223,22 @@
}
-static int m25p_remove(struct spi_device *spi)
+static int m25p_remove(struct spi_mem *spimem)
{
- struct m25p *flash = spi_get_drvdata(spi);
+ struct m25p *flash = spi_mem_get_drvdata(spimem);
+
+ spi_nor_restore(&flash->spi_nor);
/* Clean up MTD stuff. */
return mtd_device_unregister(&flash->spi_nor.mtd);
}
+static void m25p_shutdown(struct spi_mem *spimem)
+{
+ struct m25p *flash = spi_mem_get_drvdata(spimem);
+
+ spi_nor_restore(&flash->spi_nor);
+}
/*
* Do NOT add to this array without reading the following:
*
@@ -359,6 +287,7 @@
{"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
/* Everspin MRAMs (non-JEDEC) */
+ { "mr25h128" }, /* 128 Kib, 40 MHz */
{ "mr25h256" }, /* 256 Kib, 40 MHz */
{ "mr25h10" }, /* 1 Mib, 40 MHz */
{ "mr25h40" }, /* 4 Mib, 40 MHz */
@@ -377,14 +306,17 @@
};
MODULE_DEVICE_TABLE(of, m25p_of_table);
-static struct spi_driver m25p80_driver = {
- .driver = {
- .name = "m25p80",
- .of_match_table = m25p_of_table,
+static struct spi_mem_driver m25p80_driver = {
+ .spidrv = {
+ .driver = {
+ .name = "m25p80",
+ .of_match_table = m25p_of_table,
+ },
+ .id_table = m25p_ids,
},
- .id_table = m25p_ids,
.probe = m25p_probe,
.remove = m25p_remove,
+ .shutdown = m25p_shutdown,
/* REVISIT: many of these chips have deep power-down modes, which
* should clearly be entered on suspend() to minimize power use.
@@ -392,7 +324,7 @@
*/
};
-module_spi_driver(m25p80_driver);
+module_spi_mem_driver(m25p80_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mike Lavender");
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 53e5e03..fcb575d 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -48,7 +48,7 @@
#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
-#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
+#define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
#define NFC_V1_V2_WRPROT (host->regs + 0x12)
#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
@@ -1119,6 +1119,9 @@
writew(config1, NFC_V1_V2_CONFIG1);
/* preset operation */
+ /* spare area size in 16-bit half-words */
+ writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
+
/* Unlock the internal RAM Buffer */
writew(0x2, NFC_V1_V2_CONFIG);
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 528e04f..d410de3 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -440,7 +440,7 @@
for (; page < page_end; page++) {
res = chip->ecc.read_oob(mtd, chip, page);
- if (res)
+ if (res < 0)
return res;
bad = chip->oob_poi[chip->badblockpos];
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 34e04f4..3f464b9 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -996,6 +996,7 @@
{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
/* Everspin */
+ { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
{ "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
@@ -2662,17 +2663,70 @@
/* Enable Quad I/O if needed. */
enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
spi_nor_get_protocol_width(nor->write_proto) == 4);
- if (enable_quad_io && params->quad_enable) {
- err = params->quad_enable(nor);
+ if (enable_quad_io && params->quad_enable)
+ nor->quad_enable = params->quad_enable;
+ else
+ nor->quad_enable = NULL;
+
+ return 0;
+}
+
+static int spi_nor_init(struct spi_nor *nor)
+{
+ int err;
+
+ /*
+ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
+ * with the software protection bits set
+ */
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
+ nor->info->flags & SPI_NOR_HAS_LOCK) {
+ write_enable(nor);
+ write_sr(nor, 0);
+ spi_nor_wait_till_ready(nor);
+ }
+
+ if (nor->quad_enable) {
+ err = nor->quad_enable(nor);
if (err) {
dev_err(nor->dev, "quad mode not supported\n");
return err;
}
}
+ if ((nor->addr_width == 4) &&
+ (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
+ !(nor->info->flags & SPI_NOR_4B_OPCODES))
+ set_4byte(nor, nor->info, 1);
+
return 0;
}
+/* mtd resume handler */
+static void spi_nor_resume(struct mtd_info *mtd)
+{
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ struct device *dev = nor->dev;
+ int ret;
+
+ /* re-initialize the nor chip */
+ ret = spi_nor_init(nor);
+ if (ret)
+ dev_err(dev, "resume() failed\n");
+}
+
+void spi_nor_restore(struct spi_nor *nor)
+{
+ /* restore the addressing mode */
+ if ((nor->addr_width == 4) &&
+ (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
+ !(nor->info->flags & SPI_NOR_4B_OPCODES))
+ set_4byte(nor, nor->info, 0);
+}
+EXPORT_SYMBOL_GPL(spi_nor_restore);
+
int spi_nor_scan(struct spi_nor *nor, const char *name,
const struct spi_nor_hwcaps *hwcaps)
{
@@ -2740,20 +2794,6 @@
if (ret)
return ret;
- /*
- * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
- * with the software protection bits set
- */
-
- if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
- JEDEC_MFR(info) == SNOR_MFR_INTEL ||
- JEDEC_MFR(info) == SNOR_MFR_SST ||
- info->flags & SPI_NOR_HAS_LOCK) {
- write_enable(nor);
- write_sr(nor, 0);
- spi_nor_wait_till_ready(nor);
- }
-
if (!mtd->name)
mtd->name = dev_name(dev);
mtd->priv = nor;
@@ -2763,6 +2803,7 @@
mtd->size = params.size;
mtd->_erase = spi_nor_erase;
mtd->_read = spi_nor_read;
+ mtd->_resume = spi_nor_resume;
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
@@ -2836,8 +2877,6 @@
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
info->flags & SPI_NOR_4B_OPCODES)
spi_nor_set_4byte_opcodes(nor, info);
- else
- set_4byte(nor, info, 1);
} else {
nor->addr_width = 3;
}
@@ -2854,6 +2893,12 @@
return ret;
}
+ /* Send all the required SPI flash commands to initialize device */
+ nor->info = info;
+ ret = spi_nor_init(nor);
+ if (ret)
+ return ret;
+
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
(long long)mtd->size >> 10);
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index defb1cd8..18a72da 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -1082,6 +1082,9 @@
if (ubi->bgt_thread)
kthread_stop(ubi->bgt_thread);
+#ifdef CONFIG_MTD_UBI_FASTMAP
+ cancel_work_sync(&ubi->fm_work);
+#endif
ubi_debugfs_exit_dev(ubi);
uif_close(ubi);
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 388e46b..d0884bd 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -490,6 +490,82 @@
return err;
}
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * check_mapping - check and fixup a mapping
+ * @ubi: UBI device description object
+ * @vol: volume description object
+ * @lnum: logical eraseblock number
+ * @pnum: physical eraseblock number
+ *
+ * Checks whether a given mapping is valid. Fastmap cannot track LEB unmap
+ * operations, if such an operation is interrupted the mapping still looks
+ * good, but upon first read an ECC is reported to the upper layer.
+ * Normaly during the full-scan at attach time this is fixed, for Fastmap
+ * we have to deal with it while reading.
+ * If the PEB behind a LEB shows this symthom we change the mapping to
+ * %UBI_LEB_UNMAPPED and schedule the PEB for erasure.
+ *
+ * Returns 0 on success, negative error code in case of failure.
+ */
+static int check_mapping(struct ubi_device *ubi, struct ubi_volume *vol, int lnum,
+ int *pnum)
+{
+ int err;
+ struct ubi_vid_io_buf *vidb;
+
+ if (!ubi->fast_attach)
+ return 0;
+
+ vidb = ubi_alloc_vid_buf(ubi, GFP_NOFS);
+ if (!vidb)
+ return -ENOMEM;
+
+ err = ubi_io_read_vid_hdr(ubi, *pnum, vidb, 0);
+ if (err > 0 && err != UBI_IO_BITFLIPS) {
+ int torture = 0;
+
+ switch (err) {
+ case UBI_IO_FF:
+ case UBI_IO_FF_BITFLIPS:
+ case UBI_IO_BAD_HDR:
+ case UBI_IO_BAD_HDR_EBADMSG:
+ break;
+ default:
+ ubi_assert(0);
+ }
+
+ if (err == UBI_IO_BAD_HDR_EBADMSG || err == UBI_IO_FF_BITFLIPS)
+ torture = 1;
+
+ down_read(&ubi->fm_eba_sem);
+ vol->eba_tbl->entries[lnum].pnum = UBI_LEB_UNMAPPED;
+ up_read(&ubi->fm_eba_sem);
+ ubi_wl_put_peb(ubi, vol->vol_id, lnum, *pnum, torture);
+
+ *pnum = UBI_LEB_UNMAPPED;
+ } else if (err < 0) {
+ ubi_err(ubi, "unable to read VID header back from PEB %i: %i",
+ *pnum, err);
+
+ goto out_free;
+ }
+
+ err = 0;
+
+out_free:
+ ubi_free_vid_buf(vidb);
+
+ return err;
+}
+#else
+static int check_mapping(struct ubi_device *ubi, struct ubi_volume *vol, int lnum,
+ int *pnum)
+{
+ return 0;
+}
+#endif
+
/**
* ubi_eba_read_leb - read data.
* @ubi: UBI device description object
@@ -522,7 +598,13 @@
return err;
pnum = vol->eba_tbl->entries[lnum].pnum;
- if (pnum < 0) {
+ if (pnum >= 0) {
+ err = check_mapping(ubi, vol, lnum, &pnum);
+ if (err < 0)
+ goto out_unlock;
+ }
+
+ if (pnum == UBI_LEB_UNMAPPED) {
/*
* The logical eraseblock is not mapped, fill the whole buffer
* with 0xFF bytes. The exception is static volumes for which
@@ -931,6 +1013,12 @@
pnum = vol->eba_tbl->entries[lnum].pnum;
if (pnum >= 0) {
+ err = check_mapping(ubi, vol, lnum, &pnum);
+ if (err < 0)
+ goto out;
+ }
+
+ if (pnum >= 0) {
dbg_eba("write %d bytes at offset %d of LEB %d:%d, PEB %d",
len, offset, vol_id, lnum, pnum);
diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index 668b462..23a6986 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -1505,6 +1505,7 @@
}
dbg_wl("background thread \"%s\" is killed", ubi->bgt_name);
+ ubi->thread_enabled = 0;
return 0;
}
@@ -1514,9 +1515,6 @@
*/
static void shutdown_work(struct ubi_device *ubi)
{
-#ifdef CONFIG_MTD_UBI_FASTMAP
- flush_work(&ubi->fm_work);
-#endif
while (!list_empty(&ubi->works)) {
struct ubi_work *wrk;
diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
index 274f367..acf64d4 100644
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
@@ -1550,6 +1550,18 @@
.duplex_reg = B53_DUPLEX_STAT_FE,
},
{
+ .chip_id = BCM5389_DEVICE_ID,
+ .dev_name = "BCM5389",
+ .vlans = 4096,
+ .enabled_ports = 0x1f,
+ .arl_entries = 4,
+ .cpu_port = B53_CPU_PORT,
+ .vta_regs = B53_VTA_REGS,
+ .duplex_reg = B53_DUPLEX_STAT_GE,
+ .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
+ .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
+ },
+ {
.chip_id = BCM5395_DEVICE_ID,
.dev_name = "BCM5395",
.vlans = 4096,
@@ -1872,6 +1884,7 @@
else
dev->chip_id = BCM5365_DEVICE_ID;
break;
+ case BCM5389_DEVICE_ID:
case BCM5395_DEVICE_ID:
case BCM5397_DEVICE_ID:
case BCM5398_DEVICE_ID:
diff --git a/drivers/net/dsa/b53/b53_mdio.c b/drivers/net/dsa/b53/b53_mdio.c
index fa7556f..a533a90 100644
--- a/drivers/net/dsa/b53/b53_mdio.c
+++ b/drivers/net/dsa/b53/b53_mdio.c
@@ -285,6 +285,7 @@
#define B53_BRCM_OUI_1 0x0143bc00
#define B53_BRCM_OUI_2 0x03625c00
#define B53_BRCM_OUI_3 0x00406000
+#define B53_BRCM_OUI_4 0x01410c00
static int b53_mdio_probe(struct mdio_device *mdiodev)
{
@@ -311,7 +312,8 @@
*/
if ((phy_id & 0xfffffc00) != B53_BRCM_OUI_1 &&
(phy_id & 0xfffffc00) != B53_BRCM_OUI_2 &&
- (phy_id & 0xfffffc00) != B53_BRCM_OUI_3) {
+ (phy_id & 0xfffffc00) != B53_BRCM_OUI_3 &&
+ (phy_id & 0xfffffc00) != B53_BRCM_OUI_4) {
dev_err(&mdiodev->dev, "Unsupported device: 0x%08x\n", phy_id);
return -ENODEV;
}
@@ -360,6 +362,7 @@
{ .compatible = "brcm,bcm53125" },
{ .compatible = "brcm,bcm53128" },
{ .compatible = "brcm,bcm5365" },
+ { .compatible = "brcm,bcm5389" },
{ .compatible = "brcm,bcm5395" },
{ .compatible = "brcm,bcm5397" },
{ .compatible = "brcm,bcm5398" },
diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h
index 01bd8cb..6b9e39d 100644
--- a/drivers/net/dsa/b53/b53_priv.h
+++ b/drivers/net/dsa/b53/b53_priv.h
@@ -48,6 +48,7 @@
enum {
BCM5325_DEVICE_ID = 0x25,
BCM5365_DEVICE_ID = 0x65,
+ BCM5389_DEVICE_ID = 0x89,
BCM5395_DEVICE_ID = 0x95,
BCM5397_DEVICE_ID = 0x97,
BCM5398_DEVICE_ID = 0x98,
diff --git a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
index 5b4f058..519a021 100644
--- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
@@ -2863,7 +2863,7 @@
struct device *dev;
int err;
- dev = pdev->dev.parent;
+ dev = &pdev->dev;
net_dev = dev_get_drvdata(dev);
priv = netdev_priv(net_dev);
diff --git a/drivers/net/ethernet/natsemi/sonic.c b/drivers/net/ethernet/natsemi/sonic.c
index 612c7a4..2382154 100644
--- a/drivers/net/ethernet/natsemi/sonic.c
+++ b/drivers/net/ethernet/natsemi/sonic.c
@@ -71,7 +71,7 @@
for (i = 0; i < SONIC_NUM_RRS; i++) {
dma_addr_t laddr = dma_map_single(lp->device, skb_put(lp->rx_skb[i], SONIC_RBSIZE),
SONIC_RBSIZE, DMA_FROM_DEVICE);
- if (!laddr) {
+ if (dma_mapping_error(lp->device, laddr)) {
while(i > 0) { /* free any that were mapped successfully */
i--;
dma_unmap_single(lp->device, lp->rx_laddr[i], SONIC_RBSIZE, DMA_FROM_DEVICE);
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 009bdc0..3c21f57 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -1103,6 +1103,7 @@
{QMI_FIXED_INTF(0x05c6, 0x920d, 5)},
{QMI_QUIRK_SET_DTR(0x05c6, 0x9625, 4)}, /* YUGA CLM920-NC5 */
{QMI_FIXED_INTF(0x0846, 0x68a2, 8)},
+ {QMI_FIXED_INTF(0x0846, 0x68d3, 8)}, /* Netgear Aircard 779S */
{QMI_FIXED_INTF(0x12d1, 0x140c, 1)}, /* Huawei E173 */
{QMI_FIXED_INTF(0x12d1, 0x14ac, 1)}, /* Huawei E1820 */
{QMI_FIXED_INTF(0x1435, 0xd181, 3)}, /* Wistron NeWeb D18Q1 */
diff --git a/drivers/net/wireless/ath/ath10k/Kconfig b/drivers/net/wireless/ath/ath10k/Kconfig
index 84f071a..54ff593 100644
--- a/drivers/net/wireless/ath/ath10k/Kconfig
+++ b/drivers/net/wireless/ath/ath10k/Kconfig
@@ -1,15 +1,15 @@
config ATH10K
- tristate "Atheros 802.11ac wireless cards support"
- depends on MAC80211 && HAS_DMA
+ tristate "Atheros 802.11ac wireless cards support"
+ depends on MAC80211 && HAS_DMA
select ATH_COMMON
select CRC32
select WANT_DEV_COREDUMP
select ATH10K_CE
- ---help---
- This module adds support for wireless adapters based on
- Atheros IEEE 802.11ac family of chipsets.
+ ---help---
+ This module adds support for wireless adapters based on
+ Atheros IEEE 802.11ac family of chipsets.
- If you choose to build a module, it'll be called ath10k.
+ If you choose to build a module, it'll be called ath10k.
config ATH10K_CE
bool
@@ -41,12 +41,12 @@
work in progress and will not fully work.
config ATH10K_SNOC
- tristate "Qualcomm ath10k SNOC support (EXPERIMENTAL)"
- depends on ATH10K && ARCH_QCOM
- ---help---
- This module adds support for integrated WCN3990 chip connected
- to system NOC(SNOC). Currently work in progress and will not
- fully work.
+ tristate "Qualcomm ath10k SNOC support (EXPERIMENTAL)"
+ depends on ATH10K && ARCH_QCOM
+ ---help---
+ This module adds support for integrated WCN3990 chip connected
+ to system NOC(SNOC). Currently work in progress and will not
+ fully work.
config ATH10K_DEBUG
bool "Atheros ath10k debugging"
diff --git a/drivers/net/wireless/ath/ath10k/ce.h b/drivers/net/wireless/ath/ath10k/ce.h
index 0e70a072..ed96dbf 100644
--- a/drivers/net/wireless/ath/ath10k/ce.h
+++ b/drivers/net/wireless/ath/ath10k/ce.h
@@ -368,4 +368,46 @@
return CE_INTERRUPT_SUMMARY;
}
+/* Host software's Copy Engine configuration. */
+#define CE_ATTR_FLAGS 0
+
+/*
+ * Configuration information for a Copy Engine pipe.
+ * Passed from Host to Target during startup (one per CE).
+ *
+ * NOTE: Structure is shared between Host software and Target firmware!
+ */
+struct ce_pipe_config {
+ __le32 pipenum;
+ __le32 pipedir;
+ __le32 nentries;
+ __le32 nbytes_max;
+ __le32 flags;
+ __le32 reserved;
+};
+
+/*
+ * Directions for interconnect pipe configuration.
+ * These definitions may be used during configuration and are shared
+ * between Host and Target.
+ *
+ * Pipe Directions are relative to the Host, so PIPEDIR_IN means
+ * "coming IN over air through Target to Host" as with a WiFi Rx operation.
+ * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
+ * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
+ * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
+ * over the interconnect.
+ */
+#define PIPEDIR_NONE 0
+#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
+#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
+#define PIPEDIR_INOUT 3 /* bidirectional */
+
+/* Establish a mapping between a service/direction and a pipe. */
+struct service_to_pipe {
+ __le32 service_id;
+ __le32 pipedir;
+ __le32 pipenum;
+};
+
#endif /* _CE_H_ */
diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h
index 652bb050..7597d79 100644
--- a/drivers/net/wireless/ath/ath10k/pci.h
+++ b/drivers/net/wireless/ath/ath10k/pci.h
@@ -86,48 +86,6 @@
/* PCIE_CONFIG_FLAG definitions */
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
-/* Host software's Copy Engine configuration. */
-#define CE_ATTR_FLAGS 0
-
-/*
- * Configuration information for a Copy Engine pipe.
- * Passed from Host to Target during startup (one per CE).
- *
- * NOTE: Structure is shared between Host software and Target firmware!
- */
-struct ce_pipe_config {
- __le32 pipenum;
- __le32 pipedir;
- __le32 nentries;
- __le32 nbytes_max;
- __le32 flags;
- __le32 reserved;
-};
-
-/*
- * Directions for interconnect pipe configuration.
- * These definitions may be used during configuration and are shared
- * between Host and Target.
- *
- * Pipe Directions are relative to the Host, so PIPEDIR_IN means
- * "coming IN over air through Target to Host" as with a WiFi Rx operation.
- * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
- * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
- * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
- * over the interconnect.
- */
-#define PIPEDIR_NONE 0
-#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
-#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
-#define PIPEDIR_INOUT 3 /* bidirectional */
-
-/* Establish a mapping between a service/direction and a pipe. */
-struct service_to_pipe {
- __le32 service_id;
- __le32 pipedir;
- __le32 pipenum;
-};
-
/* Per-pipe state. */
struct ath10k_pci_pipe {
/* Handle of underlying Copy Engine */
diff --git a/drivers/net/wireless/ath/ath10k/snoc.c b/drivers/net/wireless/ath/ath10k/snoc.c
index 2e490ff..293f511 100644
--- a/drivers/net/wireless/ath/ath10k/snoc.c
+++ b/drivers/net/wireless/ath/ath10k/snoc.c
@@ -14,19 +14,20 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-#include <linux/module.h>
+#include <linux/clk.h>
#include <linux/kernel.h>
-#include "debug.h"
-#include "hif.h"
-#include "htc.h"
-#include "ce.h"
-#include "snoc.h"
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
-#include <linux/clk.h>
-#define WCN3990_CE_ATTR_FLAGS 0
+
+#include "ce.h"
+#include "debug.h"
+#include "hif.h"
+#include "htc.h"
+#include "snoc.h"
+
#define ATH10K_SNOC_RX_POST_RETRY_MS 50
#define CE_POLL_PIPE 4
@@ -449,7 +450,7 @@
static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
{
- struct ath10k_pci *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
+ struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
struct ath10k *ar = ar_snoc->ar;
ath10k_snoc_rx_post(ar);
@@ -817,7 +818,7 @@
.write32 = ath10k_snoc_write32,
};
-int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
+static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
{
struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
int i;
@@ -865,7 +866,7 @@
return done;
}
-void ath10k_snoc_init_napi(struct ath10k *ar)
+static void ath10k_snoc_init_napi(struct ath10k *ar)
{
netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll,
ATH10K_NAPI_BUDGET);
@@ -1300,13 +1301,13 @@
ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
ar->ce_priv = &ar_snoc->ce;
- ath10k_snoc_resource_init(ar);
+ ret = ath10k_snoc_resource_init(ar);
if (ret) {
ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
goto err_core_destroy;
}
- ath10k_snoc_setup_resource(ar);
+ ret = ath10k_snoc_setup_resource(ar);
if (ret) {
ath10k_warn(ar, "failed to setup resource: %d\n", ret);
goto err_core_destroy;
@@ -1386,25 +1387,7 @@
.of_match_table = ath10k_snoc_dt_match,
},
};
-
-static int __init ath10k_snoc_init(void)
-{
- int ret;
-
- ret = platform_driver_register(&ath10k_snoc_driver);
- if (ret)
- pr_err("failed to register ath10k snoc driver: %d\n",
- ret);
-
- return ret;
-}
-module_init(ath10k_snoc_init);
-
-static void __exit ath10k_snoc_exit(void)
-{
- platform_driver_unregister(&ath10k_snoc_driver);
-}
-module_exit(ath10k_snoc_exit);
+module_platform_driver(ath10k_snoc_driver);
MODULE_AUTHOR("Qualcomm");
MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ath/ath10k/snoc.h b/drivers/net/wireless/ath/ath10k/snoc.h
index 05dc98f..f9e5301 100644
--- a/drivers/net/wireless/ath/ath10k/snoc.h
+++ b/drivers/net/wireless/ath/ath10k/snoc.h
@@ -19,7 +19,6 @@
#include "hw.h"
#include "ce.h"
-#include "pci.h"
struct ath10k_snoc_drv_priv {
enum ath10k_hw_rev hw_rev;
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
index 12a9b86..dffa697 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
@@ -1499,14 +1499,13 @@
struct iwl_trans *trans)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
- int max_irqs, num_irqs, i, ret, nr_online_cpus;
+ int max_irqs, num_irqs, i, ret;
u16 pci_cmd;
if (!trans->cfg->mq_rx_supported)
goto enable_msi;
- nr_online_cpus = num_online_cpus();
- max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
+ max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
for (i = 0; i < max_irqs; i++)
trans_pcie->msix_entries[i].entry = i;
@@ -1532,16 +1531,17 @@
* Two interrupts less: non rx causes shared with FBQ and RSS.
* More than two interrupts: we will use fewer RSS queues.
*/
- if (num_irqs <= nr_online_cpus) {
+ if (num_irqs <= max_irqs - 2) {
trans_pcie->trans->num_rx_queues = num_irqs + 1;
trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
IWL_SHARED_IRQ_FIRST_RSS;
- } else if (num_irqs == nr_online_cpus + 1) {
+ } else if (num_irqs == max_irqs - 1) {
trans_pcie->trans->num_rx_queues = num_irqs;
trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
} else {
trans_pcie->trans->num_rx_queues = num_irqs - 1;
}
+ WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
trans_pcie->alloc_vecs = num_irqs;
trans_pcie->msix_enabled = true;
diff --git a/drivers/nvdimm/bus.c b/drivers/nvdimm/bus.c
index baf2839..2fffd42 100644
--- a/drivers/nvdimm/bus.c
+++ b/drivers/nvdimm/bus.c
@@ -565,14 +565,18 @@
{
struct device *dev = disk_to_dev(disk)->parent;
struct nd_region *nd_region = to_nd_region(dev->parent);
- const char *pol = nd_region->ro ? "only" : "write";
+ int disk_ro = get_disk_ro(disk);
- if (nd_region->ro == get_disk_ro(disk))
+ /*
+ * Upgrade to read-only if the region is read-only preserve as
+ * read-only if the disk is already read-only.
+ */
+ if (disk_ro || nd_region->ro == disk_ro)
return 0;
- dev_info(dev, "%s read-%s, marking %s read-%s\n",
- dev_name(&nd_region->dev), pol, disk->disk_name, pol);
- set_disk_ro(disk, nd_region->ro);
+ dev_info(dev, "%s read-only, marking %s read-only\n",
+ dev_name(&nd_region->dev), disk->disk_name);
+ set_disk_ro(disk, 1);
return 0;
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 3d4724e..4cac475 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -1233,17 +1233,15 @@
static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
int qid, int depth)
{
- if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
- unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
- dev->ctrl.page_size);
- nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
- nvmeq->sq_cmds_io = dev->cmb + offset;
- } else {
- nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
- &nvmeq->sq_dma_addr, GFP_KERNEL);
- if (!nvmeq->sq_cmds)
- return -ENOMEM;
- }
+
+ /* CMB SQEs will be mapped before creation */
+ if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz))
+ return 0;
+
+ nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
+ &nvmeq->sq_dma_addr, GFP_KERNEL);
+ if (!nvmeq->sq_cmds)
+ return -ENOMEM;
return 0;
}
@@ -1320,6 +1318,13 @@
struct nvme_dev *dev = nvmeq->dev;
int result;
+ if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
+ unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
+ dev->ctrl.page_size);
+ nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
+ nvmeq->sq_cmds_io = dev->cmb + offset;
+ }
+
nvmeq->cq_vector = qid - 1;
result = adapter_alloc_cq(dev, qid, nvmeq);
if (result < 0)
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index d12e5de..3456b6f 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -865,6 +865,10 @@
return cell;
}
+ /* NULL cell_id only allowed for device tree; invalid otherwise */
+ if (!cell_id)
+ return ERR_PTR(-EINVAL);
+
return nvmem_cell_get_from_list(cell_id);
}
EXPORT_SYMBOL_GPL(nvmem_cell_get);
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index e23b692..8f2c0e7 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -537,6 +537,9 @@
if (of_node_check_flag(dev->of_node, OF_POPULATED_BUS))
device_for_each_child(dev, NULL, of_platform_device_destroy);
+ of_node_clear_flag(dev->of_node, OF_POPULATED);
+ of_node_clear_flag(dev->of_node, OF_POPULATED_BUS);
+
if (dev->bus == &platform_bus_type)
platform_device_unregister(to_platform_device(dev));
#ifdef CONFIG_ARM_AMBA
@@ -544,8 +547,6 @@
amba_device_unregister(to_amba_device(dev));
#endif
- of_node_clear_flag(dev->of_node, OF_POPULATED);
- of_node_clear_flag(dev->of_node, OF_POPULATED_BUS);
return 0;
}
EXPORT_SYMBOL_GPL(of_platform_device_destroy);
diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
index bd21a66..1c8e9b2 100644
--- a/drivers/of/resolver.c
+++ b/drivers/of/resolver.c
@@ -128,6 +128,11 @@
goto err_fail;
}
+ if (offset < 0 || offset + sizeof(__be32) > prop->length) {
+ err = -EINVAL;
+ goto err_fail;
+ }
+
*(__be32 *)(prop->value + offset) = cpu_to_be32(phandle);
}
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 071407f..4db5754 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -164,20 +164,20 @@
/* Add a new property - should pass*/
prop->name = "new-property";
prop->value = "new-property-data";
- prop->length = strlen(prop->value);
+ prop->length = strlen(prop->value) + 1;
unittest(of_add_property(np, prop) == 0, "Adding a new property failed\n");
/* Try to add an existing property - should fail */
prop++;
prop->name = "new-property";
prop->value = "new-property-data-should-fail";
- prop->length = strlen(prop->value);
+ prop->length = strlen(prop->value) + 1;
unittest(of_add_property(np, prop) != 0,
"Adding an existing property should have failed\n");
/* Try to modify an existing property - should pass */
prop->value = "modify-property-data-should-pass";
- prop->length = strlen(prop->value);
+ prop->length = strlen(prop->value) + 1;
unittest(of_update_property(np, prop) == 0,
"Updating an existing property should have passed\n");
@@ -185,7 +185,7 @@
prop++;
prop->name = "modify-property";
prop->value = "modify-missing-property-data-should-pass";
- prop->length = strlen(prop->value);
+ prop->length = strlen(prop->value) + 1;
unittest(of_update_property(np, prop) == 0,
"Updating a missing property should have passed\n");
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 6d3624b..3b8c3f9 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -598,7 +598,7 @@
}
/* Scaling up? Scale voltage before frequency */
- if (freq > old_freq) {
+ if (freq >= old_freq) {
ret = _set_opp_voltage(dev, reg, new_supply);
if (ret)
goto restore_voltage;
diff --git a/drivers/pci/host/pci-hyperv.c b/drivers/pci/host/pci-hyperv.c
index 0b75022..caea7c61 100644
--- a/drivers/pci/host/pci-hyperv.c
+++ b/drivers/pci/host/pci-hyperv.c
@@ -1610,17 +1610,6 @@
get_pcichild(hpdev, hv_pcidev_ref_childlist);
spin_lock_irqsave(&hbus->device_list_lock, flags);
- /*
- * When a device is being added to the bus, we set the PCI domain
- * number to be the device serial number, which is non-zero and
- * unique on the same VM. The serial numbers start with 1, and
- * increase by 1 for each device. So device names including this
- * can have shorter names than based on the bus instance UUID.
- * Only the first device serial number is used for domain, so the
- * domain number will not change after the first device is added.
- */
- if (list_empty(&hbus->children))
- hbus->sysdata.domain = desc->ser;
list_add_tail(&hpdev->list_entry, &hbus->children);
spin_unlock_irqrestore(&hbus->device_list_lock, flags);
return hpdev;
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 06109d40c..e7d6cfaf 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -134,7 +134,7 @@
int pcie_init_notification(struct controller *ctrl);
int pciehp_enable_slot(struct slot *p_slot);
int pciehp_disable_slot(struct slot *p_slot);
-void pcie_enable_notification(struct controller *ctrl);
+void pcie_reenable_notification(struct controller *ctrl);
int pciehp_power_on_slot(struct slot *slot);
void pciehp_power_off_slot(struct slot *slot);
void pciehp_get_power_status(struct slot *slot, u8 *status);
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 35d8484..1288289 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -297,7 +297,7 @@
ctrl = get_service_data(dev);
/* reinitialize the chipset's event detection logic */
- pcie_enable_notification(ctrl);
+ pcie_reenable_notification(ctrl);
slot = ctrl->slot;
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index ee1e0ba..5255056 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -683,7 +683,7 @@
return handled;
}
-void pcie_enable_notification(struct controller *ctrl)
+static void pcie_enable_notification(struct controller *ctrl)
{
u16 cmd, mask;
@@ -721,6 +721,17 @@
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
}
+void pcie_reenable_notification(struct controller *ctrl)
+{
+ /*
+ * Clear both Presence and Data Link Layer Changed to make sure
+ * those events still fire after we have re-enabled them.
+ */
+ pcie_capability_write_word(ctrl->pcie->port, PCI_EXP_SLTSTA,
+ PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
+ pcie_enable_notification(ctrl);
+}
+
static void pcie_disable_notification(struct controller *ctrl)
{
u16 mask;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 62a0677..e792947 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1158,6 +1158,33 @@
}
}
+static void pci_restore_rebar_state(struct pci_dev *pdev)
+{
+ unsigned int pos, nbars, i;
+ u32 ctrl;
+
+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
+ if (!pos)
+ return;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+ nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
+ PCI_REBAR_CTRL_NBAR_SHIFT;
+
+ for (i = 0; i < nbars; i++, pos += 8) {
+ struct resource *res;
+ int bar_idx, size;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+ bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
+ res = pdev->resource + bar_idx;
+ size = order_base_2((resource_size(res) >> 20) | 1) - 1;
+ ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
+ ctrl |= size << 8;
+ pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
+ }
+}
+
/**
* pci_restore_state - Restore the saved state of a PCI device
* @dev: - PCI device that we're dealing with
@@ -1173,6 +1200,7 @@
pci_restore_pri_state(dev);
pci_restore_ats_state(dev);
pci_restore_vc_state(dev);
+ pci_restore_rebar_state(dev);
pci_cleanup_aer_error_status_regs(dev);
@@ -2983,6 +3011,107 @@
}
/**
+ * pci_rebar_find_pos - find position of resize ctrl reg for BAR
+ * @pdev: PCI device
+ * @bar: BAR to find
+ *
+ * Helper to find the position of the ctrl register for a BAR.
+ * Returns -ENOTSUPP if resizable BARs are not supported at all.
+ * Returns -ENOENT if no ctrl register for the BAR could be found.
+ */
+static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
+{
+ unsigned int pos, nbars, i;
+ u32 ctrl;
+
+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
+ if (!pos)
+ return -ENOTSUPP;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+ nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
+ PCI_REBAR_CTRL_NBAR_SHIFT;
+
+ for (i = 0; i < nbars; i++, pos += 8) {
+ int bar_idx;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+ bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
+ if (bar_idx == bar)
+ return pos;
+ }
+
+ return -ENOENT;
+}
+
+/**
+ * pci_rebar_get_possible_sizes - get possible sizes for BAR
+ * @pdev: PCI device
+ * @bar: BAR to query
+ *
+ * Get the possible sizes of a resizable BAR as bitmask defined in the spec
+ * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
+ */
+u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
+{
+ int pos;
+ u32 cap;
+
+ pos = pci_rebar_find_pos(pdev, bar);
+ if (pos < 0)
+ return 0;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
+ return (cap & PCI_REBAR_CAP_SIZES) >> 4;
+}
+
+/**
+ * pci_rebar_get_current_size - get the current size of a BAR
+ * @pdev: PCI device
+ * @bar: BAR to set size to
+ *
+ * Read the size of a BAR from the resizable BAR config.
+ * Returns size if found or negative error code.
+ */
+int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
+{
+ int pos;
+ u32 ctrl;
+
+ pos = pci_rebar_find_pos(pdev, bar);
+ if (pos < 0)
+ return pos;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+ return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
+}
+
+/**
+ * pci_rebar_set_size - set a new size for a BAR
+ * @pdev: PCI device
+ * @bar: BAR to set size to
+ * @size: new size as defined in the spec (0=1MB, 19=512GB)
+ *
+ * Set the new size of a BAR as defined in the spec.
+ * Returns zero if resizing was successful, error code otherwise.
+ */
+int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
+{
+ int pos;
+ u32 ctrl;
+
+ pos = pci_rebar_find_pos(pdev, bar);
+ if (pos < 0)
+ return pos;
+
+ pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+ ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
+ ctrl |= size << 8;
+ pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
+ return 0;
+}
+
+/**
* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
* @dev: the PCI device
* @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index fdb02c1..b3722eb 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -367,4 +367,12 @@
struct resource *res);
#endif
+u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
+int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
+int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
+static inline u64 pci_rebar_size_to_bytes(int size)
+{
+ return 1ULL << (size + 20);
+}
+
#endif /* DRIVERS_PCI_H */
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 929d68f..ec2911c 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4377,11 +4377,29 @@
* 0xa290-0xa29f PCI Express Root port #{0-16}
* 0xa2e7-0xa2ee PCI Express Root port #{17-24}
*
+ * Mobile chipsets are also affected, 7th & 8th Generation
+ * Specification update confirms ACS errata 22, status no fix: (7th Generation
+ * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
+ * Processor Family I/O for U Quad Core Platforms Specification Update,
+ * August 2017, Revision 002, Document#: 334660-002)[6]
+ * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
+ * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
+ * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
+ *
+ * 0x9d10-0x9d1b PCI Express Root port #{1-12}
+ *
+ * The 300 series chipset suffers from the same bug so include those root
+ * ports here as well.
+ *
+ * 0xa32c-0xa343 PCI Express Root port #{0-24}
+ *
* [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
* [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
* [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
* [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
+ * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
+ * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
*/
static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
{
@@ -4391,6 +4409,8 @@
switch (dev->device) {
case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
+ case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
+ case 0xa32c ... 0xa343: /* 300 series */
return true;
}
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 958da7d..6826a89 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1518,13 +1518,16 @@
break;
}
}
+
+#define PCI_RES_TYPE_MASK \
+ (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
+ IORESOURCE_MEM_64)
+
static void pci_bridge_release_resources(struct pci_bus *bus,
unsigned long type)
{
struct pci_dev *dev = bus->self;
struct resource *r;
- unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
- IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
unsigned old_flags = 0;
struct resource *b_res;
int idx = 1;
@@ -1567,7 +1570,7 @@
*/
release_child_resources(r);
if (!release_resource(r)) {
- type = old_flags = r->flags & type_mask;
+ type = old_flags = r->flags & PCI_RES_TYPE_MASK;
dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
PCI_BRIDGE_RESOURCES + idx, r);
/* keep the old size */
@@ -1758,8 +1761,6 @@
enum release_type rel_type = leaf_only;
LIST_HEAD(fail_head);
struct pci_dev_resource *fail_res;
- unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
- IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
int pci_try_num = 1;
enum enable_type enable_local;
@@ -1818,7 +1819,7 @@
*/
list_for_each_entry(fail_res, &fail_head, list)
pci_bus_release_bridge_resources(fail_res->dev->bus,
- fail_res->flags & type_mask,
+ fail_res->flags & PCI_RES_TYPE_MASK,
rel_type);
/* restore size and flags */
@@ -1862,8 +1863,6 @@
LIST_HEAD(fail_head);
struct pci_dev_resource *fail_res;
int retval;
- unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
- IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
again:
__pci_bus_size_bridges(parent, &add_list);
@@ -1889,7 +1888,7 @@
*/
list_for_each_entry(fail_res, &fail_head, list)
pci_bus_release_bridge_resources(fail_res->dev->bus,
- fail_res->flags & type_mask,
+ fail_res->flags & PCI_RES_TYPE_MASK,
whole_subtree);
/* restore size and flags */
@@ -1914,6 +1913,104 @@
}
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
+int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
+{
+ struct pci_dev_resource *dev_res;
+ struct pci_dev *next;
+ LIST_HEAD(saved);
+ LIST_HEAD(added);
+ LIST_HEAD(failed);
+ unsigned int i;
+ int ret;
+
+ /* Walk to the root hub, releasing bridge BARs when possible */
+ next = bridge;
+ do {
+ bridge = next;
+ for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
+ i++) {
+ struct resource *res = &bridge->resource[i];
+
+ if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
+ continue;
+
+ /* Ignore BARs which are still in use */
+ if (res->child)
+ continue;
+
+ ret = add_to_list(&saved, bridge, res, 0, 0);
+ if (ret)
+ goto cleanup;
+
+ dev_info(&bridge->dev, "BAR %d: releasing %pR\n",
+ i, res);
+
+ if (res->parent)
+ release_resource(res);
+ res->start = 0;
+ res->end = 0;
+ break;
+ }
+ if (i == PCI_BRIDGE_RESOURCE_END)
+ break;
+
+ next = bridge->bus ? bridge->bus->self : NULL;
+ } while (next);
+
+ if (list_empty(&saved))
+ return -ENOENT;
+
+ __pci_bus_size_bridges(bridge->subordinate, &added);
+ __pci_bridge_assign_resources(bridge, &added, &failed);
+ BUG_ON(!list_empty(&added));
+
+ if (!list_empty(&failed)) {
+ ret = -ENOSPC;
+ goto cleanup;
+ }
+
+ list_for_each_entry(dev_res, &saved, list) {
+ /* Skip the bridge we just assigned resources for. */
+ if (bridge == dev_res->dev)
+ continue;
+
+ bridge = dev_res->dev;
+ pci_setup_bridge(bridge->subordinate);
+ }
+
+ free_list(&saved);
+ return 0;
+
+cleanup:
+ /* restore size and flags */
+ list_for_each_entry(dev_res, &failed, list) {
+ struct resource *res = dev_res->res;
+
+ res->start = dev_res->start;
+ res->end = dev_res->end;
+ res->flags = dev_res->flags;
+ }
+ free_list(&failed);
+
+ /* Revert to the old configuration */
+ list_for_each_entry(dev_res, &saved, list) {
+ struct resource *res = dev_res->res;
+
+ bridge = dev_res->dev;
+ i = res - bridge->resource;
+
+ res->start = dev_res->start;
+ res->end = dev_res->end;
+ res->flags = dev_res->flags;
+
+ pci_claim_resource(bridge, i);
+ pci_setup_bridge(bridge->subordinate);
+ }
+ free_list(&saved);
+
+ return ret;
+}
+
void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
{
struct pci_dev *dev;
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index c039149..e815111 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -397,6 +397,64 @@
return 0;
}
+void pci_release_resource(struct pci_dev *dev, int resno)
+{
+ struct resource *res = dev->resource + resno;
+
+ dev_info(&dev->dev, "BAR %d: releasing %pR\n", resno, res);
+ release_resource(res);
+ res->end = resource_size(res) - 1;
+ res->start = 0;
+ res->flags |= IORESOURCE_UNSET;
+}
+EXPORT_SYMBOL(pci_release_resource);
+
+int pci_resize_resource(struct pci_dev *dev, int resno, int size)
+{
+ struct resource *res = dev->resource + resno;
+ int old, ret;
+ u32 sizes;
+ u16 cmd;
+
+ /* Make sure the resource isn't assigned before resizing it. */
+ if (!(res->flags & IORESOURCE_UNSET))
+ return -EBUSY;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ if (cmd & PCI_COMMAND_MEMORY)
+ return -EBUSY;
+
+ sizes = pci_rebar_get_possible_sizes(dev, resno);
+ if (!sizes)
+ return -ENOTSUPP;
+
+ if (!(sizes & BIT(size)))
+ return -EINVAL;
+
+ old = pci_rebar_get_current_size(dev, resno);
+ if (old < 0)
+ return old;
+
+ ret = pci_rebar_set_size(dev, resno, size);
+ if (ret)
+ return ret;
+
+ res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
+
+ /* Check if the new config works by trying to assign everything. */
+ ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
+ if (ret)
+ goto error_resize;
+
+ return 0;
+
+error_resize:
+ pci_rebar_set_size(dev, resno, old);
+ res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
+ return ret;
+}
+EXPORT_SYMBOL(pci_resize_resource);
+
int pci_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index b601039..c4aa411 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -101,10 +101,11 @@
}
static int dt_to_map_one_config(struct pinctrl *p,
- struct pinctrl_dev *pctldev,
+ struct pinctrl_dev *hog_pctldev,
const char *statename,
struct device_node *np_config)
{
+ struct pinctrl_dev *pctldev = NULL;
struct device_node *np_pctldev;
const struct pinctrl_ops *ops;
int ret;
@@ -123,8 +124,10 @@
return -EPROBE_DEFER;
}
/* If we're creating a hog we can use the passed pctldev */
- if (pctldev && (np_pctldev == p->dev->of_node))
+ if (hog_pctldev && (np_pctldev == p->dev->of_node)) {
+ pctldev = hog_pctldev;
break;
+ }
pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
if (pctldev)
break;
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index b7c58a1..b91db89 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -552,7 +552,8 @@
/* Each status bit covers four pins */
for (i = 0; i < 4; i++) {
regval = readl(regs + i);
- if (!(regval & PIN_IRQ_PENDING))
+ if (!(regval & PIN_IRQ_PENDING) ||
+ !(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
irq = irq_find_mapping(gc->irq.domain, irqnr + i);
generic_handle_irq(irq);
@@ -775,7 +776,7 @@
return false;
}
-int amd_gpio_suspend(struct device *dev)
+static int amd_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
@@ -794,7 +795,7 @@
return 0;
}
-int amd_gpio_resume(struct device *dev)
+static int amd_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
index 92aeea1..afeb487 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
@@ -110,12 +110,12 @@
EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
- EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
+ EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
@@ -635,7 +635,6 @@
EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
- EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
@@ -646,6 +645,7 @@
EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
+ EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c
index 48e1541d..7440f65 100644
--- a/drivers/platform/x86/asus-wmi.c
+++ b/drivers/platform/x86/asus-wmi.c
@@ -161,6 +161,16 @@
static const char * const ashs_ids[] = { "ATK4001", "ATK4002", NULL };
+static bool ashs_present(void)
+{
+ int i = 0;
+ while (ashs_ids[i]) {
+ if (acpi_dev_found(ashs_ids[i++]))
+ return true;
+ }
+ return false;
+}
+
struct bios_args {
u32 arg0;
u32 arg1;
@@ -962,6 +972,9 @@
static void asus_wmi_rfkill_exit(struct asus_wmi *asus)
{
+ if (asus->driver->wlan_ctrl_by_user && ashs_present())
+ return;
+
asus_unregister_rfkill_notifier(asus, "\\_SB.PCI0.P0P5");
asus_unregister_rfkill_notifier(asus, "\\_SB.PCI0.P0P6");
asus_unregister_rfkill_notifier(asus, "\\_SB.PCI0.P0P7");
@@ -2058,16 +2071,6 @@
return 0;
}
-static bool ashs_present(void)
-{
- int i = 0;
- while (ashs_ids[i]) {
- if (acpi_dev_found(ashs_ids[i++]))
- return true;
- }
- return false;
-}
-
/*
* WMI Driver
*/
diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
index 5d6ed150..5561b9e 100644
--- a/drivers/pwm/pwm-lpss-platform.c
+++ b/drivers/pwm/pwm-lpss-platform.c
@@ -74,6 +74,10 @@
return pwm_lpss_remove(lpwm);
}
+static SIMPLE_DEV_PM_OPS(pwm_lpss_platform_pm_ops,
+ pwm_lpss_suspend,
+ pwm_lpss_resume);
+
static const struct acpi_device_id pwm_lpss_acpi_match[] = {
{ "80860F09", (unsigned long)&pwm_lpss_byt_info },
{ "80862288", (unsigned long)&pwm_lpss_bsw_info },
@@ -86,6 +90,7 @@
.driver = {
.name = "pwm-lpss",
.acpi_match_table = pwm_lpss_acpi_match,
+ .pm = &pwm_lpss_platform_pm_ops,
},
.probe = pwm_lpss_probe_platform,
.remove = pwm_lpss_remove_platform,
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index 8db0d40..4721a26 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -32,10 +32,13 @@
/* Size of each PWM register space if multiple */
#define PWM_SIZE 0x400
+#define MAX_PWMS 4
+
struct pwm_lpss_chip {
struct pwm_chip chip;
void __iomem *regs;
const struct pwm_lpss_boardinfo *info;
+ u32 saved_ctrl[MAX_PWMS];
};
static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
@@ -177,6 +180,9 @@
unsigned long c;
int ret;
+ if (WARN_ON(info->npwm > MAX_PWMS))
+ return ERR_PTR(-ENODEV);
+
lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
if (!lpwm)
return ERR_PTR(-ENOMEM);
@@ -212,6 +218,30 @@
}
EXPORT_SYMBOL_GPL(pwm_lpss_remove);
+int pwm_lpss_suspend(struct device *dev)
+{
+ struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < lpwm->info->npwm; i++)
+ lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
+
+int pwm_lpss_resume(struct device *dev)
+{
+ struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < lpwm->info->npwm; i++)
+ writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pwm_lpss_resume);
+
MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index 98306bb..7a4238a 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -28,5 +28,7 @@
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
const struct pwm_lpss_boardinfo *info);
int pwm_lpss_remove(struct pwm_lpss_chip *lpwm);
+int pwm_lpss_suspend(struct device *dev);
+int pwm_lpss_resume(struct device *dev);
#endif /* __PWM_LPSS_H */
diff --git a/drivers/rpmsg/qcom_smd.c b/drivers/rpmsg/qcom_smd.c
index bd0577f..6fba0e6 100644
--- a/drivers/rpmsg/qcom_smd.c
+++ b/drivers/rpmsg/qcom_smd.c
@@ -1061,12 +1061,12 @@
void *info;
int ret;
- channel = devm_kzalloc(&edge->dev, sizeof(*channel), GFP_KERNEL);
+ channel = kzalloc(sizeof(*channel), GFP_KERNEL);
if (!channel)
return ERR_PTR(-ENOMEM);
channel->edge = edge;
- channel->name = devm_kstrdup(&edge->dev, name, GFP_KERNEL);
+ channel->name = kstrdup(name, GFP_KERNEL);
if (!channel->name)
return ERR_PTR(-ENOMEM);
@@ -1116,8 +1116,8 @@
return channel;
free_name_and_channel:
- devm_kfree(&edge->dev, channel->name);
- devm_kfree(&edge->dev, channel);
+ kfree(channel->name);
+ kfree(channel);
return ERR_PTR(ret);
}
@@ -1338,13 +1338,13 @@
*/
static void qcom_smd_edge_release(struct device *dev)
{
- struct qcom_smd_channel *channel;
+ struct qcom_smd_channel *channel, *tmp;
struct qcom_smd_edge *edge = to_smd_edge(dev);
- list_for_each_entry(channel, &edge->channels, list) {
- SET_RX_CHANNEL_INFO(channel, state, SMD_CHANNEL_CLOSED);
- SET_RX_CHANNEL_INFO(channel, head, 0);
- SET_RX_CHANNEL_INFO(channel, tail, 0);
+ list_for_each_entry_safe(channel, tmp, &edge->channels, list) {
+ list_del(&channel->list);
+ kfree(channel->name);
+ kfree(channel);
}
kfree(edge);
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index 3d2216c..8eb2b6d 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -74,7 +74,7 @@
#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
#define SUN6I_LOSC_OUT_GATING 0x0060
-#define SUN6I_LOSC_OUT_GATING_EN BIT(0)
+#define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
/*
* Get date values
@@ -253,7 +253,7 @@
&clkout_name);
rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
0, rtc->base + SUN6I_LOSC_OUT_GATING,
- SUN6I_LOSC_OUT_GATING_EN, 0,
+ SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
&rtc->lock);
if (IS_ERR(rtc->ext_losc)) {
pr_crit("Couldn't register the LOSC external gate\n");
diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c
index e67c1d8..d072f84 100644
--- a/drivers/s390/block/dasd.c
+++ b/drivers/s390/block/dasd.c
@@ -3049,7 +3049,8 @@
cqr->callback_data = req;
cqr->status = DASD_CQR_FILLED;
cqr->dq = dq;
- req->completion_data = cqr;
+ *((struct dasd_ccw_req **) blk_mq_rq_to_pdu(req)) = cqr;
+
blk_mq_start_request(req);
spin_lock(&block->queue_lock);
list_add_tail(&cqr->blocklist, &block->ccw_queue);
@@ -3073,12 +3074,13 @@
*/
enum blk_eh_timer_return dasd_times_out(struct request *req, bool reserved)
{
- struct dasd_ccw_req *cqr = req->completion_data;
struct dasd_block *block = req->q->queuedata;
struct dasd_device *device;
+ struct dasd_ccw_req *cqr;
unsigned long flags;
int rc = 0;
+ cqr = *((struct dasd_ccw_req **) blk_mq_rq_to_pdu(req));
if (!cqr)
return BLK_EH_NOT_HANDLED;
@@ -3184,6 +3186,7 @@
int rc;
block->tag_set.ops = &dasd_mq_ops;
+ block->tag_set.cmd_size = sizeof(struct dasd_ccw_req *);
block->tag_set.nr_hw_queues = DASD_NR_HW_QUEUES;
block->tag_set.queue_depth = DASD_MAX_LCU_DEV * DASD_REQ_PER_DEV;
block->tag_set.flags = BLK_MQ_F_SHOULD_MERGE;
diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c
index 18c4f93..b415ba42 100644
--- a/drivers/s390/scsi/zfcp_dbf.c
+++ b/drivers/s390/scsi/zfcp_dbf.c
@@ -664,6 +664,46 @@
spin_unlock_irqrestore(&dbf->scsi_lock, flags);
}
+/**
+ * zfcp_dbf_scsi_eh() - Trace event for special cases of scsi_eh callbacks.
+ * @tag: Identifier for event.
+ * @adapter: Pointer to zfcp adapter as context for this event.
+ * @scsi_id: SCSI ID/target to indicate scope of task management function (TMF).
+ * @ret: Return value of calling function.
+ *
+ * This SCSI trace variant does not depend on any of:
+ * scsi_cmnd, zfcp_fsf_req, scsi_device.
+ */
+void zfcp_dbf_scsi_eh(char *tag, struct zfcp_adapter *adapter,
+ unsigned int scsi_id, int ret)
+{
+ struct zfcp_dbf *dbf = adapter->dbf;
+ struct zfcp_dbf_scsi *rec = &dbf->scsi_buf;
+ unsigned long flags;
+ static int const level = 1;
+
+ if (unlikely(!debug_level_enabled(adapter->dbf->scsi, level)))
+ return;
+
+ spin_lock_irqsave(&dbf->scsi_lock, flags);
+ memset(rec, 0, sizeof(*rec));
+
+ memcpy(rec->tag, tag, ZFCP_DBF_TAG_LEN);
+ rec->id = ZFCP_DBF_SCSI_CMND;
+ rec->scsi_result = ret; /* re-use field, int is 4 bytes and fits */
+ rec->scsi_retries = ~0;
+ rec->scsi_allowed = ~0;
+ rec->fcp_rsp_info = ~0;
+ rec->scsi_id = scsi_id;
+ rec->scsi_lun = (u32)ZFCP_DBF_INVALID_LUN;
+ rec->scsi_lun_64_hi = (u32)(ZFCP_DBF_INVALID_LUN >> 32);
+ rec->host_scribble = ~0;
+ memset(rec->scsi_opcode, 0xff, ZFCP_DBF_SCSI_OPCODE);
+
+ debug_event(dbf->scsi, level, rec, sizeof(*rec));
+ spin_unlock_irqrestore(&dbf->scsi_lock, flags);
+}
+
static debug_info_t *zfcp_dbf_reg(const char *name, int size, int rec_size)
{
struct debug_info *d;
diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
index cbb8156b..7aa243a 100644
--- a/drivers/s390/scsi/zfcp_erp.c
+++ b/drivers/s390/scsi/zfcp_erp.c
@@ -35,11 +35,28 @@
ZFCP_ERP_STEP_LUN_OPENING = 0x2000,
};
+/**
+ * enum zfcp_erp_act_type - Type of ERP action object.
+ * @ZFCP_ERP_ACTION_REOPEN_LUN: LUN recovery.
+ * @ZFCP_ERP_ACTION_REOPEN_PORT: Port recovery.
+ * @ZFCP_ERP_ACTION_REOPEN_PORT_FORCED: Forced port recovery.
+ * @ZFCP_ERP_ACTION_REOPEN_ADAPTER: Adapter recovery.
+ * @ZFCP_ERP_ACTION_NONE: Eyecatcher pseudo flag to bitwise or-combine with
+ * either of the first four enum values.
+ * Used to indicate that an ERP action could not be
+ * set up despite a detected need for some recovery.
+ * @ZFCP_ERP_ACTION_FAILED: Eyecatcher pseudo flag to bitwise or-combine with
+ * either of the first four enum values.
+ * Used to indicate that ERP not needed because
+ * the object has ZFCP_STATUS_COMMON_ERP_FAILED.
+ */
enum zfcp_erp_act_type {
ZFCP_ERP_ACTION_REOPEN_LUN = 1,
ZFCP_ERP_ACTION_REOPEN_PORT = 2,
ZFCP_ERP_ACTION_REOPEN_PORT_FORCED = 3,
ZFCP_ERP_ACTION_REOPEN_ADAPTER = 4,
+ ZFCP_ERP_ACTION_NONE = 0xc0,
+ ZFCP_ERP_ACTION_FAILED = 0xe0,
};
enum zfcp_erp_act_state {
@@ -126,6 +143,49 @@
}
}
+static int zfcp_erp_handle_failed(int want, struct zfcp_adapter *adapter,
+ struct zfcp_port *port,
+ struct scsi_device *sdev)
+{
+ int need = want;
+ struct zfcp_scsi_dev *zsdev;
+
+ switch (want) {
+ case ZFCP_ERP_ACTION_REOPEN_LUN:
+ zsdev = sdev_to_zfcp(sdev);
+ if (atomic_read(&zsdev->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
+ need = 0;
+ break;
+ case ZFCP_ERP_ACTION_REOPEN_PORT_FORCED:
+ if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
+ need = 0;
+ break;
+ case ZFCP_ERP_ACTION_REOPEN_PORT:
+ if (atomic_read(&port->status) &
+ ZFCP_STATUS_COMMON_ERP_FAILED) {
+ need = 0;
+ /* ensure propagation of failed status to new devices */
+ zfcp_erp_set_port_status(
+ port, ZFCP_STATUS_COMMON_ERP_FAILED);
+ }
+ break;
+ case ZFCP_ERP_ACTION_REOPEN_ADAPTER:
+ if (atomic_read(&adapter->status) &
+ ZFCP_STATUS_COMMON_ERP_FAILED) {
+ need = 0;
+ /* ensure propagation of failed status to new devices */
+ zfcp_erp_set_adapter_status(
+ adapter, ZFCP_STATUS_COMMON_ERP_FAILED);
+ }
+ break;
+ default:
+ need = 0;
+ break;
+ }
+
+ return need;
+}
+
static int zfcp_erp_required_act(int want, struct zfcp_adapter *adapter,
struct zfcp_port *port,
struct scsi_device *sdev)
@@ -249,16 +309,27 @@
int retval = 1, need;
struct zfcp_erp_action *act;
- if (!adapter->erp_thread)
- return -EIO;
+ need = zfcp_erp_handle_failed(want, adapter, port, sdev);
+ if (!need) {
+ need = ZFCP_ERP_ACTION_FAILED; /* marker for trace */
+ goto out;
+ }
+
+ if (!adapter->erp_thread) {
+ need = ZFCP_ERP_ACTION_NONE; /* marker for trace */
+ retval = -EIO;
+ goto out;
+ }
need = zfcp_erp_required_act(want, adapter, port, sdev);
if (!need)
goto out;
act = zfcp_erp_setup_act(need, act_status, adapter, port, sdev);
- if (!act)
+ if (!act) {
+ need |= ZFCP_ERP_ACTION_NONE; /* marker for trace */
goto out;
+ }
atomic_or(ZFCP_STATUS_ADAPTER_ERP_PENDING, &adapter->status);
++adapter->erp_total_count;
list_add_tail(&act->list, &adapter->erp_ready_head);
@@ -269,18 +340,32 @@
return retval;
}
+void zfcp_erp_port_forced_no_port_dbf(char *id, struct zfcp_adapter *adapter,
+ u64 port_name, u32 port_id)
+{
+ unsigned long flags;
+ static /* don't waste stack */ struct zfcp_port tmpport;
+
+ write_lock_irqsave(&adapter->erp_lock, flags);
+ /* Stand-in zfcp port with fields just good enough for
+ * zfcp_dbf_rec_trig() and zfcp_dbf_set_common().
+ * Under lock because tmpport is static.
+ */
+ atomic_set(&tmpport.status, -1); /* unknown */
+ tmpport.wwpn = port_name;
+ tmpport.d_id = port_id;
+ zfcp_dbf_rec_trig(id, adapter, &tmpport, NULL,
+ ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
+ ZFCP_ERP_ACTION_NONE);
+ write_unlock_irqrestore(&adapter->erp_lock, flags);
+}
+
static int _zfcp_erp_adapter_reopen(struct zfcp_adapter *adapter,
int clear_mask, char *id)
{
zfcp_erp_adapter_block(adapter, clear_mask);
zfcp_scsi_schedule_rports_block(adapter);
- /* ensure propagation of failed status to new devices */
- if (atomic_read(&adapter->status) & ZFCP_STATUS_COMMON_ERP_FAILED) {
- zfcp_erp_set_adapter_status(adapter,
- ZFCP_STATUS_COMMON_ERP_FAILED);
- return -EIO;
- }
return zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER,
adapter, NULL, NULL, id, 0);
}
@@ -299,12 +384,8 @@
zfcp_scsi_schedule_rports_block(adapter);
write_lock_irqsave(&adapter->erp_lock, flags);
- if (atomic_read(&adapter->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
- zfcp_erp_set_adapter_status(adapter,
- ZFCP_STATUS_COMMON_ERP_FAILED);
- else
- zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER, adapter,
- NULL, NULL, id, 0);
+ zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER, adapter,
+ NULL, NULL, id, 0);
write_unlock_irqrestore(&adapter->erp_lock, flags);
}
@@ -345,9 +426,6 @@
zfcp_erp_port_block(port, clear);
zfcp_scsi_schedule_rport_block(port);
- if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
- return;
-
zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
port->adapter, port, NULL, id, 0);
}
@@ -373,12 +451,6 @@
zfcp_erp_port_block(port, clear);
zfcp_scsi_schedule_rport_block(port);
- if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED) {
- /* ensure propagation of failed status to new devices */
- zfcp_erp_set_port_status(port, ZFCP_STATUS_COMMON_ERP_FAILED);
- return -EIO;
- }
-
return zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_PORT,
port->adapter, port, NULL, id, 0);
}
@@ -418,9 +490,6 @@
zfcp_erp_lun_block(sdev, clear);
- if (atomic_read(&zfcp_sdev->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
- return;
-
zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_LUN, adapter,
zfcp_sdev->port, sdev, id, act_status);
}
diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h
index b1cbb14..c1092a1 100644
--- a/drivers/s390/scsi/zfcp_ext.h
+++ b/drivers/s390/scsi/zfcp_ext.h
@@ -52,10 +52,15 @@
extern void zfcp_dbf_san_in_els(char *, struct zfcp_fsf_req *);
extern void zfcp_dbf_scsi(char *, int, struct scsi_cmnd *,
struct zfcp_fsf_req *);
+extern void zfcp_dbf_scsi_eh(char *tag, struct zfcp_adapter *adapter,
+ unsigned int scsi_id, int ret);
/* zfcp_erp.c */
extern void zfcp_erp_set_adapter_status(struct zfcp_adapter *, u32);
extern void zfcp_erp_clear_adapter_status(struct zfcp_adapter *, u32);
+extern void zfcp_erp_port_forced_no_port_dbf(char *id,
+ struct zfcp_adapter *adapter,
+ u64 port_name, u32 port_id);
extern void zfcp_erp_adapter_reopen(struct zfcp_adapter *, int, char *);
extern void zfcp_erp_adapter_shutdown(struct zfcp_adapter *, int, char *);
extern void zfcp_erp_set_port_status(struct zfcp_port *, u32);
diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c
index 22f9562..0b6f514 100644
--- a/drivers/s390/scsi/zfcp_scsi.c
+++ b/drivers/s390/scsi/zfcp_scsi.c
@@ -181,6 +181,7 @@
if (abrt_req)
break;
+ zfcp_dbf_scsi_abort("abrt_wt", scpnt, NULL);
zfcp_erp_wait(adapter);
ret = fc_block_scsi_eh(scpnt);
if (ret) {
@@ -277,6 +278,7 @@
if (fsf_req)
break;
+ zfcp_dbf_scsi_devreset("wait", scpnt, tm_flags, NULL);
zfcp_erp_wait(adapter);
ret = fc_block_scsi_eh(scpnt);
if (ret) {
@@ -323,15 +325,16 @@
{
struct zfcp_scsi_dev *zfcp_sdev = sdev_to_zfcp(scpnt->device);
struct zfcp_adapter *adapter = zfcp_sdev->port->adapter;
- int ret;
+ int ret = SUCCESS, fc_ret;
zfcp_erp_adapter_reopen(adapter, 0, "schrh_1");
zfcp_erp_wait(adapter);
- ret = fc_block_scsi_eh(scpnt);
- if (ret)
- return ret;
+ fc_ret = fc_block_scsi_eh(scpnt);
+ if (fc_ret)
+ ret = fc_ret;
- return SUCCESS;
+ zfcp_dbf_scsi_eh("schrh_r", adapter, ~0, ret);
+ return ret;
}
struct scsi_transport_template *zfcp_scsi_transport_template;
@@ -602,6 +605,11 @@
if (port) {
zfcp_erp_port_forced_reopen(port, 0, "sctrpi1");
put_device(&port->dev);
+ } else {
+ zfcp_erp_port_forced_no_port_dbf(
+ "sctrpin", adapter,
+ rport->port_name /* zfcp_scsi_rport_register */,
+ rport->port_id /* zfcp_scsi_rport_register */);
}
}
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 5fbaf13..604a39d 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -8638,7 +8638,7 @@
kfree(options);
}
-static void hpsa_shutdown(struct pci_dev *pdev)
+static void __hpsa_shutdown(struct pci_dev *pdev)
{
struct ctlr_info *h;
@@ -8653,6 +8653,12 @@
hpsa_disable_interrupt_mode(h); /* pci_init 2 */
}
+static void hpsa_shutdown(struct pci_dev *pdev)
+{
+ __hpsa_shutdown(pdev);
+ pci_disable_device(pdev);
+}
+
static void hpsa_free_device_info(struct ctlr_info *h)
{
int i;
@@ -8696,7 +8702,7 @@
scsi_remove_host(h->scsi_host); /* init_one 8 */
/* includes hpsa_free_irqs - init_one 4 */
/* includes hpsa_disable_interrupt_mode - pci_init 2 */
- hpsa_shutdown(pdev);
+ __hpsa_shutdown(pdev);
hpsa_free_device_info(h); /* scan */
diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h
index a6722c9..81de4a1 100644
--- a/drivers/scsi/megaraid/megaraid_sas.h
+++ b/drivers/scsi/megaraid/megaraid_sas.h
@@ -1504,6 +1504,13 @@
#define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
+enum MR_ADAPTER_TYPE {
+ MFI_SERIES = 1,
+ THUNDERBOLT_SERIES = 2,
+ INVADER_SERIES = 3,
+ VENTURA_SERIES = 4,
+};
+
/*
* register set for both 1068 and 1078 controllers
* structure extended for 1078 registers
@@ -2092,6 +2099,7 @@
struct megasas_instance {
+ unsigned int *reply_map;
__le32 *producer;
dma_addr_t producer_h;
__le32 *consumer;
@@ -2236,12 +2244,12 @@
bool dev_handle;
bool fw_sync_cache_support;
u32 mfi_frame_size;
- bool is_ventura;
bool msix_combined;
u16 max_raid_mapsize;
/* preffered count to send as LDIO irrspective of FP capable.*/
u8 r1_ldio_hint_default;
u32 nvme_page_size;
+ u8 adapter_type;
};
struct MR_LD_VF_MAP {
u32 size;
diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c
index 4beb4dd..985378e 100644
--- a/drivers/scsi/megaraid/megaraid_sas_base.c
+++ b/drivers/scsi/megaraid/megaraid_sas_base.c
@@ -2023,7 +2023,7 @@
msleep(1000);
if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
(instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY) ||
- (instance->ctrl_context)) {
+ (instance->adapter_type != MFI_SERIES)) {
writel(MFI_STOP_ADP, &instance->reg_set->doorbell);
/* Flush */
readl(&instance->reg_set->doorbell);
@@ -2494,7 +2494,8 @@
dev_warn(&instance->pdev->dev, "SR-IOV: Starting heartbeat for scsi%d\n",
instance->host->host_no);
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
retval = megasas_issue_blocked_cmd(instance, cmd,
MEGASAS_ROUTINE_WAIT_TIME_VF);
else
@@ -2790,7 +2791,9 @@
/*
* First wait for all commands to complete
*/
- if (instance->ctrl_context) {
+ if (instance->adapter_type == MFI_SERIES) {
+ ret = megasas_generic_reset(scmd);
+ } else {
struct megasas_cmd_fusion *cmd;
cmd = (struct megasas_cmd_fusion *)scmd->SCp.ptr;
if (cmd)
@@ -2798,8 +2801,7 @@
MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE);
ret = megasas_reset_fusion(scmd->device->host,
SCSIIO_TIMEOUT_OCR);
- } else
- ret = megasas_generic_reset(scmd);
+ }
return ret;
}
@@ -2816,7 +2818,7 @@
instance = (struct megasas_instance *)scmd->device->host->hostdata;
- if (instance->ctrl_context)
+ if (instance->adapter_type != MFI_SERIES)
ret = megasas_task_abort_fusion(scmd);
else {
sdev_printk(KERN_NOTICE, scmd->device, "TASK ABORT not supported\n");
@@ -2838,7 +2840,7 @@
instance = (struct megasas_instance *)scmd->device->host->hostdata;
- if (instance->ctrl_context)
+ if (instance->adapter_type != MFI_SERIES)
ret = megasas_reset_target_fusion(scmd);
else {
sdev_printk(KERN_NOTICE, scmd->device, "TARGET RESET not supported\n");
@@ -3715,7 +3717,7 @@
PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
(instance->pdev->device ==
PCI_DEVICE_ID_LSI_SAS0071SKINNY) ||
- (instance->ctrl_context))
+ (instance->adapter_type != MFI_SERIES))
writel(
MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG,
&instance->reg_set->doorbell);
@@ -3733,7 +3735,7 @@
PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
(instance->pdev->device ==
PCI_DEVICE_ID_LSI_SAS0071SKINNY) ||
- (instance->ctrl_context))
+ (instance->adapter_type != MFI_SERIES))
writel(MFI_INIT_HOTPLUG,
&instance->reg_set->doorbell);
else
@@ -3753,11 +3755,11 @@
PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
(instance->pdev->device ==
PCI_DEVICE_ID_LSI_SAS0071SKINNY) ||
- (instance->ctrl_context)) {
+ (instance->adapter_type != MFI_SERIES)) {
writel(MFI_RESET_FLAGS,
&instance->reg_set->doorbell);
- if (instance->ctrl_context) {
+ if (instance->adapter_type != MFI_SERIES) {
for (i = 0; i < (10 * 1000); i += 20) {
if (readl(
&instance->
@@ -3924,7 +3926,8 @@
* max_sge_sz = 12 byte (sizeof megasas_sge64)
* Total 192 byte (3 MFI frame of 64 byte)
*/
- frame_count = instance->ctrl_context ? (3 + 1) : (15 + 1);
+ frame_count = (instance->adapter_type == MFI_SERIES) ?
+ (15 + 1) : (3 + 1);
instance->mfi_frame_size = MEGAMFI_FRAME_SIZE * frame_count;
/*
* Use DMA pool facility provided by PCI layer
@@ -3979,7 +3982,7 @@
memset(cmd->frame, 0, instance->mfi_frame_size);
cmd->frame->io.context = cpu_to_le32(cmd->index);
cmd->frame->io.pad_0 = 0;
- if (!instance->ctrl_context && reset_devices)
+ if ((instance->adapter_type == MFI_SERIES) && reset_devices)
cmd->frame->hdr.cmd = MFI_CMD_INVALID;
}
@@ -4099,7 +4102,7 @@
inline int
dcmd_timeout_ocr_possible(struct megasas_instance *instance) {
- if (!instance->ctrl_context)
+ if (instance->adapter_type == MFI_SERIES)
return KILL_ADAPTER;
else if (instance->unload ||
test_bit(MEGASAS_FUSION_IN_RESET, &instance->reset_flags))
@@ -4143,7 +4146,8 @@
dcmd->sgl.sge32[0].phys_addr = cpu_to_le32(instance->pd_info_h);
dcmd->sgl.sge32[0].length = cpu_to_le32(sizeof(struct MR_PD_INFO));
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance, cmd, MFI_IO_TIMEOUT_SECS);
else
ret = megasas_issue_polled(instance, cmd);
@@ -4240,7 +4244,8 @@
dcmd->sgl.sge32[0].phys_addr = cpu_to_le32(ci_h);
dcmd->sgl.sge32[0].length = cpu_to_le32(MEGASAS_MAX_PD * sizeof(struct MR_PD_LIST));
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance, cmd,
MFI_IO_TIMEOUT_SECS);
else
@@ -4251,7 +4256,7 @@
dev_info(&instance->pdev->dev, "MR_DCMD_PD_LIST_QUERY "
"failed/not supported by firmware\n");
- if (instance->ctrl_context)
+ if (instance->adapter_type != MFI_SERIES)
megaraid_sas_kill_hba(instance);
else
instance->pd_list_not_supported = 1;
@@ -4372,7 +4377,8 @@
dcmd->sgl.sge32[0].length = cpu_to_le32(sizeof(struct MR_LD_LIST));
dcmd->pad_0 = 0;
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance, cmd,
MFI_IO_TIMEOUT_SECS);
else
@@ -4491,7 +4497,8 @@
dcmd->sgl.sge32[0].length = cpu_to_le32(sizeof(struct MR_LD_TARGETID_LIST));
dcmd->pad_0 = 0;
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance, cmd, MFI_IO_TIMEOUT_SECS);
else
ret = megasas_issue_polled(instance, cmd);
@@ -4664,7 +4671,8 @@
dcmd->sgl.sge32[0].length = cpu_to_le32(sizeof(struct megasas_ctrl_info));
dcmd->mbox.b[0] = 1;
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance, cmd, MFI_IO_TIMEOUT_SECS);
else
ret = megasas_issue_polled(instance, cmd);
@@ -4783,7 +4791,8 @@
dcmd->sgl.sge32[0].phys_addr = cpu_to_le32(instance->crash_dump_h);
dcmd->sgl.sge32[0].length = cpu_to_le32(CRASH_DMA_BUF_SIZE);
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance, cmd, MFI_IO_TIMEOUT_SECS);
else
ret = megasas_issue_polled(instance, cmd);
@@ -5129,6 +5138,26 @@
instance->use_seqnum_jbod_fp = false;
}
+static void megasas_setup_reply_map(struct megasas_instance *instance)
+{
+ const struct cpumask *mask;
+ unsigned int queue, cpu;
+
+ for (queue = 0; queue < instance->msix_vectors; queue++) {
+ mask = pci_irq_get_affinity(instance->pdev, queue);
+ if (!mask)
+ goto fallback;
+
+ for_each_cpu(cpu, mask)
+ instance->reply_map[cpu] = queue;
+ }
+ return;
+
+fallback:
+ for_each_possible_cpu(cpu)
+ instance->reply_map[cpu] = cpu % instance->msix_vectors;
+}
+
/**
* megasas_init_fw - Initializes the FW
* @instance: Adapter soft state
@@ -5170,7 +5199,7 @@
reg_set = instance->reg_set;
- if (fusion)
+ if (instance->adapter_type != MFI_SERIES)
instance->instancet = &megasas_instance_template_fusion;
else {
switch (instance->pdev->device) {
@@ -5211,7 +5240,7 @@
goto fail_ready_state;
}
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
scratch_pad_3 =
readl(&instance->reg_set->outbound_scratch_pad_3);
instance->max_raid_mapsize = ((scratch_pad_3 >>
@@ -5229,7 +5258,8 @@
(&instance->reg_set->outbound_scratch_pad_2);
/* Check max MSI-X vectors */
if (fusion) {
- if (fusion->adapter_type == THUNDERBOLT_SERIES) { /* Thunderbolt Series*/
+ if (instance->adapter_type == THUNDERBOLT_SERIES) {
+ /* Thunderbolt Series*/
instance->msix_vectors = (scratch_pad_2
& MR_MAX_REPLY_QUEUES_OFFSET) + 1;
fw_msix_count = instance->msix_vectors;
@@ -5293,6 +5323,8 @@
goto fail_setup_irqs;
}
+ megasas_setup_reply_map(instance);
+
dev_info(&instance->pdev->dev,
"firmware supports msix\t: (%d)", fw_msix_count);
dev_info(&instance->pdev->dev,
@@ -5319,7 +5351,7 @@
if (instance->instancet->init_adapter(instance))
goto fail_init_adapter;
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
scratch_pad_4 =
readl(&instance->reg_set->outbound_scratch_pad_4);
if ((scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK) >=
@@ -5355,7 +5387,7 @@
memset(instance->ld_ids, 0xff, MEGASAS_MAX_LD_IDS);
/* stream detection initialization */
- if (instance->is_ventura && fusion) {
+ if (instance->adapter_type == VENTURA_SERIES) {
fusion->stream_detect_by_ld =
kzalloc(sizeof(struct LD_STREAM_DETECT *)
* MAX_LOGICAL_DRIVES_EXT,
@@ -5804,7 +5836,8 @@
dcmd->sgl.sge32[0].length =
cpu_to_le32(sizeof(struct MR_TARGET_PROPERTIES));
- if (instance->ctrl_context && !instance->mask_interrupts)
+ if ((instance->adapter_type != MFI_SERIES) &&
+ !instance->mask_interrupts)
ret = megasas_issue_blocked_cmd(instance,
cmd, MFI_IO_TIMEOUT_SECS);
else
@@ -5965,6 +5998,125 @@
return 1;
}
+/*
+ * megasas_set_adapter_type - Set adapter type.
+ * Supported controllers can be divided in
+ * 4 categories- enum MR_ADAPTER_TYPE {
+ * MFI_SERIES = 1,
+ * THUNDERBOLT_SERIES = 2,
+ * INVADER_SERIES = 3,
+ * VENTURA_SERIES = 4,
+ * };
+ * @instance: Adapter soft state
+ * return: void
+ */
+static inline void megasas_set_adapter_type(struct megasas_instance *instance)
+{
+ switch (instance->pdev->device) {
+ case PCI_DEVICE_ID_LSI_VENTURA:
+ case PCI_DEVICE_ID_LSI_HARPOON:
+ case PCI_DEVICE_ID_LSI_TOMCAT:
+ case PCI_DEVICE_ID_LSI_VENTURA_4PORT:
+ case PCI_DEVICE_ID_LSI_CRUSADER_4PORT:
+ instance->adapter_type = VENTURA_SERIES;
+ break;
+ case PCI_DEVICE_ID_LSI_FUSION:
+ case PCI_DEVICE_ID_LSI_PLASMA:
+ instance->adapter_type = THUNDERBOLT_SERIES;
+ break;
+ case PCI_DEVICE_ID_LSI_INVADER:
+ case PCI_DEVICE_ID_LSI_INTRUDER:
+ case PCI_DEVICE_ID_LSI_INTRUDER_24:
+ case PCI_DEVICE_ID_LSI_CUTLASS_52:
+ case PCI_DEVICE_ID_LSI_CUTLASS_53:
+ case PCI_DEVICE_ID_LSI_FURY:
+ instance->adapter_type = INVADER_SERIES;
+ break;
+ default: /* For all other supported controllers */
+ instance->adapter_type = MFI_SERIES;
+ break;
+ }
+}
+
+static inline int megasas_alloc_mfi_ctrl_mem(struct megasas_instance *instance)
+{
+ instance->producer = pci_alloc_consistent(instance->pdev, sizeof(u32),
+ &instance->producer_h);
+ instance->consumer = pci_alloc_consistent(instance->pdev, sizeof(u32),
+ &instance->consumer_h);
+
+ if (!instance->producer || !instance->consumer) {
+ dev_err(&instance->pdev->dev,
+ "Failed to allocate memory for producer, consumer\n");
+ return -1;
+ }
+
+ *instance->producer = 0;
+ *instance->consumer = 0;
+ return 0;
+}
+
+/**
+ * megasas_alloc_ctrl_mem - Allocate per controller memory for core data
+ * structures which are not common across MFI
+ * adapters and fusion adapters.
+ * For MFI based adapters, allocate producer and
+ * consumer buffers. For fusion adapters, allocate
+ * memory for fusion context.
+ * @instance: Adapter soft state
+ * return: 0 for SUCCESS
+ */
+static int megasas_alloc_ctrl_mem(struct megasas_instance *instance)
+{
+ instance->reply_map = kzalloc(sizeof(unsigned int) * nr_cpu_ids,
+ GFP_KERNEL);
+ if (!instance->reply_map)
+ return -ENOMEM;
+
+ switch (instance->adapter_type) {
+ case MFI_SERIES:
+ if (megasas_alloc_mfi_ctrl_mem(instance))
+ goto fail;
+ break;
+ case VENTURA_SERIES:
+ case THUNDERBOLT_SERIES:
+ case INVADER_SERIES:
+ if (megasas_alloc_fusion_context(instance))
+ goto fail;
+ break;
+ }
+
+ return 0;
+ fail:
+ kfree(instance->reply_map);
+ instance->reply_map = NULL;
+ return -ENOMEM;
+}
+
+/*
+ * megasas_free_ctrl_mem - Free fusion context for fusion adapters and
+ * producer, consumer buffers for MFI adapters
+ *
+ * @instance - Adapter soft instance
+ *
+ */
+static inline void megasas_free_ctrl_mem(struct megasas_instance *instance)
+{
+ kfree(instance->reply_map);
+ if (instance->adapter_type == MFI_SERIES) {
+ if (instance->producer)
+ pci_free_consistent(instance->pdev, sizeof(u32),
+ instance->producer,
+ instance->producer_h);
+ if (instance->consumer)
+ pci_free_consistent(instance->pdev, sizeof(u32),
+ instance->consumer,
+ instance->consumer_h);
+ } else {
+ megasas_free_fusion_context(instance);
+ }
+}
+
/**
* megasas_probe_one - PCI hotplug entry point
* @pdev: PCI device structure
@@ -5977,7 +6129,6 @@
struct Scsi_Host *host;
struct megasas_instance *instance;
u16 control = 0;
- struct fusion_context *fusion = NULL;
/* Reset MSI-X in the kdump kernel */
if (reset_devices) {
@@ -6022,56 +6173,10 @@
atomic_set(&instance->fw_reset_no_pci_access, 0);
instance->pdev = pdev;
- switch (instance->pdev->device) {
- case PCI_DEVICE_ID_LSI_VENTURA:
- case PCI_DEVICE_ID_LSI_HARPOON:
- case PCI_DEVICE_ID_LSI_TOMCAT:
- case PCI_DEVICE_ID_LSI_VENTURA_4PORT:
- case PCI_DEVICE_ID_LSI_CRUSADER_4PORT:
- instance->is_ventura = true;
- case PCI_DEVICE_ID_LSI_FUSION:
- case PCI_DEVICE_ID_LSI_PLASMA:
- case PCI_DEVICE_ID_LSI_INVADER:
- case PCI_DEVICE_ID_LSI_FURY:
- case PCI_DEVICE_ID_LSI_INTRUDER:
- case PCI_DEVICE_ID_LSI_INTRUDER_24:
- case PCI_DEVICE_ID_LSI_CUTLASS_52:
- case PCI_DEVICE_ID_LSI_CUTLASS_53:
- {
- if (megasas_alloc_fusion_context(instance)) {
- megasas_free_fusion_context(instance);
- goto fail_alloc_dma_buf;
- }
- fusion = instance->ctrl_context;
+ megasas_set_adapter_type(instance);
- if ((instance->pdev->device == PCI_DEVICE_ID_LSI_FUSION) ||
- (instance->pdev->device == PCI_DEVICE_ID_LSI_PLASMA))
- fusion->adapter_type = THUNDERBOLT_SERIES;
- else if (instance->is_ventura)
- fusion->adapter_type = VENTURA_SERIES;
- else
- fusion->adapter_type = INVADER_SERIES;
- }
- break;
- default: /* For all other supported controllers */
-
- instance->producer =
- pci_alloc_consistent(pdev, sizeof(u32),
- &instance->producer_h);
- instance->consumer =
- pci_alloc_consistent(pdev, sizeof(u32),
- &instance->consumer_h);
-
- if (!instance->producer || !instance->consumer) {
- dev_printk(KERN_DEBUG, &pdev->dev, "Failed to allocate "
- "memory for producer, consumer\n");
- goto fail_alloc_dma_buf;
- }
-
- *instance->producer = 0;
- *instance->consumer = 0;
- break;
- }
+ if (megasas_alloc_ctrl_mem(instance))
+ goto fail_alloc_dma_buf;
/* Crash dump feature related initialisation*/
instance->drv_buf_index = 0;
@@ -6166,7 +6271,7 @@
instance->disableOnlineCtrlReset = 1;
instance->UnevenSpanSupport = 0;
- if (instance->ctrl_context) {
+ if (instance->adapter_type != MFI_SERIES) {
INIT_WORK(&instance->work_init, megasas_fusion_ocr_wq);
INIT_WORK(&instance->crash_init, megasas_fusion_crash_dump_wq);
} else
@@ -6246,7 +6351,7 @@
instance->instancet->disable_intr(instance);
megasas_destroy_irqs(instance);
- if (instance->ctrl_context)
+ if (instance->adapter_type != MFI_SERIES)
megasas_release_fusion(instance);
else
megasas_release_mfi(instance);
@@ -6267,14 +6372,8 @@
pci_free_consistent(pdev, sizeof(struct MR_TARGET_PROPERTIES),
instance->tgt_prop,
instance->tgt_prop_h);
- if (instance->producer)
- pci_free_consistent(pdev, sizeof(u32), instance->producer,
- instance->producer_h);
- if (instance->consumer)
- pci_free_consistent(pdev, sizeof(u32), instance->consumer,
- instance->consumer_h);
+ megasas_free_ctrl_mem(instance);
scsi_host_put(host);
-
fail_alloc_instance:
fail_set_dma_mask:
pci_disable_device(pdev);
@@ -6480,7 +6579,9 @@
if (rval < 0)
goto fail_reenable_msix;
- if (instance->ctrl_context) {
+ megasas_setup_reply_map(instance);
+
+ if (instance->adapter_type != MFI_SERIES) {
megasas_reset_reply_desc(instance);
if (megasas_ioc_init_fusion(instance)) {
megasas_free_cmds(instance);
@@ -6543,12 +6644,8 @@
pci_free_consistent(pdev, sizeof(struct MR_TARGET_PROPERTIES),
instance->tgt_prop,
instance->tgt_prop_h);
- if (instance->producer)
- pci_free_consistent(pdev, sizeof(u32), instance->producer,
- instance->producer_h);
- if (instance->consumer)
- pci_free_consistent(pdev, sizeof(u32), instance->consumer,
- instance->consumer_h);
+
+ megasas_free_ctrl_mem(instance);
scsi_host_put(host);
fail_set_dma_mask:
@@ -6656,7 +6753,7 @@
if (instance->msix_vectors)
pci_free_irq_vectors(instance->pdev);
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i)
kfree(fusion->stream_detect_by_ld[i]);
kfree(fusion->stream_detect_by_ld);
@@ -6664,7 +6761,7 @@
}
- if (instance->ctrl_context) {
+ if (instance->adapter_type != MFI_SERIES) {
megasas_release_fusion(instance);
pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) +
(sizeof(struct MR_PD_CFG_SEQ) *
@@ -6689,15 +6786,8 @@
fusion->pd_seq_sync[i],
fusion->pd_seq_phys[i]);
}
- megasas_free_fusion_context(instance);
} else {
megasas_release_mfi(instance);
- pci_free_consistent(pdev, sizeof(u32),
- instance->producer,
- instance->producer_h);
- pci_free_consistent(pdev, sizeof(u32),
- instance->consumer,
- instance->consumer_h);
}
kfree(instance->ctrl_info);
@@ -6738,6 +6828,8 @@
pci_free_consistent(pdev, sizeof(struct MR_DRV_SYSTEM_INFO),
instance->system_info_buf, instance->system_info_h);
+ megasas_free_ctrl_mem(instance);
+
scsi_host_put(host);
pci_disable_device(pdev);
diff --git a/drivers/scsi/megaraid/megaraid_sas_fp.c b/drivers/scsi/megaraid/megaraid_sas_fp.c
index 0894514..f2ffde4 100644
--- a/drivers/scsi/megaraid/megaraid_sas_fp.c
+++ b/drivers/scsi/megaraid/megaraid_sas_fp.c
@@ -745,7 +745,7 @@
*pDevHandle = MR_PdDevHandleGet(pd, map);
*pPdInterface = MR_PdInterfaceTypeGet(pd, map);
/* get second pd also for raid 1/10 fast path writes*/
- if (instance->is_ventura &&
+ if ((instance->adapter_type == VENTURA_SERIES) &&
(raid->level == 1) &&
!io_info->isRead) {
r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
@@ -755,8 +755,8 @@
}
} else {
if ((raid->level >= 5) &&
- ((fusion->adapter_type == THUNDERBOLT_SERIES) ||
- ((fusion->adapter_type == INVADER_SERIES) &&
+ ((instance->adapter_type == THUNDERBOLT_SERIES) ||
+ ((instance->adapter_type == INVADER_SERIES) &&
(raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
else if (raid->level == 1) {
@@ -770,7 +770,7 @@
}
*pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
(span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
io_info->span_arm =
@@ -861,7 +861,7 @@
*pDevHandle = MR_PdDevHandleGet(pd, map);
*pPdInterface = MR_PdInterfaceTypeGet(pd, map);
/* get second pd also for raid 1/10 fast path writes*/
- if (instance->is_ventura &&
+ if ((instance->adapter_type == VENTURA_SERIES) &&
(raid->level == 1) &&
!io_info->isRead) {
r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
@@ -871,8 +871,8 @@
}
} else {
if ((raid->level >= 5) &&
- ((fusion->adapter_type == THUNDERBOLT_SERIES) ||
- ((fusion->adapter_type == INVADER_SERIES) &&
+ ((instance->adapter_type == THUNDERBOLT_SERIES) ||
+ ((instance->adapter_type == INVADER_SERIES) &&
(raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
else if (raid->level == 1) {
@@ -888,7 +888,7 @@
}
*pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
(span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
io_info->span_arm =
@@ -1096,10 +1096,10 @@
cpu_to_le16(raid->fpIoTimeoutForLd ?
raid->fpIoTimeoutForLd :
map->raidMap.fpPdIoTimeoutSec);
- if (fusion->adapter_type == INVADER_SERIES)
+ if (instance->adapter_type == INVADER_SERIES)
pRAID_Context->reg_lock_flags = (isRead) ?
raid->regTypeReqOnRead : raid->regTypeReqOnWrite;
- else if (!instance->is_ventura)
+ else if (instance->adapter_type == THUNDERBOLT_SERIES)
pRAID_Context->reg_lock_flags = (isRead) ?
REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite;
pRAID_Context->virtual_disk_tgt_id = raid->targetId;
diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c
index 72a9191..d8f6265 100644
--- a/drivers/scsi/megaraid/megaraid_sas_fusion.c
+++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c
@@ -237,7 +237,7 @@
reg_set = instance->reg_set;
/* ventura FW does not fill outbound_scratch_pad_3 with queue depth */
- if (!instance->is_ventura)
+ if (instance->adapter_type < VENTURA_SERIES)
cur_max_fw_cmds =
readl(&instance->reg_set->outbound_scratch_pad_3) & 0x00FFFF;
@@ -285,7 +285,7 @@
instance->host->can_queue = instance->cur_can_queue;
}
- if (instance->is_ventura)
+ if (instance->adapter_type == VENTURA_SERIES)
instance->max_mpt_cmds =
instance->max_fw_cmds * RAID_1_PEER_CMDS;
else
@@ -838,7 +838,7 @@
drv_ops = (MFI_CAPABILITIES *) &(init_frame->driver_operations);
/* driver support Extended MSIX */
- if (fusion->adapter_type >= INVADER_SERIES)
+ if (instance->adapter_type >= INVADER_SERIES)
drv_ops->mfi_capabilities.support_additional_msix = 1;
/* driver supports HA / Remote LUN over Fast Path interface */
drv_ops->mfi_capabilities.support_fp_remote_lun = 1;
@@ -1789,7 +1789,7 @@
fusion = instance->ctrl_context;
- if (fusion->adapter_type >= INVADER_SERIES) {
+ if (instance->adapter_type >= INVADER_SERIES) {
struct MPI25_IEEE_SGE_CHAIN64 *sgl_ptr_end = sgl_ptr;
sgl_ptr_end += fusion->max_sge_in_main_msg - 1;
sgl_ptr_end->Flags = 0;
@@ -1799,7 +1799,7 @@
sgl_ptr->Length = cpu_to_le32(sg_dma_len(os_sgl));
sgl_ptr->Address = cpu_to_le64(sg_dma_address(os_sgl));
sgl_ptr->Flags = 0;
- if (fusion->adapter_type >= INVADER_SERIES)
+ if (instance->adapter_type >= INVADER_SERIES)
if (i == sge_count - 1)
sgl_ptr->Flags = IEEE_SGE_FLAGS_END_OF_LIST;
sgl_ptr++;
@@ -1809,7 +1809,7 @@
(sge_count > fusion->max_sge_in_main_msg)) {
struct MPI25_IEEE_SGE_CHAIN64 *sg_chain;
- if (fusion->adapter_type >= INVADER_SERIES) {
+ if (instance->adapter_type >= INVADER_SERIES) {
if ((le16_to_cpu(cmd->io_request->IoFlags) &
MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) !=
MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH)
@@ -1825,7 +1825,7 @@
sg_chain = sgl_ptr;
/* Prepare chain element */
sg_chain->NextChainOffset = 0;
- if (fusion->adapter_type >= INVADER_SERIES)
+ if (instance->adapter_type >= INVADER_SERIES)
sg_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT;
else
sg_chain->Flags =
@@ -2341,15 +2341,12 @@
fp_possible = (io_info.fpOkForIo > 0) ? true : false;
}
- /* Use raw_smp_processor_id() for now until cmd->request->cpu is CPU
- id by default, not CPU group id, otherwise all MSI-X queues won't
- be utilized */
- cmd->request_desc->SCSIIO.MSIxIndex = instance->msix_vectors ?
- raw_smp_processor_id() % instance->msix_vectors : 0;
+ cmd->request_desc->SCSIIO.MSIxIndex =
+ instance->reply_map[raw_smp_processor_id()];
praid_context = &io_request->RaidContext;
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
spin_lock_irqsave(&instance->stream_lock, spinlock_flags);
megasas_stream_detect(instance, cmd, &io_info);
spin_unlock_irqrestore(&instance->stream_lock, spinlock_flags);
@@ -2402,7 +2399,7 @@
cmd->request_desc->SCSIIO.RequestFlags =
(MPI2_REQ_DESCRIPT_FLAGS_FP_IO
<< MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
- if (fusion->adapter_type == INVADER_SERIES) {
+ if (instance->adapter_type == INVADER_SERIES) {
if (io_request->RaidContext.raid_context.reg_lock_flags ==
REGION_TYPE_UNUSED)
cmd->request_desc->SCSIIO.RequestFlags =
@@ -2415,7 +2412,7 @@
io_request->RaidContext.raid_context.reg_lock_flags |=
(MR_RL_FLAGS_GRANT_DESTINATION_CUDA |
MR_RL_FLAGS_SEQ_NUM_ENABLE);
- } else if (instance->is_ventura) {
+ } else if (instance->adapter_type == VENTURA_SERIES) {
io_request->RaidContext.raid_context_g35.nseg_type |=
(1 << RAID_CONTEXT_NSEG_SHIFT);
io_request->RaidContext.raid_context_g35.nseg_type |=
@@ -2434,7 +2431,7 @@
&io_info, local_map_ptr);
scp->SCp.Status |= MEGASAS_LOAD_BALANCE_FLAG;
cmd->pd_r1_lb = io_info.pd_after_lb;
- if (instance->is_ventura)
+ if (instance->adapter_type == VENTURA_SERIES)
io_request->RaidContext.raid_context_g35.span_arm
= io_info.span_arm;
else
@@ -2444,7 +2441,7 @@
} else
scp->SCp.Status &= ~MEGASAS_LOAD_BALANCE_FLAG;
- if (instance->is_ventura)
+ if (instance->adapter_type == VENTURA_SERIES)
cmd->r1_alt_dev_handle = io_info.r1_alt_dev_handle;
else
cmd->r1_alt_dev_handle = MR_DEVHANDLE_INVALID;
@@ -2467,7 +2464,7 @@
cmd->request_desc->SCSIIO.RequestFlags =
(MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO
<< MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
- if (fusion->adapter_type == INVADER_SERIES) {
+ if (instance->adapter_type == INVADER_SERIES) {
if (io_info.do_fp_rlbypass ||
(io_request->RaidContext.raid_context.reg_lock_flags
== REGION_TYPE_UNUSED))
@@ -2480,7 +2477,7 @@
(MR_RL_FLAGS_GRANT_DESTINATION_CPU0 |
MR_RL_FLAGS_SEQ_NUM_ENABLE);
io_request->RaidContext.raid_context.nseg = 0x1;
- } else if (instance->is_ventura) {
+ } else if (instance->adapter_type == VENTURA_SERIES) {
io_request->RaidContext.raid_context_g35.routing_flags |=
(1 << MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT);
io_request->RaidContext.raid_context_g35.nseg_type |=
@@ -2555,7 +2552,7 @@
/* set RAID context values */
pRAID_Context->config_seq_num = raid->seqNum;
- if (!instance->is_ventura)
+ if (instance->adapter_type != VENTURA_SERIES)
pRAID_Context->reg_lock_flags = REGION_TYPE_SHARED_READ;
pRAID_Context->timeout_value =
cpu_to_le16(raid->fpIoTimeoutForLd);
@@ -2640,7 +2637,7 @@
cpu_to_le16(device_id + (MAX_PHYSICAL_DEVICES - 1));
pRAID_Context->config_seq_num = pd_sync->seq[pd_index].seqNum;
io_request->DevHandle = pd_sync->seq[pd_index].devHandle;
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
io_request->RaidContext.raid_context_g35.routing_flags |=
(1 << MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT);
io_request->RaidContext.raid_context_g35.nseg_type |=
@@ -2667,10 +2664,9 @@
}
cmd->request_desc->SCSIIO.DevHandle = io_request->DevHandle;
- cmd->request_desc->SCSIIO.MSIxIndex =
- instance->msix_vectors ?
- (raw_smp_processor_id() % instance->msix_vectors) : 0;
+ cmd->request_desc->SCSIIO.MSIxIndex =
+ instance->reply_map[raw_smp_processor_id()];
if (!fp_possible) {
/* system pd firmware path */
@@ -2688,7 +2684,7 @@
pRAID_Context->timeout_value =
cpu_to_le16((os_timeout_value > timeout_limit) ?
timeout_limit : os_timeout_value);
- if (fusion->adapter_type >= INVADER_SERIES)
+ if (instance->adapter_type >= INVADER_SERIES)
io_request->IoFlags |=
cpu_to_le16(MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH);
@@ -2771,7 +2767,7 @@
return 1;
}
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
set_num_sge(&io_request->RaidContext.raid_context_g35, sge_count);
cpu_to_le16s(&io_request->RaidContext.raid_context_g35.routing_flags);
cpu_to_le16s(&io_request->RaidContext.raid_context_g35.nseg_type);
@@ -3301,7 +3297,7 @@
io_req = cmd->io_request;
- if (fusion->adapter_type >= INVADER_SERIES) {
+ if (instance->adapter_type >= INVADER_SERIES) {
struct MPI25_IEEE_SGE_CHAIN64 *sgl_ptr_end =
(struct MPI25_IEEE_SGE_CHAIN64 *)&io_req->SGL;
sgl_ptr_end += fusion->max_sge_in_main_msg - 1;
@@ -4233,7 +4229,7 @@
for (i = 0 ; i < instance->max_scsi_cmds; i++) {
cmd_fusion = fusion->cmd_list[i];
/*check for extra commands issued by driver*/
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
r1_cmd = fusion->cmd_list[i + instance->max_fw_cmds];
megasas_return_cmd_fusion(instance, r1_cmd);
}
@@ -4334,7 +4330,7 @@
megasas_set_dynamic_target_properties(sdev);
/* reset stream detection array */
- if (instance->is_ventura) {
+ if (instance->adapter_type == VENTURA_SERIES) {
for (j = 0; j < MAX_LOGICAL_DRIVES_EXT; ++j) {
memset(fusion->stream_detect_by_ld[j],
0, sizeof(struct LD_STREAM_DETECT));
diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.h b/drivers/scsi/megaraid/megaraid_sas_fusion.h
index d78d7611..7c1f7cc 100644
--- a/drivers/scsi/megaraid/megaraid_sas_fusion.h
+++ b/drivers/scsi/megaraid/megaraid_sas_fusion.h
@@ -104,12 +104,6 @@
#define RAID_1_PEER_CMDS 2
#define JBOD_MAPS_COUNT 2
-enum MR_FUSION_ADAPTER_TYPE {
- THUNDERBOLT_SERIES = 0,
- INVADER_SERIES = 1,
- VENTURA_SERIES = 2,
-};
-
/*
* Raid Context structure which describes MegaRAID specific IO Parameters
* This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
@@ -1319,7 +1313,6 @@
struct LD_LOAD_BALANCE_INFO *load_balance_info;
u32 load_balance_info_pages;
LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
- u8 adapter_type;
struct LD_STREAM_DETECT **stream_detect_by_ld;
};
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index e24f579..bcde613 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -4627,7 +4627,8 @@
return;
if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
- fcport->fp_speed > ha->link_data_rate)
+ fcport->fp_speed > ha->link_data_rate ||
+ !ha->flags.gpsc_supported)
return;
rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 13a00a4..e073eb1 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -2454,8 +2454,12 @@
ox_id = le16_to_cpu(sts24->ox_id);
par_sense_len = sizeof(sts24->data);
/* Valid values of the retry delay timer are 0x1-0xffef */
- if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1)
- retry_delay = sts24->retry_delay;
+ if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1) {
+ retry_delay = sts24->retry_delay & 0x3fff;
+ ql_dbg(ql_dbg_io, sp->vha, 0x3033,
+ "%s: scope=%#x retry_delay=%#x\n", __func__,
+ sts24->retry_delay >> 14, retry_delay);
+ }
} else {
if (scsi_status & SS_SENSE_LEN_VALID)
sense_len = le16_to_cpu(sts->req_sense_length);
diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index fab538a..b6b450d 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -51,6 +51,7 @@
#include <linux/atomic.h>
#include <linux/ratelimit.h>
#include <linux/uio.h>
+#include <linux/cred.h> /* for sg_check_file_access() */
#include "scsi.h"
#include <scsi/scsi_dbg.h>
@@ -210,6 +211,33 @@
sdev_prefix_printk(prefix, (sdp)->device, \
(sdp)->disk->disk_name, fmt, ##a)
+/*
+ * The SCSI interfaces that use read() and write() as an asynchronous variant of
+ * ioctl(..., SG_IO, ...) are fundamentally unsafe, since there are lots of ways
+ * to trigger read() and write() calls from various contexts with elevated
+ * privileges. This can lead to kernel memory corruption (e.g. if these
+ * interfaces are called through splice()) and privilege escalation inside
+ * userspace (e.g. if a process with access to such a device passes a file
+ * descriptor to a SUID binary as stdin/stdout/stderr).
+ *
+ * This function provides protection for the legacy API by restricting the
+ * calling context.
+ */
+static int sg_check_file_access(struct file *filp, const char *caller)
+{
+ if (filp->f_cred != current_real_cred()) {
+ pr_err_once("%s: process %d (%s) changed security contexts after opening file descriptor, this is not allowed.\n",
+ caller, task_tgid_vnr(current), current->comm);
+ return -EPERM;
+ }
+ if (uaccess_kernel()) {
+ pr_err_once("%s: process %d (%s) called from kernel context, this is not allowed.\n",
+ caller, task_tgid_vnr(current), current->comm);
+ return -EACCES;
+ }
+ return 0;
+}
+
static int sg_allow_access(struct file *filp, unsigned char *cmd)
{
struct sg_fd *sfp = filp->private_data;
@@ -394,6 +422,14 @@
struct sg_header *old_hdr = NULL;
int retval = 0;
+ /*
+ * This could cause a response to be stranded. Close the associated
+ * file descriptor to free up any resources being held.
+ */
+ retval = sg_check_file_access(filp, __func__);
+ if (retval)
+ return retval;
+
if ((!(sfp = (Sg_fd *) filp->private_data)) || (!(sdp = sfp->parentdp)))
return -ENXIO;
SCSI_LOG_TIMEOUT(3, sg_printk(KERN_INFO, sdp,
@@ -581,9 +617,11 @@
struct sg_header old_hdr;
sg_io_hdr_t *hp;
unsigned char cmnd[SG_MAX_CDB_SIZE];
+ int retval;
- if (unlikely(uaccess_kernel()))
- return -EINVAL;
+ retval = sg_check_file_access(filp, __func__);
+ if (retval)
+ return retval;
if ((!(sfp = (Sg_fd *) filp->private_data)) || (!(sdp = sfp->parentdp)))
return -ENXIO;
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 2b38db2..221820a 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -1098,7 +1098,7 @@
hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
}
- if (host->hw_ver.major >= 0x2) {
+ if (host->hw_ver.major == 0x2) {
hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
if (!ufs_qcom_cap_qunipro(host))
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 00e7905..3704b2d 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -266,6 +266,18 @@
}
}
+static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
+{
+ if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
+ scsi_unblock_requests(hba->host);
+}
+
+static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
+{
+ if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
+ scsi_block_requests(hba->host);
+}
+
/* replace non-printable or non-ASCII characters with spaces */
static inline void ufshcd_remove_non_printable(char *val)
{
@@ -1091,12 +1103,12 @@
* make sure that there are no outstanding requests when
* clock scaling is in progress
*/
- scsi_block_requests(hba->host);
+ ufshcd_scsi_block_requests(hba);
down_write(&hba->clk_scaling_lock);
if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
ret = -EBUSY;
up_write(&hba->clk_scaling_lock);
- scsi_unblock_requests(hba->host);
+ ufshcd_scsi_unblock_requests(hba);
}
return ret;
@@ -1105,7 +1117,7 @@
static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
{
up_write(&hba->clk_scaling_lock);
- scsi_unblock_requests(hba->host);
+ ufshcd_scsi_unblock_requests(hba);
}
/**
@@ -1425,7 +1437,7 @@
hba->clk_gating.is_suspended = false;
}
unblock_reqs:
- scsi_unblock_requests(hba->host);
+ ufshcd_scsi_unblock_requests(hba);
}
/**
@@ -1481,11 +1493,12 @@
* work and to enable clocks.
*/
case CLKS_OFF:
- scsi_block_requests(hba->host);
+ ufshcd_scsi_block_requests(hba);
hba->clk_gating.state = REQ_CLKS_ON;
trace_ufshcd_clk_gating(dev_name(hba->dev),
hba->clk_gating.state);
- schedule_work(&hba->clk_gating.ungate_work);
+ queue_work(hba->clk_gating.clk_gating_workq,
+ &hba->clk_gating.ungate_work);
/*
* fall through to check if we should wait for this
* work to be done or not.
@@ -1671,6 +1684,8 @@
static void ufshcd_init_clk_gating(struct ufs_hba *hba)
{
+ char wq_name[sizeof("ufs_clk_gating_00")];
+
if (!ufshcd_is_clkgating_allowed(hba))
return;
@@ -1678,6 +1693,11 @@
INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
+ snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
+ hba->host->host_no);
+ hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
+ WQ_MEM_RECLAIM);
+
hba->clk_gating.is_enabled = true;
hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
@@ -1705,6 +1725,7 @@
device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
cancel_work_sync(&hba->clk_gating.ungate_work);
cancel_delayed_work_sync(&hba->clk_gating.gate_work);
+ destroy_workqueue(hba->clk_gating.clk_gating_workq);
}
/* Must be called with host lock acquired */
@@ -4969,6 +4990,7 @@
hba = container_of(work, struct ufs_hba, eeh_work);
pm_runtime_get_sync(hba->dev);
+ scsi_block_requests(hba->host);
err = ufshcd_get_ee_status(hba, &status);
if (err) {
dev_err(hba->dev, "%s: failed to get exception status %d\n",
@@ -4982,6 +5004,7 @@
ufshcd_bkops_exception_event_handler(hba);
out:
+ scsi_unblock_requests(hba->host);
pm_runtime_put_sync(hba->dev);
return;
}
@@ -5192,7 +5215,7 @@
out:
spin_unlock_irqrestore(hba->host->host_lock, flags);
- scsi_unblock_requests(hba->host);
+ ufshcd_scsi_unblock_requests(hba);
ufshcd_release(hba);
pm_runtime_put_sync(hba->dev);
}
@@ -5294,7 +5317,7 @@
/* handle fatal errors only when link is functional */
if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
/* block commands from scsi mid-layer */
- scsi_block_requests(hba->host);
+ ufshcd_scsi_block_requests(hba);
hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
@@ -5371,19 +5394,30 @@
u32 intr_status, enabled_intr_status;
irqreturn_t retval = IRQ_NONE;
struct ufs_hba *hba = __hba;
+ int retries = hba->nutrs;
spin_lock(hba->host->host_lock);
intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
- enabled_intr_status =
- intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
- if (intr_status)
- ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
+ /*
+ * There could be max of hba->nutrs reqs in flight and in worst case
+ * if the reqs get finished 1 by 1 after the interrupt status is
+ * read, make sure we handle them by checking the interrupt status
+ * again in a loop until we process all of the reqs before returning.
+ */
+ do {
+ enabled_intr_status =
+ intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
+ if (intr_status)
+ ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
+ if (enabled_intr_status) {
+ ufshcd_sl_intr(hba, enabled_intr_status);
+ retval = IRQ_HANDLED;
+ }
- if (enabled_intr_status) {
- ufshcd_sl_intr(hba, enabled_intr_status);
- retval = IRQ_HANDLED;
- }
+ intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
+ } while (intr_status && --retries);
+
spin_unlock(hba->host->host_lock);
return retval;
}
@@ -6799,9 +6833,16 @@
if (list_empty(head))
goto out;
- ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
- if (ret)
- return ret;
+ /*
+ * vendor specific setup_clocks ops may depend on clocks managed by
+ * this standard driver hence call the vendor specific setup_clocks
+ * before disabling the clocks managed here.
+ */
+ if (!on) {
+ ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
+ if (ret)
+ return ret;
+ }
list_for_each_entry(clki, head, list) {
if (!IS_ERR_OR_NULL(clki->clk)) {
@@ -6825,9 +6866,16 @@
}
}
- ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
- if (ret)
- return ret;
+ /*
+ * vendor specific setup_clocks ops may depend on clocks managed by
+ * this standard driver hence call the vendor specific setup_clocks
+ * after enabling the clocks managed here.
+ */
+ if (on) {
+ ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
+ if (ret)
+ return ret;
+ }
out:
if (ret) {
@@ -7904,7 +7952,7 @@
/* Hold auto suspend until async scan completes */
pm_runtime_get_sync(dev);
-
+ atomic_set(&hba->scsi_block_reqs_cnt, 0);
/*
* We are assuming that device wasn't put in sleep/power-down
* state exclusively during the boot stage before kernel.
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 8110dcd..b44b2dd 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -362,6 +362,7 @@
struct device_attribute enable_attr;
bool is_enabled;
int active_reqs;
+ struct workqueue_struct *clk_gating_workq;
};
struct ufs_saved_pwr_info {
@@ -499,6 +500,7 @@
* @urgent_bkops_lvl: keeps track of urgent bkops level for device
* @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
* device is known or not.
+ * @scsi_block_reqs_cnt: reference counting for scsi block requests
*/
struct ufs_hba {
void __iomem *mmio_base;
@@ -683,6 +685,7 @@
struct rw_semaphore clk_scaling_lock;
struct ufs_desc_size desc_size;
+ atomic_t scsi_block_reqs_cnt;
};
/* Returns true if clocks can be gated. Otherwise false */
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index e3df1e9..2afae64 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -70,6 +70,12 @@
PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
+/* Group of bits used for shown slave capability */
+#define PWRAP_SLV_CAP_SPI BIT(0)
+#define PWRAP_SLV_CAP_DUALIO BIT(1)
+#define PWRAP_SLV_CAP_SECURITY BIT(2)
+#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
+
/* defines for slave device wrapper registers */
enum dew_regs {
PWRAP_DEW_BASE,
@@ -208,6 +214,36 @@
PWRAP_ADC_RDATA_ADDR1,
PWRAP_ADC_RDATA_ADDR2,
+ /* MT7622 only regs */
+ PWRAP_EINT_STA0_ADR,
+ PWRAP_EINT_STA1_ADR,
+ PWRAP_STA,
+ PWRAP_CLR,
+ PWRAP_DVFS_ADR8,
+ PWRAP_DVFS_WDATA8,
+ PWRAP_DVFS_ADR9,
+ PWRAP_DVFS_WDATA9,
+ PWRAP_DVFS_ADR10,
+ PWRAP_DVFS_WDATA10,
+ PWRAP_DVFS_ADR11,
+ PWRAP_DVFS_WDATA11,
+ PWRAP_DVFS_ADR12,
+ PWRAP_DVFS_WDATA12,
+ PWRAP_DVFS_ADR13,
+ PWRAP_DVFS_WDATA13,
+ PWRAP_DVFS_ADR14,
+ PWRAP_DVFS_WDATA14,
+ PWRAP_DVFS_ADR15,
+ PWRAP_DVFS_WDATA15,
+ PWRAP_EXT_CK,
+ PWRAP_ADC_RDATA_ADDR,
+ PWRAP_GPS_STA,
+ PWRAP_SW_RST,
+ PWRAP_DVFS_STEP_CTRL0,
+ PWRAP_DVFS_STEP_CTRL1,
+ PWRAP_DVFS_STEP_CTRL2,
+ PWRAP_SPI2_CTRL,
+
/* MT8135 only regs */
PWRAP_CSHEXT,
PWRAP_EVENT_IN_EN,
@@ -330,6 +366,118 @@
[PWRAP_ADC_RDATA_ADDR2] = 0x154,
};
+static int mt7622_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xC,
+ [PWRAP_RDDMY] = 0x10,
+ [PWRAP_SI_CK_CON] = 0x14,
+ [PWRAP_CSHEXT_WRITE] = 0x18,
+ [PWRAP_CSHEXT_READ] = 0x1C,
+ [PWRAP_CSLEXT_START] = 0x20,
+ [PWRAP_CSLEXT_END] = 0x24,
+ [PWRAP_STAUPD_PRD] = 0x28,
+ [PWRAP_STAUPD_GRPEN] = 0x2C,
+ [PWRAP_EINT_STA0_ADR] = 0x30,
+ [PWRAP_EINT_STA1_ADR] = 0x34,
+ [PWRAP_STA] = 0x38,
+ [PWRAP_CLR] = 0x3C,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x40,
+ [PWRAP_STAUPD_STA] = 0x44,
+ [PWRAP_WRAP_STA] = 0x48,
+ [PWRAP_HARB_INIT] = 0x4C,
+ [PWRAP_HARB_HPRIO] = 0x50,
+ [PWRAP_HIPRIO_ARB_EN] = 0x54,
+ [PWRAP_HARB_STA0] = 0x58,
+ [PWRAP_HARB_STA1] = 0x5C,
+ [PWRAP_MAN_EN] = 0x60,
+ [PWRAP_MAN_CMD] = 0x64,
+ [PWRAP_MAN_RDATA] = 0x68,
+ [PWRAP_MAN_VLDCLR] = 0x6C,
+ [PWRAP_WACS0_EN] = 0x70,
+ [PWRAP_INIT_DONE0] = 0x74,
+ [PWRAP_WACS0_CMD] = 0x78,
+ [PWRAP_WACS0_RDATA] = 0x7C,
+ [PWRAP_WACS0_VLDCLR] = 0x80,
+ [PWRAP_WACS1_EN] = 0x84,
+ [PWRAP_INIT_DONE1] = 0x88,
+ [PWRAP_WACS1_CMD] = 0x8C,
+ [PWRAP_WACS1_RDATA] = 0x90,
+ [PWRAP_WACS1_VLDCLR] = 0x94,
+ [PWRAP_WACS2_EN] = 0x98,
+ [PWRAP_INIT_DONE2] = 0x9C,
+ [PWRAP_WACS2_CMD] = 0xA0,
+ [PWRAP_WACS2_RDATA] = 0xA4,
+ [PWRAP_WACS2_VLDCLR] = 0xA8,
+ [PWRAP_INT_EN] = 0xAC,
+ [PWRAP_INT_FLG_RAW] = 0xB0,
+ [PWRAP_INT_FLG] = 0xB4,
+ [PWRAP_INT_CLR] = 0xB8,
+ [PWRAP_SIG_ADR] = 0xBC,
+ [PWRAP_SIG_MODE] = 0xC0,
+ [PWRAP_SIG_VALUE] = 0xC4,
+ [PWRAP_SIG_ERRVAL] = 0xC8,
+ [PWRAP_CRC_EN] = 0xCC,
+ [PWRAP_TIMER_EN] = 0xD0,
+ [PWRAP_TIMER_STA] = 0xD4,
+ [PWRAP_WDT_UNIT] = 0xD8,
+ [PWRAP_WDT_SRC_EN] = 0xDC,
+ [PWRAP_WDT_FLG] = 0xE0,
+ [PWRAP_DEBUG_INT_SEL] = 0xE4,
+ [PWRAP_DVFS_ADR0] = 0xE8,
+ [PWRAP_DVFS_WDATA0] = 0xEC,
+ [PWRAP_DVFS_ADR1] = 0xF0,
+ [PWRAP_DVFS_WDATA1] = 0xF4,
+ [PWRAP_DVFS_ADR2] = 0xF8,
+ [PWRAP_DVFS_WDATA2] = 0xFC,
+ [PWRAP_DVFS_ADR3] = 0x100,
+ [PWRAP_DVFS_WDATA3] = 0x104,
+ [PWRAP_DVFS_ADR4] = 0x108,
+ [PWRAP_DVFS_WDATA4] = 0x10C,
+ [PWRAP_DVFS_ADR5] = 0x110,
+ [PWRAP_DVFS_WDATA5] = 0x114,
+ [PWRAP_DVFS_ADR6] = 0x118,
+ [PWRAP_DVFS_WDATA6] = 0x11C,
+ [PWRAP_DVFS_ADR7] = 0x120,
+ [PWRAP_DVFS_WDATA7] = 0x124,
+ [PWRAP_DVFS_ADR8] = 0x128,
+ [PWRAP_DVFS_WDATA8] = 0x12C,
+ [PWRAP_DVFS_ADR9] = 0x130,
+ [PWRAP_DVFS_WDATA9] = 0x134,
+ [PWRAP_DVFS_ADR10] = 0x138,
+ [PWRAP_DVFS_WDATA10] = 0x13C,
+ [PWRAP_DVFS_ADR11] = 0x140,
+ [PWRAP_DVFS_WDATA11] = 0x144,
+ [PWRAP_DVFS_ADR12] = 0x148,
+ [PWRAP_DVFS_WDATA12] = 0x14C,
+ [PWRAP_DVFS_ADR13] = 0x150,
+ [PWRAP_DVFS_WDATA13] = 0x154,
+ [PWRAP_DVFS_ADR14] = 0x158,
+ [PWRAP_DVFS_WDATA14] = 0x15C,
+ [PWRAP_DVFS_ADR15] = 0x160,
+ [PWRAP_DVFS_WDATA15] = 0x164,
+ [PWRAP_SPMINF_STA] = 0x168,
+ [PWRAP_CIPHER_KEY_SEL] = 0x16C,
+ [PWRAP_CIPHER_IV_SEL] = 0x170,
+ [PWRAP_CIPHER_EN] = 0x174,
+ [PWRAP_CIPHER_RDY] = 0x178,
+ [PWRAP_CIPHER_MODE] = 0x17C,
+ [PWRAP_CIPHER_SWRST] = 0x180,
+ [PWRAP_DCM_EN] = 0x184,
+ [PWRAP_DCM_DBC_PRD] = 0x188,
+ [PWRAP_EXT_CK] = 0x18C,
+ [PWRAP_ADC_CMD_ADDR] = 0x190,
+ [PWRAP_PWRAP_ADC_CMD] = 0x194,
+ [PWRAP_ADC_RDATA_ADDR] = 0x198,
+ [PWRAP_GPS_STA] = 0x19C,
+ [PWRAP_SW_RST] = 0x1A0,
+ [PWRAP_DVFS_STEP_CTRL0] = 0x238,
+ [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
+ [PWRAP_DVFS_STEP_CTRL2] = 0x240,
+ [PWRAP_SPI2_CTRL] = 0x244,
+};
+
static int mt8173_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
@@ -487,18 +635,31 @@
enum pmic_type {
PMIC_MT6323,
+ PMIC_MT6380,
PMIC_MT6397,
};
enum pwrap_type {
PWRAP_MT2701,
+ PWRAP_MT7622,
PWRAP_MT8135,
PWRAP_MT8173,
};
+struct pmic_wrapper;
struct pwrap_slv_type {
const u32 *dew_regs;
enum pmic_type type;
+ const struct regmap_config *regmap;
+ /* Flags indicating the capability for the target slave */
+ u32 caps;
+ /*
+ * pwrap operations are highly associated with the PMIC types,
+ * so the pointers added increases flexibility allowing determination
+ * which type is used by the detection through device tree.
+ */
+ int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
+ int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
};
struct pmic_wrapper {
@@ -593,23 +754,7 @@
} while (1);
}
-static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
-{
- int ret;
-
- ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
- if (ret) {
- pwrap_leave_fsm_vldclr(wrp);
- return ret;
- }
-
- pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
- PWRAP_WACS2_CMD);
-
- return 0;
-}
-
-static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
{
int ret;
@@ -632,6 +777,89 @@
return 0;
}
+static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+{
+ int ret, msb;
+
+ *rdata = 0;
+ for (msb = 0; msb < 2; msb++) {
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
+ PWRAP_WACS2_CMD);
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
+ if (ret)
+ return ret;
+
+ *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
+ PWRAP_WACS2_RDATA)) << (16 * msb));
+
+ pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
+ }
+
+ return 0;
+}
+
+static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+{
+ return wrp->slave->pwrap_read(wrp, adr, rdata);
+}
+
+static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+{
+ int ret;
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
+ PWRAP_WACS2_CMD);
+
+ return 0;
+}
+
+static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+{
+ int ret, msb, rdata;
+
+ for (msb = 0; msb < 2; msb++) {
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
+ ((wdata >> (msb * 16)) & 0xffff),
+ PWRAP_WACS2_CMD);
+
+ /*
+ * The pwrap_read operation is the requirement of hardware used
+ * for the synchronization between two successive 16-bit
+ * pwrap_writel operations composing one 32-bit bus writing.
+ * Otherwise, we'll find the result fails on the lower 16-bit
+ * pwrap writing.
+ */
+ if (!msb)
+ pwrap_read(wrp, adr, &rdata);
+ }
+
+ return 0;
+}
+
+static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+{
+ return wrp->slave->pwrap_write(wrp, adr, wdata);
+}
+
static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
{
return pwrap_read(context, adr, rdata);
@@ -711,23 +939,75 @@
return 0;
}
-static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
+static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
{
- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
- pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
- pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
+ int ret;
+ u32 rdata;
+
+ /* Enable dual IO mode */
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
+
+ /* Check IDLE & INIT_DONE in advance */
+ ret = pwrap_wait_for_state(wrp,
+ pwrap_is_fsm_idle_and_sync_idle);
+ if (ret) {
+ dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ pwrap_writel(wrp, 1, PWRAP_DIO_EN);
+
+ /* Read Test */
+ pwrap_read(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
+ if (rdata != PWRAP_DEW_READ_TEST_VAL) {
+ dev_err(wrp->dev,
+ "Read failed on DIO mode: 0x%04x!=0x%04x\n",
+ PWRAP_DEW_READ_TEST_VAL, rdata);
+ return -EFAULT;
+ }
return 0;
}
-static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
+/*
+ * pwrap_init_chip_select_ext is used to configure CS extension time for each
+ * phase during data transactions on the pwrap bus.
+ */
+static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
+ u8 hext_read, u8 lext_start,
+ u8 lext_end)
{
- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
+ /*
+ * After finishing a write and read transaction, extends CS high time
+ * to be at least xT of BUS CLK as hext_write and hext_read specifies
+ * respectively.
+ */
+ pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
+ pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
+
+ /*
+ * Extends CS low time after CSL and before CSH command to be at
+ * least xT of BUS CLK as lext_start and lext_end specifies
+ * respectively.
+ */
+ pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
+ pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
+}
+
+static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
+{
+ switch (wrp->master->type) {
+ case PWRAP_MT8173:
+ pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
+ break;
+ case PWRAP_MT8135:
+ pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
+ pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
+ break;
+ default:
+ break;
+ }
return 0;
}
@@ -737,20 +1017,16 @@
switch (wrp->slave->type) {
case PMIC_MT6397:
pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
+ pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
break;
case PMIC_MT6323:
pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
0x8);
- pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
+ pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
+ break;
+ default:
break;
}
@@ -794,6 +1070,9 @@
case PWRAP_MT8173:
pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
break;
+ case PWRAP_MT7622:
+ pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
+ break;
}
/* Config cipher mode @PMIC */
@@ -815,6 +1094,8 @@
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
0x1);
break;
+ default:
+ break;
}
/* wait for cipher data ready@AP */
@@ -827,7 +1108,8 @@
/* wait for cipher data ready@PMIC */
ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
if (ret) {
- dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
+ dev_err(wrp->dev,
+ "timeout waiting for cipher data ready@PMIC\n");
return ret;
}
@@ -854,6 +1136,30 @@
return 0;
}
+static int pwrap_init_security(struct pmic_wrapper *wrp)
+{
+ int ret;
+
+ /* Enable encryption */
+ ret = pwrap_init_cipher(wrp);
+ if (ret)
+ return ret;
+
+ /* Signature checking - using CRC */
+ if (pwrap_write(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
+ return -EFAULT;
+
+ pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
+ pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
+ pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
+ PWRAP_SIG_ADR);
+ pwrap_writel(wrp,
+ wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
+
+ return 0;
+}
+
static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
{
/* enable pwrap events and pwrap bridge in AP side */
@@ -911,10 +1217,18 @@
return 0;
}
+static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
+{
+ pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
+ /* enable 2wire SPI master */
+ pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
+
+ return 0;
+}
+
static int pwrap_init(struct pmic_wrapper *wrp)
{
int ret;
- u32 rdata;
reset_control_reset(wrp->rstc);
if (wrp->rstc_bridge)
@@ -926,10 +1240,12 @@
pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
}
- /* Reset SPI slave */
- ret = pwrap_reset_spislave(wrp);
- if (ret)
- return ret;
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
+ /* Reset SPI slave */
+ ret = pwrap_reset_spislave(wrp);
+ if (ret)
+ return ret;
+ }
pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
@@ -941,45 +1257,26 @@
if (ret)
return ret;
- /* Setup serial input delay */
- ret = pwrap_init_sidly(wrp);
- if (ret)
- return ret;
-
- /* Enable dual IO mode */
- pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
-
- /* Check IDLE & INIT_DONE in advance */
- ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
- if (ret) {
- dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
- return ret;
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
+ /* Setup serial input delay */
+ ret = pwrap_init_sidly(wrp);
+ if (ret)
+ return ret;
}
- pwrap_writel(wrp, 1, PWRAP_DIO_EN);
-
- /* Read Test */
- pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
- if (rdata != PWRAP_DEW_READ_TEST_VAL) {
- dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
- PWRAP_DEW_READ_TEST_VAL, rdata);
- return -EFAULT;
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
+ /* Enable dual I/O mode */
+ ret = pwrap_init_dual_io(wrp);
+ if (ret)
+ return ret;
}
- /* Enable encryption */
- ret = pwrap_init_cipher(wrp);
- if (ret)
- return ret;
-
- /* Signature checking - using CRC */
- if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
- return -EFAULT;
-
- pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
- pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
- pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
- PWRAP_SIG_ADR);
- pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
+ /* Enable security on bus */
+ ret = pwrap_init_security(wrp);
+ if (ret)
+ return ret;
+ }
if (wrp->master->type == PWRAP_MT8135)
pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
@@ -1023,7 +1320,7 @@
return IRQ_HANDLED;
}
-static const struct regmap_config pwrap_regmap_config = {
+static const struct regmap_config pwrap_regmap_config16 = {
.reg_bits = 16,
.val_bits = 16,
.reg_stride = 2,
@@ -1032,14 +1329,42 @@
.max_register = 0xffff,
};
+static const struct regmap_config pwrap_regmap_config32 = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .reg_read = pwrap_regmap_read,
+ .reg_write = pwrap_regmap_write,
+ .max_register = 0xffff,
+};
+
static const struct pwrap_slv_type pmic_mt6323 = {
.dew_regs = mt6323_regs,
.type = PMIC_MT6323,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+ PWRAP_SLV_CAP_SECURITY,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
+};
+
+static const struct pwrap_slv_type pmic_mt6380 = {
+ .dew_regs = NULL,
+ .type = PMIC_MT6380,
+ .regmap = &pwrap_regmap_config32,
+ .caps = 0,
+ .pwrap_read = pwrap_read32,
+ .pwrap_write = pwrap_write32,
};
static const struct pwrap_slv_type pmic_mt6397 = {
.dew_regs = mt6397_regs,
.type = PMIC_MT6397,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+ PWRAP_SLV_CAP_SECURITY,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
};
static const struct of_device_id of_slave_match_tbl[] = {
@@ -1047,6 +1372,12 @@
.compatible = "mediatek,mt6323",
.data = &pmic_mt6323,
}, {
+ /* The MT6380 PMIC only implements a regulator, so we bind it
+ * directly instead of using a MFD.
+ */
+ .compatible = "mediatek,mt6380-regulator",
+ .data = &pmic_mt6380,
+ }, {
.compatible = "mediatek,mt6397",
.data = &pmic_mt6397,
}, {
@@ -1067,6 +1398,18 @@
.init_soc_specific = pwrap_mt2701_init_soc_specific,
};
+static const struct pmic_wrapper_type pwrap_mt7622 = {
+ .regs = mt7622_regs,
+ .type = PWRAP_MT7622,
+ .arb_en_all = 0xff,
+ .int_en_all = ~(u32)BIT(31),
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .has_bridge = 0,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = pwrap_mt7622_init_soc_specific,
+};
+
static const struct pmic_wrapper_type pwrap_mt8135 = {
.regs = mt8135_regs,
.type = PWRAP_MT8135,
@@ -1075,7 +1418,7 @@
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.has_bridge = 1,
- .init_reg_clock = pwrap_mt8135_init_reg_clock,
+ .init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = pwrap_mt8135_init_soc_specific,
};
@@ -1087,7 +1430,7 @@
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
.has_bridge = 0,
- .init_reg_clock = pwrap_mt8173_init_reg_clock,
+ .init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = pwrap_mt8173_init_soc_specific,
};
@@ -1096,6 +1439,9 @@
.compatible = "mediatek,mt2701-pwrap",
.data = &pwrap_mt2701,
}, {
+ .compatible = "mediatek,mt7622-pwrap",
+ .data = &pwrap_mt7622,
+ }, {
.compatible = "mediatek,mt8135-pwrap",
.data = &pwrap_mt8135,
}, {
@@ -1112,19 +1458,12 @@
int ret, irq;
struct pmic_wrapper *wrp;
struct device_node *np = pdev->dev.of_node;
- const struct of_device_id *of_id =
- of_match_device(of_pwrap_match_tbl, &pdev->dev);
const struct of_device_id *of_slave_id = NULL;
struct resource *res;
- if (!of_id) {
- dev_err(&pdev->dev, "Error: No device match found\n");
- return -ENODEV;
- }
+ if (np->child)
+ of_slave_id = of_match_node(of_slave_match_tbl, np->child);
- if (pdev->dev.of_node->child)
- of_slave_id = of_match_node(of_slave_match_tbl,
- pdev->dev.of_node->child);
if (!of_slave_id) {
dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
return -EINVAL;
@@ -1136,7 +1475,7 @@
platform_set_drvdata(pdev, wrp);
- wrp->master = of_id->data;
+ wrp->master = of_device_get_match_data(&pdev->dev);
wrp->slave = of_slave_id->data;
wrp->dev = &pdev->dev;
@@ -1159,23 +1498,27 @@
if (IS_ERR(wrp->bridge_base))
return PTR_ERR(wrp->bridge_base);
- wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
+ wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
+ "pwrap-bridge");
if (IS_ERR(wrp->rstc_bridge)) {
ret = PTR_ERR(wrp->rstc_bridge);
- dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
+ dev_dbg(wrp->dev,
+ "cannot get pwrap-bridge reset: %d\n", ret);
return ret;
}
}
wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
if (IS_ERR(wrp->clk_spi)) {
- dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
+ dev_dbg(wrp->dev, "failed to get clock: %ld\n",
+ PTR_ERR(wrp->clk_spi));
return PTR_ERR(wrp->clk_spi);
}
wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
if (IS_ERR(wrp->clk_wrap)) {
- dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
+ dev_dbg(wrp->dev, "failed to get clock: %ld\n",
+ PTR_ERR(wrp->clk_wrap));
return PTR_ERR(wrp->clk_wrap);
}
@@ -1220,12 +1563,13 @@
pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
irq = platform_get_irq(pdev, 0);
- ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
- "mt-pmic-pwrap", wrp);
+ ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
+ IRQF_TRIGGER_HIGH,
+ "mt-pmic-pwrap", wrp);
if (ret)
goto err_out2;
- wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
+ wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
if (IS_ERR(wrp->regmap)) {
ret = PTR_ERR(wrp->regmap);
goto err_out2;
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index fb2a8b1..15bc6b3 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -874,15 +874,13 @@
static int scpsys_probe(struct platform_device *pdev)
{
- const struct of_device_id *match;
const struct scp_subdomain *sd;
const struct scp_soc_data *soc;
struct scp *scp;
struct genpd_onecell_data *pd_data;
int i, ret;
- match = of_match_device(of_scpsys_match_tbl, &pdev->dev);
- soc = (const struct scp_soc_data *)match->data;
+ soc = of_device_get_match_data(&pdev->dev);
scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
if (IS_ERR(scp))
diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index fcaad1a..54063a3 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -9,6 +9,7 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
@@ -333,3 +334,5 @@
return qcom_llcc_cfg_program(pdev);
}
EXPORT_SYMBOL_GPL(qcom_llcc_probe);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c
index c8999e38..8a3678c 100644
--- a/drivers/soc/qcom/rmtfs_mem.c
+++ b/drivers/soc/qcom/rmtfs_mem.c
@@ -184,6 +184,7 @@
device_initialize(&rmtfs_mem->dev);
rmtfs_mem->dev.parent = &pdev->dev;
rmtfs_mem->dev.groups = qcom_rmtfs_mem_groups;
+ rmtfs_mem->dev.release = qcom_rmtfs_mem_release_device;
rmtfs_mem->base = devm_memremap(&rmtfs_mem->dev, rmtfs_mem->addr,
rmtfs_mem->size, MEMREMAP_WC);
@@ -206,8 +207,6 @@
goto put_device;
}
- rmtfs_mem->dev.release = qcom_rmtfs_mem_release_device;
-
ret = of_property_read_u32(node, "qcom,vmid", &vmid);
if (ret < 0 && ret != -EINVAL) {
dev_err(&pdev->dev, "failed to parse qcom,vmid\n");
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 8e29775..ee75da66 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
@@ -108,8 +108,6 @@
struct tcs_group *tcs;
tcs = get_tcs_of_type(drv, type);
- if (IS_ERR(tcs))
- return PTR_ERR(tcs);
spin_lock(&tcs->lock);
if (bitmap_empty(tcs->slots, MAX_TCS_SLOTS)) {
@@ -175,9 +173,9 @@
* TCSes before making an active state request.
*/
tcs = get_tcs_of_type(drv, type);
- if (msg->state == RPMH_ACTIVE_ONLY_STATE && IS_ERR(tcs)) {
+ if (msg->state == RPMH_ACTIVE_ONLY_STATE && !tcs->num_tcs) {
tcs = get_tcs_of_type(drv, WAKE_TCS);
- if (!IS_ERR(tcs)) {
+ if (tcs->num_tcs) {
ret = rpmh_rsc_invalidate(drv);
if (ret)
return ERR_PTR(ret);
@@ -193,7 +191,7 @@
struct tcs_group *tcs;
int i;
- for (i = 0; i < drv->num_tcs; i++) {
+ for (i = 0; i < TCS_TYPE_NR; i++) {
tcs = &drv->tcs[i];
if (tcs->mask & BIT(tcs_id))
return tcs->req[tcs_id - tcs->offset];
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 40b7574..ba009bb 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -255,7 +255,7 @@
return;
else if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset,
- on ? pd->info->pwr_mask :
+ on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask));
else
regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a75f2a2..de03d67 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -51,6 +51,13 @@
if SPI_MASTER
+config SPI_MEM
+ bool "SPI memory extension"
+ help
+ Enable this option if you want to enable the SPI memory extension.
+ This extension is meant to simplify interaction with SPI memories
+ by providing an high-level interface to send memory-like commands.
+
comment "SPI Master Controller Drivers"
config SPI_ALTERA
@@ -138,14 +145,6 @@
help
Enable support for a SPI bus via the Blackfin SPORT peripheral.
-config SPI_BCM53XX
- tristate "Broadcom BCM53xx SPI controller"
- depends on ARCH_BCM_5301X
- depends on BCMA_POSSIBLE
- select BCMA
- help
- Enable support for the SPI controller on Broadcom BCM53xx ARM SoCs.
-
config SPI_BCM63XX
tristate "Broadcom BCM63xx SPI controller"
depends on BCM63XX || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8e0cda7..876f869 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -8,6 +8,7 @@
# small core, mostly translating board-specific
# config declarations into driver model code
obj-$(CONFIG_SPI_MASTER) += spi.o
+obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_SPI_SPIDEV) += spidev.o
obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
@@ -20,7 +21,6 @@
obj-$(CONFIG_SPI_AXI_SPI_ENGINE) += spi-axi-spi-engine.o
obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm2835aux.o
-obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
obj-$(CONFIG_SPI_BCM_QSPI) += spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi.o
diff --git a/drivers/spi/internals.h b/drivers/spi/internals.h
new file mode 100644
index 0000000..4a28a83
--- /dev/null
+++ b/drivers/spi/internals.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ * Copyright (C) 2018 Bootlin
+ *
+ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
+ *
+ * Helpers needed by the spi or spi-mem logic. Should not be used outside of
+ * spi-mem.c and spi.c.
+ */
+
+#ifndef __LINUX_SPI_INTERNALS_H
+#define __LINUX_SPI_INTERNALS_H
+
+#include <linux/device.h>
+#include <linux/dma-direction.h>
+#include <linux/scatterlist.h>
+#include <linux/spi/spi.h>
+
+void spi_flush_queue(struct spi_controller *ctrl);
+
+#ifdef CONFIG_HAS_DMA
+int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+ struct sg_table *sgt, void *buf, size_t len,
+ enum dma_data_direction dir);
+void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
+ struct sg_table *sgt, enum dma_data_direction dir);
+#else /* !CONFIG_HAS_DMA */
+static inline int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+ struct sg_table *sgt, void *buf, size_t len,
+ enum dma_data_direction dir)
+{
+ return -EINVAL;
+}
+
+static inline void spi_unmap_buf(struct spi_controller *ctlr,
+ struct device *dev, struct sg_table *sgt,
+ enum dma_data_direction dir)
+{
+}
+#endif /* CONFIG_HAS_DMA */
+
+#endif /* __LINUX_SPI_INTERNALS_H */
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 6573152..8612525 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -30,6 +30,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include "spi-bcm-qspi.h"
@@ -215,10 +216,10 @@
int bspi_maj_rev;
int bspi_min_rev;
int bspi_enabled;
- struct spi_flash_read_message *bspi_rf_msg;
- u32 bspi_rf_msg_idx;
- u32 bspi_rf_msg_len;
- u32 bspi_rf_msg_status;
+ const struct spi_mem_op *bspi_rf_op;
+ u32 bspi_rf_op_idx;
+ u32 bspi_rf_op_len;
+ u32 bspi_rf_op_status;
struct bcm_xfer_mode xfer_mode;
u32 s3_strap_override_ctrl;
bool bspi_mode;
@@ -313,26 +314,26 @@
static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
{
- u32 *buf = (u32 *)qspi->bspi_rf_msg->buf;
+ u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
u32 data = 0;
- dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg,
- qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len);
+ dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
+ qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
data = bcm_qspi_bspi_lr_read_fifo(qspi);
- if (likely(qspi->bspi_rf_msg_len >= 4) &&
+ if (likely(qspi->bspi_rf_op_len >= 4) &&
IS_ALIGNED((uintptr_t)buf, 4)) {
- buf[qspi->bspi_rf_msg_idx++] = data;
- qspi->bspi_rf_msg_len -= 4;
+ buf[qspi->bspi_rf_op_idx++] = data;
+ qspi->bspi_rf_op_len -= 4;
} else {
/* Read out remaining bytes, make sure*/
- u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx];
+ u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
data = cpu_to_le32(data);
- while (qspi->bspi_rf_msg_len) {
+ while (qspi->bspi_rf_op_len) {
*cbuf++ = (u8)data;
data >>= 8;
- qspi->bspi_rf_msg_len--;
+ qspi->bspi_rf_op_len--;
}
}
}
@@ -349,14 +350,12 @@
}
static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
- struct spi_flash_read_message *msg,
- int hp)
+ const struct spi_mem_op *op, int hp)
{
int bpc = 0, bpp = 0;
- u8 command = msg->read_opcode;
- int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
- int addrlen = msg->addr_width;
- int addr_nbits = msg->addr_nbits ? msg->addr_nbits : SPI_NBITS_SINGLE;
+ u8 command = op->cmd.opcode;
+ int width = op->cmd.buswidth ? op->cmd.buswidth : SPI_NBITS_SINGLE;
+ int addrlen = op->addr.nbytes * 8;
int flex_mode = 1;
dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
@@ -365,7 +364,7 @@
if (addrlen == BSPI_ADDRLEN_4BYTES)
bpp = BSPI_BPP_ADDR_SELECT_MASK;
- bpp |= msg->dummy_bytes * (8/addr_nbits);
+ bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth;
switch (width) {
case SPI_NBITS_SINGLE:
@@ -397,11 +396,10 @@
}
static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
- struct spi_flash_read_message *msg,
- int hp)
+ const struct spi_mem_op *op, int hp)
{
- int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
- int addrlen = msg->addr_width;
+ int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
+ int addrlen = op->addr.nbytes;
u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
@@ -437,17 +435,17 @@
/* set the override mode */
data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
- bcm_qspi_bspi_set_xfer_params(qspi, msg->read_opcode, 0, 0, 0);
+ bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
return 0;
}
static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
- struct spi_flash_read_message *msg, int hp)
+ const struct spi_mem_op *op, int hp)
{
int error = 0;
- int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
- int addrlen = msg->addr_width;
+ int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
+ int addrlen = op->addr.nbytes;
/* default mode */
qspi->xfer_mode.flex_mode = true;
@@ -460,12 +458,12 @@
if (val & mask || qspi->s3_strap_override_ctrl & mask) {
qspi->xfer_mode.flex_mode = false;
bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
- error = bcm_qspi_bspi_set_override(qspi, msg, hp);
+ error = bcm_qspi_bspi_set_override(qspi, op, hp);
}
}
if (qspi->xfer_mode.flex_mode)
- error = bcm_qspi_bspi_set_flex_mode(qspi, msg, hp);
+ error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
if (error) {
dev_warn(&qspi->pdev->dev,
@@ -802,19 +800,20 @@
return slot;
}
-static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
+static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
+ const struct spi_mem_op *op)
{
struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
- u32 addr = 0, len, rdlen, len_words;
+ u32 addr = 0, len, rdlen, len_words, from = 0;
int ret = 0;
unsigned long timeo = msecs_to_jiffies(100);
struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
if (bcm_qspi_bspi_ver_three(qspi))
- if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
+ if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES)
return -EIO;
+ from = op->addr.val;
bcm_qspi_chip_select(qspi, spi->chip_select);
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
@@ -823,15 +822,15 @@
* the upper address byte to bspi
*/
if (bcm_qspi_bspi_ver_three(qspi) == false) {
- addr = msg->from & 0xff000000;
+ addr = from & 0xff000000;
bcm_qspi_write(qspi, BSPI,
BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
}
if (!qspi->xfer_mode.flex_mode)
- addr = msg->from;
+ addr = from;
else
- addr = msg->from & 0x00ffffff;
+ addr = from & 0x00ffffff;
if (bcm_qspi_bspi_ver_three(qspi) == true)
addr = (addr + 0xc00000) & 0xffffff;
@@ -840,8 +839,8 @@
* read into the entire buffer by breaking the reads
* into RAF buffer read lengths
*/
- len = msg->len;
- qspi->bspi_rf_msg_idx = 0;
+ len = op->data.nbytes;
+ qspi->bspi_rf_op_idx = 0;
do {
if (len > BSPI_READ_LENGTH)
@@ -852,9 +851,9 @@
reinit_completion(&qspi->bspi_done);
bcm_qspi_enable_bspi(qspi);
len_words = (rdlen + 3) >> 2;
- qspi->bspi_rf_msg = msg;
- qspi->bspi_rf_msg_status = 0;
- qspi->bspi_rf_msg_len = rdlen;
+ qspi->bspi_rf_op = op;
+ qspi->bspi_rf_op_status = 0;
+ qspi->bspi_rf_op_len = rdlen;
dev_dbg(&qspi->pdev->dev,
"bspi xfr addr 0x%x len 0x%x", addr, rdlen);
bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
@@ -879,7 +878,6 @@
}
/* set msg return length */
- msg->retlen += rdlen;
addr += rdlen;
len -= rdlen;
} while (len);
@@ -914,61 +912,63 @@
return 0;
}
-static int bcm_qspi_mspi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
+static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
+ const struct spi_mem_op *op)
{
- struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
+ struct spi_master *master = spi->master;
+ struct bcm_qspi *qspi = spi_master_get_devdata(master);
struct spi_transfer t[2];
- u8 cmd[6];
- int ret;
+ u8 cmd[6] = { };
+ int ret, i;
memset(cmd, 0, sizeof(cmd));
memset(t, 0, sizeof(t));
/* tx */
/* opcode is in cmd[0] */
- cmd[0] = msg->read_opcode;
- cmd[1] = msg->from >> (msg->addr_width * 8 - 8);
- cmd[2] = msg->from >> (msg->addr_width * 8 - 16);
- cmd[3] = msg->from >> (msg->addr_width * 8 - 24);
- cmd[4] = msg->from >> (msg->addr_width * 8 - 32);
+ cmd[0] = op->cmd.opcode;
+ for (i = 0; i < op->addr.nbytes; i++)
+ cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
t[0].tx_buf = cmd;
- t[0].len = msg->addr_width + msg->dummy_bytes + 1;
+ t[0].len = op->addr.nbytes + op->dummy.nbytes + 1;
t[0].bits_per_word = spi->bits_per_word;
- t[0].tx_nbits = msg->opcode_nbits;
+ t[0].tx_nbits = op->cmd.buswidth;
/* lets mspi know that this is not last transfer */
qspi->trans_pos.mspi_last_trans = false;
- ret = bcm_qspi_transfer_one(spi->master, spi, &t[0]);
+ ret = bcm_qspi_transfer_one(master, spi, &t[0]);
/* rx */
qspi->trans_pos.mspi_last_trans = true;
if (!ret) {
/* rx */
- t[1].rx_buf = msg->buf;
- t[1].len = msg->len;
- t[1].rx_nbits = msg->data_nbits;
+ t[1].rx_buf = op->data.buf.in;
+ t[1].len = op->data.nbytes;
+ t[1].rx_nbits = op->data.buswidth;
t[1].bits_per_word = spi->bits_per_word;
- ret = bcm_qspi_transfer_one(spi->master, spi, &t[1]);
+ ret = bcm_qspi_transfer_one(master, spi, &t[1]);
}
- if (!ret)
- msg->retlen = msg->len;
-
return ret;
}
-static int bcm_qspi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
+static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
{
+ struct spi_device *spi = mem->spi;
struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
int ret = 0;
bool mspi_read = false;
- u32 addr, len;
+ u32 addr = 0, len;
u_char *buf;
- buf = msg->buf;
- addr = msg->from;
- len = msg->len;
+ if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 ||
+ op->data.dir != SPI_MEM_DATA_IN)
+ return -ENOTSUPP;
+
+ buf = op->data.buf.in;
+ addr = op->addr.val;
+ len = op->data.nbytes;
if (bcm_qspi_bspi_ver_three(qspi) == true) {
/*
@@ -990,12 +990,12 @@
mspi_read = true;
if (mspi_read)
- return bcm_qspi_mspi_flash_read(spi, msg);
+ return bcm_qspi_mspi_exec_mem_op(spi, op);
- ret = bcm_qspi_bspi_set_mode(qspi, msg, -1);
+ ret = bcm_qspi_bspi_set_mode(qspi, op, -1);
if (!ret)
- ret = bcm_qspi_bspi_flash_read(spi, msg);
+ ret = bcm_qspi_bspi_exec_mem_op(spi, op);
return ret;
}
@@ -1034,10 +1034,10 @@
struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
u32 status = qspi_dev_id->irqp->mask;
- if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
+ if (qspi->bspi_enabled && qspi->bspi_rf_op) {
bcm_qspi_bspi_lr_data_read(qspi);
- if (qspi->bspi_rf_msg_len == 0) {
- qspi->bspi_rf_msg = NULL;
+ if (qspi->bspi_rf_op_len == 0) {
+ qspi->bspi_rf_op = NULL;
if (qspi->soc_intc) {
/* disable soc BSPI interrupt */
soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
@@ -1046,7 +1046,7 @@
status = INTR_BSPI_LR_SESSION_DONE_MASK;
}
- if (qspi->bspi_rf_msg_status)
+ if (qspi->bspi_rf_op_status)
bcm_qspi_bspi_lr_clear(qspi);
else
bcm_qspi_bspi_flush_prefetch_buffers(qspi);
@@ -1058,7 +1058,7 @@
}
status &= INTR_BSPI_LR_SESSION_DONE_MASK;
- if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
+ if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
complete(&qspi->bspi_done);
return IRQ_HANDLED;
@@ -1071,7 +1071,7 @@
struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
dev_err(&qspi->pdev->dev, "BSPI INT error\n");
- qspi->bspi_rf_msg_status = -EIO;
+ qspi->bspi_rf_op_status = -EIO;
if (qspi->soc_intc)
/* clear soc interrupt */
soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
@@ -1194,6 +1194,10 @@
}
+static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
+ .exec_op = bcm_qspi_exec_mem_op,
+};
+
static const struct of_device_id bcm_qspi_of_match[] = {
{ .compatible = "brcm,spi-bcm-qspi" },
{},
@@ -1236,7 +1240,7 @@
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
master->setup = bcm_qspi_setup;
master->transfer_one = bcm_qspi_transfer_one;
- master->spi_flash_read = bcm_qspi_flash_read;
+ master->mem_ops = &bcm_qspi_mem_ops;
master->cleanup = bcm_qspi_cleanup;
master->dev.of_node = dev->of_node;
master->num_chipselect = NUM_CHIPSELECT;
diff --git a/drivers/spi/spi-bcm53xx.c b/drivers/spi/spi-bcm53xx.c
deleted file mode 100644
index 6e409ea..0000000
--- a/drivers/spi/spi-bcm53xx.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright (C) 2014-2016 Rafał Miłecki <rafal@milecki.pl>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/bcma/bcma.h>
-#include <linux/spi/spi.h>
-
-#include "spi-bcm53xx.h"
-
-#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */
-#define BCM53XXSPI_FLASH_WINDOW SZ_32M
-
-/* The longest observed required wait was 19 ms */
-#define BCM53XXSPI_SPE_TIMEOUT_MS 80
-
-struct bcm53xxspi {
- struct bcma_device *core;
- struct spi_master *master;
- void __iomem *mmio_base;
-
- size_t read_offset;
- bool bspi; /* Boot SPI mode with memory mapping */
-};
-
-static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
-{
- return bcma_read32(b53spi->core, offset);
-}
-
-static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
- u32 value)
-{
- bcma_write32(b53spi->core, offset, value);
-}
-
-static void bcm53xxspi_disable_bspi(struct bcm53xxspi *b53spi)
-{
- struct device *dev = &b53spi->core->dev;
- unsigned long deadline;
- u32 tmp;
-
- if (!b53spi->bspi)
- return;
-
- tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
- if (tmp & 0x1)
- return;
-
- deadline = jiffies + usecs_to_jiffies(200);
- do {
- tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_BUSY_STATUS);
- if (!(tmp & 0x1)) {
- bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL,
- 0x1);
- ndelay(200);
- b53spi->bspi = false;
- return;
- }
- udelay(1);
- } while (!time_after_eq(jiffies, deadline));
-
- dev_warn(dev, "Timeout disabling BSPI\n");
-}
-
-static void bcm53xxspi_enable_bspi(struct bcm53xxspi *b53spi)
-{
- u32 tmp;
-
- if (b53spi->bspi)
- return;
-
- tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
- if (!(tmp & 0x1))
- return;
-
- bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL, 0x0);
- b53spi->bspi = true;
-}
-
-static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
-{
- /* Do some magic calculation based on length and buad. Add 10% and 1. */
- return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
-}
-
-static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
-{
- unsigned long deadline;
- u32 tmp;
-
- /* SPE bit has to be 0 before we read MSPI STATUS */
- deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS);
- do {
- tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
- if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
- break;
- udelay(5);
- } while (!time_after_eq(jiffies, deadline));
-
- if (tmp & B53SPI_MSPI_SPCR2_SPE)
- goto spi_timeout;
-
- /* Check status */
- deadline = jiffies + msecs_to_jiffies(timeout_ms);
- do {
- tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
- if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
- bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
- return 0;
- }
-
- cpu_relax();
- udelay(100);
- } while (!time_after_eq(jiffies, deadline));
-
-spi_timeout:
- bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
-
- pr_err("Timeout waiting for SPI to be ready!\n");
-
- return -EBUSY;
-}
-
-static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
- size_t len, bool cont)
-{
- u32 tmp;
- int i;
-
- for (i = 0; i < len; i++) {
- /* Transmit Register File MSB */
- bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
- (unsigned int)w_buf[i]);
- }
-
- for (i = 0; i < len; i++) {
- tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
- B53SPI_CDRAM_PCS_DSCK;
- if (!cont && i == len - 1)
- tmp &= ~B53SPI_CDRAM_CONT;
- tmp &= ~0x1;
- /* Command Register File */
- bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
- }
-
- /* Set queue pointers */
- bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
- bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
-
- if (cont)
- bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
-
- /* Start SPI transfer */
- tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
- tmp |= B53SPI_MSPI_SPCR2_SPE;
- if (cont)
- tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
- bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
-
- /* Wait for SPI to finish */
- bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
-
- if (!cont)
- bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
-
- b53spi->read_offset = len;
-}
-
-static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
- size_t len, bool cont)
-{
- u32 tmp;
- int i;
-
- for (i = 0; i < b53spi->read_offset + len; i++) {
- tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
- B53SPI_CDRAM_PCS_DSCK;
- if (!cont && i == b53spi->read_offset + len - 1)
- tmp &= ~B53SPI_CDRAM_CONT;
- tmp &= ~0x1;
- /* Command Register File */
- bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
- }
-
- /* Set queue pointers */
- bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
- bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
- b53spi->read_offset + len - 1);
-
- if (cont)
- bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
-
- /* Start SPI transfer */
- tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
- tmp |= B53SPI_MSPI_SPCR2_SPE;
- if (cont)
- tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
- bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
-
- /* Wait for SPI to finish */
- bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
-
- if (!cont)
- bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
-
- for (i = 0; i < len; ++i) {
- int offset = b53spi->read_offset + i;
-
- /* Data stored in the transmit register file LSB */
- r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
- }
-
- b53spi->read_offset = 0;
-}
-
-static int bcm53xxspi_transfer_one(struct spi_master *master,
- struct spi_device *spi,
- struct spi_transfer *t)
-{
- struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
- u8 *buf;
- size_t left;
-
- bcm53xxspi_disable_bspi(b53spi);
-
- if (t->tx_buf) {
- buf = (u8 *)t->tx_buf;
- left = t->len;
- while (left) {
- size_t to_write = min_t(size_t, 16, left);
- bool cont = left - to_write > 0;
-
- bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
- left -= to_write;
- buf += to_write;
- }
- }
-
- if (t->rx_buf) {
- buf = (u8 *)t->rx_buf;
- left = t->len;
- while (left) {
- size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
- left);
- bool cont = left - to_read > 0;
-
- bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
- left -= to_read;
- buf += to_read;
- }
- }
-
- return 0;
-}
-
-static int bcm53xxspi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
-{
- struct bcm53xxspi *b53spi = spi_master_get_devdata(spi->master);
- int ret = 0;
-
- if (msg->from + msg->len > BCM53XXSPI_FLASH_WINDOW)
- return -EINVAL;
-
- bcm53xxspi_enable_bspi(b53spi);
- memcpy_fromio(msg->buf, b53spi->mmio_base + msg->from, msg->len);
- msg->retlen = msg->len;
-
- return ret;
-}
-
-/**************************************************
- * BCMA
- **************************************************/
-
-static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
- BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
- {},
-};
-MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
-
-static int bcm53xxspi_bcma_probe(struct bcma_device *core)
-{
- struct device *dev = &core->dev;
- struct bcm53xxspi *b53spi;
- struct spi_master *master;
- int err;
-
- if (core->bus->drv_cc.core->id.rev != 42) {
- pr_err("SPI on SoC with unsupported ChipCommon rev\n");
- return -ENOTSUPP;
- }
-
- master = spi_alloc_master(dev, sizeof(*b53spi));
- if (!master)
- return -ENOMEM;
-
- b53spi = spi_master_get_devdata(master);
- b53spi->master = master;
- b53spi->core = core;
-
- if (core->addr_s[0])
- b53spi->mmio_base = devm_ioremap(dev, core->addr_s[0],
- BCM53XXSPI_FLASH_WINDOW);
- b53spi->bspi = true;
- bcm53xxspi_disable_bspi(b53spi);
-
- master->dev.of_node = dev->of_node;
- master->transfer_one = bcm53xxspi_transfer_one;
- if (b53spi->mmio_base)
- master->spi_flash_read = bcm53xxspi_flash_read;
-
- bcma_set_drvdata(core, b53spi);
-
- err = devm_spi_register_master(dev, master);
- if (err) {
- spi_master_put(master);
- bcma_set_drvdata(core, NULL);
- return err;
- }
-
- return 0;
-}
-
-static struct bcma_driver bcm53xxspi_bcma_driver = {
- .name = KBUILD_MODNAME,
- .id_table = bcm53xxspi_bcma_tbl,
- .probe = bcm53xxspi_bcma_probe,
-};
-
-/**************************************************
- * Init & exit
- **************************************************/
-
-static int __init bcm53xxspi_module_init(void)
-{
- int err = 0;
-
- err = bcma_driver_register(&bcm53xxspi_bcma_driver);
- if (err)
- pr_err("Failed to register bcma driver: %d\n", err);
-
- return err;
-}
-
-static void __exit bcm53xxspi_module_exit(void)
-{
- bcma_driver_unregister(&bcm53xxspi_bcma_driver);
-}
-
-module_init(bcm53xxspi_module_init);
-module_exit(bcm53xxspi_module_exit);
-
-MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
-MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-bcm53xx.h b/drivers/spi/spi-bcm53xx.h
deleted file mode 100644
index 03e3442..0000000
--- a/drivers/spi/spi-bcm53xx.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef SPI_BCM53XX_H
-#define SPI_BCM53XX_H
-
-#define B53SPI_BSPI_REVISION_ID 0x000
-#define B53SPI_BSPI_SCRATCH 0x004
-#define B53SPI_BSPI_MAST_N_BOOT_CTRL 0x008
-#define B53SPI_BSPI_BUSY_STATUS 0x00c
-#define B53SPI_BSPI_INTR_STATUS 0x010
-#define B53SPI_BSPI_B0_STATUS 0x014
-#define B53SPI_BSPI_B0_CTRL 0x018
-#define B53SPI_BSPI_B1_STATUS 0x01c
-#define B53SPI_BSPI_B1_CTRL 0x020
-#define B53SPI_BSPI_STRAP_OVERRIDE_CTRL 0x024
-#define B53SPI_BSPI_FLEX_MODE_ENABLE 0x028
-#define B53SPI_BSPI_BITS_PER_CYCLE 0x02c
-#define B53SPI_BSPI_BITS_PER_PHASE 0x030
-#define B53SPI_BSPI_CMD_AND_MODE_BYTE 0x034
-#define B53SPI_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
-#define B53SPI_BSPI_BSPI_XOR_VALUE 0x03c
-#define B53SPI_BSPI_BSPI_XOR_ENABLE 0x040
-#define B53SPI_BSPI_BSPI_PIO_MODE_ENABLE 0x044
-#define B53SPI_BSPI_BSPI_PIO_IODIR 0x048
-#define B53SPI_BSPI_BSPI_PIO_DATA 0x04c
-
-/* RAF */
-#define B53SPI_RAF_START_ADDR 0x100
-#define B53SPI_RAF_NUM_WORDS 0x104
-#define B53SPI_RAF_CTRL 0x108
-#define B53SPI_RAF_FULLNESS 0x10c
-#define B53SPI_RAF_WATERMARK 0x110
-#define B53SPI_RAF_STATUS 0x114
-#define B53SPI_RAF_READ_DATA 0x118
-#define B53SPI_RAF_WORD_CNT 0x11c
-#define B53SPI_RAF_CURR_ADDR 0x120
-
-/* MSPI */
-#define B53SPI_MSPI_SPCR0_LSB 0x200
-#define B53SPI_MSPI_SPCR0_MSB 0x204
-#define B53SPI_MSPI_SPCR1_LSB 0x208
-#define B53SPI_MSPI_SPCR1_MSB 0x20c
-#define B53SPI_MSPI_NEWQP 0x210
-#define B53SPI_MSPI_ENDQP 0x214
-#define B53SPI_MSPI_SPCR2 0x218
-#define B53SPI_MSPI_SPCR2_SPE 0x00000040
-#define B53SPI_MSPI_SPCR2_CONT_AFTER_CMD 0x00000080
-#define B53SPI_MSPI_MSPI_STATUS 0x220
-#define B53SPI_MSPI_MSPI_STATUS_SPIF 0x00000001
-#define B53SPI_MSPI_CPTQP 0x224
-#define B53SPI_MSPI_TXRAM 0x240 /* 32 registers, up to 0x2b8 */
-#define B53SPI_MSPI_RXRAM 0x2c0 /* 32 registers, up to 0x33c */
-#define B53SPI_MSPI_CDRAM 0x340 /* 16 registers, up to 0x37c */
-#define B53SPI_CDRAM_PCS_PCS0 0x00000001
-#define B53SPI_CDRAM_PCS_PCS1 0x00000002
-#define B53SPI_CDRAM_PCS_PCS2 0x00000004
-#define B53SPI_CDRAM_PCS_PCS3 0x00000008
-#define B53SPI_CDRAM_PCS_DISABLE_ALL 0x0000000f
-#define B53SPI_CDRAM_PCS_DSCK 0x00000010
-#define B53SPI_CDRAM_BITSE 0x00000040
-#define B53SPI_CDRAM_CONT 0x00000080
-#define B53SPI_MSPI_WRITE_LOCK 0x380
-#define B53SPI_MSPI_DISABLE_FLUSH_GEN 0x384
-
-/* Interrupt */
-#define B53SPI_INTR_RAF_LR_FULLNESS_REACHED 0x3a0
-#define B53SPI_INTR_RAF_LR_TRUNCATED 0x3a4
-#define B53SPI_INTR_RAF_LR_IMPATIENT 0x3a8
-#define B53SPI_INTR_RAF_LR_SESSION_DONE 0x3ac
-#define B53SPI_INTR_RAF_LR_OVERREAD 0x3b0
-#define B53SPI_INTR_MSPI_DONE 0x3b4
-#define B53SPI_INTR_MSPI_HALT_SET_TRANSACTION_DONE 0x3b8
-
-#endif /* SPI_BCM53XX_H */
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
new file mode 100644
index 0000000..990770d
--- /dev/null
+++ b/drivers/spi/spi-mem.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ * Copyright (C) 2018 Bootlin
+ *
+ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+#include <linux/dmaengine.h>
+#include <linux/pm_runtime.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#include "internals.h"
+
+/**
+ * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
+ * memory operation
+ * @ctlr: the SPI controller requesting this dma_map()
+ * @op: the memory operation containing the buffer to map
+ * @sgt: a pointer to a non-initialized sg_table that will be filled by this
+ * function
+ *
+ * Some controllers might want to do DMA on the data buffer embedded in @op.
+ * This helper prepares everything for you and provides a ready-to-use
+ * sg_table. This function is not intended to be called from spi drivers.
+ * Only SPI controller drivers should use it.
+ * Note that the caller must ensure the memory region pointed by
+ * op->data.buf.{in,out} is DMA-able before calling this function.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
+ const struct spi_mem_op *op,
+ struct sg_table *sgt)
+{
+ struct device *dmadev;
+
+ if (!op->data.nbytes)
+ return -EINVAL;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
+ dmadev = ctlr->dma_tx->device->dev;
+ else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
+ dmadev = ctlr->dma_rx->device->dev;
+ else
+ dmadev = ctlr->dev.parent;
+
+ if (!dmadev)
+ return -EINVAL;
+
+ return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ DMA_FROM_DEVICE : DMA_TO_DEVICE);
+}
+EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data);
+
+/**
+ * spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a
+ * memory operation
+ * @ctlr: the SPI controller requesting this dma_unmap()
+ * @op: the memory operation containing the buffer to unmap
+ * @sgt: a pointer to an sg_table previously initialized by
+ * spi_controller_dma_map_mem_op_data()
+ *
+ * Some controllers might want to do DMA on the data buffer embedded in @op.
+ * This helper prepares things so that the CPU can access the
+ * op->data.buf.{in,out} buffer again.
+ *
+ * This function is not intended to be called from SPI drivers. Only SPI
+ * controller drivers should use it.
+ *
+ * This function should be called after the DMA operation has finished and is
+ * only valid if the previous spi_controller_dma_map_mem_op_data() call
+ * returned 0.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
+ const struct spi_mem_op *op,
+ struct sg_table *sgt)
+{
+ struct device *dmadev;
+
+ if (!op->data.nbytes)
+ return;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
+ dmadev = ctlr->dma_tx->device->dev;
+ else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
+ dmadev = ctlr->dma_rx->device->dev;
+ else
+ dmadev = ctlr->dev.parent;
+
+ spi_unmap_buf(ctlr, dmadev, sgt,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ DMA_FROM_DEVICE : DMA_TO_DEVICE);
+}
+EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data);
+
+static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)
+{
+ u32 mode = mem->spi->mode;
+
+ switch (buswidth) {
+ case 1:
+ return 0;
+
+ case 2:
+ if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) ||
+ (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD))))
+ return 0;
+
+ break;
+
+ case 4:
+ if ((tx && (mode & SPI_TX_QUAD)) ||
+ (!tx && (mode & SPI_RX_QUAD)))
+ return 0;
+
+ break;
+
+ default:
+ break;
+ }
+
+ return -ENOTSUPP;
+}
+
+static bool spi_mem_default_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (spi_check_buswidth_req(mem, op->cmd.buswidth, true))
+ return false;
+
+ if (op->addr.nbytes &&
+ spi_check_buswidth_req(mem, op->addr.buswidth, true))
+ return false;
+
+ if (op->dummy.nbytes &&
+ spi_check_buswidth_req(mem, op->dummy.buswidth, true))
+ return false;
+
+ if (op->data.nbytes &&
+ spi_check_buswidth_req(mem, op->data.buswidth,
+ op->data.dir == SPI_MEM_DATA_OUT))
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
+
+/**
+ * spi_mem_supports_op() - Check if a memory device and the controller it is
+ * connected to support a specific memory operation
+ * @mem: the SPI memory
+ * @op: the memory operation to check
+ *
+ * Some controllers are only supporting Single or Dual IOs, others might only
+ * support specific opcodes, or it can even be that the controller and device
+ * both support Quad IOs but the hardware prevents you from using it because
+ * only 2 IO lines are connected.
+ *
+ * This function checks whether a specific operation is supported.
+ *
+ * Return: true if @op is supported, false otherwise.
+ */
+bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct spi_controller *ctlr = mem->spi->controller;
+
+ if (ctlr->mem_ops && ctlr->mem_ops->supports_op)
+ return ctlr->mem_ops->supports_op(mem, op);
+
+ return spi_mem_default_supports_op(mem, op);
+}
+EXPORT_SYMBOL_GPL(spi_mem_supports_op);
+
+/**
+ * spi_mem_exec_op() - Execute a memory operation
+ * @mem: the SPI memory
+ * @op: the memory operation to execute
+ *
+ * Executes a memory operation.
+ *
+ * This function first checks that @op is supported and then tries to execute
+ * it.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ unsigned int tmpbufsize, xferpos = 0, totalxferlen = 0;
+ struct spi_controller *ctlr = mem->spi->controller;
+ struct spi_transfer xfers[4] = { };
+ struct spi_message msg;
+ u8 *tmpbuf;
+ int ret;
+
+ if (!spi_mem_supports_op(mem, op))
+ return -ENOTSUPP;
+
+ if (ctlr->mem_ops) {
+ /*
+ * Flush the message queue before executing our SPI memory
+ * operation to prevent preemption of regular SPI transfers.
+ */
+ spi_flush_queue(ctlr);
+
+ if (ctlr->auto_runtime_pm) {
+ ret = pm_runtime_get_sync(ctlr->dev.parent);
+ if (ret < 0) {
+ dev_err(&ctlr->dev,
+ "Failed to power device: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ mutex_lock(&ctlr->bus_lock_mutex);
+ mutex_lock(&ctlr->io_mutex);
+ ret = ctlr->mem_ops->exec_op(mem, op);
+ mutex_unlock(&ctlr->io_mutex);
+ mutex_unlock(&ctlr->bus_lock_mutex);
+
+ if (ctlr->auto_runtime_pm)
+ pm_runtime_put(ctlr->dev.parent);
+
+ /*
+ * Some controllers only optimize specific paths (typically the
+ * read path) and expect the core to use the regular SPI
+ * interface in other cases.
+ */
+ if (!ret || ret != -ENOTSUPP)
+ return ret;
+ }
+
+ tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes +
+ op->dummy.nbytes;
+
+ /*
+ * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
+ * we're guaranteed that this buffer is DMA-able, as required by the
+ * SPI layer.
+ */
+ tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA);
+ if (!tmpbuf)
+ return -ENOMEM;
+
+ spi_message_init(&msg);
+
+ tmpbuf[0] = op->cmd.opcode;
+ xfers[xferpos].tx_buf = tmpbuf;
+ xfers[xferpos].len = sizeof(op->cmd.opcode);
+ xfers[xferpos].tx_nbits = op->cmd.buswidth;
+ spi_message_add_tail(&xfers[xferpos], &msg);
+ xferpos++;
+ totalxferlen++;
+
+ if (op->addr.nbytes) {
+ int i;
+
+ for (i = 0; i < op->addr.nbytes; i++)
+ tmpbuf[i + 1] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ xfers[xferpos].tx_buf = tmpbuf + 1;
+ xfers[xferpos].len = op->addr.nbytes;
+ xfers[xferpos].tx_nbits = op->addr.buswidth;
+ spi_message_add_tail(&xfers[xferpos], &msg);
+ xferpos++;
+ totalxferlen += op->addr.nbytes;
+ }
+
+ if (op->dummy.nbytes) {
+ memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
+ xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
+ xfers[xferpos].len = op->dummy.nbytes;
+ xfers[xferpos].tx_nbits = op->dummy.buswidth;
+ spi_message_add_tail(&xfers[xferpos], &msg);
+ xferpos++;
+ totalxferlen += op->dummy.nbytes;
+ }
+
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ xfers[xferpos].rx_buf = op->data.buf.in;
+ xfers[xferpos].rx_nbits = op->data.buswidth;
+ } else {
+ xfers[xferpos].tx_buf = op->data.buf.out;
+ xfers[xferpos].tx_nbits = op->data.buswidth;
+ }
+
+ xfers[xferpos].len = op->data.nbytes;
+ spi_message_add_tail(&xfers[xferpos], &msg);
+ xferpos++;
+ totalxferlen += op->data.nbytes;
+ }
+
+ ret = spi_sync(mem->spi, &msg);
+
+ kfree(tmpbuf);
+
+ if (ret)
+ return ret;
+
+ if (msg.actual_length != totalxferlen)
+ return -EIO;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(spi_mem_exec_op);
+
+/**
+ * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
+ * match controller limitations
+ * @mem: the SPI memory
+ * @op: the operation to adjust
+ *
+ * Some controllers have FIFO limitations and must split a data transfer
+ * operation into multiple ones, others require a specific alignment for
+ * optimized accesses. This function allows SPI mem drivers to split a single
+ * operation into multiple sub-operations when required.
+ *
+ * Return: a negative error code if the controller can't properly adjust @op,
+ * 0 otherwise. Note that @op->data.nbytes will be updated if @op
+ * can't be handled in a single step.
+ */
+int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
+{
+ struct spi_controller *ctlr = mem->spi->controller;
+
+ if (ctlr->mem_ops && ctlr->mem_ops->adjust_op_size)
+ return ctlr->mem_ops->adjust_op_size(mem, op);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
+
+static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv)
+{
+ return container_of(drv, struct spi_mem_driver, spidrv.driver);
+}
+
+static int spi_mem_probe(struct spi_device *spi)
+{
+ struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
+ struct spi_mem *mem;
+
+ mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL);
+ if (!mem)
+ return -ENOMEM;
+
+ mem->spi = spi;
+ spi_set_drvdata(spi, mem);
+
+ return memdrv->probe(mem);
+}
+
+static int spi_mem_remove(struct spi_device *spi)
+{
+ struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
+ struct spi_mem *mem = spi_get_drvdata(spi);
+
+ if (memdrv->remove)
+ return memdrv->remove(mem);
+
+ return 0;
+}
+
+static void spi_mem_shutdown(struct spi_device *spi)
+{
+ struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
+ struct spi_mem *mem = spi_get_drvdata(spi);
+
+ if (memdrv->shutdown)
+ memdrv->shutdown(mem);
+}
+
+/**
+ * spi_mem_driver_register_with_owner() - Register a SPI memory driver
+ * @memdrv: the SPI memory driver to register
+ * @owner: the owner of this driver
+ *
+ * Registers a SPI memory driver.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+
+int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv,
+ struct module *owner)
+{
+ memdrv->spidrv.probe = spi_mem_probe;
+ memdrv->spidrv.remove = spi_mem_remove;
+ memdrv->spidrv.shutdown = spi_mem_shutdown;
+
+ return __spi_register_driver(owner, &memdrv->spidrv);
+}
+EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner);
+
+/**
+ * spi_mem_driver_unregister_with_owner() - Unregister a SPI memory driver
+ * @memdrv: the SPI memory driver to unregister
+ *
+ * Unregisters a SPI memory driver.
+ */
+void spi_mem_driver_unregister(struct spi_mem_driver *memdrv)
+{
+ spi_unregister_driver(&memdrv->spidrv);
+}
+EXPORT_SYMBOL_GPL(spi_mem_driver_unregister);
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index c24d9b4..5f19016 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -36,6 +36,7 @@
#include <linux/sizes.h>
#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
struct ti_qspi_regs {
u32 clkctrl;
@@ -50,6 +51,7 @@
struct spi_master *master;
void __iomem *base;
void __iomem *mmap_base;
+ size_t mmap_size;
struct regmap *ctrl_base;
unsigned int ctrl_reg;
struct clk *fclk;
@@ -434,12 +436,10 @@
return 0;
}
-static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi,
- struct spi_flash_read_message *msg)
+static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
+ void *to, size_t readsize)
{
- size_t readsize = msg->len;
- void *to = msg->buf;
- dma_addr_t dma_src = qspi->mmap_phys_base + msg->from;
+ dma_addr_t dma_src = qspi->mmap_phys_base + offs;
int ret = 0;
/*
@@ -507,13 +507,14 @@
qspi->mmap_enabled = false;
}
-static void ti_qspi_setup_mmap_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
+static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
+ u8 data_nbits, u8 addr_width,
+ u8 dummy_bytes)
{
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
- u32 memval = msg->read_opcode;
+ u32 memval = opcode;
- switch (msg->data_nbits) {
+ switch (data_nbits) {
case SPI_NBITS_QUAD:
memval |= QSPI_SETUP_RD_QUAD;
break;
@@ -524,48 +525,64 @@
memval |= QSPI_SETUP_RD_NORMAL;
break;
}
- memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
- msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
+ memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
+ dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
ti_qspi_write(qspi, memval,
QSPI_SPI_SETUP_REG(spi->chip_select));
}
-static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi,
- struct spi_flash_read_message *msg)
+static int ti_qspi_exec_mem_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
{
- return virt_addr_valid(msg->buf);
-}
-
-static int ti_qspi_spi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
-{
- struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
+ struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
+ u32 from = 0;
int ret = 0;
+ /* Only optimize read path. */
+ if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
+ !op->addr.nbytes || op->addr.nbytes > 4)
+ return -ENOTSUPP;
+
+ /* Address exceeds MMIO window size, fall back to regular mode. */
+ from = op->addr.val;
+ if (from + op->data.nbytes > qspi->mmap_size)
+ return -ENOTSUPP;
+
mutex_lock(&qspi->list_lock);
if (!qspi->mmap_enabled)
- ti_qspi_enable_memory_map(spi);
- ti_qspi_setup_mmap_read(spi, msg);
+ ti_qspi_enable_memory_map(mem->spi);
+ ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
+ op->addr.nbytes, op->dummy.nbytes);
if (qspi->rx_chan) {
- if (msg->cur_msg_mapped)
- ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
- else
- ret = ti_qspi_dma_bounce_buffer(qspi, msg);
- if (ret)
- goto err_unlock;
- } else {
- memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
- }
- msg->retlen = msg->len;
+ struct sg_table sgt;
-err_unlock:
+ if (virt_addr_valid(op->data.buf.in) &&
+ !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
+ &sgt)) {
+ ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
+ spi_controller_dma_unmap_mem_op_data(mem->spi->master,
+ op, &sgt);
+ } else {
+ ret = ti_qspi_dma_bounce_buffer(qspi, from,
+ op->data.buf.in,
+ op->data.nbytes);
+ }
+ } else {
+ memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
+ op->data.nbytes);
+ }
+
mutex_unlock(&qspi->list_lock);
return ret;
}
+static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
+ .exec_op = ti_qspi_exec_mem_op,
+};
+
static int ti_qspi_start_transfer_one(struct spi_master *master,
struct spi_message *m)
{
@@ -672,7 +689,7 @@
master->dev.of_node = pdev->dev.of_node;
master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
SPI_BPW_MASK(8);
- master->spi_flash_read = ti_qspi_spi_flash_read;
+ master->mem_ops = &ti_qspi_mem_ops;
if (!of_property_read_u32(np, "num-cs", &num_cs))
master->num_chipselect = num_cs;
@@ -702,6 +719,9 @@
}
}
+ if (res_mmap)
+ qspi->mmap_size = resource_size(res_mmap);
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq resource?\n");
@@ -770,7 +790,6 @@
dma_release_channel(qspi->rx_chan);
goto no_dma;
}
- master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma;
master->dma_rx = qspi->rx_chan;
init_completion(&qspi->transfer_complete);
if (res_mmap)
@@ -784,7 +803,7 @@
"mmap failed with error %ld using PIO mode\n",
PTR_ERR(qspi->mmap_base));
qspi->mmap_base = NULL;
- master->spi_flash_read = NULL;
+ master->mem_ops = NULL;
}
}
qspi->mmap_enabled = false;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index d735c2b..5a8a937 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -28,6 +28,7 @@
#include <linux/slab.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/pm_domain.h>
@@ -46,6 +47,8 @@
#define CREATE_TRACE_POINTS
#include <trace/events/spi.h>
+#include "internals.h"
+
static DEFINE_IDR(spi_master_idr);
static void spidev_release(struct device *dev)
@@ -741,9 +744,9 @@
}
#ifdef CONFIG_HAS_DMA
-static int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
- struct sg_table *sgt, void *buf, size_t len,
- enum dma_data_direction dir)
+int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+ struct sg_table *sgt, void *buf, size_t len,
+ enum dma_data_direction dir)
{
const bool vmalloced_buf = is_vmalloc_addr(buf);
unsigned int max_seg_size = dma_get_max_seg_size(dev);
@@ -822,8 +825,8 @@
return 0;
}
-static void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
- struct sg_table *sgt, enum dma_data_direction dir)
+void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
+ struct sg_table *sgt, enum dma_data_direction dir)
{
if (sgt->orig_nents) {
dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
@@ -908,19 +911,6 @@
return 0;
}
#else /* !CONFIG_HAS_DMA */
-static inline int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
- struct sg_table *sgt, void *buf, size_t len,
- enum dma_data_direction dir)
-{
- return -EINVAL;
-}
-
-static inline void spi_unmap_buf(struct spi_controller *ctlr,
- struct device *dev, struct sg_table *sgt,
- enum dma_data_direction dir)
-{
-}
-
static inline int __spi_map_msg(struct spi_controller *ctlr,
struct spi_message *msg)
{
@@ -1534,6 +1524,22 @@
return ret;
}
+/**
+ * spi_flush_queue - Send all pending messages in the queue from the callers'
+ * context
+ * @ctlr: controller to process queue for
+ *
+ * This should be used when one wants to ensure all pending messages have been
+ * sent before doing something. Is used by the spi-mem code to make sure SPI
+ * memory operations do not preempt regular SPI transfers that have been queued
+ * before the spi-mem operation.
+ */
+void spi_flush_queue(struct spi_controller *ctlr)
+{
+ if (ctlr->transfer == spi_queued_transfer)
+ __spi_pump_messages(ctlr, false);
+}
+
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_OF)
@@ -2064,6 +2070,26 @@
}
#endif
+static int spi_controller_check_ops(struct spi_controller *ctlr)
+{
+ /*
+ * The controller may implement only the high-level SPI-memory like
+ * operations if it does not support regular SPI transfers, and this is
+ * valid use case.
+ * If ->mem_ops is NULL, we request that at least one of the
+ * ->transfer_xxx() method be implemented.
+ */
+ if (ctlr->mem_ops) {
+ if (!ctlr->mem_ops->exec_op)
+ return -EINVAL;
+ } else if (!ctlr->transfer && !ctlr->transfer_one &&
+ !ctlr->transfer_one_message) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/**
* spi_register_controller - register SPI master or slave controller
* @ctlr: initialized master, originally from spi_alloc_master() or
@@ -2097,6 +2123,14 @@
if (!dev)
return -ENODEV;
+ /*
+ * Make sure all necessary hooks are implemented before registering
+ * the SPI controller.
+ */
+ status = spi_controller_check_ops(ctlr);
+ if (status)
+ return status;
+
if (!spi_controller_is_slave(ctlr)) {
status = of_spi_register_master(ctlr);
if (status)
@@ -2162,10 +2196,14 @@
spi_controller_is_slave(ctlr) ? "slave" : "master",
dev_name(&ctlr->dev));
- /* If we're using a queued driver, start the queue */
- if (ctlr->transfer)
+ /*
+ * If we're using a queued driver, start the queue. Note that we don't
+ * need the queueing logic if the driver is only supporting high-level
+ * memory operations.
+ */
+ if (ctlr->transfer) {
dev_info(dev, "controller is unqueued, this is deprecated\n");
- else {
+ } else if (ctlr->transfer_one || ctlr->transfer_one_message) {
status = spi_controller_initialize_queue(ctlr);
if (status) {
device_del(&ctlr->dev);
@@ -2893,6 +2931,13 @@
{
struct spi_controller *ctlr = spi->controller;
+ /*
+ * Some controllers do not support doing regular SPI transfers. Return
+ * ENOTSUPP when this is the case.
+ */
+ if (!ctlr->transfer)
+ return -ENOTSUPP;
+
message->spi = spi;
SPI_STATISTICS_INCREMENT_FIELD(&ctlr->statistics, spi_async);
@@ -3009,63 +3054,6 @@
}
EXPORT_SYMBOL_GPL(spi_async_locked);
-
-int spi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg)
-
-{
- struct spi_controller *master = spi->controller;
- struct device *rx_dev = NULL;
- int ret;
-
- if ((msg->opcode_nbits == SPI_NBITS_DUAL ||
- msg->addr_nbits == SPI_NBITS_DUAL) &&
- !(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD)))
- return -EINVAL;
- if ((msg->opcode_nbits == SPI_NBITS_QUAD ||
- msg->addr_nbits == SPI_NBITS_QUAD) &&
- !(spi->mode & SPI_TX_QUAD))
- return -EINVAL;
- if (msg->data_nbits == SPI_NBITS_DUAL &&
- !(spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD)))
- return -EINVAL;
- if (msg->data_nbits == SPI_NBITS_QUAD &&
- !(spi->mode & SPI_RX_QUAD))
- return -EINVAL;
-
- if (master->auto_runtime_pm) {
- ret = pm_runtime_get_sync(master->dev.parent);
- if (ret < 0) {
- dev_err(&master->dev, "Failed to power device: %d\n",
- ret);
- return ret;
- }
- }
-
- mutex_lock(&master->bus_lock_mutex);
- mutex_lock(&master->io_mutex);
- if (master->dma_rx && master->spi_flash_can_dma(spi, msg)) {
- rx_dev = master->dma_rx->device->dev;
- ret = spi_map_buf(master, rx_dev, &msg->rx_sg,
- msg->buf, msg->len,
- DMA_FROM_DEVICE);
- if (!ret)
- msg->cur_msg_mapped = true;
- }
- ret = master->spi_flash_read(spi, msg);
- if (msg->cur_msg_mapped)
- spi_unmap_buf(master, rx_dev, &msg->rx_sg,
- DMA_FROM_DEVICE);
- mutex_unlock(&master->io_mutex);
- mutex_unlock(&master->bus_lock_mutex);
-
- if (master->auto_runtime_pm)
- pm_runtime_put(master->dev.parent);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(spi_flash_read);
-
/*-------------------------------------------------------------------------*/
/* Utility methods for SPI protocol drivers, layered on
diff --git a/drivers/staging/android/ion/ion_heap.c b/drivers/staging/android/ion/ion_heap.c
index 91faa7f..babbd94 100644
--- a/drivers/staging/android/ion/ion_heap.c
+++ b/drivers/staging/android/ion/ion_heap.c
@@ -38,7 +38,7 @@
struct page **tmp = pages;
if (!pages)
- return NULL;
+ return ERR_PTR(-ENOMEM);
if (buffer->flags & ION_FLAG_CACHED)
pgprot = PAGE_KERNEL;
diff --git a/drivers/staging/comedi/drivers/quatech_daqp_cs.c b/drivers/staging/comedi/drivers/quatech_daqp_cs.c
index 802f51e..1719605 100644
--- a/drivers/staging/comedi/drivers/quatech_daqp_cs.c
+++ b/drivers/staging/comedi/drivers/quatech_daqp_cs.c
@@ -642,7 +642,7 @@
/* Make sure D/A update mode is direct update */
outb(0, dev->iobase + DAQP_AUX_REG);
- for (i = 0; i > insn->n; i++) {
+ for (i = 0; i < insn->n; i++) {
unsigned int val = data[i];
int ret;
diff --git a/drivers/staging/rtl8723bs/core/rtw_ap.c b/drivers/staging/rtl8723bs/core/rtw_ap.c
index d3007c1..a84400f 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ap.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ap.c
@@ -1059,7 +1059,7 @@
return _FAIL;
- if (len > MAX_IE_SZ)
+ if (len < 0 || len > MAX_IE_SZ)
return _FAIL;
pbss_network->IELength = len;
diff --git a/drivers/staging/rtlwifi/rtl8822be/hw.c b/drivers/staging/rtlwifi/rtl8822be/hw.c
index 7438600..c6db2bd 100644
--- a/drivers/staging/rtlwifi/rtl8822be/hw.c
+++ b/drivers/staging/rtlwifi/rtl8822be/hw.c
@@ -814,7 +814,7 @@
return;
pci_read_config_byte(rtlpci->pdev, 0x70f, &tmp);
- pci_write_config_byte(rtlpci->pdev, 0x70f, tmp | BIT(7));
+ pci_write_config_byte(rtlpci->pdev, 0x70f, tmp | ASPM_L1_LATENCY << 3);
pci_read_config_byte(rtlpci->pdev, 0x719, &tmp);
pci_write_config_byte(rtlpci->pdev, 0x719, tmp | BIT(3) | BIT(4));
diff --git a/drivers/staging/rtlwifi/wifi.h b/drivers/staging/rtlwifi/wifi.h
index eb91c13..5f0bc36 100644
--- a/drivers/staging/rtlwifi/wifi.h
+++ b/drivers/staging/rtlwifi/wifi.h
@@ -99,6 +99,7 @@
#define RTL_USB_MAX_RX_COUNT 100
#define QBSS_LOAD_SIZE 5
#define MAX_WMMELE_LENGTH 64
+#define ASPM_L1_LATENCY 7
#define TOTAL_CAM_ENTRY 32
diff --git a/drivers/staging/vboxvideo/vbox_ttm.c b/drivers/staging/vboxvideo/vbox_ttm.c
index 4eb410a..2ea3158 100644
--- a/drivers/staging/vboxvideo/vbox_ttm.c
+++ b/drivers/staging/vboxvideo/vbox_ttm.c
@@ -183,13 +183,6 @@
{
}
-static int vbox_bo_move(struct ttm_buffer_object *bo,
- bool evict, bool interruptible,
- bool no_wait_gpu, struct ttm_mem_reg *new_mem)
-{
- return ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
-}
-
static void vbox_ttm_backend_destroy(struct ttm_tt *tt)
{
ttm_tt_fini(tt);
@@ -220,9 +213,10 @@
return tt;
}
-static int vbox_ttm_tt_populate(struct ttm_tt *ttm)
+static int vbox_ttm_tt_populate(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx)
{
- return ttm_pool_populate(ttm);
+ return ttm_pool_populate(ttm, ctx);
}
static void vbox_ttm_tt_unpopulate(struct ttm_tt *ttm)
@@ -237,11 +231,9 @@
.init_mem_type = vbox_bo_init_mem_type,
.eviction_valuable = ttm_bo_eviction_valuable,
.evict_flags = vbox_bo_evict_flags,
- .move = vbox_bo_move,
.verify_access = vbox_bo_verify_access,
.io_mem_reserve = &vbox_ttm_io_mem_reserve,
.io_mem_free = &vbox_ttm_io_mem_free,
- .io_mem_pfn = ttm_bo_default_io_mem_pfn,
};
int vbox_mm_init(struct vbox_private *vbox)
@@ -374,6 +366,7 @@
int vbox_bo_pin(struct vbox_bo *bo, u32 pl_flag, u64 *gpu_addr)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (bo->pin_count) {
@@ -389,7 +382,7 @@
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -403,6 +396,7 @@
int vbox_bo_unpin(struct vbox_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
@@ -416,7 +410,7 @@
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret)
return ret;
@@ -430,6 +424,7 @@
*/
int vbox_bo_push_sysram(struct vbox_bo *bo)
{
+ struct ttm_operation_ctx ctx = { false, false };
int i, ret;
if (!bo->pin_count) {
@@ -448,7 +443,7 @@
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
- ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+ ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
if (ret) {
DRM_ERROR("pushing to VRAM failed\n");
return ret;
diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c
index 4ba5004..fd6ce99 100644
--- a/drivers/target/target_core_pr.c
+++ b/drivers/target/target_core_pr.c
@@ -3729,11 +3729,16 @@
* Check for overflow of 8byte PRI READ_KEYS payload and
* next reservation key list descriptor.
*/
- if ((add_len + 8) > (cmd->data_length - 8))
- break;
-
- put_unaligned_be64(pr_reg->pr_res_key, &buf[off]);
- off += 8;
+ if (off + 8 <= cmd->data_length) {
+ put_unaligned_be64(pr_reg->pr_res_key, &buf[off]);
+ off += 8;
+ }
+ /*
+ * SPC5r17: 6.16.2 READ KEYS service action
+ * The ADDITIONAL LENGTH field indicates the number of bytes in
+ * the Reservation key list. The contents of the ADDITIONAL
+ * LENGTH field are not altered based on the allocation length
+ */
add_len += 8;
}
spin_unlock(&dev->t10_pr.registration_lock);
diff --git a/drivers/thermal/broadcom/bcm2835_thermal.c b/drivers/thermal/broadcom/bcm2835_thermal.c
index a4d6a0e..23ad4f9 100644
--- a/drivers/thermal/broadcom/bcm2835_thermal.c
+++ b/drivers/thermal/broadcom/bcm2835_thermal.c
@@ -213,8 +213,8 @@
rate = clk_get_rate(data->clk);
if ((rate < 1920000) || (rate > 5000000))
dev_warn(&pdev->dev,
- "Clock %pCn running at %pCr Hz is outside of the recommended range: 1.92 to 5MHz\n",
- data->clk, data->clk);
+ "Clock %pCn running at %lu Hz is outside of the recommended range: 1.92 to 5MHz\n",
+ data->clk, rate);
/* register of thermal sensor and get info from DT */
tz = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 3f9fe6a..20f3b87 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -116,6 +116,7 @@
struct tsens_device *tmdev;
const struct tsens_data *data;
const struct of_device_id *id;
+ u32 num_sensors;
if (pdev->dev.of_node)
dev = &pdev->dev;
@@ -130,18 +131,23 @@
else
data = &data_8960;
- if (data->num_sensors <= 0) {
+ num_sensors = data->num_sensors;
+
+ if (np)
+ of_property_read_u32(np, "#qcom,sensors", &num_sensors);
+
+ if (num_sensors <= 0) {
dev_err(dev, "invalid number of sensors\n");
return -EINVAL;
}
tmdev = devm_kzalloc(dev, sizeof(*tmdev) +
- data->num_sensors * sizeof(*s), GFP_KERNEL);
+ num_sensors * sizeof(*s), GFP_KERNEL);
if (!tmdev)
return -ENOMEM;
tmdev->dev = dev;
- tmdev->num_sensors = data->num_sensors;
+ tmdev->num_sensors = num_sensors;
tmdev->ops = data->ops;
for (i = 0; i < tmdev->num_sensors; i++) {
if (data->hw_ids)
diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
index 4fc152b..ff16847 100644
--- a/drivers/thermal/thermal_core.c
+++ b/drivers/thermal/thermal_core.c
@@ -307,9 +307,9 @@
{
mutex_lock(&tz->lock);
- if (tz->mode == THERMAL_DEVICE_ENABLED && tz->passive)
+ if (tz->passive)
thermal_zone_device_set_polling(tz, tz->passive_delay);
- else if (tz->mode == THERMAL_DEVICE_ENABLED && tz->polling_delay)
+ else if (tz->polling_delay)
thermal_zone_device_set_polling(tz, tz->polling_delay);
else
thermal_zone_device_set_polling(tz, 0);
@@ -502,35 +502,11 @@
pos->initialized = false;
}
-int thermal_zone_set_mode(struct thermal_zone_device *tz,
- enum thermal_device_mode mode)
-{
- int result;
-
- if (!tz->ops->set_mode)
- return -EPERM;
-
- result = tz->ops->set_mode(tz, mode);
- if (result)
- return result;
-
- if (tz->mode != mode) {
- tz->mode = mode;
- monitor_thermal_zone(tz);
- }
- return 0;
-}
-EXPORT_SYMBOL_GPL(thermal_zone_set_mode);
-
void thermal_zone_device_update(struct thermal_zone_device *tz,
enum thermal_notify_event event)
{
int count;
- /* Do nothing if the thermal zone is disabled */
- if (tz->mode == THERMAL_DEVICE_DISABLED)
- return;
-
if (atomic_read(&in_suspend))
return;
@@ -1340,15 +1316,6 @@
INIT_DELAYED_WORK(&tz->poll_queue, thermal_zone_device_check);
thermal_zone_device_reset(tz);
-
- if (tz->ops->get_mode) {
- enum thermal_device_mode mode;
-
- result = tz->ops->get_mode(tz, &mode);
- tz->mode = result ? THERMAL_DEVICE_ENABLED : mode;
- } else
- tz->mode = THERMAL_DEVICE_ENABLED;
-
/* Update the new thermal zone and mark it as already updated. */
if (atomic_cmpxchg(&tz->need_update, 1, 0))
thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
diff --git a/drivers/thermal/thermal_sysfs.c b/drivers/thermal/thermal_sysfs.c
index 9e2499c..fb80c96 100644
--- a/drivers/thermal/thermal_sysfs.c
+++ b/drivers/thermal/thermal_sysfs.c
@@ -51,8 +51,17 @@
mode_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct thermal_zone_device *tz = to_thermal_zone(dev);
+ enum thermal_device_mode mode;
+ int result;
- return sprintf(buf, "%s\n", tz->mode == THERMAL_DEVICE_ENABLED ? "enabled"
+ if (!tz->ops->get_mode)
+ return -EPERM;
+
+ result = tz->ops->get_mode(tz, &mode);
+ if (result)
+ return result;
+
+ return sprintf(buf, "%s\n", mode == THERMAL_DEVICE_ENABLED ? "enabled"
: "disabled");
}
@@ -61,17 +70,18 @@
const char *buf, size_t count)
{
struct thermal_zone_device *tz = to_thermal_zone(dev);
- enum thermal_device_mode mode;
int result;
- if (!strncmp(buf, "enabled", sizeof("enabled") - 1))
- mode = THERMAL_DEVICE_ENABLED;
- else if (!strncmp(buf, "disabled", sizeof("disabled") - 1))
- mode = THERMAL_DEVICE_DISABLED;
- else
- return -EINVAL;
+ if (!tz->ops->set_mode)
+ return -EPERM;
- result = thermal_zone_set_mode(tz, mode);
+ if (!strncmp(buf, "enabled", sizeof("enabled") - 1))
+ result = tz->ops->set_mode(tz, THERMAL_DEVICE_ENABLED);
+ else if (!strncmp(buf, "disabled", sizeof("disabled") - 1))
+ result = tz->ops->set_mode(tz, THERMAL_DEVICE_DISABLED);
+ else
+ result = -EINVAL;
+
if (result)
return result;
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 1c70541..0475f96 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -126,6 +126,8 @@
struct mutex output_lock;
};
+#define MASK(x) ((x) & (N_TTY_BUF_SIZE - 1))
+
static inline size_t read_cnt(struct n_tty_data *ldata)
{
return ldata->read_head - ldata->read_tail;
@@ -143,6 +145,7 @@
static inline unsigned char echo_buf(struct n_tty_data *ldata, size_t i)
{
+ smp_rmb(); /* Matches smp_wmb() in add_echo_byte(). */
return ldata->echo_buf[i & (N_TTY_BUF_SIZE - 1)];
}
@@ -318,9 +321,7 @@
static void reset_buffer_flags(struct n_tty_data *ldata)
{
ldata->read_head = ldata->canon_head = ldata->read_tail = 0;
- ldata->echo_head = ldata->echo_tail = ldata->echo_commit = 0;
ldata->commit_head = 0;
- ldata->echo_mark = 0;
ldata->line_start = 0;
ldata->erasing = 0;
@@ -619,13 +620,20 @@
old_space = space = tty_write_room(tty);
tail = ldata->echo_tail;
- while (ldata->echo_commit != tail) {
+ while (MASK(ldata->echo_commit) != MASK(tail)) {
c = echo_buf(ldata, tail);
if (c == ECHO_OP_START) {
unsigned char op;
int no_space_left = 0;
/*
+ * Since add_echo_byte() is called without holding
+ * output_lock, we might see only portion of multi-byte
+ * operation.
+ */
+ if (MASK(ldata->echo_commit) == MASK(tail + 1))
+ goto not_yet_stored;
+ /*
* If the buffer byte is the start of a multi-byte
* operation, get the next byte, which is either the
* op code or a control character value.
@@ -636,6 +644,8 @@
unsigned int num_chars, num_bs;
case ECHO_OP_ERASE_TAB:
+ if (MASK(ldata->echo_commit) == MASK(tail + 2))
+ goto not_yet_stored;
num_chars = echo_buf(ldata, tail + 2);
/*
@@ -730,7 +740,8 @@
/* If the echo buffer is nearly full (so that the possibility exists
* of echo overrun before the next commit), then discard enough
* data at the tail to prevent a subsequent overrun */
- while (ldata->echo_commit - tail >= ECHO_DISCARD_WATERMARK) {
+ while (ldata->echo_commit > tail &&
+ ldata->echo_commit - tail >= ECHO_DISCARD_WATERMARK) {
if (echo_buf(ldata, tail) == ECHO_OP_START) {
if (echo_buf(ldata, tail + 1) == ECHO_OP_ERASE_TAB)
tail += 3;
@@ -740,6 +751,7 @@
tail++;
}
+ not_yet_stored:
ldata->echo_tail = tail;
return old_space - space;
}
@@ -750,6 +762,7 @@
size_t nr, old, echoed;
size_t head;
+ mutex_lock(&ldata->output_lock);
head = ldata->echo_head;
ldata->echo_mark = head;
old = ldata->echo_commit - ldata->echo_tail;
@@ -758,10 +771,12 @@
* is over the threshold (and try again each time another
* block is accumulated) */
nr = head - ldata->echo_tail;
- if (nr < ECHO_COMMIT_WATERMARK || (nr % ECHO_BLOCK > old % ECHO_BLOCK))
+ if (nr < ECHO_COMMIT_WATERMARK ||
+ (nr % ECHO_BLOCK > old % ECHO_BLOCK)) {
+ mutex_unlock(&ldata->output_lock);
return;
+ }
- mutex_lock(&ldata->output_lock);
ldata->echo_commit = head;
echoed = __process_echoes(tty);
mutex_unlock(&ldata->output_lock);
@@ -812,7 +827,9 @@
static inline void add_echo_byte(unsigned char c, struct n_tty_data *ldata)
{
- *echo_buf_addr(ldata, ldata->echo_head++) = c;
+ *echo_buf_addr(ldata, ldata->echo_head) = c;
+ smp_wmb(); /* Matches smp_rmb() in echo_buf(). */
+ ldata->echo_head++;
}
/**
@@ -980,14 +997,15 @@
}
seen_alnums = 0;
- while (ldata->read_head != ldata->canon_head) {
+ while (MASK(ldata->read_head) != MASK(ldata->canon_head)) {
head = ldata->read_head;
/* erase a single possibly multibyte character */
do {
head--;
c = read_buf(ldata, head);
- } while (is_continuation(c, tty) && head != ldata->canon_head);
+ } while (is_continuation(c, tty) &&
+ MASK(head) != MASK(ldata->canon_head));
/* do not partially erase */
if (is_continuation(c, tty))
@@ -1029,7 +1047,7 @@
* This info is used to go back the correct
* number of columns.
*/
- while (tail != ldata->canon_head) {
+ while (MASK(tail) != MASK(ldata->canon_head)) {
tail--;
c = read_buf(ldata, tail);
if (c == '\t') {
@@ -1304,7 +1322,7 @@
finish_erasing(ldata);
echo_char(c, tty);
echo_char_raw('\n', ldata);
- while (tail != ldata->read_head) {
+ while (MASK(tail) != MASK(ldata->read_head)) {
echo_char(read_buf(ldata, tail), tty);
tail++;
}
@@ -1880,30 +1898,21 @@
struct n_tty_data *ldata;
/* Currently a malloc failure here can panic */
- ldata = vmalloc(sizeof(*ldata));
+ ldata = vzalloc(sizeof(*ldata));
if (!ldata)
- goto err;
+ return -ENOMEM;
ldata->overrun_time = jiffies;
mutex_init(&ldata->atomic_read_lock);
mutex_init(&ldata->output_lock);
tty->disc_data = ldata;
- reset_buffer_flags(tty->disc_data);
- ldata->column = 0;
- ldata->canon_column = 0;
- ldata->num_overrun = 0;
- ldata->no_room = 0;
- ldata->lnext = 0;
tty->closing = 0;
/* indicate buffer work may resume */
clear_bit(TTY_LDISC_HALTED, &tty->flags);
n_tty_set_termios(tty, NULL);
tty_unthrottle(tty);
-
return 0;
-err:
- return -ENOMEM;
}
static inline int input_available_p(struct tty_struct *tty, int poll)
@@ -2413,7 +2422,7 @@
tail = ldata->read_tail;
nr = head - tail;
/* Skip EOF-chars.. */
- while (head != tail) {
+ while (MASK(head) != MASK(tail)) {
if (test_bit(tail & (N_TTY_BUF_SIZE - 1), ldata->read_flags) &&
read_buf(ldata, tail) == __DISABLED_CHAR)
nr--;
diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
index 97db76a..ae2564e 100644
--- a/drivers/tty/serdev/core.c
+++ b/drivers/tty/serdev/core.c
@@ -482,6 +482,7 @@
static void __exit serdev_exit(void)
{
bus_unregister(&serdev_bus_type);
+ ida_destroy(&ctrl_ida);
}
module_exit(serdev_exit);
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 0d814a8..4986b4a 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -3345,9 +3345,7 @@
/* multi-io cards handled by parport_serial */
{ PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
- { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
- { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
/* Moxa Smartio MUE boards handled by 8250_moxa */
{ PCI_VDEVICE(MOXA, 0x1024), },
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index c6daa31..8bc8fe2 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2854,16 +2854,15 @@
unsigned long flags;
int locked = 1;
- local_irq_save(flags);
#if defined(SUPPORT_SYSRQ)
if (port->sysrq)
locked = 0;
else
#endif
if (oops_in_progress)
- locked = spin_trylock(&port->lock);
+ locked = spin_trylock_irqsave(&port->lock, flags);
else
- spin_lock(&port->lock);
+ spin_lock_irqsave(&port->lock, flags);
/* first save SCSCR then disable interrupts, keep clock source */
ctrl = serial_port_in(port, SCSCR);
@@ -2883,8 +2882,7 @@
serial_port_out(port, SCSCR, ctrl);
if (locked)
- spin_unlock(&port->lock);
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&port->lock, flags);
}
static int serial_console_setup(struct console *co, char *options)
diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c
index de67abb..e77421e 100644
--- a/drivers/tty/vt/vt.c
+++ b/drivers/tty/vt/vt.c
@@ -782,7 +782,7 @@
if (!*vc->vc_uni_pagedir_loc)
con_set_default_unimap(vc);
- vc->vc_screenbuf = kmalloc(vc->vc_screenbuf_size, GFP_KERNEL);
+ vc->vc_screenbuf = kzalloc(vc->vc_screenbuf_size, GFP_KERNEL);
if (!vc->vc_screenbuf)
goto err_free;
@@ -869,7 +869,7 @@
if (new_screen_size > (4 << 20))
return -EINVAL;
- newscreen = kmalloc(new_screen_size, GFP_USER);
+ newscreen = kzalloc(new_screen_size, GFP_USER);
if (!newscreen)
return -ENOMEM;
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 22952d7..3b9aadd 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -1771,6 +1771,9 @@
{ USB_DEVICE(0x11ca, 0x0201), /* VeriFone Mx870 Gadget Serial */
.driver_info = SINGLE_RX_URB,
},
+ { USB_DEVICE(0x1965, 0x0018), /* Uniden UBC125XLT */
+ .driver_info = NO_UNION_NORMAL, /* has no union descriptor */
+ },
{ USB_DEVICE(0x22b8, 0x7000), /* Motorola Q Phone */
.driver_info = NO_UNION_NORMAL, /* has no union descriptor */
},
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index c20184c..ec0bdfe 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -3637,12 +3637,54 @@
return 0;
}
+/* Report wakeup requests from the ports of a resuming root hub */
+static void report_wakeup_requests(struct usb_hub *hub)
+{
+ struct usb_device *hdev = hub->hdev;
+ struct usb_device *udev;
+ struct usb_hcd *hcd;
+ unsigned long resuming_ports;
+ int i;
+
+ if (hdev->parent)
+ return; /* Not a root hub */
+
+ hcd = bus_to_hcd(hdev->bus);
+ if (hcd->driver->get_resuming_ports) {
+
+ /*
+ * The get_resuming_ports() method returns a bitmap (origin 0)
+ * of ports which have started wakeup signaling but have not
+ * yet finished resuming. During system resume we will
+ * resume all the enabled ports, regardless of any wakeup
+ * signals, which means the wakeup requests would be lost.
+ * To prevent this, report them to the PM core here.
+ */
+ resuming_ports = hcd->driver->get_resuming_ports(hcd);
+ for (i = 0; i < hdev->maxchild; ++i) {
+ if (test_bit(i, &resuming_ports)) {
+ udev = hub->ports[i]->child;
+ if (udev)
+ pm_wakeup_event(&udev->dev, 0);
+ }
+ }
+ }
+}
+
static int hub_resume(struct usb_interface *intf)
{
struct usb_hub *hub = usb_get_intfdata(intf);
dev_dbg(&intf->dev, "%s\n", __func__);
hub_activate(hub, HUB_RESUME);
+
+ /*
+ * This should be called only for system resume, not runtime resume.
+ * We can't tell the difference here, so some wakeup requests will be
+ * reported at the wrong time or more than once. This shouldn't
+ * matter much, so long as they do get reported.
+ */
+ report_wakeup_requests(hub);
return 0;
}
@@ -4540,7 +4582,9 @@
* reset. But only on the first attempt,
* lest we get into a time out/reset loop
*/
- if (r == 0 || (r == -ETIMEDOUT && retries == 0))
+ if (r == 0 || (r == -ETIMEDOUT &&
+ retries == 0 &&
+ udev->speed > USB_SPEED_FULL))
break;
}
udev->descriptor.bMaxPacketSize0 =
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 0847c73..554dd62 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -234,6 +234,10 @@
/* Corsair K70 RGB */
{ USB_DEVICE(0x1b1c, 0x1b13), .driver_info = USB_QUIRK_DELAY_INIT },
+ /* Corsair Strafe */
+ { USB_DEVICE(0x1b1c, 0x1b15), .driver_info = USB_QUIRK_DELAY_INIT |
+ USB_QUIRK_DELAY_CTRL_MSG },
+
/* Corsair Strafe RGB */
{ USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT |
USB_QUIRK_DELAY_CTRL_MSG },
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
index 3ae8b1b..7f51a77 100644
--- a/drivers/usb/dwc2/hcd_queue.c
+++ b/drivers/usb/dwc2/hcd_queue.c
@@ -379,7 +379,7 @@
/* Get the map and adjust if this is a multi_tt hub */
map = qh->dwc_tt->periodic_bitmaps;
if (qh->dwc_tt->usb_tt->multi)
- map += DWC2_ELEMENTS_PER_LS_BITMAP * qh->ttport;
+ map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1);
return map;
}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 6e834b83..374691cc 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1239,6 +1239,7 @@
.bus_resume = ehci_bus_resume,
.relinquish_port = ehci_relinquish_port,
.port_handed_over = ehci_port_handed_over,
+ .get_resuming_ports = ehci_get_resuming_ports,
/*
* device support
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 37ef2ac..6e88b625 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -525,10 +525,18 @@
return -ESHUTDOWN;
}
+static unsigned long ehci_get_resuming_ports(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+ return ehci->resuming_ports;
+}
+
#else
#define ehci_bus_suspend NULL
#define ehci_bus_resume NULL
+#define ehci_get_resuming_ports NULL
#endif /* CONFIG_PM */
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 00b8d4c..216c138 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -1693,4 +1693,15 @@
return 0;
}
+unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ struct xhci_bus_state *bus_state;
+
+ bus_state = &xhci->bus_state[hcd_index(hcd)];
+
+ /* USB3 port wakeups are reported via usb_wakeup_notification() */
+ return bus_state->resuming_ports; /* USB2 ports only */
+}
+
#endif /* CONFIG_PM */
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index efd7e48..b7b55eb 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -604,7 +604,7 @@
if (!ep->stream_info)
return NULL;
- if (stream_id > ep->stream_info->num_streams)
+ if (stream_id >= ep->stream_info->num_streams)
return NULL;
return ep->stream_info->stream_rings[stream_id];
}
@@ -891,12 +891,12 @@
dev = xhci->devs[slot_id];
- trace_xhci_free_virt_device(dev);
-
xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
if (!dev)
return;
+ trace_xhci_free_virt_device(dev);
+
if (dev->tt_info)
old_active_eps = dev->tt_info->active_eps;
diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
index f20753b..02a1164 100644
--- a/drivers/usb/host/xhci-trace.h
+++ b/drivers/usb/host/xhci-trace.h
@@ -158,6 +158,37 @@
TP_ARGS(ring, trb)
);
+DECLARE_EVENT_CLASS(xhci_log_free_virt_dev,
+ TP_PROTO(struct xhci_virt_device *vdev),
+ TP_ARGS(vdev),
+ TP_STRUCT__entry(
+ __field(void *, vdev)
+ __field(unsigned long long, out_ctx)
+ __field(unsigned long long, in_ctx)
+ __field(u8, fake_port)
+ __field(u8, real_port)
+ __field(u16, current_mel)
+
+ ),
+ TP_fast_assign(
+ __entry->vdev = vdev;
+ __entry->in_ctx = (unsigned long long) vdev->in_ctx->dma;
+ __entry->out_ctx = (unsigned long long) vdev->out_ctx->dma;
+ __entry->fake_port = (u8) vdev->fake_port;
+ __entry->real_port = (u8) vdev->real_port;
+ __entry->current_mel = (u16) vdev->current_mel;
+ ),
+ TP_printk("vdev %p ctx %llx | %llx fake_port %d real_port %d current_mel %d",
+ __entry->vdev, __entry->in_ctx, __entry->out_ctx,
+ __entry->fake_port, __entry->real_port, __entry->current_mel
+ )
+);
+
+DEFINE_EVENT(xhci_log_free_virt_dev, xhci_free_virt_device,
+ TP_PROTO(struct xhci_virt_device *vdev),
+ TP_ARGS(vdev)
+);
+
DECLARE_EVENT_CLASS(xhci_log_virt_dev,
TP_PROTO(struct xhci_virt_device *vdev),
TP_ARGS(vdev),
@@ -195,11 +226,6 @@
TP_ARGS(vdev)
);
-DEFINE_EVENT(xhci_log_virt_dev, xhci_free_virt_device,
- TP_PROTO(struct xhci_virt_device *vdev),
- TP_ARGS(vdev)
-);
-
DEFINE_EVENT(xhci_log_virt_dev, xhci_setup_device,
TP_PROTO(struct xhci_virt_device *vdev),
TP_ARGS(vdev)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 05f66b48..cce8fdd 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -3551,6 +3551,7 @@
del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
}
+ virt_dev->udev = NULL;
xhci_disable_slot(xhci, udev->slot_id);
/*
* Event command completion handler will free any data structures
@@ -4943,6 +4944,7 @@
.hub_status_data = xhci_hub_status_data,
.bus_suspend = xhci_bus_suspend,
.bus_resume = xhci_bus_resume,
+ .get_resuming_ports = xhci_get_resuming_ports,
/*
* call back when device connected and addressed
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 2a72060..4abf4b9 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -2090,9 +2090,11 @@
#ifdef CONFIG_PM
int xhci_bus_suspend(struct usb_hcd *hcd);
int xhci_bus_resume(struct usb_hcd *hcd);
+unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
#else
#define xhci_bus_suspend NULL
#define xhci_bus_resume NULL
+#define xhci_get_resuming_ports NULL
#endif /* CONFIG_PM */
u32 xhci_port_state_to_neutral(u32 state);
diff --git a/drivers/usb/misc/yurex.c b/drivers/usb/misc/yurex.c
index 58abdf2..4776331 100644
--- a/drivers/usb/misc/yurex.c
+++ b/drivers/usb/misc/yurex.c
@@ -400,8 +400,7 @@
loff_t *ppos)
{
struct usb_yurex *dev;
- int retval = 0;
- int bytes_read = 0;
+ int len = 0;
char in_buffer[20];
unsigned long flags;
@@ -409,26 +408,16 @@
mutex_lock(&dev->io_mutex);
if (!dev->interface) { /* already disconnected */
- retval = -ENODEV;
- goto exit;
+ mutex_unlock(&dev->io_mutex);
+ return -ENODEV;
}
spin_lock_irqsave(&dev->lock, flags);
- bytes_read = snprintf(in_buffer, 20, "%lld\n", dev->bbu);
+ len = snprintf(in_buffer, 20, "%lld\n", dev->bbu);
spin_unlock_irqrestore(&dev->lock, flags);
-
- if (*ppos < bytes_read) {
- if (copy_to_user(buffer, in_buffer + *ppos, bytes_read - *ppos))
- retval = -EFAULT;
- else {
- retval = bytes_read - *ppos;
- *ppos += bytes_read;
- }
- }
-
-exit:
mutex_unlock(&dev->io_mutex);
- return retval;
+
+ return simple_read_from_buffer(buffer, count, ppos, in_buffer, len);
}
static ssize_t yurex_write(struct file *file, const char __user *user_buffer,
diff --git a/drivers/usb/serial/ch341.c b/drivers/usb/serial/ch341.c
index 351745a..578596d 100644
--- a/drivers/usb/serial/ch341.c
+++ b/drivers/usb/serial/ch341.c
@@ -131,7 +131,7 @@
r = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), request,
USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
value, index, buf, bufsize, DEFAULT_TIMEOUT);
- if (r < bufsize) {
+ if (r < (int)bufsize) {
if (r >= 0) {
dev_err(&dev->dev,
"short control message received (%d < %u)\n",
diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
index d0f0027..c931ae6 100644
--- a/drivers/usb/serial/cp210x.c
+++ b/drivers/usb/serial/cp210x.c
@@ -98,6 +98,9 @@
{ USB_DEVICE(0x10C4, 0x8156) }, /* B&G H3000 link cable */
{ USB_DEVICE(0x10C4, 0x815E) }, /* Helicomm IP-Link 1220-DVM */
{ USB_DEVICE(0x10C4, 0x815F) }, /* Timewave HamLinkUSB */
+ { USB_DEVICE(0x10C4, 0x817C) }, /* CESINEL MEDCAL N Power Quality Monitor */
+ { USB_DEVICE(0x10C4, 0x817D) }, /* CESINEL MEDCAL NT Power Quality Monitor */
+ { USB_DEVICE(0x10C4, 0x817E) }, /* CESINEL MEDCAL S Power Quality Monitor */
{ USB_DEVICE(0x10C4, 0x818B) }, /* AVIT Research USB to TTL */
{ USB_DEVICE(0x10C4, 0x819F) }, /* MJS USB Toslink Switcher */
{ USB_DEVICE(0x10C4, 0x81A6) }, /* ThinkOptics WavIt */
@@ -115,6 +118,9 @@
{ USB_DEVICE(0x10C4, 0x826B) }, /* Cygnal Integrated Products, Inc., Fasttrax GPS demonstration module */
{ USB_DEVICE(0x10C4, 0x8281) }, /* Nanotec Plug & Drive */
{ USB_DEVICE(0x10C4, 0x8293) }, /* Telegesis ETRX2USB */
+ { USB_DEVICE(0x10C4, 0x82EF) }, /* CESINEL FALCO 6105 AC Power Supply */
+ { USB_DEVICE(0x10C4, 0x82F1) }, /* CESINEL MEDCAL EFD Earth Fault Detector */
+ { USB_DEVICE(0x10C4, 0x82F2) }, /* CESINEL MEDCAL ST Network Analyzer */
{ USB_DEVICE(0x10C4, 0x82F4) }, /* Starizona MicroTouch */
{ USB_DEVICE(0x10C4, 0x82F9) }, /* Procyon AVS */
{ USB_DEVICE(0x10C4, 0x8341) }, /* Siemens MC35PU GPRS Modem */
@@ -127,7 +133,9 @@
{ USB_DEVICE(0x10C4, 0x8470) }, /* Juniper Networks BX Series System Console */
{ USB_DEVICE(0x10C4, 0x8477) }, /* Balluff RFID */
{ USB_DEVICE(0x10C4, 0x84B6) }, /* Starizona Hyperion */
+ { USB_DEVICE(0x10C4, 0x851E) }, /* CESINEL MEDCAL PT Network Analyzer */
{ USB_DEVICE(0x10C4, 0x85A7) }, /* LifeScan OneTouch Verio IQ */
+ { USB_DEVICE(0x10C4, 0x85B8) }, /* CESINEL ReCon T Energy Logger */
{ USB_DEVICE(0x10C4, 0x85EA) }, /* AC-Services IBUS-IF */
{ USB_DEVICE(0x10C4, 0x85EB) }, /* AC-Services CIS-IBUS */
{ USB_DEVICE(0x10C4, 0x85F8) }, /* Virtenio Preon32 */
@@ -137,17 +145,24 @@
{ USB_DEVICE(0x10C4, 0x8857) }, /* CEL EM357 ZigBee USB Stick */
{ USB_DEVICE(0x10C4, 0x88A4) }, /* MMB Networks ZigBee USB Device */
{ USB_DEVICE(0x10C4, 0x88A5) }, /* Planet Innovation Ingeni ZigBee USB Device */
+ { USB_DEVICE(0x10C4, 0x88FB) }, /* CESINEL MEDCAL STII Network Analyzer */
+ { USB_DEVICE(0x10C4, 0x8938) }, /* CESINEL MEDCAL S II Network Analyzer */
{ USB_DEVICE(0x10C4, 0x8946) }, /* Ketra N1 Wireless Interface */
{ USB_DEVICE(0x10C4, 0x8962) }, /* Brim Brothers charging dock */
{ USB_DEVICE(0x10C4, 0x8977) }, /* CEL MeshWorks DevKit Device */
{ USB_DEVICE(0x10C4, 0x8998) }, /* KCF Technologies PRN */
+ { USB_DEVICE(0x10C4, 0x89A4) }, /* CESINEL FTBC Flexible Thyristor Bridge Controller */
+ { USB_DEVICE(0x10C4, 0x89FB) }, /* Qivicon ZigBee USB Radio Stick */
{ USB_DEVICE(0x10C4, 0x8A2A) }, /* HubZ dual ZigBee and Z-Wave dongle */
{ USB_DEVICE(0x10C4, 0x8A5E) }, /* CEL EM3588 ZigBee USB Stick Long Range */
{ USB_DEVICE(0x10C4, 0x8B34) }, /* Qivicon ZigBee USB Radio Stick */
{ USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */
{ USB_DEVICE(0x10C4, 0xEA61) }, /* Silicon Labs factory default */
+ { USB_DEVICE(0x10C4, 0xEA63) }, /* Silicon Labs Windows Update (CP2101-4/CP2102N) */
{ USB_DEVICE(0x10C4, 0xEA70) }, /* Silicon Labs factory default */
{ USB_DEVICE(0x10C4, 0xEA71) }, /* Infinity GPS-MIC-1 Radio Monophone */
+ { USB_DEVICE(0x10C4, 0xEA7A) }, /* Silicon Labs Windows Update (CP2105) */
+ { USB_DEVICE(0x10C4, 0xEA7B) }, /* Silicon Labs Windows Update (CP2108) */
{ USB_DEVICE(0x10C4, 0xF001) }, /* Elan Digital Systems USBscope50 */
{ USB_DEVICE(0x10C4, 0xF002) }, /* Elan Digital Systems USBwave12 */
{ USB_DEVICE(0x10C4, 0xF003) }, /* Elan Digital Systems USBpulse100 */
diff --git a/drivers/usb/serial/keyspan_pda.c b/drivers/usb/serial/keyspan_pda.c
index 196908d..f8e8285 100644
--- a/drivers/usb/serial/keyspan_pda.c
+++ b/drivers/usb/serial/keyspan_pda.c
@@ -373,8 +373,10 @@
3, /* get pins */
USB_TYPE_VENDOR|USB_RECIP_INTERFACE|USB_DIR_IN,
0, 0, data, 1, 2000);
- if (rc >= 0)
+ if (rc == 1)
*value = *data;
+ else if (rc >= 0)
+ rc = -EIO;
kfree(data);
return rc;
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index e8669aae..5e49017 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -481,6 +481,9 @@
}
dev_dbg(dev, "%s urb buffer size is %d\n", __func__, urb->actual_length);
+ if (urb->actual_length < 1)
+ goto out;
+
dev_dbg(dev, "%s mos7840_port->MsrLsr is %d port %d\n", __func__,
mos7840_port->MsrLsr, mos7840_port->port_num);
data = urb->transfer_buffer;
diff --git a/drivers/usb/typec/ucsi/ucsi.c b/drivers/usb/typec/ucsi/ucsi.c
index dd24c5c..251f5d6 100644
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -346,6 +346,19 @@
}
if (con->status.change & UCSI_CONSTAT_CONNECT_CHANGE) {
+ typec_set_pwr_role(con->port, con->status.pwr_dir);
+
+ switch (con->status.partner_type) {
+ case UCSI_CONSTAT_PARTNER_TYPE_UFP:
+ typec_set_data_role(con->port, TYPEC_HOST);
+ break;
+ case UCSI_CONSTAT_PARTNER_TYPE_DFP:
+ typec_set_data_role(con->port, TYPEC_DEVICE);
+ break;
+ default:
+ break;
+ }
+
if (con->status.connected)
ucsi_register_partner(con);
else
diff --git a/drivers/usb/typec/ucsi/ucsi_acpi.c b/drivers/usb/typec/ucsi/ucsi_acpi.c
index cabd476..494d2a4 100644
--- a/drivers/usb/typec/ucsi/ucsi_acpi.c
+++ b/drivers/usb/typec/ucsi/ucsi_acpi.c
@@ -82,6 +82,11 @@
return -ENODEV;
}
+ /* This will make sure we can use ioremap_nocache() */
+ status = acpi_release_memory(ACPI_HANDLE(&pdev->dev), res, 1);
+ if (ACPI_FAILURE(status))
+ return -ENOMEM;
+
/*
* NOTE: The memory region for the data structures is used also in an
* operation region, which means ACPI has already reserved it. Therefore
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index fb4e6a7e..d639378e 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -339,18 +339,16 @@
struct page *page[1];
struct vm_area_struct *vma;
struct vm_area_struct *vmas[1];
+ unsigned int flags = 0;
int ret;
+ if (prot & IOMMU_WRITE)
+ flags |= FOLL_WRITE;
+
+ down_read(&mm->mmap_sem);
if (mm == current->mm) {
- ret = get_user_pages_longterm(vaddr, 1, !!(prot & IOMMU_WRITE),
- page, vmas);
+ ret = get_user_pages_longterm(vaddr, 1, flags, page, vmas);
} else {
- unsigned int flags = 0;
-
- if (prot & IOMMU_WRITE)
- flags |= FOLL_WRITE;
-
- down_read(&mm->mmap_sem);
ret = get_user_pages_remote(NULL, mm, vaddr, 1, flags, page,
vmas, NULL);
/*
@@ -364,8 +362,8 @@
ret = -EOPNOTSUPP;
put_page(page[0]);
}
- up_read(&mm->mmap_sem);
}
+ up_read(&mm->mmap_sem);
if (ret == 1) {
*pfn = page_to_pfn(page[0]);
diff --git a/drivers/video/backlight/as3711_bl.c b/drivers/video/backlight/as3711_bl.c
index 734a915..e55304d 100644
--- a/drivers/video/backlight/as3711_bl.c
+++ b/drivers/video/backlight/as3711_bl.c
@@ -262,10 +262,10 @@
static int as3711_backlight_parse_dt(struct device *dev)
{
struct as3711_bl_pdata *pdata = dev_get_platdata(dev);
- struct device_node *bl =
- of_find_node_by_name(dev->parent->of_node, "backlight"), *fb;
+ struct device_node *bl, *fb;
int ret;
+ bl = of_get_child_by_name(dev->parent->of_node, "backlight");
if (!bl) {
dev_dbg(dev, "backlight node not found\n");
return -ENODEV;
@@ -279,7 +279,7 @@
if (pdata->su1_max_uA <= 0)
ret = -EINVAL;
if (ret < 0)
- return ret;
+ goto err_put_bl;
}
fb = of_parse_phandle(bl, "su2-dev", 0);
@@ -292,7 +292,7 @@
if (pdata->su2_max_uA <= 0)
ret = -EINVAL;
if (ret < 0)
- return ret;
+ goto err_put_bl;
if (of_find_property(bl, "su2-feedback-voltage", NULL)) {
pdata->su2_feedback = AS3711_SU2_VOLTAGE;
@@ -314,8 +314,10 @@
pdata->su2_feedback = AS3711_SU2_CURR_AUTO;
count++;
}
- if (count != 1)
- return -EINVAL;
+ if (count != 1) {
+ ret = -EINVAL;
+ goto err_put_bl;
+ }
count = 0;
if (of_find_property(bl, "su2-fbprot-lx-sd4", NULL)) {
@@ -334,8 +336,10 @@
pdata->su2_fbprot = AS3711_SU2_GPIO4;
count++;
}
- if (count != 1)
- return -EINVAL;
+ if (count != 1) {
+ ret = -EINVAL;
+ goto err_put_bl;
+ }
count = 0;
if (of_find_property(bl, "su2-auto-curr1", NULL)) {
@@ -355,11 +359,20 @@
* At least one su2-auto-curr* must be specified iff
* AS3711_SU2_CURR_AUTO is used
*/
- if (!count ^ (pdata->su2_feedback != AS3711_SU2_CURR_AUTO))
- return -EINVAL;
+ if (!count ^ (pdata->su2_feedback != AS3711_SU2_CURR_AUTO)) {
+ ret = -EINVAL;
+ goto err_put_bl;
+ }
}
+ of_node_put(bl);
+
return 0;
+
+err_put_bl:
+ of_node_put(bl);
+
+ return ret;
}
static int as3711_backlight_probe(struct platform_device *pdev)
diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c
index 7b738d6..f3aa608 100644
--- a/drivers/video/backlight/max8925_bl.c
+++ b/drivers/video/backlight/max8925_bl.c
@@ -116,7 +116,7 @@
if (!pdata)
return;
- np = of_find_node_by_name(nproot, "backlight");
+ np = of_get_child_by_name(nproot, "backlight");
if (!np) {
dev_err(&pdev->dev, "failed to find backlight node\n");
return;
@@ -125,6 +125,8 @@
if (!of_property_read_u32(np, "maxim,max8925-dual-string", &val))
pdata->dual_string = val;
+ of_node_put(np);
+
pdev->dev.platform_data = pdata;
}
diff --git a/drivers/video/backlight/tps65217_bl.c b/drivers/video/backlight/tps65217_bl.c
index fd524ad..f45d0c9 100644
--- a/drivers/video/backlight/tps65217_bl.c
+++ b/drivers/video/backlight/tps65217_bl.c
@@ -184,11 +184,11 @@
tps65217_bl_parse_dt(struct platform_device *pdev)
{
struct tps65217 *tps = dev_get_drvdata(pdev->dev.parent);
- struct device_node *node = of_node_get(tps->dev->of_node);
+ struct device_node *node;
struct tps65217_bl_pdata *pdata, *err;
u32 val;
- node = of_find_node_by_name(node, "backlight");
+ node = of_get_child_by_name(tps->dev->of_node, "backlight");
if (!node)
return ERR_PTR(-ENODEV);
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index 04612f9..fb317ed 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -963,10 +963,13 @@
ops->cur_rotate = -1;
ops->cur_blink_jiffies = HZ / 5;
info->fbcon_par = ops;
- if (initial_rotation != -1)
- p->con_rotate = initial_rotation;
- else
+
+ p->con_rotate = initial_rotation;
+ if (p->con_rotate == -1)
+ p->con_rotate = info->fbcon_rotate_hint;
+ if (p->con_rotate == -1)
p->con_rotate = fbcon_platform_get_rotate(info);
+
set_blitting_type(vc, info);
if (info->fix.type != FB_TYPE_TEXT) {
@@ -1103,10 +1106,13 @@
ops = info->fbcon_par;
ops->cur_blink_jiffies = msecs_to_jiffies(vc->vc_cur_blink_ms);
- if (initial_rotation != -1)
- p->con_rotate = initial_rotation;
- else
+
+ p->con_rotate = initial_rotation;
+ if (p->con_rotate == -1)
+ p->con_rotate = info->fbcon_rotate_hint;
+ if (p->con_rotate == -1)
p->con_rotate = fbcon_platform_get_rotate(info);
+
set_blitting_type(vc, info);
cols = vc->vc_cols;
diff --git a/drivers/video/fbdev/core/fbsysfs.c b/drivers/video/fbdev/core/fbsysfs.c
index 15755ce..e31a182 100644
--- a/drivers/video/fbdev/core/fbsysfs.c
+++ b/drivers/video/fbdev/core/fbsysfs.c
@@ -58,6 +58,7 @@
info->par = p + fb_info_size;
info->device = dev;
+ info->fbcon_rotate_hint = -1;
#ifdef CONFIG_FB_BACKLIGHT
mutex_init(&info->bl_curve_mutex);
diff --git a/drivers/video/fbdev/uvesafb.c b/drivers/video/fbdev/uvesafb.c
index 73676eb..c592ca5 100644
--- a/drivers/video/fbdev/uvesafb.c
+++ b/drivers/video/fbdev/uvesafb.c
@@ -1044,7 +1044,8 @@
info->cmap.len || cmap->start < info->cmap.start)
return -EINVAL;
- entries = kmalloc(sizeof(*entries) * cmap->len, GFP_KERNEL);
+ entries = kmalloc_array(cmap->len, sizeof(*entries),
+ GFP_KERNEL);
if (!entries)
return -ENOMEM;
diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c
index 0c2a5a8..6f9e950 100644
--- a/drivers/w1/w1.c
+++ b/drivers/w1/w1.c
@@ -750,7 +750,7 @@
/* slave modules need to be loaded in a context with unlocked mutex */
mutex_unlock(&dev->mutex);
- request_module("w1-family-0x%02x", rn->family);
+ request_module("w1-family-0x%02X", rn->family);
mutex_lock(&dev->mutex);
spin_lock(&w1_flock);
diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 762378f..08e4af0 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -628,8 +628,6 @@
xen_irq_info_cleanup(info);
}
- BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
-
xen_free_irq(irq);
}
diff --git a/fs/afs/security.c b/fs/afs/security.c
index faca662..859096e 100644
--- a/fs/afs/security.c
+++ b/fs/afs/security.c
@@ -323,18 +323,14 @@
mask, access, S_ISDIR(inode->i_mode) ? "dir" : "file");
if (S_ISDIR(inode->i_mode)) {
- if (mask & MAY_EXEC) {
+ if (mask & (MAY_EXEC | MAY_READ | MAY_CHDIR)) {
if (!(access & AFS_ACE_LOOKUP))
goto permission_denied;
- } else if (mask & MAY_READ) {
- if (!(access & AFS_ACE_LOOKUP))
- goto permission_denied;
- } else if (mask & MAY_WRITE) {
+ }
+ if (mask & MAY_WRITE) {
if (!(access & (AFS_ACE_DELETE | /* rmdir, unlink, rename from */
AFS_ACE_INSERT))) /* create, mkdir, symlink, rename to */
goto permission_denied;
- } else {
- BUG();
}
} else {
if (!(access & AFS_ACE_LOOKUP))
diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
index 73b01e4..c0e3f91e 100644
--- a/fs/binfmt_elf.c
+++ b/fs/binfmt_elf.c
@@ -1235,9 +1235,8 @@
goto out_free_ph;
}
- len = ELF_PAGESTART(eppnt->p_filesz + eppnt->p_vaddr +
- ELF_MIN_ALIGN - 1);
- bss = eppnt->p_memsz + eppnt->p_vaddr;
+ len = ELF_PAGEALIGN(eppnt->p_filesz + eppnt->p_vaddr);
+ bss = ELF_PAGEALIGN(eppnt->p_memsz + eppnt->p_vaddr);
if (bss > len) {
error = vm_brk(len, bss - len);
if (error)
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 3a079009..f5b90dc 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -9769,6 +9769,7 @@
u64 new_idx = 0;
u64 root_objectid;
int ret;
+ int ret2;
bool root_log_pinned = false;
bool dest_log_pinned = false;
@@ -9965,7 +9966,8 @@
dest_log_pinned = false;
}
}
- ret = btrfs_end_transaction(trans);
+ ret2 = btrfs_end_transaction(trans);
+ ret = ret ? ret : ret2;
out_notrans:
if (new_ino == BTRFS_FIRST_FREE_OBJECTID)
up_read(&fs_info->subvol_sem);
diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index 33d6eb58..f29cdb1 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -1340,6 +1340,7 @@
/* one of these for every pending CIFS request to the server */
struct mid_q_entry {
struct list_head qhead; /* mids waiting on reply from this server */
+ struct kref refcount;
struct TCP_Server_Info *server; /* server corresponding to this mid */
__u64 mid; /* multiplex id */
__u32 pid; /* process id */
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 762d513..ccdb42f 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -76,6 +76,7 @@
struct TCP_Server_Info *server);
extern void DeleteMidQEntry(struct mid_q_entry *midEntry);
extern void cifs_delete_mid(struct mid_q_entry *mid);
+extern void cifs_mid_q_entry_release(struct mid_q_entry *midEntry);
extern void cifs_wake_up_task(struct mid_q_entry *mid);
extern int cifs_handle_standard(struct TCP_Server_Info *server,
struct mid_q_entry *mid);
diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c
index 7fd39ea..b5a4365 100644
--- a/fs/cifs/cifssmb.c
+++ b/fs/cifs/cifssmb.c
@@ -150,8 +150,14 @@
* greater than cifs socket timeout which is 7 seconds
*/
while (server->tcpStatus == CifsNeedReconnect) {
- wait_event_interruptible_timeout(server->response_q,
- (server->tcpStatus != CifsNeedReconnect), 10 * HZ);
+ rc = wait_event_interruptible_timeout(server->response_q,
+ (server->tcpStatus != CifsNeedReconnect),
+ 10 * HZ);
+ if (rc < 0) {
+ cifs_dbg(FYI, "%s: aborting reconnect due to a received"
+ " signal by the process\n", __func__);
+ return -ERESTARTSYS;
+ }
/* are we still trying to reconnect? */
if (server->tcpStatus != CifsNeedReconnect)
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index f7db2fe..fd24c72 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -889,6 +889,7 @@
continue;
server->total_read += length;
+ mid_entry = NULL;
if (server->ops->is_transform_hdr &&
server->ops->receive_transform &&
server->ops->is_transform_hdr(buf)) {
@@ -903,8 +904,11 @@
length = mid_entry->receive(server, mid_entry);
}
- if (length < 0)
+ if (length < 0) {
+ if (mid_entry)
+ cifs_mid_q_entry_release(mid_entry);
continue;
+ }
if (server->large_buf)
buf = server->bigbuf;
@@ -920,6 +924,8 @@
if (!mid_entry->multiRsp || mid_entry->multiEnd)
mid_entry->callback(mid_entry);
+
+ cifs_mid_q_entry_release(mid_entry);
} else if (server->ops->is_oplock_break &&
server->ops->is_oplock_break(buf, server)) {
cifs_dbg(FYI, "Received oplock break\n");
diff --git a/fs/cifs/smb1ops.c b/fs/cifs/smb1ops.c
index a723df3e..d8cd820 100644
--- a/fs/cifs/smb1ops.c
+++ b/fs/cifs/smb1ops.c
@@ -105,6 +105,7 @@
if (compare_mid(mid->mid, buf) &&
mid->mid_state == MID_REQUEST_SUBMITTED &&
le16_to_cpu(mid->command) == buf->Command) {
+ kref_get(&mid->refcount);
spin_unlock(&GlobalMid_Lock);
return mid;
}
diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index 36bc9a7..83267ac 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -202,6 +202,7 @@
if ((mid->mid == wire_mid) &&
(mid->mid_state == MID_REQUEST_SUBMITTED) &&
(mid->command == shdr->Command)) {
+ kref_get(&mid->refcount);
spin_unlock(&GlobalMid_Lock);
return mid;
}
@@ -635,6 +636,8 @@
rc = SMB2_set_ea(xid, tcon, fid.persistent_fid, fid.volatile_fid, ea,
len);
+ kfree(ea);
+
SMB2_close(xid, tcon, fid.persistent_fid, fid.volatile_fid);
return rc;
diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
index 5247b40..0480cd9 100644
--- a/fs/cifs/smb2pdu.c
+++ b/fs/cifs/smb2pdu.c
@@ -153,7 +153,7 @@
static int
smb2_reconnect(__le16 smb2_command, struct cifs_tcon *tcon)
{
- int rc = 0;
+ int rc;
struct nls_table *nls_codepage;
struct cifs_ses *ses;
struct TCP_Server_Info *server;
@@ -164,10 +164,10 @@
* for those three - in the calling routine.
*/
if (tcon == NULL)
- return rc;
+ return 0;
if (smb2_command == SMB2_TREE_CONNECT)
- return rc;
+ return 0;
if (tcon->tidStatus == CifsExiting) {
/*
@@ -210,8 +210,14 @@
return -EAGAIN;
}
- wait_event_interruptible_timeout(server->response_q,
- (server->tcpStatus != CifsNeedReconnect), 10 * HZ);
+ rc = wait_event_interruptible_timeout(server->response_q,
+ (server->tcpStatus != CifsNeedReconnect),
+ 10 * HZ);
+ if (rc < 0) {
+ cifs_dbg(FYI, "%s: aborting reconnect due to a received"
+ " signal by the process\n", __func__);
+ return -ERESTARTSYS;
+ }
/* are we still trying to reconnect? */
if (server->tcpStatus != CifsNeedReconnect)
@@ -229,7 +235,7 @@
}
if (!tcon->ses->need_reconnect && !tcon->need_reconnect)
- return rc;
+ return 0;
nls_codepage = load_nls_default();
@@ -332,7 +338,10 @@
return rc;
/* BB eventually switch this to SMB2 specific small buf size */
- *request_buf = cifs_small_buf_get();
+ if (smb2_command == SMB2_SET_INFO)
+ *request_buf = cifs_buf_get();
+ else
+ *request_buf = cifs_small_buf_get();
if (*request_buf == NULL) {
/* BB should we add a retry in here if not a writepage? */
return -ENOMEM;
@@ -3162,7 +3171,7 @@
}
rc = SendReceive2(xid, ses, iov, num, &resp_buftype, flags, &rsp_iov);
- cifs_small_buf_release(req);
+ cifs_buf_release(req);
rsp = (struct smb2_set_info_rsp *)rsp_iov.iov_base;
if (rc != 0)
diff --git a/fs/cifs/smb2transport.c b/fs/cifs/smb2transport.c
index bf49cb7..a41fc4a 100644
--- a/fs/cifs/smb2transport.c
+++ b/fs/cifs/smb2transport.c
@@ -548,6 +548,7 @@
temp = mempool_alloc(cifs_mid_poolp, GFP_NOFS);
memset(temp, 0, sizeof(struct mid_q_entry));
+ kref_init(&temp->refcount);
temp->mid = le64_to_cpu(shdr->MessageId);
temp->pid = current->pid;
temp->command = shdr->Command; /* Always LE */
diff --git a/fs/cifs/transport.c b/fs/cifs/transport.c
index 7efbab0..a10f51d 100644
--- a/fs/cifs/transport.c
+++ b/fs/cifs/transport.c
@@ -56,6 +56,7 @@
temp = mempool_alloc(cifs_mid_poolp, GFP_NOFS);
memset(temp, 0, sizeof(struct mid_q_entry));
+ kref_init(&temp->refcount);
temp->mid = get_mid(smb_buffer);
temp->pid = current->pid;
temp->command = cpu_to_le16(smb_buffer->Command);
@@ -77,6 +78,21 @@
return temp;
}
+static void _cifs_mid_q_entry_release(struct kref *refcount)
+{
+ struct mid_q_entry *mid = container_of(refcount, struct mid_q_entry,
+ refcount);
+
+ mempool_free(mid, cifs_mid_poolp);
+}
+
+void cifs_mid_q_entry_release(struct mid_q_entry *midEntry)
+{
+ spin_lock(&GlobalMid_Lock);
+ kref_put(&midEntry->refcount, _cifs_mid_q_entry_release);
+ spin_unlock(&GlobalMid_Lock);
+}
+
void
DeleteMidQEntry(struct mid_q_entry *midEntry)
{
@@ -105,7 +121,7 @@
}
}
#endif
- mempool_free(midEntry, cifs_mid_poolp);
+ cifs_mid_q_entry_release(midEntry);
}
void
diff --git a/fs/devpts/inode.c b/fs/devpts/inode.c
index e31d6ed..542364b 100644
--- a/fs/devpts/inode.c
+++ b/fs/devpts/inode.c
@@ -138,10 +138,6 @@
struct super_block *sb;
int err;
- /* Has the devpts filesystem already been found? */
- if (path->mnt->mnt_sb->s_magic == DEVPTS_SUPER_MAGIC)
- return 0;
-
/* Is a devpts filesystem at "pts" in the same directory? */
err = path_pts(path);
if (err)
@@ -159,22 +155,32 @@
struct vfsmount *devpts_mntget(struct file *filp, struct pts_fs_info *fsi)
{
struct path path;
- int err;
+ int err = 0;
path = filp->f_path;
path_get(&path);
- err = devpts_ptmx_path(&path);
+ /* Walk upward while the start point is a bind mount of
+ * a single file.
+ */
+ while (path.mnt->mnt_root == path.dentry)
+ if (follow_up(&path) == 0)
+ break;
+
+ /* devpts_ptmx_path() finds a devpts fs or returns an error. */
+ if ((path.mnt->mnt_sb->s_magic != DEVPTS_SUPER_MAGIC) ||
+ (DEVPTS_SB(path.mnt->mnt_sb) != fsi))
+ err = devpts_ptmx_path(&path);
dput(path.dentry);
- if (err) {
- mntput(path.mnt);
- return ERR_PTR(err);
+ if (!err) {
+ if (DEVPTS_SB(path.mnt->mnt_sb) == fsi)
+ return path.mnt;
+
+ err = -ENODEV;
}
- if (DEVPTS_SB(path.mnt->mnt_sb) != fsi) {
- mntput(path.mnt);
- return ERR_PTR(-ENODEV);
- }
- return path.mnt;
+
+ mntput(path.mnt);
+ return ERR_PTR(err);
}
struct pts_fs_info *devpts_acquire(struct file *filp)
@@ -182,15 +188,19 @@
struct pts_fs_info *result;
struct path path;
struct super_block *sb;
- int err;
path = filp->f_path;
path_get(&path);
- err = devpts_ptmx_path(&path);
- if (err) {
- result = ERR_PTR(err);
- goto out;
+ /* Has the devpts filesystem already been found? */
+ if (path.mnt->mnt_sb->s_magic != DEVPTS_SUPER_MAGIC) {
+ int err;
+
+ err = devpts_ptmx_path(&path);
+ if (err) {
+ result = ERR_PTR(err);
+ goto out;
+ }
}
/*
diff --git a/fs/esdfs/dentry.c b/fs/esdfs/dentry.c
index bfbadd5..8333dbd 100644
--- a/fs/esdfs/dentry.c
+++ b/fs/esdfs/dentry.c
@@ -90,12 +90,6 @@
return err;
}
-/* 1 = delete, 0 = cache */
-static int esdfs_d_delete(const struct dentry *d)
-{
- return 0;
-}
-
/* directly from fs/fat/namei_vfat.c */
static unsigned int __vfat_striptail_len(unsigned int len, const char *name)
{
@@ -165,7 +159,7 @@
const struct dentry_operations esdfs_dops = {
.d_revalidate = esdfs_d_revalidate,
- .d_delete = esdfs_d_delete,
+ .d_delete = always_delete_dentry,
.d_hash = esdfs_d_hash,
.d_compare = esdfs_d_compare,
.d_release = esdfs_d_release,
diff --git a/fs/ext2/super.c b/fs/ext2/super.c
index 1458706..726e680 100644
--- a/fs/ext2/super.c
+++ b/fs/ext2/super.c
@@ -953,8 +953,7 @@
blocksize = BLOCK_SIZE << le32_to_cpu(sbi->s_es->s_log_block_size);
if (sbi->s_mount_opt & EXT2_MOUNT_DAX) {
- err = bdev_dax_supported(sb, blocksize);
- if (err)
+ if (!bdev_dax_supported(sb->s_bdev, blocksize))
goto failed_mount;
}
diff --git a/fs/ext4/balloc.c b/fs/ext4/balloc.c
index 58db810..9c9eafd 100644
--- a/fs/ext4/balloc.c
+++ b/fs/ext4/balloc.c
@@ -184,7 +184,6 @@
unsigned int bit, bit_max;
struct ext4_sb_info *sbi = EXT4_SB(sb);
ext4_fsblk_t start, tmp;
- int flex_bg = 0;
struct ext4_group_info *grp;
J_ASSERT_BH(bh, buffer_locked(bh));
@@ -217,22 +216,19 @@
start = ext4_group_first_block_no(sb, block_group);
- if (ext4_has_feature_flex_bg(sb))
- flex_bg = 1;
-
/* Set bits for block and inode bitmaps, and inode table */
tmp = ext4_block_bitmap(sb, gdp);
- if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
+ if (ext4_block_in_group(sb, tmp, block_group))
ext4_set_bit(EXT4_B2C(sbi, tmp - start), bh->b_data);
tmp = ext4_inode_bitmap(sb, gdp);
- if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
+ if (ext4_block_in_group(sb, tmp, block_group))
ext4_set_bit(EXT4_B2C(sbi, tmp - start), bh->b_data);
tmp = ext4_inode_table(sb, gdp);
for (; tmp < ext4_inode_table(sb, gdp) +
sbi->s_itb_per_group; tmp++) {
- if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
+ if (ext4_block_in_group(sb, tmp, block_group))
ext4_set_bit(EXT4_B2C(sbi, tmp - start), bh->b_data);
}
@@ -455,7 +451,16 @@
goto verify;
}
ext4_lock_group(sb, block_group);
- if (desc->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
+ if (ext4_has_group_desc_csum(sb) &&
+ (desc->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT))) {
+ if (block_group == 0) {
+ ext4_unlock_group(sb, block_group);
+ unlock_buffer(bh);
+ ext4_error(sb, "Block bitmap for bg 0 marked "
+ "uninitialized");
+ err = -EFSCORRUPTED;
+ goto out;
+ }
err = ext4_init_block_bitmap(sb, bh, block_group, desc);
set_bitmap_uptodate(bh);
set_buffer_uptodate(bh);
diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h
index b7a2545..893e43e 100644
--- a/fs/ext4/ext4.h
+++ b/fs/ext4/ext4.h
@@ -1542,11 +1542,6 @@
static inline int ext4_valid_inum(struct super_block *sb, unsigned long ino)
{
return ino == EXT4_ROOT_INO ||
- ino == EXT4_USR_QUOTA_INO ||
- ino == EXT4_GRP_QUOTA_INO ||
- ino == EXT4_BOOT_LOADER_INO ||
- ino == EXT4_JOURNAL_INO ||
- ino == EXT4_RESIZE_INO ||
(ino >= EXT4_FIRST_INO(sb) &&
ino <= le32_to_cpu(EXT4_SB(sb)->s_es->s_inodes_count));
}
@@ -3050,9 +3045,6 @@
extern int ext4_inline_data_fiemap(struct inode *inode,
struct fiemap_extent_info *fieinfo,
int *has_inline, __u64 start, __u64 len);
-extern int ext4_try_to_evict_inline_data(handle_t *handle,
- struct inode *inode,
- int needed);
extern int ext4_inline_data_truncate(struct inode *inode, int *has_inline);
extern int ext4_convert_inline_data(struct inode *inode);
diff --git a/fs/ext4/ext4_extents.h b/fs/ext4/ext4_extents.h
index 8ecf84b..a284fb2 100644
--- a/fs/ext4/ext4_extents.h
+++ b/fs/ext4/ext4_extents.h
@@ -103,6 +103,7 @@
};
#define EXT4_EXT_MAGIC cpu_to_le16(0xf30a)
+#define EXT4_MAX_EXTENT_DEPTH 5
#define EXT4_EXTENT_TAIL_OFFSET(hdr) \
(sizeof(struct ext4_extent_header) + \
diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c
index 883e89a..5592b77 100644
--- a/fs/ext4/extents.c
+++ b/fs/ext4/extents.c
@@ -881,6 +881,12 @@
eh = ext_inode_hdr(inode);
depth = ext_depth(inode);
+ if (depth < 0 || depth > EXT4_MAX_EXTENT_DEPTH) {
+ EXT4_ERROR_INODE(inode, "inode has invalid extent depth: %d",
+ depth);
+ ret = -EFSCORRUPTED;
+ goto err;
+ }
if (path) {
ext4_ext_drop_refs(path);
diff --git a/fs/ext4/ialloc.c b/fs/ext4/ialloc.c
index f420124..95341bc 100644
--- a/fs/ext4/ialloc.c
+++ b/fs/ext4/ialloc.c
@@ -155,7 +155,16 @@
}
ext4_lock_group(sb, block_group);
- if (desc->bg_flags & cpu_to_le16(EXT4_BG_INODE_UNINIT)) {
+ if (ext4_has_group_desc_csum(sb) &&
+ (desc->bg_flags & cpu_to_le16(EXT4_BG_INODE_UNINIT))) {
+ if (block_group == 0) {
+ ext4_unlock_group(sb, block_group);
+ unlock_buffer(bh);
+ ext4_error(sb, "Inode bitmap for bg 0 marked "
+ "uninitialized");
+ err = -EFSCORRUPTED;
+ goto out;
+ }
memset(bh->b_data, 0, (EXT4_INODES_PER_GROUP(sb) + 7) / 8);
ext4_mark_bitmap_end(EXT4_INODES_PER_GROUP(sb),
sb->s_blocksize * 8, bh->b_data);
@@ -1000,7 +1009,8 @@
/* recheck and clear flag under lock if we still need to */
ext4_lock_group(sb, group);
- if (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
+ if (ext4_has_group_desc_csum(sb) &&
+ (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT))) {
gdp->bg_flags &= cpu_to_le16(~EXT4_BG_BLOCK_UNINIT);
ext4_free_group_clusters_set(sb, gdp,
ext4_free_clusters_after_init(sb, group, gdp));
diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c
index 8f5dc24..7d498f4 100644
--- a/fs/ext4/inline.c
+++ b/fs/ext4/inline.c
@@ -443,6 +443,7 @@
memset((void *)ext4_raw_inode(&is.iloc)->i_block,
0, EXT4_MIN_INLINE_DATA_SIZE);
+ memset(ei->i_data, 0, EXT4_MIN_INLINE_DATA_SIZE);
if (ext4_has_feature_extents(inode->i_sb)) {
if (S_ISDIR(inode->i_mode) ||
@@ -892,11 +893,11 @@
flags |= AOP_FLAG_NOFS;
if (ret == -ENOSPC) {
+ ext4_journal_stop(handle);
ret = ext4_da_convert_inline_data_to_extent(mapping,
inode,
flags,
fsdata);
- ext4_journal_stop(handle);
if (ret == -ENOSPC &&
ext4_should_retry_alloc(inode->i_sb, &retries))
goto retry_journal;
@@ -1864,42 +1865,6 @@
return (error < 0 ? error : 0);
}
-/*
- * Called during xattr set, and if we can sparse space 'needed',
- * just create the extent tree evict the data to the outer block.
- *
- * We use jbd2 instead of page cache to move data to the 1st block
- * so that the whole transaction can be committed as a whole and
- * the data isn't lost because of the delayed page cache write.
- */
-int ext4_try_to_evict_inline_data(handle_t *handle,
- struct inode *inode,
- int needed)
-{
- int error;
- struct ext4_xattr_entry *entry;
- struct ext4_inode *raw_inode;
- struct ext4_iloc iloc;
-
- error = ext4_get_inode_loc(inode, &iloc);
- if (error)
- return error;
-
- raw_inode = ext4_raw_inode(&iloc);
- entry = (struct ext4_xattr_entry *)((void *)raw_inode +
- EXT4_I(inode)->i_inline_off);
- if (EXT4_XATTR_LEN(entry->e_name_len) +
- EXT4_XATTR_SIZE(le32_to_cpu(entry->e_value_size)) < needed) {
- error = -ENOSPC;
- goto out;
- }
-
- error = ext4_convert_inline_data_nolock(handle, inode, &iloc);
-out:
- brelse(iloc.bh);
- return error;
-}
-
int ext4_inline_data_truncate(struct inode *inode, int *has_inline)
{
handle_t *handle;
diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
index bd6453e..c2efe4d 100644
--- a/fs/ext4/inode.c
+++ b/fs/ext4/inode.c
@@ -401,9 +401,9 @@
if (!ext4_data_block_valid(EXT4_SB(inode->i_sb), map->m_pblk,
map->m_len)) {
ext4_error_inode(inode, func, line, map->m_pblk,
- "lblock %lu mapped to illegal pblock "
+ "lblock %lu mapped to illegal pblock %llu "
"(length %d)", (unsigned long) map->m_lblk,
- map->m_len);
+ map->m_pblk, map->m_len);
return -EFSCORRUPTED;
}
return 0;
@@ -4455,7 +4455,8 @@
int inodes_per_block, inode_offset;
iloc->bh = NULL;
- if (!ext4_valid_inum(sb, inode->i_ino))
+ if (inode->i_ino < EXT4_ROOT_INO ||
+ inode->i_ino > le32_to_cpu(EXT4_SB(sb)->s_es->s_inodes_count))
return -EFSCORRUPTED;
iloc->block_group = (inode->i_ino - 1) / EXT4_INODES_PER_GROUP(sb);
diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index dcccb4d..8585a97 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -2456,7 +2456,8 @@
* initialize bb_free to be able to skip
* empty groups without initialization
*/
- if (desc->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
+ if (ext4_has_group_desc_csum(sb) &&
+ (desc->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT))) {
meta_group_info[i]->bb_free =
ext4_free_clusters_after_init(sb, group, desc);
} else {
@@ -3024,7 +3025,8 @@
#endif
ext4_set_bits(bitmap_bh->b_data, ac->ac_b_ex.fe_start,
ac->ac_b_ex.fe_len);
- if (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
+ if (ext4_has_group_desc_csum(sb) &&
+ (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT))) {
gdp->bg_flags &= cpu_to_le16(~EXT4_BG_BLOCK_UNINIT);
ext4_free_group_clusters_set(sb, gdp,
ext4_free_clusters_after_init(sb,
diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index ec74d06..fc32a67 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -2301,6 +2301,7 @@
struct ext4_sb_info *sbi = EXT4_SB(sb);
ext4_fsblk_t first_block = le32_to_cpu(sbi->s_es->s_first_data_block);
ext4_fsblk_t last_block;
+ ext4_fsblk_t last_bg_block = sb_block + ext4_bg_num_gdb(sb, 0) + 1;
ext4_fsblk_t block_bitmap;
ext4_fsblk_t inode_bitmap;
ext4_fsblk_t inode_table;
@@ -2333,6 +2334,14 @@
if (!sb_rdonly(sb))
return 0;
}
+ if (block_bitmap >= sb_block + 1 &&
+ block_bitmap <= last_bg_block) {
+ ext4_msg(sb, KERN_ERR, "ext4_check_descriptors: "
+ "Block bitmap for group %u overlaps "
+ "block group descriptors", i);
+ if (!sb_rdonly(sb))
+ return 0;
+ }
if (block_bitmap < first_block || block_bitmap > last_block) {
ext4_msg(sb, KERN_ERR, "ext4_check_descriptors: "
"Block bitmap for group %u not in group "
@@ -2347,6 +2356,14 @@
if (!sb_rdonly(sb))
return 0;
}
+ if (inode_bitmap >= sb_block + 1 &&
+ inode_bitmap <= last_bg_block) {
+ ext4_msg(sb, KERN_ERR, "ext4_check_descriptors: "
+ "Inode bitmap for group %u overlaps "
+ "block group descriptors", i);
+ if (!sb_rdonly(sb))
+ return 0;
+ }
if (inode_bitmap < first_block || inode_bitmap > last_block) {
ext4_msg(sb, KERN_ERR, "ext4_check_descriptors: "
"Inode bitmap for group %u not in group "
@@ -2361,6 +2378,14 @@
if (!sb_rdonly(sb))
return 0;
}
+ if (inode_table >= sb_block + 1 &&
+ inode_table <= last_bg_block) {
+ ext4_msg(sb, KERN_ERR, "ext4_check_descriptors: "
+ "Inode table for group %u overlaps "
+ "block group descriptors", i);
+ if (!sb_rdonly(sb))
+ return 0;
+ }
if (inode_table < first_block ||
inode_table + sbi->s_itb_per_group - 1 > last_block) {
ext4_msg(sb, KERN_ERR, "ext4_check_descriptors: "
@@ -3070,13 +3095,22 @@
ext4_group_t group, ngroups = EXT4_SB(sb)->s_groups_count;
struct ext4_group_desc *gdp = NULL;
+ if (!ext4_has_group_desc_csum(sb))
+ return ngroups;
+
for (group = 0; group < ngroups; group++) {
gdp = ext4_get_group_desc(sb, group, NULL);
if (!gdp)
continue;
- if (!(gdp->bg_flags & cpu_to_le16(EXT4_BG_INODE_ZEROED)))
+ if (gdp->bg_flags & cpu_to_le16(EXT4_BG_INODE_ZEROED))
+ continue;
+ if (group != 0)
break;
+ ext4_error(sb, "Inode table for bg 0 marked as "
+ "needing zeroing");
+ if (sb_rdonly(sb))
+ return ngroups;
}
return group;
@@ -3715,6 +3749,13 @@
le32_to_cpu(es->s_log_block_size));
goto failed_mount;
}
+ if (le32_to_cpu(es->s_log_cluster_size) >
+ (EXT4_MAX_CLUSTER_LOG_SIZE - EXT4_MIN_BLOCK_LOG_SIZE)) {
+ ext4_msg(sb, KERN_ERR,
+ "Invalid log cluster size: %u",
+ le32_to_cpu(es->s_log_cluster_size));
+ goto failed_mount;
+ }
if (le16_to_cpu(sbi->s_es->s_reserved_gdt_blocks) > (blocksize / 4)) {
ext4_msg(sb, KERN_ERR,
@@ -3729,8 +3770,7 @@
" that may contain inline data");
goto failed_mount;
}
- err = bdev_dax_supported(sb, blocksize);
- if (err)
+ if (!bdev_dax_supported(sb->s_bdev, blocksize))
goto failed_mount;
}
@@ -3777,6 +3817,11 @@
} else {
sbi->s_inode_size = le16_to_cpu(es->s_inode_size);
sbi->s_first_ino = le32_to_cpu(es->s_first_ino);
+ if (sbi->s_first_ino < EXT4_GOOD_OLD_FIRST_INO) {
+ ext4_msg(sb, KERN_ERR, "invalid first ino: %u",
+ sbi->s_first_ino);
+ goto failed_mount;
+ }
if ((sbi->s_inode_size < EXT4_GOOD_OLD_INODE_SIZE) ||
(!is_power_of_2(sbi->s_inode_size)) ||
(sbi->s_inode_size > blocksize)) {
@@ -3853,13 +3898,6 @@
"block size (%d)", clustersize, blocksize);
goto failed_mount;
}
- if (le32_to_cpu(es->s_log_cluster_size) >
- (EXT4_MAX_CLUSTER_LOG_SIZE - EXT4_MIN_BLOCK_LOG_SIZE)) {
- ext4_msg(sb, KERN_ERR,
- "Invalid log cluster size: %u",
- le32_to_cpu(es->s_log_cluster_size));
- goto failed_mount;
- }
sbi->s_cluster_bits = le32_to_cpu(es->s_log_cluster_size) -
le32_to_cpu(es->s_log_block_size);
sbi->s_clusters_per_group =
@@ -3880,10 +3918,10 @@
}
} else {
if (clustersize != blocksize) {
- ext4_warning(sb, "fragment/cluster size (%d) != "
- "block size (%d)", clustersize,
- blocksize);
- clustersize = blocksize;
+ ext4_msg(sb, KERN_ERR,
+ "fragment/cluster size (%d) != "
+ "block size (%d)", clustersize, blocksize);
+ goto failed_mount;
}
if (sbi->s_blocks_per_group > blocksize * 8) {
ext4_msg(sb, KERN_ERR,
@@ -3937,6 +3975,13 @@
ext4_blocks_count(es));
goto failed_mount;
}
+ if ((es->s_first_data_block == 0) && (es->s_log_block_size == 0) &&
+ (sbi->s_cluster_ratio == 1)) {
+ ext4_msg(sb, KERN_WARNING, "bad geometry: first data "
+ "block is 0 with a 1k block and cluster size");
+ goto failed_mount;
+ }
+
blocks_count = (ext4_blocks_count(es) -
le32_to_cpu(es->s_first_data_block) +
EXT4_BLOCKS_PER_GROUP(sb) - 1);
@@ -3972,6 +4017,14 @@
ret = -ENOMEM;
goto failed_mount;
}
+ if (((u64)sbi->s_groups_count * sbi->s_inodes_per_group) !=
+ le32_to_cpu(es->s_inodes_count)) {
+ ext4_msg(sb, KERN_ERR, "inodes count not valid: %u vs %llu",
+ le32_to_cpu(es->s_inodes_count),
+ ((u64)sbi->s_groups_count * sbi->s_inodes_per_group));
+ ret = -EINVAL;
+ goto failed_mount;
+ }
bgl_lock_init(sbi->s_blockgroup_lock);
@@ -4700,6 +4753,14 @@
if (!sbh || block_device_ejected(sb))
return error;
+
+ /*
+ * The superblock bh should be mapped, but it might not be if the
+ * device was hot-removed. Not much we can do but fail the I/O.
+ */
+ if (!buffer_mapped(sbh))
+ return error;
+
/*
* If the file system is mounted read-only, don't update the
* superblock write time. This avoids updating the superblock
diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c
index ed1cf24..c7c8c16 100644
--- a/fs/ext4/xattr.c
+++ b/fs/ext4/xattr.c
@@ -229,12 +229,12 @@
{
int error = -EFSCORRUPTED;
- if (buffer_verified(bh))
- return 0;
-
if (BHDR(bh)->h_magic != cpu_to_le32(EXT4_XATTR_MAGIC) ||
BHDR(bh)->h_blocks != cpu_to_le32(1))
goto errout;
+ if (buffer_verified(bh))
+ return 0;
+
error = -EFSBADCRC;
if (!ext4_xattr_block_csum_verify(inode, bh))
goto errout;
@@ -1559,7 +1559,7 @@
handle_t *handle, struct inode *inode,
bool is_block)
{
- struct ext4_xattr_entry *last;
+ struct ext4_xattr_entry *last, *next;
struct ext4_xattr_entry *here = s->here;
size_t min_offs = s->end - s->base, name_len = strlen(i->name);
int in_inode = i->in_inode;
@@ -1594,7 +1594,13 @@
/* Compute min_offs and last. */
last = s->first;
- for (; !IS_LAST_ENTRY(last); last = EXT4_XATTR_NEXT(last)) {
+ for (; !IS_LAST_ENTRY(last); last = next) {
+ next = EXT4_XATTR_NEXT(last);
+ if ((void *)next >= s->end) {
+ EXT4_ERROR_INODE(inode, "corrupted xattr entries");
+ ret = -EFSCORRUPTED;
+ goto out;
+ }
if (!last->e_value_inum && last->e_value_size) {
size_t offs = le16_to_cpu(last->e_value_offs);
if (offs < min_offs)
@@ -2205,23 +2211,8 @@
if (EXT4_I(inode)->i_extra_isize == 0)
return -ENOSPC;
error = ext4_xattr_set_entry(i, s, handle, inode, false /* is_block */);
- if (error) {
- if (error == -ENOSPC &&
- ext4_has_inline_data(inode)) {
- error = ext4_try_to_evict_inline_data(handle, inode,
- EXT4_XATTR_LEN(strlen(i->name) +
- EXT4_XATTR_SIZE(i->value_len)));
- if (error)
- return error;
- error = ext4_xattr_ibody_find(inode, i, is);
- if (error)
- return error;
- error = ext4_xattr_set_entry(i, s, handle, inode,
- false /* is_block */);
- }
- if (error)
- return error;
- }
+ if (error)
+ return error;
header = IHDR(inode, ext4_raw_inode(&is->iloc));
if (!IS_LAST_ENTRY(s->first)) {
header->h_magic = cpu_to_le32(EXT4_XATTR_MAGIC);
@@ -2650,6 +2641,11 @@
last = IFIRST(header);
/* Find the entry best suited to be pushed into EA block */
for (; !IS_LAST_ENTRY(last); last = EXT4_XATTR_NEXT(last)) {
+ /* never move system.data out of the inode */
+ if ((last->e_name_len == 4) &&
+ (last->e_name_index == EXT4_XATTR_INDEX_SYSTEM) &&
+ !memcmp(last->e_name, "data", 4))
+ continue;
total_size = EXT4_XATTR_LEN(last->e_name_len);
if (!last->e_value_inum)
total_size += EXT4_XATTR_SIZE(
diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h
index 4b4a72f..3b34004 100644
--- a/fs/f2fs/f2fs.h
+++ b/fs/f2fs/f2fs.h
@@ -1471,18 +1471,6 @@
}
/*
- * Check whether the given nid is within node id range.
- */
-static inline int check_nid_range(struct f2fs_sb_info *sbi, nid_t nid)
-{
- if (unlikely(nid < F2FS_ROOT_INO(sbi)))
- return -EINVAL;
- if (unlikely(nid >= NM_I(sbi)->max_nid))
- return -EINVAL;
- return 0;
-}
-
-/*
* Check whether the inode has blocks or not
*/
static inline int F2FS_HAS_BLOCKS(struct inode *inode)
@@ -2470,6 +2458,7 @@
struct dnode_of_data;
struct node_info;
+int check_nid_range(struct f2fs_sb_info *sbi, nid_t nid);
bool available_free_memory(struct f2fs_sb_info *sbi, int type);
int need_dentry_mark(struct f2fs_sb_info *sbi, nid_t nid);
bool is_checkpointed_node(struct f2fs_sb_info *sbi, nid_t nid);
diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c
index 29c5f79..72c6a9e 100644
--- a/fs/f2fs/file.c
+++ b/fs/f2fs/file.c
@@ -2694,11 +2694,16 @@
inode_lock(inode);
ret = generic_write_checks(iocb, from);
if (ret > 0) {
+ bool preallocated = false;
+ size_t target_size = 0;
int err;
if (iov_iter_fault_in_readable(from, iov_iter_count(from)))
set_inode_flag(inode, FI_NO_PREALLOC);
+ preallocated = true;
+ target_size = iocb->ki_pos + iov_iter_count(from);
+
err = f2fs_preallocate_blocks(iocb, from);
if (err) {
clear_inode_flag(inode, FI_NO_PREALLOC);
@@ -2710,6 +2715,10 @@
blk_finish_plug(&plug);
clear_inode_flag(inode, FI_NO_PREALLOC);
+ /* if we couldn't write data, we should deallocate blocks. */
+ if (preallocated && i_size_read(inode) < target_size)
+ f2fs_truncate(inode);
+
if (ret > 0)
f2fs_update_iostat(F2FS_I_SB(inode), APP_WRITE_IO, ret);
}
diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c
index 50c88e37..259b0aa 100644
--- a/fs/f2fs/inode.c
+++ b/fs/f2fs/inode.c
@@ -188,12 +188,8 @@
projid_t i_projid;
/* Check if ino is within scope */
- if (check_nid_range(sbi, inode->i_ino)) {
- f2fs_msg(inode->i_sb, KERN_ERR, "bad inode number: %lu",
- (unsigned long) inode->i_ino);
- WARN_ON(1);
+ if (check_nid_range(sbi, inode->i_ino))
return -EINVAL;
- }
node_page = get_node_page(sbi, inode->i_ino);
if (IS_ERR(node_page))
@@ -538,8 +534,11 @@
alloc_nid_failed(sbi, inode->i_ino);
clear_inode_flag(inode, FI_FREE_NID);
} else {
- f2fs_bug_on(sbi, err &&
- !exist_written_data(sbi, inode->i_ino, ORPHAN_INO));
+ /*
+ * If xattr nid is corrupted, we can reach out error condition,
+ * err & !exist_written_data(sbi, inode->i_ino, ORPHAN_INO)).
+ * In that case, check_nid_range() is enough to give a clue.
+ */
}
out_clear:
fscrypt_put_encryption_info(inode, NULL);
diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c
index fca8783..f623da2 100644
--- a/fs/f2fs/node.c
+++ b/fs/f2fs/node.c
@@ -29,6 +29,21 @@
static struct kmem_cache *free_nid_slab;
static struct kmem_cache *nat_entry_set_slab;
+/*
+ * Check whether the given nid is within node id range.
+ */
+int check_nid_range(struct f2fs_sb_info *sbi, nid_t nid)
+{
+ if (unlikely(nid < F2FS_ROOT_INO(sbi) || nid >= NM_I(sbi)->max_nid)) {
+ set_sbi_flag(sbi, SBI_NEED_FSCK);
+ f2fs_msg(sbi->sb, KERN_WARNING,
+ "%s: out-of-range nid=%x, run fsck to fix.",
+ __func__, nid);
+ return -EINVAL;
+ }
+ return 0;
+}
+
bool available_free_memory(struct f2fs_sb_info *sbi, int type)
{
struct f2fs_nm_info *nm_i = NM_I(sbi);
@@ -1122,7 +1137,8 @@
if (!nid)
return;
- f2fs_bug_on(sbi, check_nid_range(sbi, nid));
+ if (check_nid_range(sbi, nid))
+ return;
rcu_read_lock();
apage = radix_tree_lookup(&NODE_MAPPING(sbi)->page_tree, nid);
@@ -1146,7 +1162,8 @@
if (!nid)
return ERR_PTR(-ENOENT);
- f2fs_bug_on(sbi, check_nid_range(sbi, nid));
+ if (check_nid_range(sbi, nid))
+ return ERR_PTR(-EINVAL);
repeat:
page = f2fs_grab_cache_page(NODE_MAPPING(sbi), nid, false);
if (!page)
diff --git a/fs/fuse/control.c b/fs/fuse/control.c
index b9ea99c..5be0339 100644
--- a/fs/fuse/control.c
+++ b/fs/fuse/control.c
@@ -211,10 +211,11 @@
if (!dentry)
return NULL;
- fc->ctl_dentry[fc->ctl_ndents++] = dentry;
inode = new_inode(fuse_control_sb);
- if (!inode)
+ if (!inode) {
+ dput(dentry);
return NULL;
+ }
inode->i_ino = get_next_ino();
inode->i_mode = mode;
@@ -228,6 +229,9 @@
set_nlink(inode, nlink);
inode->i_private = fc;
d_add(dentry, inode);
+
+ fc->ctl_dentry[fc->ctl_ndents++] = dentry;
+
return dentry;
}
@@ -284,7 +288,10 @@
for (i = fc->ctl_ndents - 1; i >= 0; i--) {
struct dentry *dentry = fc->ctl_dentry[i];
d_inode(dentry)->i_private = NULL;
- d_drop(dentry);
+ if (!i) {
+ /* Get rid of submounts: */
+ d_invalidate(dentry);
+ }
dput(dentry);
}
drop_nlink(d_inode(fuse_control_sb->s_root));
diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 0324850..c158e34 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -383,8 +383,7 @@
if (!fc->blocked && waitqueue_active(&fc->blocked_waitq))
wake_up(&fc->blocked_waitq);
- if (fc->num_background == fc->congestion_threshold &&
- fc->connected && fc->sb) {
+ if (fc->num_background == fc->congestion_threshold && fc->sb) {
clear_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC);
clear_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC);
}
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index cebd108..556053b 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -1675,8 +1675,19 @@
return err;
if (attr->ia_valid & ATTR_OPEN) {
- if (fc->atomic_o_trunc)
+ /* This is coming from open(..., ... | O_TRUNC); */
+ WARN_ON(!(attr->ia_valid & ATTR_SIZE));
+ WARN_ON(attr->ia_size != 0);
+ if (fc->atomic_o_trunc) {
+ /*
+ * No need to send request to userspace, since actual
+ * truncation has already been done by OPEN. But still
+ * need to truncate page cache.
+ */
+ i_size_write(inode, 0);
+ truncate_pagecache(inode, 0);
return 0;
+ }
file = NULL;
}
diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index 94a745a..a13ecef 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -1176,6 +1176,7 @@
fuse_dev_free(fud);
err_put_conn:
fuse_conn_put(fc);
+ sb->s_fs_info = NULL;
err_fput:
fput(file);
err:
diff --git a/fs/inode.c b/fs/inode.c
index f9497e6..602e28f 100644
--- a/fs/inode.c
+++ b/fs/inode.c
@@ -177,6 +177,7 @@
mapping->a_ops = &empty_aops;
mapping->host = inode;
mapping->flags = 0;
+ mapping->wb_err = 0;
atomic_set(&mapping->i_mmap_writable, 0);
mapping_set_gfp_mask(mapping, GFP_HIGHUSER_MOVABLE);
mapping->private_data = NULL;
@@ -2005,8 +2006,14 @@
inode->i_uid = current_fsuid();
if (dir && dir->i_mode & S_ISGID) {
inode->i_gid = dir->i_gid;
+
+ /* Directories are special, and always inherit S_ISGID */
if (S_ISDIR(mode))
mode |= S_ISGID;
+ else if ((mode & (S_ISGID | S_IXGRP)) == (S_ISGID | S_IXGRP) &&
+ !in_group_p(inode->i_gid) &&
+ !capable_wrt_inode_uidgid(dir, CAP_FSETID))
+ mode &= ~S_ISGID;
} else
inode->i_gid = current_fsgid();
inode->i_mode = mode;
diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c
index 07793e2..e42736c 100644
--- a/fs/jbd2/transaction.c
+++ b/fs/jbd2/transaction.c
@@ -1366,6 +1366,13 @@
if (jh->b_transaction == transaction &&
jh->b_jlist != BJ_Metadata) {
jbd_lock_bh_state(bh);
+ if (jh->b_transaction == transaction &&
+ jh->b_jlist != BJ_Metadata)
+ pr_err("JBD2: assertion failure: h_type=%u "
+ "h_line_no=%u block_no=%llu jlist=%u\n",
+ handle->h_type, handle->h_line_no,
+ (unsigned long long) bh->b_blocknr,
+ jh->b_jlist);
J_ASSERT_JH(jh, jh->b_transaction != transaction ||
jh->b_jlist == BJ_Metadata);
jbd_unlock_bh_state(bh);
@@ -1385,11 +1392,11 @@
* of the transaction. This needs to be done
* once a transaction -bzzz
*/
- jh->b_modified = 1;
if (handle->h_buffer_credits <= 0) {
ret = -ENOSPC;
goto out_unlock_bh;
}
+ jh->b_modified = 1;
handle->h_buffer_credits--;
}
diff --git a/fs/nfs/callback_proc.c b/fs/nfs/callback_proc.c
index 19151f6..516b224 100644
--- a/fs/nfs/callback_proc.c
+++ b/fs/nfs/callback_proc.c
@@ -420,11 +420,8 @@
return htonl(NFS4ERR_SEQ_FALSE_RETRY);
}
- /* Wraparound */
- if (unlikely(slot->seq_nr == 0xFFFFFFFFU)) {
- if (args->csa_sequenceid == 1)
- return htonl(NFS4_OK);
- } else if (likely(args->csa_sequenceid == slot->seq_nr + 1))
+ /* Note: wraparound relies on seq_nr being of type u32 */
+ if (likely(args->csa_sequenceid == slot->seq_nr + 1))
return htonl(NFS4_OK);
/* Misordered request */
diff --git a/fs/nfs/nfs4idmap.c b/fs/nfs/nfs4idmap.c
index 22dc30a..b6f9d84b 100644
--- a/fs/nfs/nfs4idmap.c
+++ b/fs/nfs/nfs4idmap.c
@@ -343,7 +343,7 @@
int id_len;
ssize_t ret;
- id_len = snprintf(id_str, sizeof(id_str), "%u", id);
+ id_len = nfs_map_numeric_to_string(id, id_str, sizeof(id_str));
ret = nfs_idmap_get_key(id_str, id_len, type, buf, buflen, idmap);
if (ret < 0)
return -EINVAL;
@@ -627,7 +627,8 @@
if (strcmp(upcall->im_name, im->im_name) != 0)
break;
/* Note: here we store the NUL terminator too */
- len = sprintf(id_str, "%d", im->im_id) + 1;
+ len = 1 + nfs_map_numeric_to_string(im->im_id, id_str,
+ sizeof(id_str));
ret = nfs_idmap_instantiate(key, authkey, id_str, len);
break;
case IDMAP_CONV_IDTONAME:
diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index 8ff98bb..928bbc3 100644
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -750,7 +750,7 @@
* The slot id we used was probably retired. Try again
* using a different slot id.
*/
- if (slot->seq_nr < slot->table->target_highest_slotid)
+ if (slot->slot_nr < slot->table->target_highest_slotid)
goto session_recover;
goto retry_nowait;
case -NFS4ERR_SEQ_MISORDERED:
diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
index df2b884..f6588cc 100644
--- a/fs/nfsd/nfs4xdr.c
+++ b/fs/nfsd/nfs4xdr.c
@@ -3645,7 +3645,8 @@
nfserr = nfserr_resource;
goto err_no_verf;
}
- maxcount = min_t(u32, readdir->rd_maxcount, INT_MAX);
+ maxcount = svc_max_payload(resp->rqstp);
+ maxcount = min_t(u32, readdir->rd_maxcount, maxcount);
/*
* Note the rfc defines rd_maxcount as the size of the
* READDIR4resok structure, which includes the verifier above
@@ -3659,7 +3660,7 @@
/* RFC 3530 14.2.24 allows us to ignore dircount when it's 0: */
if (!readdir->rd_dircount)
- readdir->rd_dircount = INT_MAX;
+ readdir->rd_dircount = svc_max_payload(resp->rqstp);
readdir->xdr = xdr;
readdir->rd_maxcount = maxcount;
diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 5294e70..4da7def 100644
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -912,7 +912,7 @@
mss->private_hugetlb >> 10,
mss->swap >> 10,
(unsigned long)(mss->swap_pss >> (10 + PSS_SHIFT)),
- (unsigned long)(mss->pss >> (10 + PSS_SHIFT)));
+ (unsigned long)(mss->pss_locked >> (10 + PSS_SHIFT)));
if (!rollup_mode) {
arch_show_smap(m, vma);
diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c
index 04c4ec6..8ae1cd8 100644
--- a/fs/ubifs/journal.c
+++ b/fs/ubifs/journal.c
@@ -1283,10 +1283,11 @@
int *new_len)
{
void *buf;
- int err, dlen, compr_type, out_len, old_dlen;
+ int err, compr_type;
+ u32 dlen, out_len, old_dlen;
out_len = le32_to_cpu(dn->size);
- buf = kmalloc(out_len * WORST_COMPR_FACTOR, GFP_NOFS);
+ buf = kmalloc_array(out_len, WORST_COMPR_FACTOR, GFP_NOFS);
if (!buf)
return -ENOMEM;
diff --git a/fs/udf/directory.c b/fs/udf/directory.c
index 7aa48bd..a636b3b 100644
--- a/fs/udf/directory.c
+++ b/fs/udf/directory.c
@@ -151,6 +151,9 @@
sizeof(struct fileIdentDesc));
}
}
+ /* Got last entry outside of dir size - fs is corrupted! */
+ if (*nf_pos > dir->i_size)
+ return NULL;
return fi;
}
diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c
index 5811bb0..16d44aa 100644
--- a/fs/userfaultfd.c
+++ b/fs/userfaultfd.c
@@ -220,24 +220,26 @@
unsigned long reason)
{
struct mm_struct *mm = ctx->mm;
- pte_t *pte;
+ pte_t *ptep, pte;
bool ret = true;
VM_BUG_ON(!rwsem_is_locked(&mm->mmap_sem));
- pte = huge_pte_offset(mm, address, vma_mmu_pagesize(vma));
- if (!pte)
+ ptep = huge_pte_offset(mm, address, vma_mmu_pagesize(vma));
+
+ if (!ptep)
goto out;
ret = false;
+ pte = huge_ptep_get(ptep);
/*
* Lockless access: we're in a wait_event so it's ok if it
* changes under us.
*/
- if (huge_pte_none(*pte))
+ if (huge_pte_none(pte))
ret = true;
- if (!huge_pte_write(*pte) && (reason & VM_UFFD_WP))
+ if (!huge_pte_write(pte) && (reason & VM_UFFD_WP))
ret = true;
out:
return ret;
diff --git a/fs/xfs/xfs_ioctl.c b/fs/xfs/xfs_ioctl.c
index aa75389..79a9a0d 100644
--- a/fs/xfs/xfs_ioctl.c
+++ b/fs/xfs/xfs_ioctl.c
@@ -1101,7 +1101,8 @@
if (fa->fsx_xflags & FS_XFLAG_DAX) {
if (!(S_ISREG(inode->i_mode) || S_ISDIR(inode->i_mode)))
return -EINVAL;
- if (bdev_dax_supported(sb, sb->s_blocksize) < 0)
+ if (!bdev_dax_supported(xfs_find_bdev_for_inode(VFS_I(ip)),
+ sb->s_blocksize))
return -EINVAL;
}
diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c
index f24e5b6..1daa965 100644
--- a/fs/xfs/xfs_iops.c
+++ b/fs/xfs/xfs_iops.c
@@ -1184,6 +1184,30 @@
.update_time = xfs_vn_update_time,
};
+/* Figure out if this file actually supports DAX. */
+static bool
+xfs_inode_supports_dax(
+ struct xfs_inode *ip)
+{
+ struct xfs_mount *mp = ip->i_mount;
+
+ /* Only supported on non-reflinked files. */
+ if (!S_ISREG(VFS_I(ip)->i_mode) || xfs_is_reflink_inode(ip))
+ return false;
+
+ /* DAX mount option or DAX iflag must be set. */
+ if (!(mp->m_flags & XFS_MOUNT_DAX) &&
+ !(ip->i_d.di_flags2 & XFS_DIFLAG2_DAX))
+ return false;
+
+ /* Block size must match page size */
+ if (mp->m_sb.sb_blocksize != PAGE_SIZE)
+ return false;
+
+ /* Device has to support DAX too. */
+ return xfs_find_daxdev_for_inode(VFS_I(ip)) != NULL;
+}
+
STATIC void
xfs_diflags_to_iflags(
struct inode *inode,
@@ -1202,11 +1226,7 @@
inode->i_flags |= S_SYNC;
if (flags & XFS_DIFLAG_NOATIME)
inode->i_flags |= S_NOATIME;
- if (S_ISREG(inode->i_mode) &&
- ip->i_mount->m_sb.sb_blocksize == PAGE_SIZE &&
- !xfs_is_reflink_inode(ip) &&
- (ip->i_mount->m_flags & XFS_MOUNT_DAX ||
- ip->i_d.di_flags2 & XFS_DIFLAG2_DAX))
+ if (xfs_inode_supports_dax(ip))
inode->i_flags |= S_DAX;
}
diff --git a/fs/xfs/xfs_super.c b/fs/xfs/xfs_super.c
index f663022..0b0282d 100644
--- a/fs/xfs/xfs_super.c
+++ b/fs/xfs/xfs_super.c
@@ -1640,11 +1640,17 @@
sb->s_flags |= SB_I_VERSION;
if (mp->m_flags & XFS_MOUNT_DAX) {
+ bool rtdev_is_dax = false, datadev_is_dax;
+
xfs_warn(mp,
"DAX enabled. Warning: EXPERIMENTAL, use at your own risk");
- error = bdev_dax_supported(sb, sb->s_blocksize);
- if (error) {
+ datadev_is_dax = bdev_dax_supported(mp->m_ddev_targp->bt_bdev,
+ sb->s_blocksize);
+ if (mp->m_rtdev_targp)
+ rtdev_is_dax = bdev_dax_supported(
+ mp->m_rtdev_targp->bt_bdev, sb->s_blocksize);
+ if (!rtdev_is_dax && !datadev_is_dax) {
xfs_alert(mp,
"DAX unsupported by block device. Turning off DAX.");
mp->m_flags &= ~XFS_MOUNT_DAX;
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 1d7281d..8094fad 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -134,6 +134,15 @@
* &drm_pending_vblank_event pointer to clean up private events.
*/
struct drm_pending_vblank_event *event;
+
+ /**
+ * @abort_completion:
+ *
+ * A flag that's set after drm_atomic_helper_setup_commit takes a second
+ * reference for the completion of $drm_crtc_state.event. It's used by
+ * the free code to remove the second reference if commit fails.
+ */
+ bool abort_completion;
};
struct __drm_planes_state {
@@ -189,12 +198,40 @@
struct drm_private_state *state);
};
+/**
+ * struct drm_private_obj - base struct for driver private atomic object
+ *
+ * A driver private object is initialized by calling
+ * drm_atomic_private_obj_init() and cleaned up by calling
+ * drm_atomic_private_obj_fini().
+ *
+ * Currently only tracks the state update functions and the opaque driver
+ * private state itself, but in the future might also track which
+ * &drm_modeset_lock is required to duplicate and update this object's state.
+ */
struct drm_private_obj {
+ /**
+ * @state: Current atomic state for this driver private object.
+ */
struct drm_private_state *state;
+ /**
+ * @funcs:
+ *
+ * Functions to manipulate the state of this driver private object, see
+ * &drm_private_state_funcs.
+ */
const struct drm_private_state_funcs *funcs;
};
+/**
+ * struct drm_private_state - base struct for driver private object state
+ * @state: backpointer to global drm_atomic_state
+ *
+ * Currently only contains a backpointer to the overall atomic update, but in
+ * the future also might hold synchronization information similar to e.g.
+ * &drm_crtc.commit.
+ */
struct drm_private_state {
struct drm_atomic_state *state;
};
@@ -218,6 +255,10 @@
* @num_private_objs: size of the @private_objs array
* @private_objs: pointer to array of private object pointers
* @acquire_ctx: acquire context for this atomic modeset state update
+ *
+ * States are added to an atomic update by calling drm_atomic_get_crtc_state(),
+ * drm_atomic_get_plane_state(), drm_atomic_get_connector_state(), or for
+ * private state structures, drm_atomic_get_private_obj_state().
*/
struct drm_atomic_state {
struct kref ref;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index b476aad..499c9ceb 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -177,6 +177,35 @@
};
/**
+ * enum drm_panel_orientation - panel_orientation info for &drm_display_info
+ *
+ * This enum is used to track the (LCD) panel orientation. There are no
+ * separate #defines for the uapi!
+ *
+ * @DRM_MODE_PANEL_ORIENTATION_UNKNOWN: The drm driver has not provided any
+ * panel orientation information (normal
+ * for non panels) in this case the "panel
+ * orientation" connector prop will not be
+ * attached.
+ * @DRM_MODE_PANEL_ORIENTATION_NORMAL: The top side of the panel matches the
+ * top side of the device's casing.
+ * @DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP: The top side of the panel matches the
+ * bottom side of the device's casing, iow
+ * the panel is mounted upside-down.
+ * @DRM_MODE_PANEL_ORIENTATION_LEFT_UP: The left side of the panel matches the
+ * top side of the device's casing.
+ * @DRM_MODE_PANEL_ORIENTATION_RIGHT_UP: The right side of the panel matches the
+ * top side of the device's casing.
+ */
+enum drm_panel_orientation {
+ DRM_MODE_PANEL_ORIENTATION_UNKNOWN = -1,
+ DRM_MODE_PANEL_ORIENTATION_NORMAL = 0,
+ DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP,
+ DRM_MODE_PANEL_ORIENTATION_LEFT_UP,
+ DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
+/**
* struct drm_display_info - runtime data about the connected sink
*
* Describes a given display (e.g. CRT or flat panel) and its limitations. For
@@ -224,6 +253,15 @@
#define DRM_COLOR_FORMAT_YCRCB420 (1<<3)
/**
+ * @panel_orientation: Read only connector property for built-in panels,
+ * indicating the orientation of the panel vs the device's casing.
+ * drm_connector_init() sets this to DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
+ * When not UNKNOWN this gets used by the drm_fb_helpers to rotate the
+ * fb to compensate and gets exported as prop to userspace.
+ */
+ int panel_orientation;
+
+ /**
* @color_formats: HDMI Color formats, selects between RGB and YCrCb
* modes. Used DRM_COLOR_FORMAT\_ defines, which are _not_ the same ones
* as used to describe the pixel format in framebuffers, and also don't
@@ -1046,6 +1084,8 @@
const struct edid *edid);
void drm_mode_connector_set_link_status_property(struct drm_connector *connector,
uint64_t link_status);
+int drm_connector_init_panel_orientation_property(
+ struct drm_connector *connector, int width, int height);
/**
* struct drm_tile_group - Tile group metadata
diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
index 65def43..d532f88a 100644
--- a/include/drm/drm_fb_cma_helper.h
+++ b/include/drm/drm_fb_cma_helper.h
@@ -16,6 +16,13 @@
struct drm_plane;
struct drm_plane_state;
+int drm_fb_cma_fbdev_init_with_funcs(struct drm_device *dev,
+ unsigned int preferred_bpp, unsigned int max_conn_count,
+ const struct drm_framebuffer_funcs *funcs);
+int drm_fb_cma_fbdev_init(struct drm_device *dev, unsigned int preferred_bpp,
+ unsigned int max_conn_count);
+void drm_fb_cma_fbdev_fini(struct drm_device *dev);
+
struct drm_fbdev_cma *drm_fbdev_cma_init_with_funcs(struct drm_device *dev,
unsigned int preferred_bpp, unsigned int max_conn_count,
const struct drm_framebuffer_funcs *funcs);
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index 877e5b3..b069433 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -33,6 +33,7 @@
struct drm_fb_helper;
#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
#include <linux/kgdb.h>
enum mode_set_atomic {
@@ -48,6 +49,7 @@
struct drm_mode_set mode_set;
struct drm_display_mode *desired_mode;
int x, y;
+ int rotation;
};
/**
@@ -159,6 +161,13 @@
int connector_count;
int connector_info_alloc_count;
/**
+ * @sw_rotations:
+ * Bitmask of all rotations requested for panel-orientation which
+ * could not be handled in hardware. If only one bit is set
+ * fbdev->fbcon_rotate_hint gets set to the requested rotation.
+ */
+ int sw_rotations;
+ /**
* @connector_info:
*
* Array of per-connector information. Do not iterate directly, but use
@@ -267,6 +276,7 @@
void drm_fb_helper_deferred_io(struct fb_info *info,
struct list_head *pagelist);
+int drm_fb_helper_defio_init(struct drm_fb_helper *fb_helper);
ssize_t drm_fb_helper_sys_read(struct fb_info *info, char __user *buf,
size_t count, loff_t *ppos);
@@ -311,6 +321,13 @@
int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,
struct drm_connector *connector);
+int drm_fb_helper_fbdev_setup(struct drm_device *dev,
+ struct drm_fb_helper *fb_helper,
+ const struct drm_fb_helper_funcs *funcs,
+ unsigned int preferred_bpp,
+ unsigned int max_conn_count);
+void drm_fb_helper_fbdev_teardown(struct drm_device *dev);
+
void drm_fb_helper_lastclose(struct drm_device *dev);
void drm_fb_helper_output_poll_changed(struct drm_device *dev);
#else
@@ -324,11 +341,17 @@
struct drm_fb_helper *helper,
int max_conn)
{
+ /* So drivers can use it to free the struct */
+ helper->dev = dev;
+ dev->fb_helper = helper;
+
return 0;
}
static inline void drm_fb_helper_fini(struct drm_fb_helper *helper)
{
+ if (helper && helper->dev)
+ helper->dev->fb_helper = NULL;
}
static inline int drm_fb_helper_blank(int blank, struct fb_info *info)
@@ -401,6 +424,11 @@
{
}
+static inline int drm_fb_helper_defio_init(struct drm_fb_helper *fb_helper)
+{
+ return -ENODEV;
+}
+
static inline ssize_t drm_fb_helper_sys_read(struct fb_info *info,
char __user *buf, size_t count,
loff_t *ppos)
@@ -510,6 +538,24 @@
return 0;
}
+static inline int
+drm_fb_helper_fbdev_setup(struct drm_device *dev,
+ struct drm_fb_helper *fb_helper,
+ const struct drm_fb_helper_funcs *funcs,
+ unsigned int preferred_bpp,
+ unsigned int max_conn_count)
+{
+ /* So drivers can use it to free the struct */
+ dev->fb_helper = fb_helper;
+
+ return 0;
+}
+
+static inline void drm_fb_helper_fbdev_teardown(struct drm_device *dev)
+{
+ dev->fb_helper = NULL;
+}
+
static inline void drm_fb_helper_lastclose(struct drm_device *dev)
{
}
diff --git a/include/drm/drm_framebuffer.h b/include/drm/drm_framebuffer.h
index dccb897..c50502c 100644
--- a/include/drm/drm_framebuffer.h
+++ b/include/drm/drm_framebuffer.h
@@ -121,6 +121,12 @@
* @base: base modeset object structure, contains the reference count.
*/
struct drm_mode_object base;
+
+ /**
+ * @comm: Name of the process allocating the fb, used for fb dumping.
+ */
+ char comm[TASK_COMM_LEN];
+
/**
* @format: framebuffer format information
*/
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index aef5aa51..2cb6f02 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -269,6 +269,9 @@
* state easily. If this hook is implemented, drivers must also
* implement @atomic_state_clear and @atomic_state_free.
*
+ * Subclassing of &drm_atomic_state is deprecated in favour of using
+ * &drm_private_state and &drm_private_obj.
+ *
* RETURNS:
*
* A new &drm_atomic_state on success or NULL on failure.
@@ -290,6 +293,9 @@
*
* Drivers that implement this must call drm_atomic_state_default_clear()
* to clear common state.
+ *
+ * Subclassing of &drm_atomic_state is deprecated in favour of using
+ * &drm_private_state and &drm_private_obj.
*/
void (*atomic_state_clear)(struct drm_atomic_state *state);
@@ -302,6 +308,9 @@
*
* Drivers that implement this must call
* drm_atomic_state_default_release() to release common resources.
+ *
+ * Subclassing of &drm_atomic_state is deprecated in favour of using
+ * &drm_private_state and &drm_private_obj.
*/
void (*atomic_state_free)(struct drm_atomic_state *state);
};
@@ -751,6 +760,13 @@
*/
struct drm_property *non_desktop_property;
+ /**
+ * @panel_orientation_property: Optional connector property indicating
+ * how the lcd-panel is mounted inside the casing (e.g. normal or
+ * upside-down).
+ */
+ struct drm_property *panel_orientation_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
@@ -776,6 +792,15 @@
/* cursor size */
uint32_t cursor_width, cursor_height;
+ /**
+ * @suspend_state:
+ *
+ * Atomic state when suspended.
+ * Set by drm_mode_config_helper_suspend() and cleared by
+ * drm_mode_config_helper_resume().
+ */
+ struct drm_atomic_state *suspend_state;
+
const struct drm_mode_config_helper_funcs *helper_private;
};
diff --git a/include/drm/drm_modeset_helper.h b/include/drm/drm_modeset_helper.h
index cb0ec92..efa337f 100644
--- a/include/drm/drm_modeset_helper.h
+++ b/include/drm/drm_modeset_helper.h
@@ -34,4 +34,7 @@
int drm_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
const struct drm_crtc_funcs *funcs);
+int drm_mode_config_helper_suspend(struct drm_device *dev);
+int drm_mode_config_helper_resume(struct drm_device *dev);
+
#endif
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 5f9932e..2a4a42e 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -80,13 +80,13 @@
__printf(2, 3)
void drm_printf(struct drm_printer *p, const char *f, ...);
+__printf(2, 0)
/**
* drm_vprintf - print to a &drm_printer stream
* @p: the &drm_printer
* @fmt: format string
* @va: the va_list
*/
-__printf(2, 0)
static inline void
drm_vprintf(struct drm_printer *p, const char *fmt, va_list *va)
{
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index 9e8ba90..3980602 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -33,36 +33,31 @@
/**
* struct drm_syncobj - sync object.
*
- * This structure defines a generic sync object which wraps a dma fence.
+ * This structure defines a generic sync object which wraps a &dma_fence.
*/
struct drm_syncobj {
/**
- * @refcount:
- *
- * Reference count of this object.
+ * @refcount: Reference count of this object.
*/
struct kref refcount;
/**
* @fence:
* NULL or a pointer to the fence bound to this object.
*
- * This field should not be used directly. Use drm_syncobj_fence_get
- * and drm_syncobj_replace_fence instead.
+ * This field should not be used directly. Use drm_syncobj_fence_get()
+ * and drm_syncobj_replace_fence() instead.
*/
struct dma_fence __rcu *fence;
/**
- * @cb_list:
- * List of callbacks to call when the fence gets replaced
+ * @cb_list: List of callbacks to call when the &fence gets replaced.
*/
struct list_head cb_list;
/**
- * @lock:
- * locks cb_list and write-locks fence.
+ * @lock: Protects &cb_list and write-locks &fence.
*/
spinlock_t lock;
/**
- * @file:
- * a file backing for this syncobj.
+ * @file: A file backing for this syncobj.
*/
struct file *file;
};
@@ -73,7 +68,7 @@
/**
* struct drm_syncobj_cb - callback for drm_syncobj_add_callback
* @node: used by drm_syncob_add_callback to append this struct to
- * syncobj::cb_list
+ * &drm_syncobj.cb_list
* @func: drm_syncobj_func_t to call
*
* This struct will be initialized by drm_syncobj_add_callback, additional
@@ -92,7 +87,7 @@
* drm_syncobj_get - acquire a syncobj reference
* @obj: sync object
*
- * This acquires additional reference to @obj. It is illegal to call this
+ * This acquires an additional reference to @obj. It is illegal to call this
* without already holding a reference. No locks required.
*/
static inline void
@@ -111,6 +106,17 @@
kref_put(&obj->refcount, drm_syncobj_free);
}
+/**
+ * drm_syncobj_fence_get - get a reference to a fence in a sync object
+ * @syncobj: sync object.
+ *
+ * This acquires additional reference to &drm_syncobj.fence contained in @obj,
+ * if not NULL. It is illegal to call this without already holding a reference.
+ * No locks required.
+ *
+ * Returns:
+ * Either the fence of @obj or NULL if there's none.
+ */
static inline struct dma_fence *
drm_syncobj_fence_get(struct drm_syncobj *syncobj)
{
diff --git a/include/drm/drm_utils.h b/include/drm/drm_utils.h
new file mode 100644
index 0000000..a803988
--- /dev/null
+++ b/include/drm/drm_utils.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Function prototypes for misc. drm utility functions.
+ * Specifically this file is for function prototypes for functions which
+ * may also be used outside of drm code (e.g. in fbdev drivers).
+ *
+ * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef __DRM_UTILS_H__
+#define __DRM_UTILS_H__
+
+int drm_get_panel_orientation_quirk(int width, int height);
+
+#endif
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
new file mode 100644
index 0000000..dfd54fb
--- /dev/null
+++ b/include/drm/gpu_scheduler.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _DRM_GPU_SCHEDULER_H_
+#define _DRM_GPU_SCHEDULER_H_
+
+#include <drm/spsc_queue.h>
+#include <linux/dma-fence.h>
+
+struct drm_gpu_scheduler;
+struct drm_sched_rq;
+
+enum drm_sched_priority {
+ DRM_SCHED_PRIORITY_MIN,
+ DRM_SCHED_PRIORITY_LOW = DRM_SCHED_PRIORITY_MIN,
+ DRM_SCHED_PRIORITY_NORMAL,
+ DRM_SCHED_PRIORITY_HIGH_SW,
+ DRM_SCHED_PRIORITY_HIGH_HW,
+ DRM_SCHED_PRIORITY_KERNEL,
+ DRM_SCHED_PRIORITY_MAX,
+ DRM_SCHED_PRIORITY_INVALID = -1,
+ DRM_SCHED_PRIORITY_UNSET = -2
+};
+
+/**
+ * A scheduler entity is a wrapper around a job queue or a group
+ * of other entities. Entities take turns emitting jobs from their
+ * job queues to corresponding hardware ring based on scheduling
+ * policy.
+*/
+struct drm_sched_entity {
+ struct list_head list;
+ struct drm_sched_rq *rq;
+ spinlock_t rq_lock;
+ struct drm_gpu_scheduler *sched;
+
+ spinlock_t queue_lock;
+ struct spsc_queue job_queue;
+
+ atomic_t fence_seq;
+ uint64_t fence_context;
+
+ struct dma_fence *dependency;
+ struct dma_fence_cb cb;
+ atomic_t *guilty; /* points to ctx's guilty */
+};
+
+/**
+ * Run queue is a set of entities scheduling command submissions for
+ * one specific ring. It implements the scheduling policy that selects
+ * the next entity to emit commands from.
+*/
+struct drm_sched_rq {
+ spinlock_t lock;
+ struct list_head entities;
+ struct drm_sched_entity *current_entity;
+};
+
+struct drm_sched_fence {
+ struct dma_fence scheduled;
+ struct dma_fence finished;
+ struct dma_fence_cb cb;
+ struct dma_fence *parent;
+ struct drm_gpu_scheduler *sched;
+ spinlock_t lock;
+ void *owner;
+};
+
+struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f);
+
+struct drm_sched_job {
+ struct spsc_node queue_node;
+ struct drm_gpu_scheduler *sched;
+ struct drm_sched_fence *s_fence;
+ struct dma_fence_cb finish_cb;
+ struct work_struct finish_work;
+ struct list_head node;
+ struct delayed_work work_tdr;
+ uint64_t id;
+ atomic_t karma;
+ enum drm_sched_priority s_priority;
+};
+
+static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
+ int threshold)
+{
+ return (s_job && atomic_inc_return(&s_job->karma) > threshold);
+}
+
+/**
+ * Define the backend operations called by the scheduler,
+ * these functions should be implemented in driver side
+*/
+struct drm_sched_backend_ops {
+ struct dma_fence *(*dependency)(struct drm_sched_job *sched_job,
+ struct drm_sched_entity *s_entity);
+ struct dma_fence *(*run_job)(struct drm_sched_job *sched_job);
+ void (*timedout_job)(struct drm_sched_job *sched_job);
+ void (*free_job)(struct drm_sched_job *sched_job);
+};
+
+/**
+ * One scheduler is implemented for each hardware ring
+*/
+struct drm_gpu_scheduler {
+ const struct drm_sched_backend_ops *ops;
+ uint32_t hw_submission_limit;
+ long timeout;
+ const char *name;
+ struct drm_sched_rq sched_rq[DRM_SCHED_PRIORITY_MAX];
+ wait_queue_head_t wake_up_worker;
+ wait_queue_head_t job_scheduled;
+ atomic_t hw_rq_count;
+ atomic64_t job_id_count;
+ struct task_struct *thread;
+ struct list_head ring_mirror_list;
+ spinlock_t job_list_lock;
+ int hang_limit;
+};
+
+int drm_sched_init(struct drm_gpu_scheduler *sched,
+ const struct drm_sched_backend_ops *ops,
+ uint32_t hw_submission, unsigned hang_limit, long timeout,
+ const char *name);
+void drm_sched_fini(struct drm_gpu_scheduler *sched);
+
+int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity,
+ struct drm_sched_rq *rq,
+ uint32_t jobs, atomic_t *guilty);
+void drm_sched_entity_fini(struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity);
+void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
+ struct drm_sched_entity *entity);
+void drm_sched_entity_set_rq(struct drm_sched_entity *entity,
+ struct drm_sched_rq *rq);
+
+struct drm_sched_fence *drm_sched_fence_create(
+ struct drm_sched_entity *s_entity, void *owner);
+void drm_sched_fence_scheduled(struct drm_sched_fence *fence);
+void drm_sched_fence_finished(struct drm_sched_fence *fence);
+int drm_sched_job_init(struct drm_sched_job *job,
+ struct drm_gpu_scheduler *sched,
+ struct drm_sched_entity *entity,
+ void *owner);
+void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched,
+ struct drm_sched_job *job);
+void drm_sched_job_recovery(struct drm_gpu_scheduler *sched);
+bool drm_sched_dependency_optimized(struct dma_fence* fence,
+ struct drm_sched_entity *entity);
+void drm_sched_job_kickout(struct drm_sched_job *s_job);
+
+#endif
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/include/drm/gpu_scheduler_trace.h
similarity index 88%
rename from drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h
rename to include/drm/gpu_scheduler_trace.h
index b42a789..0789e8d 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h
+++ b/include/drm/gpu_scheduler_trace.h
@@ -31,14 +31,14 @@
#include <drm/drmP.h>
#undef TRACE_SYSTEM
-#define TRACE_SYSTEM gpu_sched
-#define TRACE_INCLUDE_FILE gpu_sched_trace
+#define TRACE_SYSTEM gpu_scheduler
+#define TRACE_INCLUDE_FILE gpu_scheduler_trace
-TRACE_EVENT(amd_sched_job,
- TP_PROTO(struct amd_sched_job *sched_job, struct amd_sched_entity *entity),
+TRACE_EVENT(drm_sched_job,
+ TP_PROTO(struct drm_sched_job *sched_job, struct drm_sched_entity *entity),
TP_ARGS(sched_job, entity),
TP_STRUCT__entry(
- __field(struct amd_sched_entity *, entity)
+ __field(struct drm_sched_entity *, entity)
__field(struct dma_fence *, fence)
__field(const char *, name)
__field(uint64_t, id)
@@ -61,8 +61,8 @@
__entry->job_count, __entry->hw_job_count)
);
-TRACE_EVENT(amd_sched_process_job,
- TP_PROTO(struct amd_sched_fence *fence),
+TRACE_EVENT(drm_sched_process_job,
+ TP_PROTO(struct drm_sched_fence *fence),
TP_ARGS(fence),
TP_STRUCT__entry(
__field(struct dma_fence *, fence)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 4e1b274..c9e5a66 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -36,6 +36,9 @@
extern bool i915_gpu_busy(void);
extern bool i915_gpu_turbo_disable(void);
+/* Exported from arch/x86/kernel/early-quirks.c */
+extern struct resource intel_graphics_stolen_res;
+
/*
* The Bridge device's PCI config space has information about the
* fb aperture size and the amount of pre-reserved memory.
diff --git a/drivers/gpu/drm/amd/scheduler/spsc_queue.h b/include/drm/spsc_queue.h
similarity index 95%
rename from drivers/gpu/drm/amd/scheduler/spsc_queue.h
rename to include/drm/spsc_queue.h
index 5902f35..125f096 100644
--- a/drivers/gpu/drm/amd/scheduler/spsc_queue.h
+++ b/include/drm/spsc_queue.h
@@ -21,10 +21,11 @@
*
*/
-#ifndef AMD_SCHEDULER_SPSC_QUEUE_H_
-#define AMD_SCHEDULER_SPSC_QUEUE_H_
+#ifndef DRM_SCHEDULER_SPSC_QUEUE_H_
+#define DRM_SCHEDULER_SPSC_QUEUE_H_
#include <linux/atomic.h>
+#include <linux/preempt.h>
/** SPSC lockless queue */
@@ -118,4 +119,4 @@
-#endif /* AMD_SCHEDULER_SPSC_QUEUE_H_ */
+#endif /* DRM_SCHEDULER_SPSC_QUEUE_H_ */
diff --git a/include/drm/tinydrm/mipi-dbi.h b/include/drm/tinydrm/mipi-dbi.h
index 83346dd..5d0e82b 100644
--- a/include/drm/tinydrm/mipi-dbi.h
+++ b/include/drm/tinydrm/mipi-dbi.h
@@ -72,10 +72,12 @@
void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe);
void mipi_dbi_hw_reset(struct mipi_dbi *mipi);
bool mipi_dbi_display_is_on(struct mipi_dbi *mipi);
+u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len);
int mipi_dbi_command_read(struct mipi_dbi *mipi, u8 cmd, u8 *val);
int mipi_dbi_command_buf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len);
-
+int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
+ struct drm_clip_rect *clip, bool swap);
/**
* mipi_dbi_command - MIPI DCS command with optional parameter(s)
* @mipi: MIPI structure
diff --git a/include/drm/tinydrm/tinydrm.h b/include/drm/tinydrm/tinydrm.h
index 4238289..07a9a11 100644
--- a/include/drm/tinydrm/tinydrm.h
+++ b/include/drm/tinydrm/tinydrm.h
@@ -19,16 +19,12 @@
* @drm: DRM device
* @pipe: Display pipe structure
* @dirty_lock: Serializes framebuffer flushing
- * @fbdev_cma: CMA fbdev structure
- * @suspend_state: Atomic state when suspended
* @fb_funcs: Framebuffer functions used when creating framebuffers
*/
struct tinydrm_device {
struct drm_device *drm;
struct drm_simple_display_pipe pipe;
struct mutex dirty_lock;
- struct drm_fbdev_cma *fbdev_cma;
- struct drm_atomic_state *suspend_state;
const struct drm_framebuffer_funcs *fb_funcs;
};
@@ -82,7 +78,6 @@
.type = DRM_MODE_TYPE_DRIVER, \
.clock = 1 /* pass validation */
-void tinydrm_lastclose(struct drm_device *drm);
void tinydrm_gem_cma_free_object(struct drm_gem_object *gem_obj);
struct drm_gem_object *
tinydrm_gem_cma_prime_import_sg_table(struct drm_device *drm,
@@ -93,8 +88,6 @@
struct drm_driver *driver);
int devm_tinydrm_register(struct tinydrm_device *tdev);
void tinydrm_shutdown(struct tinydrm_device *tdev);
-int tinydrm_suspend(struct tinydrm_device *tdev);
-int tinydrm_resume(struct tinydrm_device *tdev);
void tinydrm_display_pipe_update(struct drm_simple_display_pipe *pipe,
struct drm_plane_state *old_state);
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index fa07be1..2cd025c 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -224,7 +224,6 @@
*/
uint64_t offset; /* GPU address space is independent of CPU word size */
- uint32_t cur_placement;
struct sg_table *sg;
@@ -260,6 +259,25 @@
};
/**
+ * struct ttm_operation_ctx
+ *
+ * @interruptible: Sleep interruptible if sleeping.
+ * @no_wait_gpu: Return immediately if the GPU is busy.
+ * @allow_reserved_eviction: Allow eviction of reserved BOs.
+ * @resv: Reservation object to allow reserved evictions with.
+ *
+ * Context for TTM operations like changing buffer placement or general memory
+ * allocation.
+ */
+struct ttm_operation_ctx {
+ bool interruptible;
+ bool no_wait_gpu;
+ bool allow_reserved_eviction;
+ struct reservation_object *resv;
+ uint64_t bytes_moved;
+};
+
+/**
* ttm_bo_reference - reference a struct ttm_buffer_object
*
* @bo: The buffer object.
@@ -288,8 +306,7 @@
* Returns -EBUSY if no_wait is true and the buffer is busy.
* Returns -ERESTARTSYS if interrupted by a signal.
*/
-extern int ttm_bo_wait(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait);
+int ttm_bo_wait(struct ttm_buffer_object *bo, bool interruptible, bool no_wait);
/**
* ttm_bo_mem_compat - Check if proposed placement is compatible with a bo
@@ -300,17 +317,15 @@
*
* Returns true if the placement is compatible
*/
-extern bool ttm_bo_mem_compat(struct ttm_placement *placement,
- struct ttm_mem_reg *mem,
- uint32_t *new_flags);
+bool ttm_bo_mem_compat(struct ttm_placement *placement, struct ttm_mem_reg *mem,
+ uint32_t *new_flags);
/**
* ttm_bo_validate
*
* @bo: The buffer object.
* @placement: Proposed placement for the buffer object.
- * @interruptible: Sleep interruptible if sleeping.
- * @no_wait_gpu: Return immediately if the GPU is busy.
+ * @ctx: validation parameters.
*
* Changes placement and caching policy of the buffer object
* according proposed placement.
@@ -320,10 +335,9 @@
* -EBUSY if no_wait is true and buffer busy.
* -ERESTARTSYS if interrupted by a signal.
*/
-extern int ttm_bo_validate(struct ttm_buffer_object *bo,
- struct ttm_placement *placement,
- bool interruptible,
- bool no_wait_gpu);
+int ttm_bo_validate(struct ttm_buffer_object *bo,
+ struct ttm_placement *placement,
+ struct ttm_operation_ctx *ctx);
/**
* ttm_bo_unref
@@ -332,7 +346,7 @@
*
* Unreference and clear a pointer to a buffer object.
*/
-extern void ttm_bo_unref(struct ttm_buffer_object **bo);
+void ttm_bo_unref(struct ttm_buffer_object **bo);
/**
* ttm_bo_add_to_lru
@@ -344,7 +358,7 @@
* This function must be called with struct ttm_bo_global::lru_lock held, and
* is typically called immediately prior to unreserving a bo.
*/
-extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
+void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
/**
* ttm_bo_del_from_lru
@@ -356,7 +370,7 @@
* and is usually called just immediately after the bo has been reserved to
* avoid recursive reservation from lru lists.
*/
-extern void ttm_bo_del_from_lru(struct ttm_buffer_object *bo);
+void ttm_bo_del_from_lru(struct ttm_buffer_object *bo);
/**
* ttm_bo_move_to_lru_tail
@@ -367,7 +381,7 @@
* object. This function must be called with struct ttm_bo_global::lru_lock
* held, and is used to make a BO less likely to be considered for eviction.
*/
-extern void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo);
+void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo);
/**
* ttm_bo_lock_delayed_workqueue
@@ -376,15 +390,14 @@
* Returns
* True if the workqueue was queued at the time
*/
-extern int ttm_bo_lock_delayed_workqueue(struct ttm_bo_device *bdev);
+int ttm_bo_lock_delayed_workqueue(struct ttm_bo_device *bdev);
/**
* ttm_bo_unlock_delayed_workqueue
*
* Allows the delayed workqueue to run.
*/
-extern void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev,
- int resched);
+void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, int resched);
/**
* ttm_bo_eviction_valuable
@@ -411,8 +424,7 @@
* -EBUSY if the buffer is busy and no_wait is true.
* -ERESTARTSYS if interrupted by a signal.
*/
-extern int
-ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait);
+int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait);
/**
* ttm_bo_synccpu_write_release:
@@ -421,7 +433,7 @@
*
* Releases a synccpu lock.
*/
-extern void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo);
+void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo);
/**
* ttm_bo_acc_size
@@ -448,8 +460,7 @@
* @type: Requested type of buffer object.
* @flags: Initial placement flags.
* @page_alignment: Data alignment in pages.
- * @interruptible: If needing to sleep to wait for GPU resources,
- * sleep interruptible.
+ * @ctx: TTM operation context for memory allocation.
* @persistent_swap_storage: Usually the swap storage is deleted for buffers
* pinned in physical memory. If this behaviour is not desired, this member
* holds a pointer to a persistent shmem object. Typically, this would
@@ -480,18 +491,18 @@
* -ERESTARTSYS: Interrupted by signal while sleeping waiting for resources.
*/
-extern int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
- struct ttm_buffer_object *bo,
- unsigned long size,
- enum ttm_bo_type type,
- struct ttm_placement *placement,
- uint32_t page_alignment,
- bool interrubtible,
- struct file *persistent_swap_storage,
- size_t acc_size,
- struct sg_table *sg,
- struct reservation_object *resv,
- void (*destroy) (struct ttm_buffer_object *));
+int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
+ struct ttm_buffer_object *bo,
+ unsigned long size,
+ enum ttm_bo_type type,
+ struct ttm_placement *placement,
+ uint32_t page_alignment,
+ struct ttm_operation_ctx *ctx,
+ struct file *persistent_swap_storage,
+ size_t acc_size,
+ struct sg_table *sg,
+ struct reservation_object *resv,
+ void (*destroy) (struct ttm_buffer_object *));
/**
* ttm_bo_init
@@ -531,19 +542,13 @@
* -EINVAL: Invalid placement flags.
* -ERESTARTSYS: Interrupted by signal while sleeping waiting for resources.
*/
-
-extern int ttm_bo_init(struct ttm_bo_device *bdev,
- struct ttm_buffer_object *bo,
- unsigned long size,
- enum ttm_bo_type type,
- struct ttm_placement *placement,
- uint32_t page_alignment,
- bool interrubtible,
- struct file *persistent_swap_storage,
- size_t acc_size,
- struct sg_table *sg,
- struct reservation_object *resv,
- void (*destroy) (struct ttm_buffer_object *));
+int ttm_bo_init(struct ttm_bo_device *bdev, struct ttm_buffer_object *bo,
+ unsigned long size, enum ttm_bo_type type,
+ struct ttm_placement *placement,
+ uint32_t page_alignment, bool interrubtible,
+ struct file *persistent_swap_storage, size_t acc_size,
+ struct sg_table *sg, struct reservation_object *resv,
+ void (*destroy) (struct ttm_buffer_object *));
/**
* ttm_bo_create
@@ -569,15 +574,11 @@
* -EINVAL: Invalid placement flags.
* -ERESTARTSYS: Interrupted by signal while waiting for resources.
*/
-
-extern int ttm_bo_create(struct ttm_bo_device *bdev,
- unsigned long size,
- enum ttm_bo_type type,
- struct ttm_placement *placement,
- uint32_t page_alignment,
- bool interruptible,
- struct file *persistent_swap_storage,
- struct ttm_buffer_object **p_bo);
+int ttm_bo_create(struct ttm_bo_device *bdev, unsigned long size,
+ enum ttm_bo_type type, struct ttm_placement *placement,
+ uint32_t page_alignment, bool interruptible,
+ struct file *persistent_swap_storage,
+ struct ttm_buffer_object **p_bo);
/**
* ttm_bo_init_mm
@@ -594,9 +595,9 @@
* -ENOMEM: Not enough memory.
* May also return driver-specified errors.
*/
+int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
+ unsigned long p_size);
-extern int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
- unsigned long p_size);
/**
* ttm_bo_clean_mm
*
@@ -623,8 +624,7 @@
* -EINVAL: invalid or uninitialized memory type.
* -EBUSY: There are still buffers left in this memory type.
*/
-
-extern int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type);
+int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type);
/**
* ttm_bo_evict_mm
@@ -644,8 +644,7 @@
* -ERESTARTSYS: The call was interrupted by a signal while waiting to
* evict a buffer.
*/
-
-extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type);
+int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type);
/**
* ttm_kmap_obj_virtual
@@ -658,7 +657,6 @@
* If *is_iomem is 1 on return, the virtual address points to an io memory area,
* that should strictly be accessed by the iowriteXX() and similar functions.
*/
-
static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map,
bool *is_iomem)
{
@@ -682,9 +680,8 @@
* -ENOMEM: Out of memory.
* -EINVAL: Invalid range.
*/
-
-extern int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page,
- unsigned long num_pages, struct ttm_bo_kmap_obj *map);
+int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page,
+ unsigned long num_pages, struct ttm_bo_kmap_obj *map);
/**
* ttm_bo_kunmap
@@ -693,8 +690,7 @@
*
* Unmaps a kernel map set up by ttm_bo_kmap.
*/
-
-extern void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map);
+void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map);
/**
* ttm_fbdev_mmap - mmap fbdev memory backed by a ttm buffer object.
@@ -706,20 +702,7 @@
* This function is intended to be called by the fbdev mmap method
* if the fbdev address space is to be backed by a bo.
*/
-
-extern int ttm_fbdev_mmap(struct vm_area_struct *vma,
- struct ttm_buffer_object *bo);
-
-/**
- * ttm_bo_default_iomem_pfn - get a pfn for a page offset
- *
- * @bo: the BO we need to look up the pfn for
- * @page_offset: offset inside the BO to look up.
- *
- * Calculate the PFN for iomem based mappings during page fault
- */
-unsigned long ttm_bo_default_io_mem_pfn(struct ttm_buffer_object *bo,
- unsigned long page_offset);
+int ttm_fbdev_mmap(struct vm_area_struct *vma, struct ttm_buffer_object *bo);
/**
* ttm_bo_mmap - mmap out of the ttm device address space.
@@ -731,9 +714,8 @@
* This function is intended to be called by the device mmap method.
* if the device address space is to be backed by the bo manager.
*/
-
-extern int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma,
- struct ttm_bo_device *bdev);
+int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma,
+ struct ttm_bo_device *bdev);
/**
* ttm_bo_io
@@ -755,11 +737,12 @@
* the function may return -ERESTARTSYS if
* interrupted by a signal.
*/
+ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
+ const char __user *wbuf, char __user *rbuf,
+ size_t count, loff_t *f_pos, bool write);
-extern ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
- const char __user *wbuf, char __user *rbuf,
- size_t count, loff_t *f_pos, bool write);
-
-extern void ttm_bo_swapout_all(struct ttm_bo_device *bdev);
-extern int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo);
+int ttm_bo_swapout(struct ttm_bo_global *glob,
+ struct ttm_operation_ctx *ctx);
+void ttm_bo_swapout_all(struct ttm_bo_device *bdev);
+int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo);
#endif
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 5f821a9b..94064b1 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -352,7 +352,8 @@
* Returns:
* -ENOMEM: Out of memory.
*/
- int (*ttm_tt_populate)(struct ttm_tt *ttm);
+ int (*ttm_tt_populate)(struct ttm_tt *ttm,
+ struct ttm_operation_ctx *ctx);
/**
* ttm_tt_unpopulate
@@ -409,15 +410,13 @@
* @bo: the buffer to move
* @evict: whether this motion is evicting the buffer from
* the graphics address space
- * @interruptible: Use interruptible sleeps if possible when sleeping.
- * @no_wait: whether this should give up and return -EBUSY
- * if this move would require sleeping
+ * @ctx: context for this move with parameters
* @new_mem: the new memory region receiving the buffer
*
* Move a buffer between two memory regions.
*/
int (*move)(struct ttm_buffer_object *bo, bool evict,
- bool interruptible, bool no_wait_gpu,
+ struct ttm_operation_ctx *ctx,
struct ttm_mem_reg *new_mem);
/**
@@ -524,7 +523,6 @@
struct kobject kobj;
struct ttm_mem_global *mem_glob;
struct page *dummy_read_page;
- struct ttm_mem_shrink shrink;
struct mutex device_list_mutex;
spinlock_t lru_lock;
@@ -627,12 +625,12 @@
* Returns:
* NULL: Out of memory.
*/
-extern int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
- unsigned long size, uint32_t page_flags,
- struct page *dummy_read_page);
-extern int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev,
- unsigned long size, uint32_t page_flags,
- struct page *dummy_read_page);
+int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
+ unsigned long size, uint32_t page_flags,
+ struct page *dummy_read_page);
+int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev,
+ unsigned long size, uint32_t page_flags,
+ struct page *dummy_read_page);
/**
* ttm_tt_fini
@@ -641,8 +639,8 @@
*
* Free memory of ttm_tt structure
*/
-extern void ttm_tt_fini(struct ttm_tt *ttm);
-extern void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma);
+void ttm_tt_fini(struct ttm_tt *ttm);
+void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma);
/**
* ttm_ttm_bind:
@@ -652,7 +650,8 @@
*
* Bind the pages of @ttm to an aperture location identified by @bo_mem
*/
-extern int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem);
+int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem,
+ struct ttm_operation_ctx *ctx);
/**
* ttm_ttm_destroy:
@@ -661,7 +660,7 @@
*
* Unbind, unpopulate and destroy common struct ttm_tt.
*/
-extern void ttm_tt_destroy(struct ttm_tt *ttm);
+void ttm_tt_destroy(struct ttm_tt *ttm);
/**
* ttm_ttm_unbind:
@@ -670,7 +669,7 @@
*
* Unbind a struct ttm_tt.
*/
-extern void ttm_tt_unbind(struct ttm_tt *ttm);
+void ttm_tt_unbind(struct ttm_tt *ttm);
/**
* ttm_tt_swapin:
@@ -679,7 +678,7 @@
*
* Swap in a previously swap out ttm_tt.
*/
-extern int ttm_tt_swapin(struct ttm_tt *ttm);
+int ttm_tt_swapin(struct ttm_tt *ttm);
/**
* ttm_tt_set_placement_caching:
@@ -694,9 +693,8 @@
* hit RAM. This function may be very costly as it involves global TLB
* and cache flushes and potential page splitting / combining.
*/
-extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement);
-extern int ttm_tt_swapout(struct ttm_tt *ttm,
- struct file *persistent_swap_storage);
+int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement);
+int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage);
/**
* ttm_tt_unpopulate - free pages from a ttm
@@ -705,7 +703,7 @@
*
* Calls the driver method to free all pages from a ttm
*/
-extern void ttm_tt_unpopulate(struct ttm_tt *ttm);
+void ttm_tt_unpopulate(struct ttm_tt *ttm);
/*
* ttm_bo.c
@@ -720,8 +718,7 @@
* Returns true if the memory described by @mem is PCI memory,
* false otherwise.
*/
-extern bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev,
- struct ttm_mem_reg *mem);
+bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem);
/**
* ttm_bo_mem_space
@@ -742,21 +739,19 @@
* fragmentation or concurrent allocators.
* -ERESTARTSYS: An interruptible sleep was interrupted by a signal.
*/
-extern int ttm_bo_mem_space(struct ttm_buffer_object *bo,
- struct ttm_placement *placement,
- struct ttm_mem_reg *mem,
- bool interruptible,
- bool no_wait_gpu);
+int ttm_bo_mem_space(struct ttm_buffer_object *bo,
+ struct ttm_placement *placement,
+ struct ttm_mem_reg *mem,
+ struct ttm_operation_ctx *ctx);
-extern void ttm_bo_mem_put(struct ttm_buffer_object *bo,
+void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem);
+void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo,
struct ttm_mem_reg *mem);
-extern void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo,
- struct ttm_mem_reg *mem);
-extern void ttm_bo_global_release(struct drm_global_reference *ref);
-extern int ttm_bo_global_init(struct drm_global_reference *ref);
+void ttm_bo_global_release(struct drm_global_reference *ref);
+int ttm_bo_global_init(struct drm_global_reference *ref);
-extern int ttm_bo_device_release(struct ttm_bo_device *bdev);
+int ttm_bo_device_release(struct ttm_bo_device *bdev);
/**
* ttm_bo_device_init
@@ -773,18 +768,17 @@
* Returns:
* !0: Failure.
*/
-extern int ttm_bo_device_init(struct ttm_bo_device *bdev,
- struct ttm_bo_global *glob,
- struct ttm_bo_driver *driver,
- struct address_space *mapping,
- uint64_t file_page_offset, bool need_dma32);
+int ttm_bo_device_init(struct ttm_bo_device *bdev, struct ttm_bo_global *glob,
+ struct ttm_bo_driver *driver,
+ struct address_space *mapping,
+ uint64_t file_page_offset, bool need_dma32);
/**
* ttm_bo_unmap_virtual
*
* @bo: tear down the virtual mappings for this BO
*/
-extern void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
+void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
/**
* ttm_bo_unmap_virtual
@@ -793,16 +787,15 @@
*
* The caller must take ttm_mem_io_lock before calling this function.
*/
-extern void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo);
+void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo);
-extern int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo);
-extern void ttm_mem_io_free_vm(struct ttm_buffer_object *bo);
-extern int ttm_mem_io_lock(struct ttm_mem_type_manager *man,
- bool interruptible);
-extern void ttm_mem_io_unlock(struct ttm_mem_type_manager *man);
+int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo);
+void ttm_mem_io_free_vm(struct ttm_buffer_object *bo);
+int ttm_mem_io_lock(struct ttm_mem_type_manager *man, bool interruptible);
+void ttm_mem_io_unlock(struct ttm_mem_type_manager *man);
-extern void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo);
-extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
+void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo);
+void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
/**
* __ttm_bo_reserve:
@@ -836,14 +829,14 @@
if (WARN_ON(ticket))
return -EBUSY;
- success = ww_mutex_trylock(&bo->resv->lock);
+ success = reservation_object_trylock(bo->resv);
return success ? 0 : -EBUSY;
}
if (interruptible)
- ret = ww_mutex_lock_interruptible(&bo->resv->lock, ticket);
+ ret = reservation_object_lock_interruptible(bo->resv, ticket);
else
- ret = ww_mutex_lock(&bo->resv->lock, ticket);
+ ret = reservation_object_lock(bo->resv, ticket);
if (ret == -EINTR)
return -ERESTARTSYS;
return ret;
@@ -941,18 +934,6 @@
}
/**
- * __ttm_bo_unreserve
- * @bo: A pointer to a struct ttm_buffer_object.
- *
- * Unreserve a previous reservation of @bo where the buffer object is
- * already on lru lists.
- */
-static inline void __ttm_bo_unreserve(struct ttm_buffer_object *bo)
-{
- ww_mutex_unlock(&bo->resv->lock);
-}
-
-/**
* ttm_bo_unreserve
*
* @bo: A pointer to a struct ttm_buffer_object.
@@ -966,20 +947,7 @@
ttm_bo_add_to_lru(bo);
spin_unlock(&bo->glob->lru_lock);
}
- __ttm_bo_unreserve(bo);
-}
-
-/**
- * ttm_bo_unreserve_ticket
- * @bo: A pointer to a struct ttm_buffer_object.
- * @ticket: ww_acquire_ctx used for reserving
- *
- * Unreserve a previous reservation of @bo made with @ticket.
- */
-static inline void ttm_bo_unreserve_ticket(struct ttm_buffer_object *bo,
- struct ww_acquire_ctx *t)
-{
- ttm_bo_unreserve(bo);
+ reservation_object_unlock(bo->resv);
}
/*
@@ -1008,9 +976,9 @@
* !0: Failure.
*/
-extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait_gpu,
- struct ttm_mem_reg *new_mem);
+int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_mem);
/**
* ttm_bo_move_memcpy
@@ -1030,9 +998,9 @@
* !0: Failure.
*/
-extern int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait_gpu,
- struct ttm_mem_reg *new_mem);
+int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_mem);
/**
* ttm_bo_free_old_node
@@ -1041,7 +1009,7 @@
*
* Utility function to free an old placement after a successful move.
*/
-extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo);
+void ttm_bo_free_old_node(struct ttm_buffer_object *bo);
/**
* ttm_bo_move_accel_cleanup.
@@ -1058,10 +1026,9 @@
* destroyed when the move is complete. This will help pipeline
* buffer moves.
*/
-
-extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
- struct dma_fence *fence, bool evict,
- struct ttm_mem_reg *new_mem);
+int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
+ struct dma_fence *fence, bool evict,
+ struct ttm_mem_reg *new_mem);
/**
* ttm_bo_pipeline_move.
@@ -1087,7 +1054,7 @@
* Utility function that returns the pgprot_t that should be used for
* setting up a PTE with the caching model indicated by @c_state.
*/
-extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
+pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
extern const struct ttm_mem_type_manager_func ttm_bo_manager_func;
@@ -1108,11 +1075,11 @@
* for TT memory. This function uses the linux agpgart interface to
* bind and unbind memory backing a ttm_tt.
*/
-extern struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev,
- struct agp_bridge_data *bridge,
- unsigned long size, uint32_t page_flags,
- struct page *dummy_read_page);
-int ttm_agp_tt_populate(struct ttm_tt *ttm);
+struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev,
+ struct agp_bridge_data *bridge,
+ unsigned long size, uint32_t page_flags,
+ struct page *dummy_read_page);
+int ttm_agp_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx);
void ttm_agp_tt_unpopulate(struct ttm_tt *ttm);
#endif
diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h
index 2c1e359..8936285 100644
--- a/include/drm/ttm/ttm_memory.h
+++ b/include/drm/ttm/ttm_memory.h
@@ -35,20 +35,7 @@
#include <linux/errno.h>
#include <linux/kobject.h>
#include <linux/mm.h>
-
-/**
- * struct ttm_mem_shrink - callback to shrink TTM memory usage.
- *
- * @do_shrink: The callback function.
- *
- * Arguments to the do_shrink functions are intended to be passed using
- * inheritance. That is, the argument class derives from struct ttm_mem_shrink,
- * and can be accessed using container_of().
- */
-
-struct ttm_mem_shrink {
- int (*do_shrink) (struct ttm_mem_shrink *);
-};
+#include "ttm_bo_api.h"
/**
* struct ttm_mem_global - Global memory accounting structure.
@@ -76,7 +63,7 @@
struct ttm_mem_zone;
struct ttm_mem_global {
struct kobject kobj;
- struct ttm_mem_shrink *shrink;
+ struct ttm_bo_global *bo_glob;
struct workqueue_struct *swap_queue;
struct work_struct work;
spinlock_t lock;
@@ -90,67 +77,15 @@
#endif
};
-/**
- * ttm_mem_init_shrink - initialize a struct ttm_mem_shrink object
- *
- * @shrink: The object to initialize.
- * @func: The callback function.
- */
-
-static inline void ttm_mem_init_shrink(struct ttm_mem_shrink *shrink,
- int (*func) (struct ttm_mem_shrink *))
-{
- shrink->do_shrink = func;
-}
-
-/**
- * ttm_mem_register_shrink - register a struct ttm_mem_shrink object.
- *
- * @glob: The struct ttm_mem_global object to register with.
- * @shrink: An initialized struct ttm_mem_shrink object to register.
- *
- * Returns:
- * -EBUSY: There's already a callback registered. (May change).
- */
-
-static inline int ttm_mem_register_shrink(struct ttm_mem_global *glob,
- struct ttm_mem_shrink *shrink)
-{
- spin_lock(&glob->lock);
- if (glob->shrink != NULL) {
- spin_unlock(&glob->lock);
- return -EBUSY;
- }
- glob->shrink = shrink;
- spin_unlock(&glob->lock);
- return 0;
-}
-
-/**
- * ttm_mem_unregister_shrink - unregister a struct ttm_mem_shrink object.
- *
- * @glob: The struct ttm_mem_global object to unregister from.
- * @shrink: A previously registert struct ttm_mem_shrink object.
- *
- */
-
-static inline void ttm_mem_unregister_shrink(struct ttm_mem_global *glob,
- struct ttm_mem_shrink *shrink)
-{
- spin_lock(&glob->lock);
- BUG_ON(glob->shrink != shrink);
- glob->shrink = NULL;
- spin_unlock(&glob->lock);
-}
-
extern int ttm_mem_global_init(struct ttm_mem_global *glob);
extern void ttm_mem_global_release(struct ttm_mem_global *glob);
extern int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
- bool no_wait, bool interruptible);
+ struct ttm_operation_ctx *ctx);
extern void ttm_mem_global_free(struct ttm_mem_global *glob,
uint64_t amount);
extern int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
- struct page *page, uint64_t size);
+ struct page *page, uint64_t size,
+ struct ttm_operation_ctx *ctx);
extern void ttm_mem_global_free_page(struct ttm_mem_global *glob,
struct page *page, uint64_t size);
extern size_t ttm_round_pot(size_t size);
diff --git a/include/drm/ttm/ttm_page_alloc.h b/include/drm/ttm/ttm_page_alloc.h
index 5938113..4d9b019 100644
--- a/include/drm/ttm/ttm_page_alloc.h
+++ b/include/drm/ttm/ttm_page_alloc.h
@@ -47,7 +47,7 @@
*
* Add backing pages to all of @ttm
*/
-int ttm_pool_populate(struct ttm_tt *ttm);
+int ttm_pool_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx);
/**
* ttm_pool_unpopulate:
@@ -61,7 +61,8 @@
/**
* Populates and DMA maps pages to fullfil a ttm_dma_populate() request
*/
-int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt);
+int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt,
+ struct ttm_operation_ctx *ctx);
/**
* Unpopulates and DMA unmaps pages as part of a
@@ -89,7 +90,8 @@
*/
int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
-int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev);
+int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev,
+ struct ttm_operation_ctx *ctx);
void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev);
#else
@@ -106,7 +108,8 @@
return 0;
}
static inline int ttm_dma_populate(struct ttm_dma_tt *ttm_dma,
- struct device *dev)
+ struct device *dev,
+ struct ttm_operation_ctx *ctx)
{
return -ENOMEM;
}
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
index aca6126..f96fc2d 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -192,6 +192,8 @@
#define GCC_VS_CTRL_CLK_SRC 182
#define GCC_VSENSOR_CLK_SRC 183
#define GPLL4 184
+#define GCC_CPUSS_DVM_BUS_CLK 185
+#define GCC_CPUSS_GNOC_CLK 186
/* GCC Resets */
#define GCC_MMSS_BCR 0
diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
index e162045..e2d3892 100644
--- a/include/dt-bindings/sound/qcom,q6afe.h
+++ b/include/dt-bindings/sound/qcom,q6afe.h
@@ -26,6 +26,86 @@
#define TERTIARY_MI2S_TX 21
#define QUATERNARY_MI2S_RX 22
#define QUATERNARY_MI2S_TX 23
+#define PRIMARY_TDM_RX_0 24
+#define PRIMARY_TDM_TX_0 25
+#define PRIMARY_TDM_RX_1 26
+#define PRIMARY_TDM_TX_1 27
+#define PRIMARY_TDM_RX_2 28
+#define PRIMARY_TDM_TX_2 29
+#define PRIMARY_TDM_RX_3 30
+#define PRIMARY_TDM_TX_3 31
+#define PRIMARY_TDM_RX_4 32
+#define PRIMARY_TDM_TX_4 33
+#define PRIMARY_TDM_RX_5 34
+#define PRIMARY_TDM_TX_5 35
+#define PRIMARY_TDM_RX_6 36
+#define PRIMARY_TDM_TX_6 37
+#define PRIMARY_TDM_RX_7 38
+#define PRIMARY_TDM_TX_7 39
+#define SECONDARY_TDM_RX_0 40
+#define SECONDARY_TDM_TX_0 41
+#define SECONDARY_TDM_RX_1 42
+#define SECONDARY_TDM_TX_1 43
+#define SECONDARY_TDM_RX_2 44
+#define SECONDARY_TDM_TX_2 45
+#define SECONDARY_TDM_RX_3 46
+#define SECONDARY_TDM_TX_3 47
+#define SECONDARY_TDM_RX_4 48
+#define SECONDARY_TDM_TX_4 49
+#define SECONDARY_TDM_RX_5 50
+#define SECONDARY_TDM_TX_5 51
+#define SECONDARY_TDM_RX_6 52
+#define SECONDARY_TDM_TX_6 53
+#define SECONDARY_TDM_RX_7 54
+#define SECONDARY_TDM_TX_7 55
+#define TERTIARY_TDM_RX_0 56
+#define TERTIARY_TDM_TX_0 57
+#define TERTIARY_TDM_RX_1 58
+#define TERTIARY_TDM_TX_1 59
+#define TERTIARY_TDM_RX_2 60
+#define TERTIARY_TDM_TX_2 61
+#define TERTIARY_TDM_RX_3 62
+#define TERTIARY_TDM_TX_3 63
+#define TERTIARY_TDM_RX_4 64
+#define TERTIARY_TDM_TX_4 65
+#define TERTIARY_TDM_RX_5 66
+#define TERTIARY_TDM_TX_5 67
+#define TERTIARY_TDM_RX_6 68
+#define TERTIARY_TDM_TX_6 69
+#define TERTIARY_TDM_RX_7 70
+#define TERTIARY_TDM_TX_7 71
+#define QUATERNARY_TDM_RX_0 72
+#define QUATERNARY_TDM_TX_0 73
+#define QUATERNARY_TDM_RX_1 74
+#define QUATERNARY_TDM_TX_1 75
+#define QUATERNARY_TDM_RX_2 76
+#define QUATERNARY_TDM_TX_2 77
+#define QUATERNARY_TDM_RX_3 78
+#define QUATERNARY_TDM_TX_3 79
+#define QUATERNARY_TDM_RX_4 80
+#define QUATERNARY_TDM_TX_4 81
+#define QUATERNARY_TDM_RX_5 82
+#define QUATERNARY_TDM_TX_5 83
+#define QUATERNARY_TDM_RX_6 84
+#define QUATERNARY_TDM_TX_6 85
+#define QUATERNARY_TDM_RX_7 86
+#define QUATERNARY_TDM_TX_7 87
+#define QUINARY_TDM_RX_0 88
+#define QUINARY_TDM_TX_0 89
+#define QUINARY_TDM_RX_1 90
+#define QUINARY_TDM_TX_1 91
+#define QUINARY_TDM_RX_2 92
+#define QUINARY_TDM_TX_2 93
+#define QUINARY_TDM_RX_3 94
+#define QUINARY_TDM_TX_3 95
+#define QUINARY_TDM_RX_4 96
+#define QUINARY_TDM_TX_4 97
+#define QUINARY_TDM_RX_5 98
+#define QUINARY_TDM_TX_5 99
+#define QUINARY_TDM_RX_6 100
+#define QUINARY_TDM_TX_6 101
+#define QUINARY_TDM_RX_7 102
+#define QUINARY_TDM_TX_7 103
#endif /* __DT_BINDINGS_Q6_AFE_H__ */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 53dbb1b8..7e66417 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -441,6 +441,9 @@
int acpi_check_region(resource_size_t start, resource_size_t n,
const char *name);
+acpi_status acpi_release_memory(acpi_handle handle, struct resource *res,
+ u32 level);
+
int acpi_resources_are_enforced(void);
#ifdef CONFIG_HIBERNATION
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 6362e36..4d4af0e 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -1088,8 +1088,8 @@
if (!q->limits.chunk_sectors)
return q->limits.max_sectors;
- return q->limits.chunk_sectors -
- (offset & (q->limits.chunk_sectors - 1));
+ return min(q->limits.max_sectors, (unsigned int)(q->limits.chunk_sectors -
+ (offset & (q->limits.chunk_sectors - 1))));
}
static inline unsigned int blk_rq_get_max_sectors(struct request *rq,
diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h
index 8ae9a95..2c75fd9a 100644
--- a/include/linux/clockchips.h
+++ b/include/linux/clockchips.h
@@ -67,12 +67,20 @@
*/
# define CLOCK_EVT_FEAT_HRTIMER 0x000080
+/*
+ * Clockevent device may run during freeze
+ */
+# define CLOCK_EVT_FEAT_FREEZE_NONSTOP 0x000100
+
/**
* struct clock_event_device - clock event device descriptor
* @event_handler: Assigned by the framework to be called by the low
* level handler of the event source
* @set_next_event: set next event function using a clocksource delta
* @set_next_ktime: set next event function using a direct ktime value
+ * @event_expired: check if the programmed event is expired. Used for
+ * freeze events when timekeeping is suspended and
+ * irqs are disabled.
* @next_event: local storage for the next event in oneshot mode
* @max_delta_ns: maximum delta value in ns
* @min_delta_ns: minimum delta value in ns
@@ -101,6 +109,7 @@
void (*event_handler)(struct clock_event_device *);
int (*set_next_event)(unsigned long evt, struct clock_event_device *);
int (*set_next_ktime)(ktime_t expires, struct clock_event_device *);
+ int (*event_expired)(struct clock_event_device *);
ktime_t next_event;
u64 max_delta_ns;
u64 min_delta_ns;
diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h
index d3f264a..7fdc321 100644
--- a/include/linux/compiler-clang.h
+++ b/include/linux/compiler-clang.h
@@ -32,3 +32,17 @@
#ifdef __noretpoline
#undef __noretpoline
#endif
+
+/*
+ * Not all versions of clang implement the the type-generic versions
+ * of the builtin overflow checkers. Fortunately, clang implements
+ * __has_builtin allowing us to avoid awkward version
+ * checks. Unfortunately, we don't know which version of gcc clang
+ * pretends to be, so the macro may or may not be defined.
+ */
+#undef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
+#if __has_builtin(__builtin_mul_overflow) && \
+ __has_builtin(__builtin_add_overflow) && \
+ __has_builtin(__builtin_sub_overflow)
+#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
+#endif
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index f43113b..a0014bc 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -66,25 +66,40 @@
#endif
/*
+ * Feature detection for gnu_inline (gnu89 extern inline semantics). Either
+ * __GNUC_STDC_INLINE__ is defined (not using gnu89 extern inline semantics,
+ * and we opt in to the gnu89 semantics), or __GNUC_STDC_INLINE__ is not
+ * defined so the gnu89 semantics are the default.
+ */
+#ifdef __GNUC_STDC_INLINE__
+# define __gnu_inline __attribute__((gnu_inline))
+#else
+# define __gnu_inline
+#endif
+
+/*
* Force always-inline if the user requests it so via the .config,
* or if gcc is too old.
* GCC does not warn about unused static inline functions for
* -Wunused-function. This turns out to avoid the need for complex #ifdef
* directives. Suppress the warning in clang as well by using "unused"
* function attribute, which is redundant but not harmful for gcc.
+ * Prefer gnu_inline, so that extern inline functions do not emit an
+ * externally visible function. This makes extern inline behave as per gnu89
+ * semantics rather than c99. This prevents multiple symbol definition errors
+ * of extern inline functions at link time.
+ * A lot of inline functions can cause havoc with function tracing.
*/
#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
!defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-#define inline inline __attribute__((always_inline,unused)) notrace
-#define __inline__ __inline__ __attribute__((always_inline,unused)) notrace
-#define __inline __inline __attribute__((always_inline,unused)) notrace
+#define inline \
+ inline __attribute__((always_inline, unused)) notrace __gnu_inline
#else
-/* A lot of inline functions can cause havoc with function tracing */
-#define inline inline __attribute__((unused)) notrace
-#define __inline__ __inline__ __attribute__((unused)) notrace
-#define __inline __inline __attribute__((unused)) notrace
+#define inline inline __attribute__((unused)) notrace __gnu_inline
#endif
+#define __inline__ inline
+#define __inline inline
#define __always_inline inline __attribute__((always_inline))
#define noinline __attribute__((noinline))
@@ -343,3 +358,7 @@
* code
*/
#define uninitialized_var(x) x = x
+
+#if GCC_VERSION >= 50100
+#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
+#endif
diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h
index bfa0816..547cdc9 100644
--- a/include/linux/compiler-intel.h
+++ b/include/linux/compiler-intel.h
@@ -44,3 +44,7 @@
#define __builtin_bswap16 _bswap16
#endif
+/*
+ * icc defines __GNUC__, but does not implement the builtin overflow checkers.
+ */
+#undef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 853929f9..a704d03 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -21,7 +21,7 @@
#define unlikely_notrace(x) __builtin_expect(!!(x), 0)
#define __branch_check__(x, expect, is_constant) ({ \
- int ______r; \
+ long ______r; \
static struct ftrace_likely_data \
__attribute__((__aligned__(4))) \
__attribute__((section("_ftrace_annotated_branch"))) \
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index a6989e02..f6ad4c4 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -54,9 +54,9 @@
/*
* CPUs execute ->enter_s2idle with the local tick or entire timekeeping
* suspended, so it must not re-enable interrupts at any point (even
- * temporarily) or attempt to change states of clock event devices.
+ * temporarily). Returns 0 on success and non-zero if an error occurred.
*/
- void (*enter_s2idle) (struct cpuidle_device *dev,
+ int (*enter_s2idle) (struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index);
};
@@ -201,6 +201,8 @@
extern int cpuidle_enter_s2idle(struct cpuidle_driver *drv,
struct cpuidle_device *dev);
extern void cpuidle_use_deepest_state(bool enable);
+extern void cpuidle_prepare_freeze(void);
+extern int cpuidle_complete_freeze(void);
#else
static inline int cpuidle_find_deepest_state(struct cpuidle_driver *drv,
struct cpuidle_device *dev)
@@ -211,6 +213,8 @@
static inline void cpuidle_use_deepest_state(bool enable)
{
}
+static inline void cpuidle_prepare_freeze(void) { }
+static inline int cpuidle_complete_freeze(void) { return -ENODEV; }
#endif
/* kernel/sched/idle.c */
diff --git a/include/linux/dax.h b/include/linux/dax.h
index 895e16f..07d6bc1 100644
--- a/include/linux/dax.h
+++ b/include/linux/dax.h
@@ -40,10 +40,10 @@
int bdev_dax_pgoff(struct block_device *, sector_t, size_t, pgoff_t *pgoff);
#if IS_ENABLED(CONFIG_FS_DAX)
-int __bdev_dax_supported(struct super_block *sb, int blocksize);
-static inline int bdev_dax_supported(struct super_block *sb, int blocksize)
+bool __bdev_dax_supported(struct block_device *bdev, int blocksize);
+static inline bool bdev_dax_supported(struct block_device *bdev, int blocksize)
{
- return __bdev_dax_supported(sb, blocksize);
+ return __bdev_dax_supported(bdev, blocksize);
}
static inline struct dax_device *fs_dax_get_by_host(const char *host)
@@ -58,9 +58,10 @@
struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev);
#else
-static inline int bdev_dax_supported(struct super_block *sb, int blocksize)
+static inline bool bdev_dax_supported(struct block_device *bdev,
+ int blocksize)
{
- return -EOPNOTSUPP;
+ return false;
}
static inline struct dax_device *fs_dax_get_by_host(const char *host)
diff --git a/include/linux/fb.h b/include/linux/fb.h
index bc24e48..d1e5bed 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -465,6 +465,11 @@
atomic_t count;
int node;
int flags;
+ /*
+ * -1 by default, set to a FB_ROTATE_* value by the driver, if it knows
+ * a lcd is not mounted upright and fbcon should rotate to compensate.
+ */
+ int fbcon_rotate_hint;
struct mutex lock; /* Lock for open/release/ioctl funcs */
struct mutex mm_lock; /* Lock for fb_mmap and smem_* fields */
struct fb_var_screeninfo var; /* Current var */
diff --git a/include/linux/iova.h b/include/linux/iova.h
index d179b9b..928442d 100644
--- a/include/linux/iova.h
+++ b/include/linux/iova.h
@@ -70,10 +70,12 @@
struct iova_domain {
spinlock_t iova_rbtree_lock; /* Lock to protect update of rbtree */
struct rb_root rbroot; /* iova domain rbtree root */
- struct rb_node *cached32_node; /* Save last alloced node */
+ struct rb_node *cached_node; /* Save last alloced node */
+ struct rb_node *cached32_node; /* Save last 32-bit alloced node */
unsigned long granule; /* pfn granularity for this domain */
unsigned long start_pfn; /* Lower limit for this domain */
unsigned long dma_32bit_pfn;
+ struct iova anchor; /* rbtree lookup anchor */
struct iova_rcache rcaches[IOVA_RANGE_CACHE_MAX_SIZE]; /* IOVA range caches */
iova_flush_cb flush_cb; /* Call-Back function to flush IOMMU
@@ -148,12 +150,12 @@
unsigned long pfn, unsigned long pages,
unsigned long data);
unsigned long alloc_iova_fast(struct iova_domain *iovad, unsigned long size,
- unsigned long limit_pfn);
+ unsigned long limit_pfn, bool flush_rcache);
struct iova *reserve_iova(struct iova_domain *iovad, unsigned long pfn_lo,
unsigned long pfn_hi);
void copy_reserved_iova(struct iova_domain *from, struct iova_domain *to);
void init_iova_domain(struct iova_domain *iovad, unsigned long granule,
- unsigned long start_pfn, unsigned long pfn_32bit);
+ unsigned long start_pfn);
int init_iova_flush_queue(struct iova_domain *iovad,
iova_flush_cb flush_cb, iova_entry_dtor entry_dtor);
struct iova *find_iova(struct iova_domain *iovad, unsigned long pfn);
@@ -210,7 +212,8 @@
static inline unsigned long alloc_iova_fast(struct iova_domain *iovad,
unsigned long size,
- unsigned long limit_pfn)
+ unsigned long limit_pfn,
+ bool flush_rcache)
{
return 0;
}
@@ -229,8 +232,7 @@
static inline void init_iova_domain(struct iova_domain *iovad,
unsigned long granule,
- unsigned long start_pfn,
- unsigned long pfn_32bit)
+ unsigned long start_pfn)
{
}
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 931c32f..c5188dc 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -211,6 +211,7 @@
ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */
/* (doesn't imply presence) */
ATA_FLAG_SATA = (1 << 1),
+ ATA_FLAG_NO_LPM = (1 << 2), /* host not happy with LPM */
ATA_FLAG_NO_LOG_PAGE = (1 << 5), /* do not issue log page read */
ATA_FLAG_NO_ATAPI = (1 << 6), /* No ATAPI support */
ATA_FLAG_PIO_DMA = (1 << 7), /* PIO cmds via DMA */
diff --git a/include/linux/low-mem-notify.h b/include/linux/low-mem-notify.h
index 42d09a6f..71ddb10 100644
--- a/include/linux/low-mem-notify.h
+++ b/include/linux/low-mem-notify.h
@@ -17,11 +17,11 @@
/*
* Compute available memory used by files that can be reclaimed quickly.
*/
-static inline unsigned long get_available_file_mem(int lru_base)
+static inline unsigned long get_available_file_mem(void)
{
unsigned long file_mem =
- global_zone_page_state(lru_base + LRU_ACTIVE_FILE) +
- global_zone_page_state(lru_base + LRU_INACTIVE_FILE);
+ global_node_page_state(NR_ACTIVE_FILE) +
+ global_node_page_state(NR_INACTIVE_FILE);
unsigned long dirty_mem = global_node_page_state(NR_FILE_DIRTY);
unsigned long min_file_mem = min_filelist_kbytes >> (PAGE_SHIFT - 10);
unsigned long clean_file_mem = file_mem - dirty_mem;
@@ -35,7 +35,7 @@
* Compute "available" memory, that is either free memory or memory that can be
* reclaimed quickly, adjusted for the presence of swap.
*/
-static inline unsigned long get_available_mem_adj(int lru_base)
+static inline unsigned long get_available_mem_adj(void)
{
/* min_free_kbytes is reserved for emergency allocation like when
* PF_MEMALLOC is set. In general it's not usable in normal page
@@ -49,7 +49,7 @@
unsigned long free_mem =
global_zone_page_state(NR_FREE_PAGES) - min_free_pages;
unsigned long available_mem = free_mem +
- get_available_file_mem(lru_base);
+ get_available_file_mem();
long _nr_swap_pages = get_nr_swap_pages();
/*
* The contribution of swap is reduced by a factor of
@@ -63,18 +63,17 @@
*/
static inline bool _is_low_mem_situation(void)
{
- const int lru_base = NR_LRU_BASE - LRU_BASE;
static bool was_low_mem; /* = false, as per style guide */
/* We declare a low-memory condition when a combination of RAM and swap
* space is low.
*/
- unsigned long available_mem = get_available_mem_adj(lru_base);
+ unsigned long available_mem = get_available_mem_adj();
bool is_low_mem = available_mem < low_mem_minfree;
if (unlikely(is_low_mem && !was_low_mem)) {
unsigned long anon_mem =
- global_zone_page_state(lru_base + LRU_ACTIVE_ANON) +
- global_zone_page_state(lru_base + LRU_INACTIVE_ANON);
+ global_node_page_state(NR_ACTIVE_ANON) +
+ global_node_page_state(NR_INACTIVE_ANON);
if (unlikely(anon_mem < low_mem_lowest_seen_anon_mem)) {
printk(KERN_INFO "entering low_mem "
"(avail RAM = %lu kB, avail swap %lu kB, "
@@ -82,7 +81,7 @@
"with lowest seen anon mem: %lu kB\n",
available_mem * PAGE_SIZE / 1024,
get_nr_swap_pages() * PAGE_SIZE / 1024,
- get_available_file_mem(lru_base) * PAGE_SIZE /
+ get_available_file_mem() * PAGE_SIZE /
1024,
anon_mem * PAGE_SIZE / 1024);
low_mem_lowest_seen_anon_mem = anon_mem -
diff --git a/include/linux/mm.h b/include/linux/mm.h
index a4fd82c..f1bf550 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -2553,6 +2553,7 @@
MF_MSG_POISONED_HUGE,
MF_MSG_HUGE,
MF_MSG_FREE_HUGE,
+ MF_MSG_NON_PMD_HUGE,
MF_MSG_UNMAP_FAILED,
MF_MSG_DIRTY_SWAPCACHE,
MF_MSG_CLEAN_SWAPCACHE,
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 1f0a7fc..db78a3c 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -232,10 +232,17 @@
};
/**
+ * struct flash_info - Forward declaration of a structure used internally by
+ * spi_nor_scan()
+ */
+struct flash_info;
+
+/**
* struct spi_nor - Structure for defining a the SPI NOR layer
* @mtd: point to a mtd_info structure
* @lock: the lock for the read/write/erase/lock/unlock operations
* @dev: point to a spi device, or a spi nor controller device.
+ * @info: spi-nor part JDEC MFR id and other info
* @page_size: the page size of the SPI NOR
* @addr_width: number of address bytes
* @erase_opcode: the opcode for erasing a sector
@@ -262,6 +269,7 @@
* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
+ * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
* completely locked
* @priv: the private data
*/
@@ -269,6 +277,7 @@
struct mtd_info mtd;
struct mutex lock;
struct device *dev;
+ const struct flash_info *info;
u32 page_size;
u8 addr_width;
u8 erase_opcode;
@@ -296,6 +305,7 @@
int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
+ int (*quad_enable)(struct spi_nor *nor);
void *priv;
};
@@ -389,4 +399,10 @@
int spi_nor_scan(struct spi_nor *nor, const char *name,
const struct spi_nor_hwcaps *hwcaps);
+/**
+ * spi_nor_restore_addr_mode() - restore the status of SPI NOR
+ * @nor: the spi_nor structure
+ */
+void spi_nor_restore(struct spi_nor *nor);
+
#endif
diff --git a/include/linux/overflow.h b/include/linux/overflow.h
new file mode 100644
index 0000000..8712ff7
--- /dev/null
+++ b/include/linux/overflow.h
@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+#ifndef __LINUX_OVERFLOW_H
+#define __LINUX_OVERFLOW_H
+
+#include <linux/compiler.h>
+
+/*
+ * In the fallback code below, we need to compute the minimum and
+ * maximum values representable in a given type. These macros may also
+ * be useful elsewhere, so we provide them outside the
+ * COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW block.
+ *
+ * It would seem more obvious to do something like
+ *
+ * #define type_min(T) (T)(is_signed_type(T) ? (T)1 << (8*sizeof(T)-1) : 0)
+ * #define type_max(T) (T)(is_signed_type(T) ? ((T)1 << (8*sizeof(T)-1)) - 1 : ~(T)0)
+ *
+ * Unfortunately, the middle expressions, strictly speaking, have
+ * undefined behaviour, and at least some versions of gcc warn about
+ * the type_max expression (but not if -fsanitize=undefined is in
+ * effect; in that case, the warning is deferred to runtime...).
+ *
+ * The slightly excessive casting in type_min is to make sure the
+ * macros also produce sensible values for the exotic type _Bool. [The
+ * overflow checkers only almost work for _Bool, but that's
+ * a-feature-not-a-bug, since people shouldn't be doing arithmetic on
+ * _Bools. Besides, the gcc builtins don't allow _Bool* as third
+ * argument.]
+ *
+ * Idea stolen from
+ * https://mail-index.netbsd.org/tech-misc/2007/02/05/0000.html -
+ * credit to Christian Biere.
+ */
+#define is_signed_type(type) (((type)(-1)) < (type)1)
+#define __type_half_max(type) ((type)1 << (8*sizeof(type) - 1 - is_signed_type(type)))
+#define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
+#define type_min(T) ((T)((T)-type_max(T)-(T)1))
+
+
+#ifdef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
+/*
+ * For simplicity and code hygiene, the fallback code below insists on
+ * a, b and *d having the same type (similar to the min() and max()
+ * macros), whereas gcc's type-generic overflow checkers accept
+ * different types. Hence we don't just make check_add_overflow an
+ * alias for __builtin_add_overflow, but add type checks similar to
+ * below.
+ */
+#define check_add_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ __builtin_add_overflow(__a, __b, __d); \
+})
+
+#define check_sub_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ __builtin_sub_overflow(__a, __b, __d); \
+})
+
+#define check_mul_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ __builtin_mul_overflow(__a, __b, __d); \
+})
+
+#else
+
+
+/* Checking for unsigned overflow is relatively easy without causing UB. */
+#define __unsigned_add_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ *__d = __a + __b; \
+ *__d < __a; \
+})
+#define __unsigned_sub_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ *__d = __a - __b; \
+ __a < __b; \
+})
+/*
+ * If one of a or b is a compile-time constant, this avoids a division.
+ */
+#define __unsigned_mul_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ *__d = __a * __b; \
+ __builtin_constant_p(__b) ? \
+ __b > 0 && __a > type_max(typeof(__a)) / __b : \
+ __a > 0 && __b > type_max(typeof(__b)) / __a; \
+})
+
+/*
+ * For signed types, detecting overflow is much harder, especially if
+ * we want to avoid UB. But the interface of these macros is such that
+ * we must provide a result in *d, and in fact we must produce the
+ * result promised by gcc's builtins, which is simply the possibly
+ * wrapped-around value. Fortunately, we can just formally do the
+ * operations in the widest relevant unsigned type (u64) and then
+ * truncate the result - gcc is smart enough to generate the same code
+ * with and without the (u64) casts.
+ */
+
+/*
+ * Adding two signed integers can overflow only if they have the same
+ * sign, and overflow has happened iff the result has the opposite
+ * sign.
+ */
+#define __signed_add_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ *__d = (u64)__a + (u64)__b; \
+ (((~(__a ^ __b)) & (*__d ^ __a)) \
+ & type_min(typeof(__a))) != 0; \
+})
+
+/*
+ * Subtraction is similar, except that overflow can now happen only
+ * when the signs are opposite. In this case, overflow has happened if
+ * the result has the opposite sign of a.
+ */
+#define __signed_sub_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ *__d = (u64)__a - (u64)__b; \
+ ((((__a ^ __b)) & (*__d ^ __a)) \
+ & type_min(typeof(__a))) != 0; \
+})
+
+/*
+ * Signed multiplication is rather hard. gcc always follows C99, so
+ * division is truncated towards 0. This means that we can write the
+ * overflow check like this:
+ *
+ * (a > 0 && (b > MAX/a || b < MIN/a)) ||
+ * (a < -1 && (b > MIN/a || b < MAX/a) ||
+ * (a == -1 && b == MIN)
+ *
+ * The redundant casts of -1 are to silence an annoying -Wtype-limits
+ * (included in -Wextra) warning: When the type is u8 or u16, the
+ * __b_c_e in check_mul_overflow obviously selects
+ * __unsigned_mul_overflow, but unfortunately gcc still parses this
+ * code and warns about the limited range of __b.
+ */
+
+#define __signed_mul_overflow(a, b, d) ({ \
+ typeof(a) __a = (a); \
+ typeof(b) __b = (b); \
+ typeof(d) __d = (d); \
+ typeof(a) __tmax = type_max(typeof(a)); \
+ typeof(a) __tmin = type_min(typeof(a)); \
+ (void) (&__a == &__b); \
+ (void) (&__a == __d); \
+ *__d = (u64)__a * (u64)__b; \
+ (__b > 0 && (__a > __tmax/__b || __a < __tmin/__b)) || \
+ (__b < (typeof(__b))-1 && (__a > __tmin/__b || __a < __tmax/__b)) || \
+ (__b == (typeof(__b))-1 && __a == __tmin); \
+})
+
+
+#define check_add_overflow(a, b, d) \
+ __builtin_choose_expr(is_signed_type(typeof(a)), \
+ __signed_add_overflow(a, b, d), \
+ __unsigned_add_overflow(a, b, d))
+
+#define check_sub_overflow(a, b, d) \
+ __builtin_choose_expr(is_signed_type(typeof(a)), \
+ __signed_sub_overflow(a, b, d), \
+ __unsigned_sub_overflow(a, b, d))
+
+#define check_mul_overflow(a, b, d) \
+ __builtin_choose_expr(is_signed_type(typeof(a)), \
+ __signed_mul_overflow(a, b, d), \
+ __unsigned_mul_overflow(a, b, d))
+
+
+#endif /* COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW */
+
+/**
+ * array_size() - Calculate size of 2-dimensional array.
+ *
+ * @a: dimension one
+ * @b: dimension two
+ *
+ * Calculates size of 2-dimensional array: @a * @b.
+ *
+ * Returns: number of bytes needed to represent the array or SIZE_MAX on
+ * overflow.
+ */
+static inline __must_check size_t array_size(size_t a, size_t b)
+{
+ size_t bytes;
+
+ if (check_mul_overflow(a, b, &bytes))
+ return SIZE_MAX;
+
+ return bytes;
+}
+
+/**
+ * array3_size() - Calculate size of 3-dimensional array.
+ *
+ * @a: dimension one
+ * @b: dimension two
+ * @c: dimension three
+ *
+ * Calculates size of 3-dimensional array: @a * @b * @c.
+ *
+ * Returns: number of bytes needed to represent the array or SIZE_MAX on
+ * overflow.
+ */
+static inline __must_check size_t array3_size(size_t a, size_t b, size_t c)
+{
+ size_t bytes;
+
+ if (check_mul_overflow(a, b, &bytes))
+ return SIZE_MAX;
+ if (check_mul_overflow(bytes, c, &bytes))
+ return SIZE_MAX;
+
+ return bytes;
+}
+
+static inline __must_check size_t __ab_c_size(size_t n, size_t size, size_t c)
+{
+ size_t bytes;
+
+ if (check_mul_overflow(n, size, &bytes))
+ return SIZE_MAX;
+ if (check_add_overflow(bytes, c, &bytes))
+ return SIZE_MAX;
+
+ return bytes;
+}
+
+/**
+ * struct_size() - Calculate size of structure with trailing array.
+ * @p: Pointer to the structure.
+ * @member: Name of the array member.
+ * @n: Number of elements in the array.
+ *
+ * Calculates size of memory needed for structure @p followed by an
+ * array of @n @member elements.
+ *
+ * Return: number of bytes needed or SIZE_MAX on overflow.
+ */
+#define struct_size(p, member, n) \
+ __ab_c_size(n, \
+ sizeof(*(p)->member) + __must_be_array((p)->member),\
+ sizeof(*(p)))
+
+#endif /* __LINUX_OVERFLOW_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 727e309..a469dd0 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1107,6 +1107,8 @@
void pci_update_resource(struct pci_dev *dev, int resno);
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
+void pci_release_resource(struct pci_dev *dev, int resno);
+int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
bool pci_device_is_present(struct pci_dev *pdev);
void pci_ignore_hotplug(struct pci_dev *dev);
@@ -1186,6 +1188,7 @@
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
+int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
void pdev_enable_device(struct pci_dev *);
int pci_enable_resources(struct pci_dev *, int mask);
void pci_assign_irq(struct pci_dev *dev);
diff --git a/include/linux/reservation.h b/include/linux/reservation.h
index 21fc84d8..02166e8 100644
--- a/include/linux/reservation.h
+++ b/include/linux/reservation.h
@@ -167,6 +167,29 @@
}
/**
+ * reservation_object_lock_interruptible - lock the reservation object
+ * @obj: the reservation object
+ * @ctx: the locking context
+ *
+ * Locks the reservation object interruptible for exclusive access and
+ * modification. Note, that the lock is only against other writers, readers
+ * will run concurrently with a writer under RCU. The seqlock is used to
+ * notify readers if they overlap with a writer.
+ *
+ * As the reservation object may be locked by multiple parties in an
+ * undefined order, a #ww_acquire_ctx is passed to unwind if a cycle
+ * is detected. See ww_mutex_lock() and ww_acquire_init(). A reservation
+ * object may be locked by itself by passing NULL as @ctx.
+ */
+static inline int
+reservation_object_lock_interruptible(struct reservation_object *obj,
+ struct ww_acquire_ctx *ctx)
+{
+ return ww_mutex_lock_interruptible(&obj->lock, ctx);
+}
+
+
+/**
* reservation_object_trylock - trylock the reservation object
* @obj: the reservation object
*
diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h
index 39fa09b..2038ab5 100644
--- a/include/linux/slub_def.h
+++ b/include/linux/slub_def.h
@@ -151,8 +151,12 @@
#ifdef CONFIG_SYSFS
#define SLAB_SUPPORTS_SYSFS
+void sysfs_slab_unlink(struct kmem_cache *);
void sysfs_slab_release(struct kmem_cache *);
#else
+static inline void sysfs_slab_unlink(struct kmem_cache *s)
+{
+}
static inline void sysfs_slab_release(struct kmem_cache *s)
{
}
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
new file mode 100644
index 0000000..bb4bd15
--- /dev/null
+++ b/include/linux/spi/spi-mem.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ * Copyright (C) 2018 Bootlin
+ *
+ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+
+#ifndef __LINUX_SPI_MEM_H
+#define __LINUX_SPI_MEM_H
+
+#include <linux/spi/spi.h>
+
+#define SPI_MEM_OP_CMD(__opcode, __buswidth) \
+ { \
+ .buswidth = __buswidth, \
+ .opcode = __opcode, \
+ }
+
+#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
+ { \
+ .nbytes = __nbytes, \
+ .val = __val, \
+ .buswidth = __buswidth, \
+ }
+
+#define SPI_MEM_OP_NO_ADDR { }
+
+#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \
+ { \
+ .nbytes = __nbytes, \
+ .buswidth = __buswidth, \
+ }
+
+#define SPI_MEM_OP_NO_DUMMY { }
+
+#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \
+ { \
+ .dir = SPI_MEM_DATA_IN, \
+ .nbytes = __nbytes, \
+ .buf.in = __buf, \
+ .buswidth = __buswidth, \
+ }
+
+#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
+ { \
+ .dir = SPI_MEM_DATA_OUT, \
+ .nbytes = __nbytes, \
+ .buf.out = __buf, \
+ .buswidth = __buswidth, \
+ }
+
+#define SPI_MEM_OP_NO_DATA { }
+
+/**
+ * enum spi_mem_data_dir - describes the direction of a SPI memory data
+ * transfer from the controller perspective
+ * @SPI_MEM_DATA_IN: data coming from the SPI memory
+ * @SPI_MEM_DATA_OUT: data sent the SPI memory
+ */
+enum spi_mem_data_dir {
+ SPI_MEM_DATA_IN,
+ SPI_MEM_DATA_OUT,
+};
+
+/**
+ * struct spi_mem_op - describes a SPI memory operation
+ * @cmd.buswidth: number of IO lines used to transmit the command
+ * @cmd.opcode: operation opcode
+ * @addr.nbytes: number of address bytes to send. Can be zero if the operation
+ * does not need to send an address
+ * @addr.buswidth: number of IO lines used to transmit the address cycles
+ * @addr.val: address value. This value is always sent MSB first on the bus.
+ * Note that only @addr.nbytes are taken into account in this
+ * address value, so users should make sure the value fits in the
+ * assigned number of bytes.
+ * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
+ * be zero if the operation does not require dummy bytes
+ * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
+ * @data.buswidth: number of IO lanes used to send/receive the data
+ * @data.dir: direction of the transfer
+ * @data.buf.in: input buffer
+ * @data.buf.out: output buffer
+ */
+struct spi_mem_op {
+ struct {
+ u8 buswidth;
+ u8 opcode;
+ } cmd;
+
+ struct {
+ u8 nbytes;
+ u8 buswidth;
+ u64 val;
+ } addr;
+
+ struct {
+ u8 nbytes;
+ u8 buswidth;
+ } dummy;
+
+ struct {
+ u8 buswidth;
+ enum spi_mem_data_dir dir;
+ unsigned int nbytes;
+ /* buf.{in,out} must be DMA-able. */
+ union {
+ void *in;
+ const void *out;
+ } buf;
+ } data;
+};
+
+#define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \
+ { \
+ .cmd = __cmd, \
+ .addr = __addr, \
+ .dummy = __dummy, \
+ .data = __data, \
+ }
+
+/**
+ * struct spi_mem - describes a SPI memory device
+ * @spi: the underlying SPI device
+ * @drvpriv: spi_mem_drviver private data
+ *
+ * Extra information that describe the SPI memory device and may be needed by
+ * the controller to properly handle this device should be placed here.
+ *
+ * One example would be the device size since some controller expose their SPI
+ * mem devices through a io-mapped region.
+ */
+struct spi_mem {
+ struct spi_device *spi;
+ void *drvpriv;
+};
+
+/**
+ * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem
+ * device
+ * @mem: memory device
+ * @data: data to attach to the memory device
+ */
+static inline void spi_mem_set_drvdata(struct spi_mem *mem, void *data)
+{
+ mem->drvpriv = data;
+}
+
+/**
+ * struct spi_mem_get_drvdata() - get driver private data attached to a SPI mem
+ * device
+ * @mem: memory device
+ *
+ * Return: the data attached to the mem device.
+ */
+static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
+{
+ return mem->drvpriv;
+}
+
+/**
+ * struct spi_controller_mem_ops - SPI memory operations
+ * @adjust_op_size: shrink the data xfer of an operation to match controller's
+ * limitations (can be alignment of max RX/TX size
+ * limitations)
+ * @supports_op: check if an operation is supported by the controller
+ * @exec_op: execute a SPI memory operation
+ *
+ * This interface should be implemented by SPI controllers providing an
+ * high-level interface to execute SPI memory operation, which is usually the
+ * case for QSPI controllers.
+ */
+struct spi_controller_mem_ops {
+ int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op);
+ bool (*supports_op)(struct spi_mem *mem,
+ const struct spi_mem_op *op);
+ int (*exec_op)(struct spi_mem *mem,
+ const struct spi_mem_op *op);
+};
+
+/**
+ * struct spi_mem_driver - SPI memory driver
+ * @spidrv: inherit from a SPI driver
+ * @probe: probe a SPI memory. Usually where detection/initialization takes
+ * place
+ * @remove: remove a SPI memory
+ * @shutdown: take appropriate action when the system is shutdown
+ *
+ * This is just a thin wrapper around a spi_driver. The core takes care of
+ * allocating the spi_mem object and forwarding the probe/remove/shutdown
+ * request to the spi_mem_driver. The reason we use this wrapper is because
+ * we might have to stuff more information into the spi_mem struct to let
+ * SPI controllers know more about the SPI memory they interact with, and
+ * having this intermediate layer allows us to do that without adding more
+ * useless fields to the spi_device object.
+ */
+struct spi_mem_driver {
+ struct spi_driver spidrv;
+ int (*probe)(struct spi_mem *mem);
+ int (*remove)(struct spi_mem *mem);
+ void (*shutdown)(struct spi_mem *mem);
+};
+
+#if IS_ENABLED(CONFIG_SPI_MEM)
+int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
+ const struct spi_mem_op *op,
+ struct sg_table *sg);
+
+void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
+ const struct spi_mem_op *op,
+ struct sg_table *sg);
+#else
+static inline int
+spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
+ const struct spi_mem_op *op,
+ struct sg_table *sg)
+{
+ return -ENOTSUPP;
+}
+
+static inline void
+spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
+ const struct spi_mem_op *op,
+ struct sg_table *sg)
+{
+}
+#endif /* CONFIG_SPI_MEM */
+
+int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
+
+bool spi_mem_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op);
+
+int spi_mem_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op);
+
+int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
+ struct module *owner);
+
+void spi_mem_driver_unregister(struct spi_mem_driver *drv);
+
+#define spi_mem_driver_register(__drv) \
+ spi_mem_driver_register_with_owner(__drv, THIS_MODULE)
+
+#define module_spi_mem_driver(__drv) \
+ module_driver(__drv, spi_mem_driver_register, \
+ spi_mem_driver_unregister)
+
+#endif /* __LINUX_SPI_MEM_H */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 7b2170b..aca5a64 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -26,7 +26,7 @@
struct property_entry;
struct spi_controller;
struct spi_transfer;
-struct spi_flash_read_message;
+struct spi_controller_mem_ops;
/*
* INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
@@ -376,13 +376,11 @@
* transfer_one callback.
* @handle_err: the subsystem calls the driver to handle an error that occurs
* in the generic implementation of transfer_one_message().
+ * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
+ * This field is optional and should only be implemented if the
+ * controller has native support for memory like operations.
* @unprepare_message: undo any work done by prepare_message().
* @slave_abort: abort the ongoing transfer request on an SPI slave controller
- * @spi_flash_read: to support spi-controller hardwares that provide
- * accelerated interface to read from flash devices.
- * @spi_flash_can_dma: analogous to can_dma() interface, but for
- * controllers implementing spi_flash_read.
- * @flash_read_supported: spi device supports flash read
* @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
* number. Any individual value may be -ENOENT for CS lines that
* are not GPIOs (driven by the SPI controller itself).
@@ -548,11 +546,6 @@
int (*unprepare_message)(struct spi_controller *ctlr,
struct spi_message *message);
int (*slave_abort)(struct spi_controller *ctlr);
- int (*spi_flash_read)(struct spi_device *spi,
- struct spi_flash_read_message *msg);
- bool (*spi_flash_can_dma)(struct spi_device *spi,
- struct spi_flash_read_message *msg);
- bool (*flash_read_supported)(struct spi_device *spi);
/*
* These hooks are for drivers that use a generic implementation
@@ -564,6 +557,9 @@
void (*handle_err)(struct spi_controller *ctlr,
struct spi_message *message);
+ /* Optimized handlers for SPI memory-like operations. */
+ const struct spi_controller_mem_ops *mem_ops;
+
/* gpio chip select */
int *cs_gpios;
@@ -1183,48 +1179,6 @@
return be16_to_cpu(result);
}
-/**
- * struct spi_flash_read_message - flash specific information for
- * spi-masters that provide accelerated flash read interfaces
- * @buf: buffer to read data
- * @from: offset within the flash from where data is to be read
- * @len: length of data to be read
- * @retlen: actual length of data read
- * @read_opcode: read_opcode to be used to communicate with flash
- * @addr_width: number of address bytes
- * @dummy_bytes: number of dummy bytes
- * @opcode_nbits: number of lines to send opcode
- * @addr_nbits: number of lines to send address
- * @data_nbits: number of lines for data
- * @rx_sg: Scatterlist for receive data read from flash
- * @cur_msg_mapped: message has been mapped for DMA
- */
-struct spi_flash_read_message {
- void *buf;
- loff_t from;
- size_t len;
- size_t retlen;
- u8 read_opcode;
- u8 addr_width;
- u8 dummy_bytes;
- u8 opcode_nbits;
- u8 addr_nbits;
- u8 data_nbits;
- struct sg_table rx_sg;
- bool cur_msg_mapped;
-};
-
-/* SPI core interface for flash read support */
-static inline bool spi_flash_read_supported(struct spi_device *spi)
-{
- return spi->controller->spi_flash_read &&
- (!spi->controller->flash_read_supported ||
- spi->controller->flash_read_supported(spi));
-}
-
-int spi_flash_read(struct spi_device *spi,
- struct spi_flash_read_message *msg);
-
/*---------------------------------------------------------------------------*/
/*
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index 92ff02a..b487e4f 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -254,6 +254,8 @@
extern void __init pm_states_init(void);
extern void s2idle_set_ops(const struct platform_s2idle_ops *ops);
extern void s2idle_wake(void);
+int tick_set_freeze_event(int cpu, ktime_t expires);
+int tick_clear_freeze_event(int cpu);
/**
* arch_suspend_disable_irqs - disable IRQs for suspend
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index 1c40ecf..848156b 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -212,7 +212,6 @@
struct thermal_attr *trip_type_attrs;
struct thermal_attr *trip_hyst_attrs;
void *devdata;
- enum thermal_device_mode mode;
int trips;
unsigned long trips_disabled; /* bitmap for disabled trips */
int passive_delay;
@@ -468,8 +467,6 @@
int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp);
int thermal_zone_get_slope(struct thermal_zone_device *tz);
int thermal_zone_get_offset(struct thermal_zone_device *tz);
-int thermal_zone_set_mode(struct thermal_zone_device *tz,
- enum thermal_device_mode mode);
int get_tz_trend(struct thermal_zone_device *, int);
struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,
diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
index a1f03eb..f1ac093 100644
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -315,6 +315,7 @@
int (*bus_suspend)(struct usb_hcd *);
int (*bus_resume)(struct usb_hcd *);
int (*start_port_reset)(struct usb_hcd *, unsigned port_num);
+ unsigned long (*get_resuming_ports)(struct usb_hcd *);
/* force handover of high-speed port to full-speed companion */
void (*relinquish_port)(struct usb_hcd *, int);
diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h
index 079c69c..59a4f50 100644
--- a/include/net/netfilter/nf_tables.h
+++ b/include/net/netfilter/nf_tables.h
@@ -177,6 +177,7 @@
int nft_data_init(const struct nft_ctx *ctx,
struct nft_data *data, unsigned int size,
struct nft_data_desc *desc, const struct nlattr *nla);
+void nft_data_hold(const struct nft_data *data, enum nft_data_types type);
void nft_data_release(const struct nft_data *data, enum nft_data_types type);
int nft_data_dump(struct sk_buff *skb, int attr, const struct nft_data *data,
enum nft_data_types type, unsigned int len);
@@ -731,6 +732,10 @@
int (*init)(const struct nft_ctx *ctx,
const struct nft_expr *expr,
const struct nlattr * const tb[]);
+ void (*activate)(const struct nft_ctx *ctx,
+ const struct nft_expr *expr);
+ void (*deactivate)(const struct nft_ctx *ctx,
+ const struct nft_expr *expr);
void (*destroy)(const struct nft_ctx *ctx,
const struct nft_expr *expr);
int (*dump)(struct sk_buff *skb,
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index 08f3d86..5a24b4c 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -3558,6 +3558,20 @@
return 0;
}
+static inline bool ib_access_writable(int access_flags)
+{
+ /*
+ * We have writable memory backing the MR if any of the following
+ * access flags are set. "Local write" and "remote write" obviously
+ * require write access. "Remote atomic" can do things like fetch and
+ * add, which will modify memory, and "MW bind" can change permissions
+ * by binding a window.
+ */
+ return access_flags &
+ (IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE |
+ IB_ACCESS_REMOTE_ATOMIC | IB_ACCESS_MW_BIND);
+}
+
/**
* ib_check_mr_status: lightweight check of MR status.
* This routine may provide status checks on a selected
diff --git a/include/rdma/rdma_vt.h b/include/rdma/rdma_vt.h
index 1ba84a78..c653af9 100644
--- a/include/rdma/rdma_vt.h
+++ b/include/rdma/rdma_vt.h
@@ -409,7 +409,7 @@
spinlock_t pending_lock; /* protect pending mmap list */
/* CQ */
- struct kthread_worker *worker; /* per device cq worker */
+ struct kthread_worker __rcu *worker; /* per device cq worker */
u32 n_cqs_allocated; /* number of CQs allocated for device */
spinlock_t n_cqs_lock; /* protect count of in use cqs */
diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h
index da10aa2..d447f24 100644
--- a/include/trace/events/sched.h
+++ b/include/trace/events/sched.h
@@ -435,7 +435,9 @@
memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
__entry->pid = tsk->pid;
__entry->oldprio = tsk->prio;
- __entry->newprio = pi_task ? pi_task->prio : tsk->prio;
+ __entry->newprio = pi_task ?
+ min(tsk->normal_prio, pi_task->prio) :
+ tsk->normal_prio;
/* XXX SCHED_DEADLINE bits missing */
),
diff --git a/include/uapi/drm/evdi_drm.h b/include/uapi/drm/evdi_drm.h
new file mode 100644
index 0000000..72b4b1a
--- /dev/null
+++ b/include/uapi/drm/evdi_drm.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2015 - 2017 DisplayLink (UK) Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef __UAPI_EVDI_DRM_H__
+#define __UAPI_EVDI_DRM_H__
+
+/* Output events sent from driver to evdi lib */
+#define DRM_EVDI_EVENT_UPDATE_READY 0x80000000
+#define DRM_EVDI_EVENT_DPMS 0x80000001
+#define DRM_EVDI_EVENT_MODE_CHANGED 0x80000002
+#define DRM_EVDI_EVENT_CRTC_STATE 0x80000003
+#define DRM_EVDI_EVENT_CURSOR_SET 0x80000004
+#define DRM_EVDI_EVENT_CURSOR_MOVE 0x80000005
+
+struct drm_evdi_event_update_ready {
+ struct drm_event base;
+};
+
+struct drm_evdi_event_dpms {
+ struct drm_event base;
+ int32_t mode;
+};
+
+struct drm_evdi_event_mode_changed {
+ struct drm_event base;
+ int32_t hdisplay;
+ int32_t vdisplay;
+ int32_t vrefresh;
+ int32_t bits_per_pixel;
+ uint32_t pixel_format;
+};
+
+struct drm_evdi_event_crtc_state {
+ struct drm_event base;
+ int32_t state;
+};
+
+struct drm_evdi_connect {
+ int32_t connected;
+ int32_t dev_index;
+ const unsigned char * __user edid;
+ uint32_t edid_length;
+ uint32_t sku_area_limit;
+};
+
+struct drm_evdi_request_update {
+ int32_t reserved;
+};
+
+enum drm_evdi_grabpix_mode {
+ EVDI_GRABPIX_MODE_RECTS = 0,
+ EVDI_GRABPIX_MODE_DIRTY = 1,
+};
+
+struct drm_evdi_grabpix {
+ enum drm_evdi_grabpix_mode mode;
+ int32_t buf_width;
+ int32_t buf_height;
+ int32_t buf_byte_stride;
+ unsigned char __user *buffer;
+ int32_t num_rects;
+ struct drm_clip_rect __user *rects;
+};
+
+struct drm_evdi_event_cursor_set {
+ struct drm_event base;
+ int32_t hot_x;
+ int32_t hot_y;
+ uint32_t width;
+ uint32_t height;
+ uint8_t enabled;
+ uint32_t buffer_handle;
+ uint32_t buffer_length;
+ uint32_t pixel_format;
+ uint32_t stride;
+};
+
+struct drm_evdi_event_cursor_move {
+ struct drm_event base;
+ int32_t x;
+ int32_t y;
+};
+
+/* Input ioctls from evdi lib to driver */
+#define DRM_EVDI_CONNECT 0x00
+#define DRM_EVDI_REQUEST_UPDATE 0x01
+#define DRM_EVDI_GRABPIX 0x02
+/* LAST_IOCTL 0x5F -- 96 driver specific ioctls to use */
+
+#define DRM_IOCTL_EVDI_CONNECT DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_EVDI_CONNECT, struct drm_evdi_connect)
+#define DRM_IOCTL_EVDI_REQUEST_UPDATE DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_EVDI_REQUEST_UPDATE, struct drm_evdi_request_update)
+#define DRM_IOCTL_EVDI_GRABPIX DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_EVDI_GRABPIX, struct drm_evdi_grabpix)
+
+#endif /* __EVDI_UAPI_DRM_H__ */
+
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 6e80501..f4cab5b 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -58,7 +58,8 @@
__u64 eop_buffer_address; /* to KFD */
__u64 eop_buffer_size; /* to KFD */
__u64 ctx_save_restore_address; /* to KFD */
- __u64 ctx_save_restore_size; /* to KFD */
+ __u32 ctx_save_restore_size; /* to KFD */
+ __u32 ctl_stack_size; /* to KFD */
};
struct kfd_ioctl_destroy_queue_args {
@@ -261,6 +262,13 @@
*/
};
+struct kfd_ioctl_set_trap_handler_args {
+ uint64_t tba_addr; /* to KFD */
+ uint64_t tma_addr; /* to KFD */
+ uint32_t gpu_id; /* to KFD */
+ uint32_t pad;
+};
+
#define AMDKFD_IOCTL_BASE 'K'
#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
@@ -321,7 +329,10 @@
#define AMDKFD_IOC_GET_TILE_CONFIG \
AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
+#define AMDKFD_IOC_SET_TRAP_HANDLER \
+ AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
+
#define AMDKFD_COMMAND_START 0x01
-#define AMDKFD_COMMAND_END 0x13
+#define AMDKFD_COMMAND_END 0x14
#endif
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 87c2c84..09227ad 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -940,9 +940,13 @@
#define PCI_SATA_SIZEOF_LONG 16
/* Resizable BARs */
+#define PCI_REBAR_CAP 4 /* capability register */
+#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */
#define PCI_REBAR_CTRL 8 /* control register */
-#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
-#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
+#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */
+#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */
+#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */
+#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */
/* Dynamic Power Allocation */
#define PCI_DPA_CAP 4 /* capability register */
diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c
index e12d351..a37a3b4 100644
--- a/kernel/irq/affinity.c
+++ b/kernel/irq/affinity.c
@@ -39,7 +39,7 @@
}
}
-static cpumask_var_t *alloc_node_to_present_cpumask(void)
+static cpumask_var_t *alloc_node_to_possible_cpumask(void)
{
cpumask_var_t *masks;
int node;
@@ -62,7 +62,7 @@
return NULL;
}
-static void free_node_to_present_cpumask(cpumask_var_t *masks)
+static void free_node_to_possible_cpumask(cpumask_var_t *masks)
{
int node;
@@ -71,22 +71,22 @@
kfree(masks);
}
-static void build_node_to_present_cpumask(cpumask_var_t *masks)
+static void build_node_to_possible_cpumask(cpumask_var_t *masks)
{
int cpu;
- for_each_present_cpu(cpu)
+ for_each_possible_cpu(cpu)
cpumask_set_cpu(cpu, masks[cpu_to_node(cpu)]);
}
-static int get_nodes_in_cpumask(cpumask_var_t *node_to_present_cpumask,
+static int get_nodes_in_cpumask(cpumask_var_t *node_to_possible_cpumask,
const struct cpumask *mask, nodemask_t *nodemsk)
{
int n, nodes = 0;
/* Calculate the number of nodes in the supplied affinity mask */
for_each_node(n) {
- if (cpumask_intersects(mask, node_to_present_cpumask[n])) {
+ if (cpumask_intersects(mask, node_to_possible_cpumask[n])) {
node_set(n, *nodemsk);
nodes++;
}
@@ -109,7 +109,7 @@
int last_affv = affv + affd->pre_vectors;
nodemask_t nodemsk = NODE_MASK_NONE;
struct cpumask *masks;
- cpumask_var_t nmsk, *node_to_present_cpumask;
+ cpumask_var_t nmsk, *node_to_possible_cpumask;
/*
* If there aren't any vectors left after applying the pre/post
@@ -125,8 +125,8 @@
if (!masks)
goto out;
- node_to_present_cpumask = alloc_node_to_present_cpumask();
- if (!node_to_present_cpumask)
+ node_to_possible_cpumask = alloc_node_to_possible_cpumask();
+ if (!node_to_possible_cpumask)
goto out;
/* Fill out vectors at the beginning that don't need affinity */
@@ -135,8 +135,8 @@
/* Stabilize the cpumasks */
get_online_cpus();
- build_node_to_present_cpumask(node_to_present_cpumask);
- nodes = get_nodes_in_cpumask(node_to_present_cpumask, cpu_present_mask,
+ build_node_to_possible_cpumask(node_to_possible_cpumask);
+ nodes = get_nodes_in_cpumask(node_to_possible_cpumask, cpu_possible_mask,
&nodemsk);
/*
@@ -146,7 +146,7 @@
if (affv <= nodes) {
for_each_node_mask(n, nodemsk) {
cpumask_copy(masks + curvec,
- node_to_present_cpumask[n]);
+ node_to_possible_cpumask[n]);
if (++curvec == last_affv)
break;
}
@@ -160,7 +160,7 @@
vecs_per_node = (affv - (curvec - affd->pre_vectors)) / nodes;
/* Get the cpus on this node which are in the mask */
- cpumask_and(nmsk, cpu_present_mask, node_to_present_cpumask[n]);
+ cpumask_and(nmsk, cpu_possible_mask, node_to_possible_cpumask[n]);
/* Calculate the number of cpus per vector */
ncpus = cpumask_weight(nmsk);
@@ -192,7 +192,7 @@
/* Fill out vectors at the end that don't need affinity */
for (; curvec < nvecs; curvec++)
cpumask_copy(masks + curvec, irq_default_affinity);
- free_node_to_present_cpumask(node_to_present_cpumask);
+ free_node_to_possible_cpumask(node_to_possible_cpumask);
out:
free_cpumask_var(nmsk);
return masks;
@@ -214,7 +214,7 @@
return 0;
get_online_cpus();
- ret = min_t(int, cpumask_weight(cpu_present_mask), vecs) + resv;
+ ret = min_t(int, cpumask_weight(cpu_possible_mask), vecs) + resv;
put_online_cpus();
return ret;
}
diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c
index 82afb7e..e97bbae 100644
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -27,7 +27,7 @@
#if defined(CONFIG_SMP)
static int __init irq_affinity_setup(char *str)
{
- zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
+ alloc_bootmem_cpumask_var(&irq_default_affinity);
cpulist_parse(str, irq_default_affinity);
/*
* Set at least the boot cpu. We don't want to end up with
@@ -40,10 +40,8 @@
static void __init init_irq_default_affinity(void)
{
-#ifdef CONFIG_CPUMASK_OFFSTACK
- if (!irq_default_affinity)
+ if (!cpumask_available(irq_default_affinity))
zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
-#endif
if (cpumask_empty(irq_default_affinity))
cpumask_setall(irq_default_affinity);
}
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index 6964e8c..35cd3b7 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -75,8 +75,10 @@
s2idle_state = S2IDLE_STATE_NONE;
}
-static void s2idle_enter(void)
+static int s2idle_enter(void)
{
+ int error = 0;
+
trace_suspend_resume(TPS("machine_suspend"), PM_SUSPEND_TO_IDLE, true);
spin_lock_irq(&s2idle_lock);
@@ -87,7 +89,7 @@
spin_unlock_irq(&s2idle_lock);
get_online_cpus();
- cpuidle_resume();
+ cpuidle_prepare_freeze();
/* Push all the CPUs into the idle loop. */
wake_up_all_idle_cpus();
@@ -95,7 +97,7 @@
wait_event(s2idle_wait_head,
s2idle_state == S2IDLE_STATE_WAKE);
- cpuidle_pause();
+ error = cpuidle_complete_freeze();
put_online_cpus();
spin_lock_irq(&s2idle_lock);
@@ -105,10 +107,12 @@
spin_unlock_irq(&s2idle_lock);
trace_suspend_resume(TPS("machine_suspend"), PM_SUSPEND_TO_IDLE, false);
+ return error;
}
-static void s2idle_loop(void)
+static int s2idle_loop(void)
{
+ int ret = 0;
pm_pr_dbg("suspend-to-idle\n");
for (;;) {
@@ -127,7 +131,7 @@
*/
error = dpm_noirq_suspend_devices(PMSG_SUSPEND);
if (!error)
- s2idle_enter();
+ ret = s2idle_enter();
else if (error == -EBUSY && pm_wakeup_pending())
error = 0;
@@ -144,13 +148,14 @@
if (s2idle_ops && s2idle_ops->sync)
s2idle_ops->sync();
- if (pm_wakeup_pending())
+ if (ret < 0 || pm_wakeup_pending())
break;
pm_wakeup_clear(false);
}
pm_pr_dbg("resume from suspend-to-idle\n");
+ return ret;
}
void s2idle_wake(void)
@@ -407,7 +412,7 @@
goto Devices_early_resume;
if (state == PM_SUSPEND_TO_IDLE && pm_test_level != TEST_PLATFORM) {
- s2idle_loop();
+ error = s2idle_loop();
goto Platform_early_resume;
}
diff --git a/kernel/power/user.c b/kernel/power/user.c
index 22df9f7..69017a5 100644
--- a/kernel/power/user.c
+++ b/kernel/power/user.c
@@ -186,6 +186,11 @@
res = PAGE_SIZE - pg_offp;
}
+ if (!data_of(data->handle)) {
+ res = -EINVAL;
+ goto unlock;
+ }
+
res = simple_write_to_buffer(data_of(data->handle), res, &pg_offp,
buf, count);
if (res > 0)
diff --git a/kernel/printk/printk_safe.c b/kernel/printk/printk_safe.c
index 3cdaeae..d989cc2 100644
--- a/kernel/printk/printk_safe.c
+++ b/kernel/printk/printk_safe.c
@@ -85,6 +85,7 @@
{
int add;
size_t len;
+ va_list ap;
again:
len = atomic_read(&s->len);
@@ -103,7 +104,9 @@
if (!len)
smp_rmb();
- add = vscnprintf(s->buffer + len, sizeof(s->buffer) - len, fmt, args);
+ va_copy(ap, args);
+ add = vscnprintf(s->buffer + len, sizeof(s->buffer) - len, fmt, ap);
+ va_end(ap);
if (!add)
return 0;
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 0532a31..2b0bf13 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -894,6 +894,33 @@
}
#ifdef CONFIG_SMP
+
+static inline bool is_per_cpu_kthread(struct task_struct *p)
+{
+ if (!(p->flags & PF_KTHREAD))
+ return false;
+
+ if (p->nr_cpus_allowed != 1)
+ return false;
+
+ return true;
+}
+
+/*
+ * Per-CPU kthreads are allowed to run on !actie && online CPUs, see
+ * __set_cpus_allowed_ptr() and select_fallback_rq().
+ */
+static inline bool is_cpu_allowed(struct task_struct *p, int cpu)
+{
+ if (!cpumask_test_cpu(cpu, &p->cpus_allowed))
+ return false;
+
+ if (is_per_cpu_kthread(p))
+ return cpu_online(cpu);
+
+ return cpu_active(cpu);
+}
+
/*
* This is how migration works:
*
@@ -951,16 +978,8 @@
static struct rq *__migrate_task(struct rq *rq, struct rq_flags *rf,
struct task_struct *p, int dest_cpu)
{
- if (p->flags & PF_KTHREAD) {
- if (unlikely(!cpu_online(dest_cpu)))
- return rq;
- } else {
- if (unlikely(!cpu_active(dest_cpu)))
- return rq;
- }
-
/* Affinity changed (again). */
- if (!cpumask_test_cpu(dest_cpu, &p->cpus_allowed))
+ if (!is_cpu_allowed(p, dest_cpu))
return rq;
update_rq_clock(rq);
@@ -1489,10 +1508,9 @@
for (;;) {
/* Any allowed, online CPU? */
for_each_cpu(dest_cpu, &p->cpus_allowed) {
- if (!(p->flags & PF_KTHREAD) && !cpu_active(dest_cpu))
+ if (!is_cpu_allowed(p, dest_cpu))
continue;
- if (!cpu_online(dest_cpu))
- continue;
+
goto out;
}
@@ -1555,8 +1573,7 @@
* [ this allows ->select_task() to simply return task_cpu(p) and
* not worry about this generic constraint ]
*/
- if (unlikely(!cpumask_test_cpu(cpu, &p->cpus_allowed) ||
- !cpu_online(cpu)))
+ if (unlikely(!is_cpu_allowed(p, cpu)))
cpu = select_fallback_rq(task_cpu(p), p);
return cpu;
diff --git a/kernel/time/tick-common.c b/kernel/time/tick-common.c
index 49edc1c..2a871c4 100644
--- a/kernel/time/tick-common.c
+++ b/kernel/time/tick-common.c
@@ -499,6 +499,84 @@
}
/**
+ * tick_set_freeze_event - Set timer to wake up the CPU from freeze.
+ *
+ * @cpu: CPU to set the clock event for
+ * @delta: time to wait before waking the CPU
+ *
+ * Returns 0 on success and -EERROR on failure.
+ */
+int tick_set_freeze_event(int cpu, ktime_t delta)
+{
+ struct clock_event_device *dev = per_cpu(tick_cpu_device, cpu).evtdev;
+ u64 delta_ns;
+ int ret;
+
+ if (!dev->set_next_event ||
+ !(dev->features & CLOCK_EVT_FEAT_FREEZE_NONSTOP)) {
+ printk_deferred(KERN_WARNING
+ "[%s] unsupported by clock event device\n",
+ __func__);
+ return -EPERM;
+ }
+
+ if (!clockevent_state_shutdown(dev)) {
+ printk_deferred(KERN_WARNING
+ "[%s] clock event device in use\n",
+ __func__);
+ return -EBUSY;
+ }
+
+ delta_ns = ktime_to_ns(delta);
+ if (delta_ns > dev->max_delta_ns || delta_ns < dev->min_delta_ns) {
+ printk_deferred(KERN_WARNING
+ "[%s] %lluns outside range: [%lluns, %lluns]\n",
+ __func__, delta_ns, dev->min_delta_ns,
+ dev->max_delta_ns);
+ return -ERANGE;
+ }
+ clockevents_tick_resume(dev);
+ clockevents_switch_state(dev, CLOCK_EVT_STATE_ONESHOT);
+ ret = dev->set_next_event((delta_ns * dev->mult) >> dev->shift, dev);
+ if (ret < 0) {
+ printk_deferred(KERN_WARNING
+ "Failed to program freeze event\n");
+ clockevents_shutdown(dev);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(tick_set_freeze_event);
+
+/**
+ * tick_clear_freeze_event - Shuts down the clock device after programming a
+ * freeze event.
+ *
+ * @cpu: CPU to shutdown the clock device for
+ *
+ * Returns 0 on success and -EERROR otherwise.
+ */
+int tick_clear_freeze_event(int cpu)
+{
+ struct clock_event_device *dev = per_cpu(tick_cpu_device, cpu).evtdev;
+ int ret;
+
+ if (!(dev && dev->event_expired))
+ return 0;
+
+ /* Must be called in oneshot mode and while
+ * timekeeping is suspended */
+ if (!(clockevent_state_oneshot(dev) && timekeeping_suspended))
+ return 0;
+
+ ret = dev->event_expired(dev);
+ clockevents_shutdown(dev);
+ return ret;
+
+}
+EXPORT_SYMBOL_GPL(tick_clear_freeze_event);
+
+/**
* tick_unfreeze - Resume the local tick and (possibly) timekeeping.
*
* Check if this is the first CPU executing the function and if so, resume
diff --git a/kernel/time/time.c b/kernel/time/time.c
index 44a8c14..319935a 100644
--- a/kernel/time/time.c
+++ b/kernel/time/time.c
@@ -28,6 +28,7 @@
*/
#include <linux/export.h>
+#include <linux/kernel.h>
#include <linux/timex.h>
#include <linux/capability.h>
#include <linux/timekeeper_internal.h>
@@ -348,9 +349,10 @@
return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);
#else
# if BITS_PER_LONG == 32
- return (HZ_TO_MSEC_MUL32 * j) >> HZ_TO_MSEC_SHR32;
+ return (HZ_TO_MSEC_MUL32 * j + (1ULL << HZ_TO_MSEC_SHR32) - 1) >>
+ HZ_TO_MSEC_SHR32;
# else
- return (j * HZ_TO_MSEC_NUM) / HZ_TO_MSEC_DEN;
+ return DIV_ROUND_UP(j * HZ_TO_MSEC_NUM, HZ_TO_MSEC_DEN);
# endif
#endif
}
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index d0be1f1..b834a21 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3359,8 +3359,8 @@
print_event_info(buf, m);
- seq_printf(m, "# TASK-PID CPU# %s TIMESTAMP FUNCTION\n", tgid ? "TGID " : "");
- seq_printf(m, "# | | | %s | |\n", tgid ? " | " : "");
+ seq_printf(m, "# TASK-PID %s CPU# TIMESTAMP FUNCTION\n", tgid ? "TGID " : "");
+ seq_printf(m, "# | | %s | | |\n", tgid ? " | " : "");
}
static void print_func_help_header_irq(struct trace_buffer *buf, struct seq_file *m,
@@ -3380,9 +3380,9 @@
tgid ? tgid_space : space);
seq_printf(m, "# %s||| / delay\n",
tgid ? tgid_space : space);
- seq_printf(m, "# TASK-PID CPU#%s|||| TIMESTAMP FUNCTION\n",
+ seq_printf(m, "# TASK-PID %sCPU# |||| TIMESTAMP FUNCTION\n",
tgid ? " TGID " : space);
- seq_printf(m, "# | | | %s|||| | |\n",
+ seq_printf(m, "# | | %s | |||| | |\n",
tgid ? " | " : space);
}
diff --git a/kernel/trace/trace_functions_graph.c b/kernel/trace/trace_functions_graph.c
index 23c0b0c..169b3c4 100644
--- a/kernel/trace/trace_functions_graph.c
+++ b/kernel/trace/trace_functions_graph.c
@@ -831,6 +831,7 @@
struct ftrace_graph_ret *graph_ret;
struct ftrace_graph_ent *call;
unsigned long long duration;
+ int cpu = iter->cpu;
int i;
graph_ret = &ret_entry->ret;
@@ -839,7 +840,6 @@
if (data) {
struct fgraph_cpu_data *cpu_data;
- int cpu = iter->cpu;
cpu_data = per_cpu_ptr(data->cpu_data, cpu);
@@ -869,6 +869,9 @@
trace_seq_printf(s, "%ps();\n", (void *)call->func);
+ print_graph_irq(iter, graph_ret->func, TRACE_GRAPH_RET,
+ cpu, iter->ent->pid, flags);
+
return trace_handle_return(s);
}
diff --git a/kernel/trace/trace_output.c b/kernel/trace/trace_output.c
index c738e76..4500b00 100644
--- a/kernel/trace/trace_output.c
+++ b/kernel/trace/trace_output.c
@@ -594,8 +594,7 @@
trace_find_cmdline(entry->pid, comm);
- trace_seq_printf(s, "%16s-%-5d [%03d] ",
- comm, entry->pid, iter->cpu);
+ trace_seq_printf(s, "%16s-%-5d ", comm, entry->pid);
if (tr->trace_flags & TRACE_ITER_RECORD_TGID) {
unsigned int tgid = trace_find_tgid(entry->pid);
@@ -606,6 +605,8 @@
trace_seq_printf(s, "(%5d) ", tgid);
}
+ trace_seq_printf(s, "[%03d] ", iter->cpu);
+
if (tr->trace_flags & TRACE_ITER_IRQ_INFO)
trace_print_lat_fmt(s, entry);
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 86c3385..4a990f3 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -1392,9 +1392,6 @@
return string(buf, end, NULL, spec);
switch (fmt[1]) {
- case 'r':
- return number(buf, end, clk_get_rate(clk), spec);
-
case 'n':
default:
#ifdef CONFIG_COMMON_CLK
diff --git a/mm/gup.c b/mm/gup.c
index d2ba0be..4cc8a6f 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -1235,8 +1235,6 @@
int locked = 0;
long ret = 0;
- VM_BUG_ON(start & ~PAGE_MASK);
- VM_BUG_ON(len != PAGE_ALIGN(len));
end = start + len;
for (nstart = start; nstart < end; nstart = nend) {
@@ -1469,32 +1467,48 @@
return 1;
}
-static int __gup_device_huge_pmd(pmd_t pmd, unsigned long addr,
+static int __gup_device_huge_pmd(pmd_t orig, pmd_t *pmdp, unsigned long addr,
unsigned long end, struct page **pages, int *nr)
{
unsigned long fault_pfn;
+ int nr_start = *nr;
- fault_pfn = pmd_pfn(pmd) + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
- return __gup_device_huge(fault_pfn, addr, end, pages, nr);
+ fault_pfn = pmd_pfn(orig) + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
+ if (!__gup_device_huge(fault_pfn, addr, end, pages, nr))
+ return 0;
+
+ if (unlikely(pmd_val(orig) != pmd_val(*pmdp))) {
+ undo_dev_pagemap(nr, nr_start, pages);
+ return 0;
+ }
+ return 1;
}
-static int __gup_device_huge_pud(pud_t pud, unsigned long addr,
+static int __gup_device_huge_pud(pud_t orig, pud_t *pudp, unsigned long addr,
unsigned long end, struct page **pages, int *nr)
{
unsigned long fault_pfn;
+ int nr_start = *nr;
- fault_pfn = pud_pfn(pud) + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
- return __gup_device_huge(fault_pfn, addr, end, pages, nr);
+ fault_pfn = pud_pfn(orig) + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
+ if (!__gup_device_huge(fault_pfn, addr, end, pages, nr))
+ return 0;
+
+ if (unlikely(pud_val(orig) != pud_val(*pudp))) {
+ undo_dev_pagemap(nr, nr_start, pages);
+ return 0;
+ }
+ return 1;
}
#else
-static int __gup_device_huge_pmd(pmd_t pmd, unsigned long addr,
+static int __gup_device_huge_pmd(pmd_t orig, pmd_t *pmdp, unsigned long addr,
unsigned long end, struct page **pages, int *nr)
{
BUILD_BUG();
return 0;
}
-static int __gup_device_huge_pud(pud_t pud, unsigned long addr,
+static int __gup_device_huge_pud(pud_t pud, pud_t *pudp, unsigned long addr,
unsigned long end, struct page **pages, int *nr)
{
BUILD_BUG();
@@ -1512,7 +1526,7 @@
return 0;
if (pmd_devmap(orig))
- return __gup_device_huge_pmd(orig, addr, end, pages, nr);
+ return __gup_device_huge_pmd(orig, pmdp, addr, end, pages, nr);
refs = 0;
page = pmd_page(orig) + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
@@ -1550,7 +1564,7 @@
return 0;
if (pud_devmap(orig))
- return __gup_device_huge_pud(orig, addr, end, pages, nr);
+ return __gup_device_huge_pud(orig, pudp, addr, end, pages, nr);
refs = 0;
page = pud_page(orig) + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index b1f841a..dfd2947 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -2159,6 +2159,7 @@
*/
if (hstate_is_gigantic(h))
adjust_managed_page_count(page, 1 << h->order);
+ cond_resched();
}
}
diff --git a/mm/ksm.c b/mm/ksm.c
index fdc8746..f50cc57 100644
--- a/mm/ksm.c
+++ b/mm/ksm.c
@@ -199,6 +199,8 @@
#define SEQNR_MASK 0x0ff /* low bits of unstable tree seqnr */
#define UNSTABLE_FLAG 0x100 /* is a node of the unstable tree */
#define STABLE_FLAG 0x200 /* is listed from the stable tree */
+#define KSM_FLAG_MASK (SEQNR_MASK|UNSTABLE_FLAG|STABLE_FLAG)
+ /* to mask all the flags */
/* The stable and unstable tree heads */
static struct rb_root one_stable_tree[1] = { RB_ROOT };
@@ -2562,10 +2564,15 @@
anon_vma_lock_read(anon_vma);
anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root,
0, ULONG_MAX) {
+ unsigned long addr;
+
cond_resched();
vma = vmac->vma;
- if (rmap_item->address < vma->vm_start ||
- rmap_item->address >= vma->vm_end)
+
+ /* Ignore the stable/unstable/sqnr flags */
+ addr = rmap_item->address & ~KSM_FLAG_MASK;
+
+ if (addr < vma->vm_start || addr >= vma->vm_end)
continue;
/*
* Initially we examine only the vma which covers this
@@ -2579,8 +2586,7 @@
if (rwc->invalid_vma && rwc->invalid_vma(vma, rwc->arg))
continue;
- if (!rwc->rmap_one(page, vma,
- rmap_item->address, rwc->arg)) {
+ if (!rwc->rmap_one(page, vma, addr, rwc->arg)) {
anon_vma_unlock_read(anon_vma);
return;
}
diff --git a/mm/low-mem-notify.c b/mm/low-mem-notify.c
index 0a7b071..ce3c4e8 100644
--- a/mm/low-mem-notify.c
+++ b/mm/low-mem-notify.c
@@ -189,8 +189,7 @@
struct kobj_attribute *attr,
char *buf)
{
- const int lru_base = NR_LRU_BASE - LRU_BASE;
- unsigned long available_mem = get_available_mem_adj(lru_base);
+ unsigned long available_mem = get_available_mem_adj();
return sprintf(buf, "%lu\n",
available_mem / (1024 * 1024 / PAGE_SIZE));
diff --git a/mm/memory-failure.c b/mm/memory-failure.c
index 1cd3b35..345e69d 100644
--- a/mm/memory-failure.c
+++ b/mm/memory-failure.c
@@ -508,6 +508,7 @@
[MF_MSG_POISONED_HUGE] = "huge page already hardware poisoned",
[MF_MSG_HUGE] = "huge page",
[MF_MSG_FREE_HUGE] = "free huge page",
+ [MF_MSG_NON_PMD_HUGE] = "non-pmd-sized huge page",
[MF_MSG_UNMAP_FAILED] = "unmapping failed page",
[MF_MSG_DIRTY_SWAPCACHE] = "dirty swapcache page",
[MF_MSG_CLEAN_SWAPCACHE] = "clean swapcache page",
@@ -1090,6 +1091,21 @@
return 0;
}
+ /*
+ * TODO: hwpoison for pud-sized hugetlb doesn't work right now, so
+ * simply disable it. In order to make it work properly, we need
+ * make sure that:
+ * - conversion of a pud that maps an error hugetlb into hwpoison
+ * entry properly works, and
+ * - other mm code walking over page table is aware of pud-aligned
+ * hwpoison entries.
+ */
+ if (huge_page_size(page_hstate(head)) > PMD_SIZE) {
+ action_result(pfn, MF_MSG_NON_PMD_HUGE, MF_IGNORED);
+ res = -EBUSY;
+ goto out;
+ }
+
if (!hwpoison_user_mappings(p, pfn, trapno, flags, &head)) {
action_result(pfn, MF_MSG_UNMAP_FAILED, MF_IGNORED);
res = -EBUSY;
diff --git a/mm/mmap.c b/mm/mmap.c
index 4641e73..caa55ba 100644
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -177,8 +177,8 @@
return next;
}
-static int do_brk(unsigned long addr, unsigned long len, struct list_head *uf);
-
+static int do_brk_flags(unsigned long addr, unsigned long request, unsigned long flags,
+ struct list_head *uf);
SYSCALL_DEFINE1(brk, unsigned long, brk)
{
unsigned long retval;
@@ -236,7 +236,7 @@
goto out;
/* Ok, looks good - let it rip. */
- if (do_brk(oldbrk, newbrk-oldbrk, &uf) < 0)
+ if (do_brk_flags(oldbrk, newbrk-oldbrk, 0, &uf) < 0)
goto out;
set_brk:
@@ -2897,21 +2897,14 @@
* anonymous maps. eventually we may be able to do some
* brk-specific accounting here.
*/
-static int do_brk_flags(unsigned long addr, unsigned long request, unsigned long flags, struct list_head *uf)
+static int do_brk_flags(unsigned long addr, unsigned long len, unsigned long flags, struct list_head *uf)
{
struct mm_struct *mm = current->mm;
struct vm_area_struct *vma, *prev;
- unsigned long len;
struct rb_node **rb_link, *rb_parent;
pgoff_t pgoff = addr >> PAGE_SHIFT;
int error;
- len = PAGE_ALIGN(request);
- if (len < request)
- return -ENOMEM;
- if (!len)
- return 0;
-
/* Until we need other flags, refuse anything except VM_EXEC. */
if ((flags & (~VM_EXEC)) != 0)
return -EINVAL;
@@ -2983,18 +2976,20 @@
return 0;
}
-static int do_brk(unsigned long addr, unsigned long len, struct list_head *uf)
-{
- return do_brk_flags(addr, len, 0, uf);
-}
-
-int vm_brk_flags(unsigned long addr, unsigned long len, unsigned long flags)
+int vm_brk_flags(unsigned long addr, unsigned long request, unsigned long flags)
{
struct mm_struct *mm = current->mm;
+ unsigned long len;
int ret;
bool populate;
LIST_HEAD(uf);
+ len = PAGE_ALIGN(request);
+ if (len < request)
+ return -ENOMEM;
+ if (!len)
+ return 0;
+
if (down_write_killable(&mm->mmap_sem))
return -EINTR;
diff --git a/mm/rmap.c b/mm/rmap.c
index b874c47..97edcf4 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -64,6 +64,7 @@
#include <linux/backing-dev.h>
#include <linux/page_idle.h>
#include <linux/memremap.h>
+#include <linux/userfaultfd_k.h>
#include <asm/tlbflush.h>
@@ -1476,11 +1477,16 @@
set_pte_at(mm, address, pvmw.pte, pteval);
}
- } else if (pte_unused(pteval)) {
+ } else if (pte_unused(pteval) && !userfaultfd_armed(vma)) {
/*
* The guest indicated that the page content is of no
* interest anymore. Simply discard the pte, vmscan
* will take care of the rest.
+ * A future reference will then fault in a new zero
+ * page. When userfaultfd is active, we must not drop
+ * this page though, as its main user (postcopy
+ * migration) will not expect userfaults on already
+ * copied pages.
*/
dec_mm_counter(mm, mm_counter(page));
} else if (IS_ENABLED(CONFIG_MIGRATION) &&
diff --git a/mm/slab_common.c b/mm/slab_common.c
index 65212ca..91d271b 100644
--- a/mm/slab_common.c
+++ b/mm/slab_common.c
@@ -546,10 +546,14 @@
list_del(&s->list);
if (s->flags & SLAB_TYPESAFE_BY_RCU) {
+#ifdef SLAB_SUPPORTS_SYSFS
+ sysfs_slab_unlink(s);
+#endif
list_add_tail(&s->list, &slab_caches_to_rcu_destroy);
schedule_work(&slab_caches_to_rcu_destroy_work);
} else {
#ifdef SLAB_SUPPORTS_SYSFS
+ sysfs_slab_unlink(s);
sysfs_slab_release(s);
#else
slab_kmem_cache_release(s);
diff --git a/mm/slub.c b/mm/slub.c
index 41c0169..c38e71c 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -5660,7 +5660,6 @@
kset_unregister(s->memcg_kset);
#endif
kobject_uevent(&s->kobj, KOBJ_REMOVE);
- kobject_del(&s->kobj);
out:
kobject_put(&s->kobj);
}
@@ -5745,6 +5744,12 @@
schedule_work(&s->kobj_remove_work);
}
+void sysfs_slab_unlink(struct kmem_cache *s)
+{
+ if (slab_state >= FULL)
+ kobject_del(&s->kobj);
+}
+
void sysfs_slab_release(struct kmem_cache *s)
{
if (slab_state >= FULL)
diff --git a/mm/vmstat.c b/mm/vmstat.c
index e085b13..4bb13e7 100644
--- a/mm/vmstat.c
+++ b/mm/vmstat.c
@@ -1770,11 +1770,9 @@
* to occur in the future. Keep on running the
* update worker thread.
*/
- preempt_disable();
queue_delayed_work_on(smp_processor_id(), mm_percpu_wq,
this_cpu_ptr(&vmstat_work),
round_jiffies_relative(sysctl_stat_interval));
- preempt_enable();
}
}
diff --git a/mm/z3fold.c b/mm/z3fold.c
index faac9d4..66582d8 100644
--- a/mm/z3fold.c
+++ b/mm/z3fold.c
@@ -746,6 +746,9 @@
}
if (bud == HEADLESS) {
+ if (test_bit(UNDER_RECLAIM, &page->private))
+ return;
+
spin_lock(&pool->lock);
list_del(&page->lru);
spin_unlock(&pool->lock);
@@ -836,20 +839,20 @@
}
list_for_each_prev(pos, &pool->lru) {
page = list_entry(pos, struct page, lru);
+ zhdr = page_address(page);
if (test_bit(PAGE_HEADLESS, &page->private))
/* candidate found */
break;
- zhdr = page_address(page);
if (!z3fold_page_trylock(zhdr))
continue; /* can't evict at this point */
kref_get(&zhdr->refcount);
list_del_init(&zhdr->buddy);
zhdr->cpu = -1;
- set_bit(UNDER_RECLAIM, &page->private);
break;
}
+ set_bit(UNDER_RECLAIM, &page->private);
list_del_init(&page->lru);
spin_unlock(&pool->lock);
@@ -898,6 +901,7 @@
if (test_bit(PAGE_HEADLESS, &page->private)) {
if (ret == 0) {
free_z3fold_page(page);
+ atomic64_dec(&pool->pages_nr);
return 0;
}
spin_lock(&pool->lock);
diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c
index 5b8cd35..25738b2 100644
--- a/net/bridge/netfilter/ebtables.c
+++ b/net/bridge/netfilter/ebtables.c
@@ -696,6 +696,8 @@
}
i = 0;
+ memset(&mtpar, 0, sizeof(mtpar));
+ memset(&tgpar, 0, sizeof(tgpar));
mtpar.net = tgpar.net = net;
mtpar.table = tgpar.table = name;
mtpar.entryinfo = tgpar.entryinfo = e;
@@ -1950,7 +1952,8 @@
int off, pad = 0;
unsigned int size_kern, match_size = mwt->match_size;
- strlcpy(name, mwt->u.name, sizeof(name));
+ if (strscpy(name, mwt->u.name, sizeof(name)) < 0)
+ return -EINVAL;
if (state->buf_kern_start)
dst = state->buf_kern_start + state->buf_kern_offset;
diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c
index 1a925f2..114d4be 100644
--- a/net/ipv4/netfilter/ip_tables.c
+++ b/net/ipv4/netfilter/ip_tables.c
@@ -541,6 +541,7 @@
return -ENOMEM;
j = 0;
+ memset(&mtpar, 0, sizeof(mtpar));
mtpar.net = net;
mtpar.table = name;
mtpar.entryinfo = &e->ip;
diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c
index c5fe42e..2e51e01 100644
--- a/net/ipv6/netfilter/ip6_tables.c
+++ b/net/ipv6/netfilter/ip6_tables.c
@@ -561,6 +561,7 @@
return -ENOMEM;
j = 0;
+ memset(&mtpar, 0, sizeof(mtpar));
mtpar.net = net;
mtpar.table = name;
mtpar.entryinfo = &e->ipv6;
diff --git a/net/ipv6/netfilter/ip6t_rpfilter.c b/net/ipv6/netfilter/ip6t_rpfilter.c
index b12e61b7..1c4a5de3f 100644
--- a/net/ipv6/netfilter/ip6t_rpfilter.c
+++ b/net/ipv6/netfilter/ip6t_rpfilter.c
@@ -48,10 +48,8 @@
}
fl6.flowi6_mark = flags & XT_RPFILTER_VALID_MARK ? skb->mark : 0;
- if ((flags & XT_RPFILTER_LOOSE) == 0) {
+ if ((flags & XT_RPFILTER_LOOSE) == 0)
fl6.flowi6_oif = dev->ifindex;
- lookup_flags |= RT6_LOOKUP_F_IFACE;
- }
rt = (void *) ip6_route_lookup(net, &fl6, lookup_flags);
if (rt->dst.error)
diff --git a/net/ipv6/netfilter/nft_fib_ipv6.c b/net/ipv6/netfilter/nft_fib_ipv6.c
index 54b5899..fd9a45c 100644
--- a/net/ipv6/netfilter/nft_fib_ipv6.c
+++ b/net/ipv6/netfilter/nft_fib_ipv6.c
@@ -182,7 +182,6 @@
}
*dest = 0;
- again:
rt = (void *)ip6_route_lookup(nft_net(pkt), &fl6, lookup_flags);
if (rt->dst.error)
goto put_rt_err;
@@ -191,15 +190,8 @@
if (rt->rt6i_flags & (RTF_REJECT | RTF_ANYCAST | RTF_LOCAL))
goto put_rt_err;
- if (oif && oif != rt->rt6i_idev->dev) {
- /* multipath route? Try again with F_IFACE */
- if ((lookup_flags & RT6_LOOKUP_F_IFACE) == 0) {
- lookup_flags |= RT6_LOOKUP_F_IFACE;
- fl6.flowi6_oif = oif->ifindex;
- ip6_rt_put(rt);
- goto again;
- }
- }
+ if (oif && oif != rt->rt6i_idev->dev)
+ goto put_rt_err;
switch (priv->result) {
case NFT_FIB_RESULT_OIF:
diff --git a/net/ipv6/xfrm6_policy.c b/net/ipv6/xfrm6_policy.c
index 17e95a0..d6b0122 100644
--- a/net/ipv6/xfrm6_policy.c
+++ b/net/ipv6/xfrm6_policy.c
@@ -123,7 +123,7 @@
struct flowi6 *fl6 = &fl->u.ip6;
int onlyproto = 0;
const struct ipv6hdr *hdr = ipv6_hdr(skb);
- u16 offset = sizeof(*hdr);
+ u32 offset = sizeof(*hdr);
struct ipv6_opt_hdr *exthdr;
const unsigned char *nh = skb_network_header(skb);
u16 nhoff = IP6CB(skb)->nhoff;
diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c
index e8f1556..327ebe7 100644
--- a/net/netfilter/ipvs/ip_vs_ctl.c
+++ b/net/netfilter/ipvs/ip_vs_ctl.c
@@ -2384,8 +2384,10 @@
struct ipvs_sync_daemon_cfg cfg;
memset(&cfg, 0, sizeof(cfg));
- strlcpy(cfg.mcast_ifn, dm->mcast_ifn,
- sizeof(cfg.mcast_ifn));
+ ret = -EINVAL;
+ if (strscpy(cfg.mcast_ifn, dm->mcast_ifn,
+ sizeof(cfg.mcast_ifn)) <= 0)
+ goto out_dec;
cfg.syncid = dm->syncid;
ret = start_sync_thread(ipvs, &cfg, dm->state);
} else {
@@ -2423,12 +2425,19 @@
}
}
+ if ((cmd == IP_VS_SO_SET_ADD || cmd == IP_VS_SO_SET_EDIT) &&
+ strnlen(usvc.sched_name, IP_VS_SCHEDNAME_MAXLEN) ==
+ IP_VS_SCHEDNAME_MAXLEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
/* Check for valid protocol: TCP or UDP or SCTP, even for fwmark!=0 */
if (usvc.protocol != IPPROTO_TCP && usvc.protocol != IPPROTO_UDP &&
usvc.protocol != IPPROTO_SCTP) {
- pr_err("set_ctl: invalid protocol: %d %pI4:%d %s\n",
+ pr_err("set_ctl: invalid protocol: %d %pI4:%d\n",
usvc.protocol, &usvc.addr.ip,
- ntohs(usvc.port), usvc.sched_name);
+ ntohs(usvc.port));
ret = -EFAULT;
goto out_unlock;
}
@@ -2850,7 +2859,7 @@
static const struct nla_policy ip_vs_daemon_policy[IPVS_DAEMON_ATTR_MAX + 1] = {
[IPVS_DAEMON_ATTR_STATE] = { .type = NLA_U32 },
[IPVS_DAEMON_ATTR_MCAST_IFN] = { .type = NLA_NUL_STRING,
- .len = IP_VS_IFNAME_MAXLEN },
+ .len = IP_VS_IFNAME_MAXLEN - 1 },
[IPVS_DAEMON_ATTR_SYNC_ID] = { .type = NLA_U32 },
[IPVS_DAEMON_ATTR_SYNC_MAXLEN] = { .type = NLA_U16 },
[IPVS_DAEMON_ATTR_MCAST_GROUP] = { .type = NLA_U32 },
@@ -2868,7 +2877,7 @@
[IPVS_SVC_ATTR_PORT] = { .type = NLA_U16 },
[IPVS_SVC_ATTR_FWMARK] = { .type = NLA_U32 },
[IPVS_SVC_ATTR_SCHED_NAME] = { .type = NLA_NUL_STRING,
- .len = IP_VS_SCHEDNAME_MAXLEN },
+ .len = IP_VS_SCHEDNAME_MAXLEN - 1 },
[IPVS_SVC_ATTR_PE_NAME] = { .type = NLA_NUL_STRING,
.len = IP_VS_PENAME_MAXLEN },
[IPVS_SVC_ATTR_FLAGS] = { .type = NLA_BINARY,
diff --git a/net/netfilter/nf_log.c b/net/netfilter/nf_log.c
index 8bb152a..276324a 100644
--- a/net/netfilter/nf_log.c
+++ b/net/netfilter/nf_log.c
@@ -458,14 +458,17 @@
rcu_assign_pointer(net->nf.nf_loggers[tindex], logger);
mutex_unlock(&nf_log_mutex);
} else {
+ struct ctl_table tmp = *table;
+
+ tmp.data = buf;
mutex_lock(&nf_log_mutex);
logger = nft_log_dereference(net->nf.nf_loggers[tindex]);
if (!logger)
- table->data = "NONE";
+ strlcpy(buf, "NONE", sizeof(buf));
else
- table->data = logger->name;
- r = proc_dostring(table, write, buffer, lenp, ppos);
+ strlcpy(buf, logger->name, sizeof(buf));
mutex_unlock(&nf_log_mutex);
+ r = proc_dostring(&tmp, write, buffer, lenp, ppos);
}
return r;
diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index cf30c44..85b549e 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -220,6 +220,34 @@
return err;
}
+static void nft_rule_expr_activate(const struct nft_ctx *ctx,
+ struct nft_rule *rule)
+{
+ struct nft_expr *expr;
+
+ expr = nft_expr_first(rule);
+ while (expr != nft_expr_last(rule) && expr->ops) {
+ if (expr->ops->activate)
+ expr->ops->activate(ctx, expr);
+
+ expr = nft_expr_next(expr);
+ }
+}
+
+static void nft_rule_expr_deactivate(const struct nft_ctx *ctx,
+ struct nft_rule *rule)
+{
+ struct nft_expr *expr;
+
+ expr = nft_expr_first(rule);
+ while (expr != nft_expr_last(rule) && expr->ops) {
+ if (expr->ops->deactivate)
+ expr->ops->deactivate(ctx, expr);
+
+ expr = nft_expr_next(expr);
+ }
+}
+
static int
nf_tables_delrule_deactivate(struct nft_ctx *ctx, struct nft_rule *rule)
{
@@ -265,6 +293,7 @@
nft_trans_destroy(trans);
return err;
}
+ nft_rule_expr_deactivate(ctx, rule);
return 0;
}
@@ -1237,8 +1266,10 @@
rcu_assign_pointer(chain->stats, newstats);
synchronize_rcu();
free_percpu(oldstats);
- } else
+ } else {
rcu_assign_pointer(chain->stats, newstats);
+ static_branch_inc(&nft_counters_enabled);
+ }
}
static void nf_tables_chain_destroy(struct nft_chain *chain)
@@ -1947,6 +1978,7 @@
[NFTA_RULE_POSITION] = { .type = NLA_U64 },
[NFTA_RULE_USERDATA] = { .type = NLA_BINARY,
.len = NFT_USERDATA_MAXLEN },
+ [NFTA_RULE_ID] = { .type = NLA_U32 },
};
static int nf_tables_fill_rule_info(struct sk_buff *skb, struct net *net,
@@ -2218,6 +2250,13 @@
kfree(rule);
}
+static void nf_tables_rule_release(const struct nft_ctx *ctx,
+ struct nft_rule *rule)
+{
+ nft_rule_expr_deactivate(ctx, rule);
+ nf_tables_rule_destroy(ctx, rule);
+}
+
#define NFT_RULE_MAXEXPRS 128
static struct nft_expr_info *info;
@@ -2385,7 +2424,7 @@
return 0;
err2:
- nf_tables_rule_destroy(&ctx, rule);
+ nf_tables_rule_release(&ctx, rule);
err1:
for (i = 0; i < n; i++) {
if (info[i].ops != NULL)
@@ -3374,6 +3413,8 @@
[NFTA_SET_ELEM_TIMEOUT] = { .type = NLA_U64 },
[NFTA_SET_ELEM_USERDATA] = { .type = NLA_BINARY,
.len = NFT_USERDATA_MAXLEN },
+ [NFTA_SET_ELEM_EXPR] = { .type = NLA_NESTED },
+ [NFTA_SET_ELEM_OBJREF] = { .type = NLA_STRING },
};
static const struct nla_policy nft_set_elem_list_policy[NFTA_SET_ELEM_LIST_MAX + 1] = {
@@ -3961,8 +4002,10 @@
if (nft_set_ext_exists(ext, NFT_SET_EXT_DATA) ^
nft_set_ext_exists(ext2, NFT_SET_EXT_DATA) ||
nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF) ^
- nft_set_ext_exists(ext2, NFT_SET_EXT_OBJREF))
- return -EBUSY;
+ nft_set_ext_exists(ext2, NFT_SET_EXT_OBJREF)) {
+ err = -EBUSY;
+ goto err5;
+ }
if ((nft_set_ext_exists(ext, NFT_SET_EXT_DATA) &&
nft_set_ext_exists(ext2, NFT_SET_EXT_DATA) &&
memcmp(nft_set_ext_data(ext),
@@ -4054,7 +4097,7 @@
* NFT_GOTO verdicts. This function must be called on active data objects
* from the second phase of the commit protocol.
*/
-static void nft_data_hold(const struct nft_data *data, enum nft_data_types type)
+void nft_data_hold(const struct nft_data *data, enum nft_data_types type)
{
if (type == NFT_DATA_VERDICT) {
switch (data->verdict.code) {
@@ -4571,7 +4614,7 @@
if (idx > s_idx)
memset(&cb->args[1], 0,
sizeof(cb->args) - sizeof(cb->args[0]));
- if (filter && filter->table[0] &&
+ if (filter && filter->table &&
strcmp(filter->table, table->name))
goto cont;
if (filter &&
@@ -5221,10 +5264,12 @@
case NFT_MSG_NEWRULE:
trans->ctx.chain->use--;
list_del_rcu(&nft_trans_rule(trans)->list);
+ nft_rule_expr_deactivate(&trans->ctx, nft_trans_rule(trans));
break;
case NFT_MSG_DELRULE:
trans->ctx.chain->use++;
nft_clear(trans->ctx.net, nft_trans_rule(trans));
+ nft_rule_expr_activate(&trans->ctx, nft_trans_rule(trans));
nft_trans_destroy(trans);
break;
case NFT_MSG_NEWSET:
@@ -5798,7 +5843,7 @@
list_for_each_entry_safe(rule, nr, &ctx->chain->rules, list) {
list_del(&rule->list);
ctx->chain->use--;
- nf_tables_rule_destroy(ctx, rule);
+ nf_tables_rule_release(ctx, rule);
}
list_del(&ctx->chain->list);
ctx->table->use--;
@@ -5832,7 +5877,7 @@
list_for_each_entry_safe(rule, nr, &chain->rules, list) {
list_del(&rule->list);
chain->use--;
- nf_tables_rule_destroy(&ctx, rule);
+ nf_tables_rule_release(&ctx, rule);
}
}
list_for_each_entry_safe(set, ns, &table->sets, list) {
diff --git a/net/netfilter/nf_tables_core.c b/net/netfilter/nf_tables_core.c
index dfd0bf3..32b7896 100644
--- a/net/netfilter/nf_tables_core.c
+++ b/net/netfilter/nf_tables_core.c
@@ -119,14 +119,21 @@
static noinline void nft_update_chain_stats(const struct nft_chain *chain,
const struct nft_pktinfo *pkt)
{
+ struct nft_base_chain *base_chain;
struct nft_stats *stats;
+ base_chain = nft_base_chain(chain);
+ if (!base_chain->stats)
+ return;
+
local_bh_disable();
- stats = this_cpu_ptr(rcu_dereference(nft_base_chain(chain)->stats));
- u64_stats_update_begin(&stats->syncp);
- stats->pkts++;
- stats->bytes += pkt->skb->len;
- u64_stats_update_end(&stats->syncp);
+ stats = this_cpu_ptr(rcu_dereference(base_chain->stats));
+ if (stats) {
+ u64_stats_update_begin(&stats->syncp);
+ stats->pkts++;
+ stats->bytes += pkt->skb->len;
+ u64_stats_update_end(&stats->syncp);
+ }
local_bh_enable();
}
@@ -201,7 +208,8 @@
switch (regs.verdict.code) {
case NFT_JUMP:
- BUG_ON(stackptr >= NFT_JUMP_STACK_SIZE);
+ if (WARN_ON_ONCE(stackptr >= NFT_JUMP_STACK_SIZE))
+ return NF_DROP;
jumpstack[stackptr].chain = chain;
jumpstack[stackptr].rule = rule;
jumpstack[stackptr].rulenum = rulenum;
diff --git a/net/netfilter/nfnetlink_queue.c b/net/netfilter/nfnetlink_queue.c
index c979662..02bbc2f 100644
--- a/net/netfilter/nfnetlink_queue.c
+++ b/net/netfilter/nfnetlink_queue.c
@@ -1228,6 +1228,9 @@
static const struct nla_policy nfqa_cfg_policy[NFQA_CFG_MAX+1] = {
[NFQA_CFG_CMD] = { .len = sizeof(struct nfqnl_msg_config_cmd) },
[NFQA_CFG_PARAMS] = { .len = sizeof(struct nfqnl_msg_config_params) },
+ [NFQA_CFG_QUEUE_MAXLEN] = { .type = NLA_U32 },
+ [NFQA_CFG_MASK] = { .type = NLA_U32 },
+ [NFQA_CFG_FLAGS] = { .type = NLA_U32 },
};
static const struct nf_queue_handler nfqh = {
diff --git a/net/netfilter/nft_compat.c b/net/netfilter/nft_compat.c
index b89f4f6..3bd637e 100644
--- a/net/netfilter/nft_compat.c
+++ b/net/netfilter/nft_compat.c
@@ -27,14 +27,31 @@
struct list_head head;
struct nft_expr_ops ops;
unsigned int refcnt;
+
+ /* Unlike other expressions, ops doesn't have static storage duration.
+ * nft core assumes they do. We use kfree_rcu so that nft core can
+ * can check expr->ops->size even after nft_compat->destroy() frees
+ * the nft_xt struct that holds the ops structure.
+ */
+ struct rcu_head rcu_head;
};
-static void nft_xt_put(struct nft_xt *xt)
+/* Used for matches where *info is larger than X byte */
+#define NFT_MATCH_LARGE_THRESH 192
+
+struct nft_xt_match_priv {
+ void *info;
+};
+
+static bool nft_xt_put(struct nft_xt *xt)
{
if (--xt->refcnt == 0) {
list_del(&xt->head);
- kfree(xt);
+ kfree_rcu(xt, rcu_head);
+ return true;
}
+
+ return false;
}
static int nft_compat_chain_validate_dependency(const char *tablename,
@@ -226,6 +243,7 @@
struct xt_target *target = expr->ops->data;
struct xt_tgchk_param par;
size_t size = XT_ALIGN(nla_len(tb[NFTA_TARGET_INFO]));
+ struct nft_xt *nft_xt;
u16 proto = 0;
bool inv = false;
union nft_entry e = {};
@@ -236,25 +254,22 @@
if (ctx->nla[NFTA_RULE_COMPAT]) {
ret = nft_parse_compat(ctx->nla[NFTA_RULE_COMPAT], &proto, &inv);
if (ret < 0)
- goto err;
+ return ret;
}
nft_target_set_tgchk_param(&par, ctx, target, info, &e, proto, inv);
ret = xt_check_target(&par, size, proto, inv);
if (ret < 0)
- goto err;
+ return ret;
/* The standard target cannot be used */
- if (target->target == NULL) {
- ret = -EINVAL;
- goto err;
- }
+ if (!target->target)
+ return -EINVAL;
+ nft_xt = container_of(expr->ops, struct nft_xt, ops);
+ nft_xt->refcnt++;
return 0;
-err:
- module_put(target->me);
- return ret;
}
static void
@@ -271,8 +286,8 @@
if (par.target->destroy != NULL)
par.target->destroy(&par);
- nft_xt_put(container_of(expr->ops, struct nft_xt, ops));
- module_put(target->me);
+ if (nft_xt_put(container_of(expr->ops, struct nft_xt, ops)))
+ module_put(target->me);
}
static int nft_target_dump(struct sk_buff *skb, const struct nft_expr *expr)
@@ -316,11 +331,11 @@
return 0;
}
-static void nft_match_eval(const struct nft_expr *expr,
- struct nft_regs *regs,
- const struct nft_pktinfo *pkt)
+static void __nft_match_eval(const struct nft_expr *expr,
+ struct nft_regs *regs,
+ const struct nft_pktinfo *pkt,
+ void *info)
{
- void *info = nft_expr_priv(expr);
struct xt_match *match = expr->ops->data;
struct sk_buff *skb = pkt->skb;
bool ret;
@@ -344,6 +359,22 @@
}
}
+static void nft_match_large_eval(const struct nft_expr *expr,
+ struct nft_regs *regs,
+ const struct nft_pktinfo *pkt)
+{
+ struct nft_xt_match_priv *priv = nft_expr_priv(expr);
+
+ __nft_match_eval(expr, regs, pkt, priv->info);
+}
+
+static void nft_match_eval(const struct nft_expr *expr,
+ struct nft_regs *regs,
+ const struct nft_pktinfo *pkt)
+{
+ __nft_match_eval(expr, regs, pkt, nft_expr_priv(expr));
+}
+
static const struct nla_policy nft_match_policy[NFTA_MATCH_MAX + 1] = {
[NFTA_MATCH_NAME] = { .type = NLA_NUL_STRING },
[NFTA_MATCH_REV] = { .type = NLA_U32 },
@@ -404,13 +435,14 @@
}
static int
-nft_match_init(const struct nft_ctx *ctx, const struct nft_expr *expr,
- const struct nlattr * const tb[])
+__nft_match_init(const struct nft_ctx *ctx, const struct nft_expr *expr,
+ const struct nlattr * const tb[],
+ void *info)
{
- void *info = nft_expr_priv(expr);
struct xt_match *match = expr->ops->data;
struct xt_mtchk_param par;
size_t size = XT_ALIGN(nla_len(tb[NFTA_MATCH_INFO]));
+ struct nft_xt *nft_xt;
u16 proto = 0;
bool inv = false;
union nft_entry e = {};
@@ -421,26 +453,50 @@
if (ctx->nla[NFTA_RULE_COMPAT]) {
ret = nft_parse_compat(ctx->nla[NFTA_RULE_COMPAT], &proto, &inv);
if (ret < 0)
- goto err;
+ return ret;
}
nft_match_set_mtchk_param(&par, ctx, match, info, &e, proto, inv);
ret = xt_check_match(&par, size, proto, inv);
if (ret < 0)
- goto err;
+ return ret;
+ nft_xt = container_of(expr->ops, struct nft_xt, ops);
+ nft_xt->refcnt++;
return 0;
-err:
- module_put(match->me);
+}
+
+static int
+nft_match_init(const struct nft_ctx *ctx, const struct nft_expr *expr,
+ const struct nlattr * const tb[])
+{
+ return __nft_match_init(ctx, expr, tb, nft_expr_priv(expr));
+}
+
+static int
+nft_match_large_init(const struct nft_ctx *ctx, const struct nft_expr *expr,
+ const struct nlattr * const tb[])
+{
+ struct nft_xt_match_priv *priv = nft_expr_priv(expr);
+ struct xt_match *m = expr->ops->data;
+ int ret;
+
+ priv->info = kmalloc(XT_ALIGN(m->matchsize), GFP_KERNEL);
+ if (!priv->info)
+ return -ENOMEM;
+
+ ret = __nft_match_init(ctx, expr, tb, priv->info);
+ if (ret)
+ kfree(priv->info);
return ret;
}
static void
-nft_match_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr)
+__nft_match_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr,
+ void *info)
{
struct xt_match *match = expr->ops->data;
- void *info = nft_expr_priv(expr);
struct xt_mtdtor_param par;
par.net = ctx->net;
@@ -450,13 +506,28 @@
if (par.match->destroy != NULL)
par.match->destroy(&par);
- nft_xt_put(container_of(expr->ops, struct nft_xt, ops));
- module_put(match->me);
+ if (nft_xt_put(container_of(expr->ops, struct nft_xt, ops)))
+ module_put(match->me);
}
-static int nft_match_dump(struct sk_buff *skb, const struct nft_expr *expr)
+static void
+nft_match_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr)
{
- void *info = nft_expr_priv(expr);
+ __nft_match_destroy(ctx, expr, nft_expr_priv(expr));
+}
+
+static void
+nft_match_large_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr)
+{
+ struct nft_xt_match_priv *priv = nft_expr_priv(expr);
+
+ __nft_match_destroy(ctx, expr, priv->info);
+ kfree(priv->info);
+}
+
+static int __nft_match_dump(struct sk_buff *skb, const struct nft_expr *expr,
+ void *info)
+{
struct xt_match *match = expr->ops->data;
if (nla_put_string(skb, NFTA_MATCH_NAME, match->name) ||
@@ -470,6 +541,18 @@
return -1;
}
+static int nft_match_dump(struct sk_buff *skb, const struct nft_expr *expr)
+{
+ return __nft_match_dump(skb, expr, nft_expr_priv(expr));
+}
+
+static int nft_match_large_dump(struct sk_buff *skb, const struct nft_expr *e)
+{
+ struct nft_xt_match_priv *priv = nft_expr_priv(e);
+
+ return __nft_match_dump(skb, e, priv->info);
+}
+
static int nft_match_validate(const struct nft_ctx *ctx,
const struct nft_expr *expr,
const struct nft_data **data)
@@ -637,6 +720,7 @@
{
struct nft_xt *nft_match;
struct xt_match *match;
+ unsigned int matchsize;
char *mt_name;
u32 rev, family;
int err;
@@ -654,13 +738,8 @@
list_for_each_entry(nft_match, &nft_match_list, head) {
struct xt_match *match = nft_match->ops.data;
- if (nft_match_cmp(match, mt_name, rev, family)) {
- if (!try_module_get(match->me))
- return ERR_PTR(-ENOENT);
-
- nft_match->refcnt++;
+ if (nft_match_cmp(match, mt_name, rev, family))
return &nft_match->ops;
- }
}
match = xt_request_find_match(family, mt_name, rev);
@@ -679,9 +758,8 @@
goto err;
}
- nft_match->refcnt = 1;
+ nft_match->refcnt = 0;
nft_match->ops.type = &nft_match_type;
- nft_match->ops.size = NFT_EXPR_SIZE(XT_ALIGN(match->matchsize));
nft_match->ops.eval = nft_match_eval;
nft_match->ops.init = nft_match_init;
nft_match->ops.destroy = nft_match_destroy;
@@ -689,6 +767,18 @@
nft_match->ops.validate = nft_match_validate;
nft_match->ops.data = match;
+ matchsize = NFT_EXPR_SIZE(XT_ALIGN(match->matchsize));
+ if (matchsize > NFT_MATCH_LARGE_THRESH) {
+ matchsize = NFT_EXPR_SIZE(sizeof(struct nft_xt_match_priv));
+
+ nft_match->ops.eval = nft_match_large_eval;
+ nft_match->ops.init = nft_match_large_init;
+ nft_match->ops.destroy = nft_match_large_destroy;
+ nft_match->ops.dump = nft_match_large_dump;
+ }
+
+ nft_match->ops.size = matchsize;
+
list_add(&nft_match->head, &nft_match_list);
return &nft_match->ops;
@@ -739,13 +829,8 @@
list_for_each_entry(nft_target, &nft_target_list, head) {
struct xt_target *target = nft_target->ops.data;
- if (nft_target_cmp(target, tg_name, rev, family)) {
- if (!try_module_get(target->me))
- return ERR_PTR(-ENOENT);
-
- nft_target->refcnt++;
+ if (nft_target_cmp(target, tg_name, rev, family))
return &nft_target->ops;
- }
}
target = xt_request_find_target(family, tg_name, rev);
@@ -764,7 +849,7 @@
goto err;
}
- nft_target->refcnt = 1;
+ nft_target->refcnt = 0;
nft_target->ops.type = &nft_target_type;
nft_target->ops.size = NFT_EXPR_SIZE(XT_ALIGN(target->targetsize));
nft_target->ops.init = nft_target_init;
@@ -825,6 +910,32 @@
static void __exit nft_compat_module_exit(void)
{
+ struct nft_xt *xt, *next;
+
+ /* list should be empty here, it can be non-empty only in case there
+ * was an error that caused nft_xt expr to not be initialized fully
+ * and noone else requested the same expression later.
+ *
+ * In this case, the lists contain 0-refcount entries that still
+ * hold module reference.
+ */
+ list_for_each_entry_safe(xt, next, &nft_target_list, head) {
+ struct xt_target *target = xt->ops.data;
+
+ if (WARN_ON_ONCE(xt->refcnt))
+ continue;
+ module_put(target->me);
+ kfree(xt);
+ }
+
+ list_for_each_entry_safe(xt, next, &nft_match_list, head) {
+ struct xt_match *match = xt->ops.data;
+
+ if (WARN_ON_ONCE(xt->refcnt))
+ continue;
+ module_put(match->me);
+ kfree(xt);
+ }
nfnetlink_subsys_unregister(&nfnl_compat_subsys);
nft_unregister_expr(&nft_target_type);
nft_unregister_expr(&nft_match_type);
diff --git a/net/netfilter/nft_immediate.c b/net/netfilter/nft_immediate.c
index 4717d77..aa87ff8 100644
--- a/net/netfilter/nft_immediate.c
+++ b/net/netfilter/nft_immediate.c
@@ -69,8 +69,16 @@
return err;
}
-static void nft_immediate_destroy(const struct nft_ctx *ctx,
- const struct nft_expr *expr)
+static void nft_immediate_activate(const struct nft_ctx *ctx,
+ const struct nft_expr *expr)
+{
+ const struct nft_immediate_expr *priv = nft_expr_priv(expr);
+
+ return nft_data_hold(&priv->data, nft_dreg_to_type(priv->dreg));
+}
+
+static void nft_immediate_deactivate(const struct nft_ctx *ctx,
+ const struct nft_expr *expr)
{
const struct nft_immediate_expr *priv = nft_expr_priv(expr);
@@ -108,7 +116,8 @@
.size = NFT_EXPR_SIZE(sizeof(struct nft_immediate_expr)),
.eval = nft_immediate_eval,
.init = nft_immediate_init,
- .destroy = nft_immediate_destroy,
+ .activate = nft_immediate_activate,
+ .deactivate = nft_immediate_deactivate,
.dump = nft_immediate_dump,
.validate = nft_immediate_validate,
};
diff --git a/net/netfilter/nft_limit.c b/net/netfilter/nft_limit.c
index a9fc298..72f13a1 100644
--- a/net/netfilter/nft_limit.c
+++ b/net/netfilter/nft_limit.c
@@ -51,10 +51,13 @@
return !limit->invert;
}
+/* Use same default as in iptables. */
+#define NFT_LIMIT_PKT_BURST_DEFAULT 5
+
static int nft_limit_init(struct nft_limit *limit,
- const struct nlattr * const tb[])
+ const struct nlattr * const tb[], bool pkts)
{
- u64 unit;
+ u64 unit, tokens;
if (tb[NFTA_LIMIT_RATE] == NULL ||
tb[NFTA_LIMIT_UNIT] == NULL)
@@ -68,18 +71,25 @@
if (tb[NFTA_LIMIT_BURST])
limit->burst = ntohl(nla_get_be32(tb[NFTA_LIMIT_BURST]));
- else
- limit->burst = 0;
+
+ if (pkts && limit->burst == 0)
+ limit->burst = NFT_LIMIT_PKT_BURST_DEFAULT;
if (limit->rate + limit->burst < limit->rate)
return -EOVERFLOW;
- /* The token bucket size limits the number of tokens can be
- * accumulated. tokens_max specifies the bucket size.
- * tokens_max = unit * (rate + burst) / rate.
- */
- limit->tokens = div_u64(limit->nsecs * (limit->rate + limit->burst),
- limit->rate);
+ if (pkts) {
+ tokens = div_u64(limit->nsecs, limit->rate) * limit->burst;
+ } else {
+ /* The token bucket size limits the number of tokens can be
+ * accumulated. tokens_max specifies the bucket size.
+ * tokens_max = unit * (rate + burst) / rate.
+ */
+ tokens = div_u64(limit->nsecs * (limit->rate + limit->burst),
+ limit->rate);
+ }
+
+ limit->tokens = tokens;
limit->tokens_max = limit->tokens;
if (tb[NFTA_LIMIT_FLAGS]) {
@@ -144,7 +154,7 @@
struct nft_limit_pkts *priv = nft_expr_priv(expr);
int err;
- err = nft_limit_init(&priv->limit, tb);
+ err = nft_limit_init(&priv->limit, tb, true);
if (err < 0)
return err;
@@ -185,7 +195,7 @@
{
struct nft_limit *priv = nft_expr_priv(expr);
- return nft_limit_init(priv, tb);
+ return nft_limit_init(priv, tb, false);
}
static int nft_limit_bytes_dump(struct sk_buff *skb,
@@ -246,7 +256,7 @@
struct nft_limit_pkts *priv = nft_obj_data(obj);
int err;
- err = nft_limit_init(&priv->limit, tb);
+ err = nft_limit_init(&priv->limit, tb, true);
if (err < 0)
return err;
@@ -289,7 +299,7 @@
{
struct nft_limit *priv = nft_obj_data(obj);
- return nft_limit_init(priv, tb);
+ return nft_limit_init(priv, tb, false);
}
static int nft_limit_obj_bytes_dump(struct sk_buff *skb,
diff --git a/net/netfilter/nft_meta.c b/net/netfilter/nft_meta.c
index 5a60eb2..c71184d 100644
--- a/net/netfilter/nft_meta.c
+++ b/net/netfilter/nft_meta.c
@@ -229,7 +229,7 @@
struct sk_buff *skb = pkt->skb;
u32 *sreg = ®s->data[meta->sreg];
u32 value = *sreg;
- u8 pkt_type;
+ u8 value8;
switch (meta->key) {
case NFT_META_MARK:
@@ -239,15 +239,17 @@
skb->priority = value;
break;
case NFT_META_PKTTYPE:
- pkt_type = nft_reg_load8(sreg);
+ value8 = nft_reg_load8(sreg);
- if (skb->pkt_type != pkt_type &&
- skb_pkt_type_ok(pkt_type) &&
+ if (skb->pkt_type != value8 &&
+ skb_pkt_type_ok(value8) &&
skb_pkt_type_ok(skb->pkt_type))
- skb->pkt_type = pkt_type;
+ skb->pkt_type = value8;
break;
case NFT_META_NFTRACE:
- skb->nf_trace = !!value;
+ value8 = nft_reg_load8(sreg);
+
+ skb->nf_trace = !!value8;
break;
default:
WARN_ON(1);
diff --git a/net/sunrpc/xprtrdma/rpc_rdma.c b/net/sunrpc/xprtrdma/rpc_rdma.c
index 491ae9f..991d5a9 100644
--- a/net/sunrpc/xprtrdma/rpc_rdma.c
+++ b/net/sunrpc/xprtrdma/rpc_rdma.c
@@ -229,7 +229,7 @@
*/
*ppages = alloc_page(GFP_ATOMIC);
if (!*ppages)
- return -EAGAIN;
+ return -ENOBUFS;
}
seg->mr_page = *ppages;
seg->mr_offset = (char *)page_base;
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 9776946..fcbbecf 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -8,6 +8,7 @@
empty :=
space := $(empty) $(empty)
space_escape := _-_SPACE_-_
+pound := \#
###
# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
@@ -251,11 +252,11 @@
# Replace >$< with >$$< to preserve $ when reloading the .cmd file
# (needed for make)
-# Replace >#< with >\#< to avoid starting a comment in the .cmd file
+# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
# (needed for make)
# Replace >'< with >'\''< to be able to enclose the whole string in '...'
# (needed for the shell)
-make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1)))))
+make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
# Find any prerequisites that is newer than target or that does not exist.
# PHONY targets skipped in both cases.
diff --git a/security/chromiumos/alt-syscall.c b/security/chromiumos/alt-syscall.c
index e9b5f3d..649d330 100644
--- a/security/chromiumos/alt-syscall.c
+++ b/security/chromiumos/alt-syscall.c
@@ -250,6 +250,7 @@
#define __NR_compat_io_setup __NR_ia32_io_setup
#define __NR_compat_io_submit __NR_ia32_io_submit
#define __NR_compat_ioprio_set __NR_ia32_ioprio_set
+#define __NR_compat_keyctl __NR_ia32_keyctl
#define __NR_compat_kill __NR_ia32_kill
#define __NR_compat_lgetxattr __NR_ia32_lgetxattr
#define __NR_compat_link __NR_ia32_link
@@ -357,6 +358,7 @@
#define __NR_compat_statfs __NR_ia32_statfs
#define __NR_compat_symlink __NR_ia32_symlink
#define __NR_compat_symlinkat __NR_ia32_symlinkat
+#define __NR_compat_sync __NR_ia32_sync
#define __NR_compat_sync_file_range __NR_ia32_sync_file_range
#define __NR_compat_syncfs __NR_ia32_syncfs
#define __NR_compat_sysinfo __NR_ia32_sysinfo
@@ -515,6 +517,14 @@
return -nice + 20;
}
+/* Android does not get to call keyctl. */
+static asmlinkage long android_keyctl(int cmd, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
+{
+ return -EACCES;
+}
+
/* Make sure nothing sets a nice value more favorable than -10. */
static asmlinkage long android_setpriority(int which, int who, int niceval)
{
@@ -697,6 +707,7 @@
SYSCALL_ENTRY(io_setup),
SYSCALL_ENTRY(io_submit),
SYSCALL_ENTRY(ioprio_set),
+ SYSCALL_ENTRY_ALT(keyctl, android_keyctl),
SYSCALL_ENTRY(kill),
SYSCALL_ENTRY(lgetxattr),
SYSCALL_ENTRY(linkat),
@@ -784,6 +795,7 @@
SYSCALL_ENTRY(symlinkat),
SYSCALL_ENTRY(sysinfo),
SYSCALL_ENTRY(syslog),
+ SYSCALL_ENTRY(sync),
SYSCALL_ENTRY(syncfs),
SYSCALL_ENTRY(tee),
SYSCALL_ENTRY(tgkill),
@@ -1217,6 +1229,7 @@
COMPAT_SYSCALL_ENTRY(io_submit),
COMPAT_SYSCALL_ENTRY(ioctl),
COMPAT_SYSCALL_ENTRY(ioprio_set),
+ COMPAT_SYSCALL_ENTRY_ALT(keyctl, android_keyctl),
COMPAT_SYSCALL_ENTRY(kill),
COMPAT_SYSCALL_ENTRY(lgetxattr),
COMPAT_SYSCALL_ENTRY(link),
@@ -1384,6 +1397,7 @@
COMPAT_SYSCALL_ENTRY(setuid32),
COMPAT_SYSCALL_ENTRY(stat64),
COMPAT_SYSCALL_ENTRY(statfs64),
+ COMPAT_SYSCALL_ENTRY(sync),
COMPAT_SYSCALL_ENTRY(syncfs),
COMPAT_SYSCALL_ENTRY(truncate64),
COMPAT_SYSCALL_ENTRY(ugetrlimit),
diff --git a/security/chromiumos/lsm.c b/security/chromiumos/lsm.c
index 171e269..a56a98a 100644
--- a/security/chromiumos/lsm.c
+++ b/security/chromiumos/lsm.c
@@ -83,20 +83,32 @@
#endif
#ifdef CONFIG_SECURITY_CHROMIUMOS_NO_UNPRIVILEGED_UNSAFE_MOUNTS
- if (!(flags & (MS_BIND | MS_MOVE | MS_SHARED | MS_PRIVATE | MS_SLAVE |
- MS_UNBINDABLE)) &&
+ if ((!(flags & (MS_BIND | MS_MOVE | MS_SHARED | MS_PRIVATE | MS_SLAVE |
+ MS_UNBINDABLE)) ||
+ ((flags & MS_REMOUNT) && (flags & MS_BIND))) &&
!capable(CAP_SYS_ADMIN)) {
+ int required_mnt_flags = MNT_NOEXEC | MNT_NOSUID | MNT_NODEV;
+
+ if (flags & MS_REMOUNT) {
+ /*
+ * If this is a remount, we only require that the
+ * requested flags are a superset of the original mount
+ * flags.
+ */
+ required_mnt_flags &= path->mnt->mnt_flags;
+ }
/*
* The three flags we are interested in disallowing in
* unprivileged user namespaces (MS_NOEXEC, MS_NOSUID, MS_NODEV)
- * cannot be modified when doing a remount/bind. The kernel
+ * cannot be modified when doing a bind-mount. The kernel
* attempts to dispatch calls to do_mount() within
* fs/namespace.c in the following order:
*
* * If the MS_REMOUNT flag is present, it calls do_remount().
- * When MS_BIND is also present, it only allows to set/unset
- * MS_RDONLY. Otherwise it bails in the absence of the
- * CAP_SYS_ADMIN in the init ns.
+ * When MS_BIND is also present, it only allows to modify the
+ * per-mount flags, which are copied into
+ * |required_mnt_flags|. Otherwise it bails in the absence of
+ * the CAP_SYS_ADMIN in the init ns.
* * If the MS_BIND flag is present, the only other flag checked
* is MS_REC.
* * If any of the mount propagation flags are present
@@ -105,21 +117,22 @@
* flags.
* * If MS_MOVE flag is present, all other flags are ignored.
*/
- if (!(flags & MS_NOEXEC)) {
+ if ((required_mnt_flags & MNT_NOEXEC) && !(flags & MS_NOEXEC)) {
report("sb_mount", path,
"Mounting a filesystem with 'exec' flag requires CAP_SYS_ADMIN in init ns");
pr_notice("sb_mount dev=%s type=%s flags=%#lx\n",
dev_name, type, flags);
return -EPERM;
}
- if (!(flags & MS_NOSUID)) {
+ if ((required_mnt_flags & MNT_NOSUID) && !(flags & MS_NOSUID)) {
report("sb_mount", path,
"Mounting a filesystem with 'suid' flag requires CAP_SYS_ADMIN in init ns");
pr_notice("sb_mount dev=%s type=%s flags=%#lx\n",
dev_name, type, flags);
return -EPERM;
}
- if (!(flags & MS_NODEV) && strcmp(type, "devpts")) {
+ if ((required_mnt_flags & MNT_NODEV) && !(flags & MS_NODEV) &&
+ strcmp(type, "devpts")) {
report("sb_mount", path,
"Mounting a filesystem with 'dev' flag requires CAP_SYS_ADMIN in init ns");
pr_notice("sb_mount dev=%s type=%s flags=%#lx\n",
diff --git a/sound/core/timer.c b/sound/core/timer.c
index 4fdc9e1..2c0f292 100644
--- a/sound/core/timer.c
+++ b/sound/core/timer.c
@@ -1514,7 +1514,7 @@
} else {
if (id.subdevice < 0)
id.subdevice = 0;
- else
+ else if (id.subdevice < INT_MAX)
id.subdevice++;
}
}
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 7d7eb13..ffb6aba 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/asoundef.h>
@@ -764,8 +765,10 @@
if (pin_idx < 0)
return;
+ mutex_lock(&spec->pcm_lock);
if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
snd_hda_jack_report_sync(codec);
+ mutex_unlock(&spec->pcm_lock);
}
static void jack_callback(struct hda_codec *codec,
@@ -1628,21 +1631,23 @@
static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
{
struct hda_codec *codec = per_pin->codec;
- struct hdmi_spec *spec = codec->spec;
int ret;
/* no temporary power up/down needed for component notifier */
- if (!codec_has_acomp(codec))
- snd_hda_power_up_pm(codec);
+ if (!codec_has_acomp(codec)) {
+ ret = snd_hda_power_up_pm(codec);
+ if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
+ snd_hda_power_down_pm(codec);
+ return false;
+ }
+ }
- mutex_lock(&spec->pcm_lock);
if (codec_has_acomp(codec)) {
sync_eld_via_acomp(codec, per_pin);
ret = false; /* don't call snd_hda_jack_report_sync() */
} else {
ret = hdmi_present_sense_via_verbs(per_pin, repoll);
}
- mutex_unlock(&spec->pcm_lock);
if (!codec_has_acomp(codec))
snd_hda_power_down_pm(codec);
@@ -1654,12 +1659,16 @@
{
struct hdmi_spec_per_pin *per_pin =
container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
+ struct hda_codec *codec = per_pin->codec;
+ struct hdmi_spec *spec = codec->spec;
if (per_pin->repoll_count++ > 6)
per_pin->repoll_count = 0;
+ mutex_lock(&spec->pcm_lock);
if (hdmi_present_sense(per_pin, per_pin->repoll_count))
snd_hda_jack_report_sync(per_pin->codec);
+ mutex_unlock(&spec->pcm_lock);
}
static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 2a8aa2b..bf7737f 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -2518,6 +2518,7 @@
SND_PCI_QUIRK(0x10cf, 0x1397, "Fujitsu Lifebook S7110", ALC262_FIXUP_FSC_S7110),
SND_PCI_QUIRK(0x10cf, 0x142d, "Fujitsu Lifebook E8410", ALC262_FIXUP_BENQ),
SND_PCI_QUIRK(0x10f1, 0x2915, "Tyan Thunder n6650W", ALC262_FIXUP_TYAN),
+ SND_PCI_QUIRK(0x1734, 0x1141, "FSC ESPRIMO U9210", ALC262_FIXUP_FSC_H270),
SND_PCI_QUIRK(0x1734, 0x1147, "FSC Celsius H270", ALC262_FIXUP_FSC_H270),
SND_PCI_QUIRK(0x17aa, 0x384e, "Lenovo 3000", ALC262_FIXUP_LENOVO_3000),
SND_PCI_QUIRK(0x17ff, 0x0560, "Benq ED8", ALC262_FIXUP_BENQ),
@@ -4844,7 +4845,6 @@
struct alc_spec *spec = codec->spec;
if (action == HDA_FIXUP_ACT_PRE_PROBE) {
- spec->shutup = alc_no_shutup; /* reduce click noise */
spec->reboot_notify = alc_d3_at_reboot; /* reduce noise */
spec->parse_flags = HDA_PINCFG_NO_HP_FIXUP;
codec->power_save_node = 0; /* avoid click noises */
@@ -5243,6 +5243,13 @@
/* for hda_fixup_thinkpad_acpi() */
#include "thinkpad_helper.c"
+static void alc_fixup_thinkpad_acpi(struct hda_codec *codec,
+ const struct hda_fixup *fix, int action)
+{
+ alc_fixup_no_shutup(codec, fix, action); /* reduce click noise */
+ hda_fixup_thinkpad_acpi(codec, fix, action);
+}
+
/* for dell wmi mic mute led */
#include "dell_wmi_helper.c"
@@ -5786,7 +5793,7 @@
},
[ALC269_FIXUP_THINKPAD_ACPI] = {
.type = HDA_FIXUP_FUNC,
- .v.func = hda_fixup_thinkpad_acpi,
+ .v.func = alc_fixup_thinkpad_acpi,
.chained = true,
.chain_id = ALC269_FIXUP_SKU_IGNORE,
},
@@ -6436,8 +6443,8 @@
SND_PCI_QUIRK(0x17aa, 0x30bb, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),
SND_PCI_QUIRK(0x17aa, 0x30e2, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),
SND_PCI_QUIRK(0x17aa, 0x310c, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),
+ SND_PCI_QUIRK(0x17aa, 0x312a, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),
SND_PCI_QUIRK(0x17aa, 0x312f, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),
- SND_PCI_QUIRK(0x17aa, 0x3138, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),
SND_PCI_QUIRK(0x17aa, 0x313c, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),
SND_PCI_QUIRK(0x17aa, 0x3902, "Lenovo E50-80", ALC269_FIXUP_DMIC_THINKPAD_ACPI),
SND_PCI_QUIRK(0x17aa, 0x3977, "IdeaPad S210", ALC283_FIXUP_INT_MIC),
@@ -6614,6 +6621,17 @@
{0x14, 0x90170110},
{0x19, 0x02a11030},
{0x21, 0x02211020}),
+ SND_HDA_PIN_QUIRK(0x10ec0235, 0x17aa, "Lenovo", ALC294_FIXUP_LENOVO_MIC_LOCATION,
+ {0x14, 0x90170110},
+ {0x19, 0x02a11030},
+ {0x1a, 0x02a11040},
+ {0x1b, 0x01014020},
+ {0x21, 0x0221101f}),
+ SND_HDA_PIN_QUIRK(0x10ec0235, 0x17aa, "Lenovo", ALC294_FIXUP_LENOVO_MIC_LOCATION,
+ {0x14, 0x90170110},
+ {0x19, 0x02a11020},
+ {0x1a, 0x02a11030},
+ {0x21, 0x0221101f}),
SND_HDA_PIN_QUIRK(0x10ec0236, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
{0x12, 0x90a60140},
{0x14, 0x90170150},
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 804d2ee..cf16c03 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -410,10 +410,8 @@
switch (ch_num) {
case ACP_TO_I2S_DMA_CH_NUM:
case ACP_TO_SYSRAM_CH_NUM:
- case I2S_TO_ACP_DMA_CH_NUM:
case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM:
- case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
break;
default:
@@ -695,29 +693,16 @@
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
- if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
- valid_irq = true;
- snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
- acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
- acp_mmio, mmACP_EXTERNAL_INTR_STAT);
- }
-
if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
valid_irq = true;
+ snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
- if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
- valid_irq = true;
- snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
- acp_reg_write((intr_flag &
- BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
- acp_mmio, mmACP_EXTERNAL_INTR_STAT);
- }
-
if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) {
valid_irq = true;
+ snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
acp_reg_write((intr_flag &
BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
@@ -894,8 +879,8 @@
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
- rtd->ch1 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
- rtd->ch2 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
+ rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
+ rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
rtd->destination = FROM_BLUETOOTH;
rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
@@ -909,8 +894,8 @@
case I2S_SP_INSTANCE:
default:
rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
- rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
- rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
+ rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;
+ rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;
switch (adata->asic_type) {
case CHIP_STONEY:
rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
@@ -990,8 +975,7 @@
buffersize = frames_to_bytes(runtime, runtime->buffer_size);
bytescount = acp_get_byte_count(rtd);
- if (bytescount > rtd->bytescount)
- bytescount -= rtd->bytescount;
+ bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(runtime, pos);
}
@@ -1024,7 +1008,6 @@
static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
{
int ret;
- u64 bytescount = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
@@ -1035,13 +1018,8 @@
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
- bytescount = acp_get_byte_count(rtd);
- if (rtd->bytescount == 0)
- rtd->bytescount = bytescount;
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- acp_dma_start(rtd->acp_mmio, rtd->ch1);
- acp_dma_start(rtd->acp_mmio, rtd->ch2);
- } else {
+ rtd->bytescount = acp_get_byte_count(rtd);
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
if (rtd->capture_channel == CAP_CHANNEL0) {
acp_dma_cap_channel_disable(rtd->acp_mmio,
CAP_CHANNEL1);
@@ -1054,30 +1032,16 @@
acp_dma_cap_channel_enable(rtd->acp_mmio,
CAP_CHANNEL1);
}
- acp_dma_start(rtd->acp_mmio, rtd->ch2);
- acp_dma_start(rtd->acp_mmio, rtd->ch1);
}
+ acp_dma_start(rtd->acp_mmio, rtd->ch1);
+ acp_dma_start(rtd->acp_mmio, rtd->ch2);
ret = 0;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
- /* For playback, non circular dma should be stopped first
- * i.e Sysram to acp dma transfer channel(rtd->ch1) should be
- * stopped before stopping cirular dma which is acp sram to i2s
- * fifo dma transfer channel(rtd->ch2). Where as in Capture
- * scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped
- * first before stopping acp sram to sysram which is circular
- * dma(rtd->ch1).
- */
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- acp_dma_stop(rtd->acp_mmio, rtd->ch1);
- ret = acp_dma_stop(rtd->acp_mmio, rtd->ch2);
- } else {
- acp_dma_stop(rtd->acp_mmio, rtd->ch2);
- ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
- }
- rtd->bytescount = 0;
+ acp_dma_stop(rtd->acp_mmio, rtd->ch2);
+ ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
break;
default:
ret = -EINVAL;
diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h
index 3190fdc..0a2240b 100644
--- a/sound/soc/amd/acp.h
+++ b/sound/soc/amd/acp.h
@@ -74,16 +74,16 @@
#define ACP_TO_I2S_DMA_CH_NUM 13
/* Capture DMA channels */
-#define ACP_TO_SYSRAM_CH_NUM 14
-#define I2S_TO_ACP_DMA_CH_NUM 15
+#define I2S_TO_ACP_DMA_CH_NUM 14
+#define ACP_TO_SYSRAM_CH_NUM 15
/* Playback DMA Channels for I2S BT instance */
#define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM 8
#define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9
/* Capture DMA Channels for I2S BT Instance */
-#define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 10
-#define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 11
+#define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 10
+#define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 11
#define NUM_DSCRS_PER_CHANNEL 2
diff --git a/sound/soc/cirrus/edb93xx.c b/sound/soc/cirrus/edb93xx.c
index c53bd6f..3d011ab 100644
--- a/sound/soc/cirrus/edb93xx.c
+++ b/sound/soc/cirrus/edb93xx.c
@@ -67,7 +67,7 @@
.cpu_dai_name = "ep93xx-i2s",
.codec_name = "spi0.0",
.codec_dai_name = "cs4271-hifi",
- .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &edb93xx_ops,
};
diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c
index 934f8ae..0dc3852 100644
--- a/sound/soc/cirrus/ep93xx-i2s.c
+++ b/sound/soc/cirrus/ep93xx-i2s.c
@@ -51,7 +51,9 @@
#define EP93XX_I2S_WRDLEN_24 (1 << 0)
#define EP93XX_I2S_WRDLEN_32 (2 << 0)
-#define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
+#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
+
+#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
@@ -170,25 +172,25 @@
unsigned int fmt)
{
struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
- unsigned int clk_cfg, lin_ctrl;
+ unsigned int clk_cfg;
+ unsigned int txlin_ctrl = 0;
+ unsigned int rxlin_ctrl = 0;
clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
- lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
clk_cfg |= EP93XX_I2S_CLKCFG_REL;
- lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
break;
case SND_SOC_DAIFMT_LEFT_J:
clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
- lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
break;
case SND_SOC_DAIFMT_RIGHT_J:
clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
- lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
+ rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
+ txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
break;
default:
@@ -213,32 +215,32 @@
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
/* Negative bit clock, lrclk low on left word */
- clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
+ clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
break;
case SND_SOC_DAIFMT_NB_IF:
/* Negative bit clock, lrclk low on right word */
clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
- clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+ clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Positive bit clock, lrclk low on left word */
clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
- clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+ clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
break;
case SND_SOC_DAIFMT_IB_IF:
/* Positive bit clock, lrclk low on right word */
- clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
+ clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
break;
}
/* Write new register values */
ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
- ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
- ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
return 0;
}
diff --git a/sound/soc/cirrus/snappercl15.c b/sound/soc/cirrus/snappercl15.c
index 2334ec1..11ff7b2 100644
--- a/sound/soc/cirrus/snappercl15.c
+++ b/sound/soc/cirrus/snappercl15.c
@@ -72,7 +72,7 @@
.codec_dai_name = "tlv320aic23-hifi",
.codec_name = "tlv320aic23-codec.0-001a",
.platform_name = "ep93xx-i2s",
- .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &snappercl15_ops,
};
diff --git a/sound/soc/codecs/cs35l35.c b/sound/soc/codecs/cs35l35.c
index 129978d..51ce53e2 100644
--- a/sound/soc/codecs/cs35l35.c
+++ b/sound/soc/codecs/cs35l35.c
@@ -1106,6 +1106,7 @@
.readable_reg = cs35l35_readable_register,
.precious_reg = cs35l35_precious_register,
.cache_type = REGCACHE_RBTREE,
+ .use_single_rw = true,
};
static irqreturn_t cs35l35_irq(int irq, void *data)
diff --git a/sound/soc/codecs/rt5682.c b/sound/soc/codecs/rt5682.c
index 61a9730..1f7e068 100644
--- a/sound/soc/codecs/rt5682.c
+++ b/sound/soc/codecs/rt5682.c
@@ -857,6 +857,8 @@
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
pr_debug("%s btn_type=%x\n", __func__, btn_type);
+ snd_soc_component_update_bits(component,
+ RT5682_SAR_IL_CMD_2, 0x10, 0x10);
return btn_type;
}
@@ -1645,6 +1647,8 @@
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
+ SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
+ 14, 1, NULL, 0),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -1807,6 +1811,8 @@
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
+ {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
+
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
diff --git a/sound/soc/intel/boards/glk_rt5682_max98357a.c b/sound/soc/intel/boards/glk_rt5682_max98357a.c
index f8774d2..7c67a52 100644
--- a/sound/soc/intel/boards/glk_rt5682_max98357a.c
+++ b/sound/soc/intel/boards/glk_rt5682_max98357a.c
@@ -70,10 +70,9 @@
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
- ret = snd_soc_dai_set_pll(codec_dai, 0,
- RT5682_PLL1_S_MCLK, 0, 0);
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 0, 0);
if (ret)
- dev_err(card->dev, "failed to stop PLL: %d\n", ret);
+ dev_err(card->dev, "failed to stop sysclk: %d\n", ret);
} else if (SND_SOC_DAPM_EVENT_ON(event)) {
ret = snd_soc_dai_set_pll(codec_dai, 0, RT5682_PLL1_S_MCLK,
GLK_PLAT_CLK_FREQ, RT5682_PLL_FREQ);
diff --git a/sound/soc/mediatek/common/mtk-afe-platform-driver.c b/sound/soc/mediatek/common/mtk-afe-platform-driver.c
index 82d439c..e58fbef 100644
--- a/sound/soc/mediatek/common/mtk-afe-platform-driver.c
+++ b/sound/soc/mediatek/common/mtk-afe-platform-driver.c
@@ -63,13 +63,13 @@
static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
{
size_t size;
- struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
size = afe->mtk_afe_hardware->buffer_bytes_max;
return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
- card->dev, size, size);
+ rtd->platform->dev,
+ size, size);
}
static void mtk_afe_pcm_free(struct snd_pcm *pcm)
diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
index f2bf31f..87a66c9 100644
--- a/sound/soc/qcom/Kconfig
+++ b/sound/soc/qcom/Kconfig
@@ -55,14 +55,12 @@
config SND_SOC_QDSP6_AFE_DAI
tristate
- depends on BROKEN
config SND_SOC_QDSP6_ADM
tristate
config SND_SOC_QDSP6_ROUTING
tristate
- depends on BROKEN
config SND_SOC_QDSP6_ASM
tristate
@@ -73,7 +71,6 @@
config SND_SOC_QDSP6
tristate "SoC ALSA audio driver for QDSP6"
depends on QCOM_APR && HAS_DMA
- depends on BROKEN
select SND_SOC_QDSP6_COMMON
select SND_SOC_QDSP6_CORE
select SND_SOC_QDSP6_AFE
@@ -91,7 +88,6 @@
config SND_SOC_MSM8996
tristate "SoC Machine driver for MSM8996 and APQ8096 boards"
depends on QCOM_APR
- depends on BROKEN
select SND_SOC_QDSP6
help
Support for Qualcomm Technologies LPASS audio block in
diff --git a/sound/soc/qcom/qdsp6/q6afe-dai.c b/sound/soc/qcom/qdsp6/q6afe-dai.c
index 4378e29..5002dd0 100644
--- a/sound/soc/qcom/qdsp6/q6afe-dai.c
+++ b/sound/soc/qcom/qdsp6/q6afe-dai.c
@@ -14,8 +14,56 @@
#include <sound/pcm_params.h>
#include "q6afe.h"
+#define Q6AFE_TDM_PB_DAI(pre, num, did) { \
+ .playback = { \
+ .stream_name = pre" TDM"#num" Playback", \
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_176400, \
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE, \
+ .channels_min = 1, \
+ .channels_max = 8, \
+ .rate_min = 8000, \
+ .rate_max = 176400, \
+ }, \
+ .name = #did, \
+ .ops = &q6tdm_ops, \
+ .id = did, \
+ .probe = msm_dai_q6_dai_probe, \
+ .remove = msm_dai_q6_dai_remove, \
+ }
+
+#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \
+ .capture = { \
+ .stream_name = pre" TDM"#num" Capture", \
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_176400, \
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE, \
+ .channels_min = 1, \
+ .channels_max = 8, \
+ .rate_min = 8000, \
+ .rate_max = 176400, \
+ }, \
+ .name = #did, \
+ .ops = &q6tdm_ops, \
+ .id = did, \
+ .probe = msm_dai_q6_dai_probe, \
+ .remove = msm_dai_q6_dai_remove, \
+ }
+
struct q6afe_dai_priv_data {
uint32_t sd_line_mask;
+ uint32_t sync_mode;
+ uint32_t sync_src;
+ uint32_t data_out_enable;
+ uint32_t invert_sync;
+ uint32_t data_delay;
+ uint32_t data_align;
};
struct q6afe_dai_data {
@@ -130,6 +178,137 @@
return 0;
}
+static int q6tdm_set_tdm_slot(struct snd_soc_dai *dai,
+ unsigned int tx_mask,
+ unsigned int rx_mask,
+ int slots, int slot_width)
+{
+
+ struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
+ struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm;
+ unsigned int cap_mask;
+ int rc = 0;
+
+ /* HW only supports 16 and 32 bit slot width configuration */
+ if ((slot_width != 16) && (slot_width != 32)) {
+ dev_err(dai->dev, "%s: invalid slot_width %d\n",
+ __func__, slot_width);
+ return -EINVAL;
+ }
+
+ /* HW supports 1-32 slots configuration. Typical: 1, 2, 4, 8, 16, 32 */
+ switch (slots) {
+ case 2:
+ cap_mask = 0x03;
+ break;
+ case 4:
+ cap_mask = 0x0F;
+ break;
+ case 8:
+ cap_mask = 0xFF;
+ break;
+ case 16:
+ cap_mask = 0xFFFF;
+ break;
+ default:
+ dev_err(dai->dev, "%s: invalid slots %d\n",
+ __func__, slots);
+ return -EINVAL;
+ }
+
+ switch (dai->id) {
+ case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
+ tdm->nslots_per_frame = slots;
+ tdm->slot_width = slot_width;
+ /* TDM RX dais ids are even and tx are odd */
+ tdm->slot_mask = (dai->id & 0x1 ? tx_mask : rx_mask) & cap_mask;
+ break;
+ default:
+ dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
+ __func__, dai->id);
+ return -EINVAL;
+ }
+
+ return rc;
+}
+
+static int q6tdm_set_channel_map(struct snd_soc_dai *dai,
+ unsigned int tx_num, unsigned int *tx_slot,
+ unsigned int rx_num, unsigned int *rx_slot)
+{
+
+ struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
+ struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm;
+ int rc = 0;
+ int i = 0;
+
+ switch (dai->id) {
+ case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
+ if (dai->id & 0x1) {
+ if (!tx_slot) {
+ dev_err(dai->dev, "tx slot not found\n");
+ return -EINVAL;
+ }
+ if (tx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) {
+ dev_err(dai->dev, "invalid tx num %d\n",
+ tx_num);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < tx_num; i++)
+ tdm->ch_mapping[i] = tx_slot[i];
+
+ for (i = tx_num; i < AFE_PORT_MAX_AUDIO_CHAN_CNT; i++)
+ tdm->ch_mapping[i] = Q6AFE_CMAP_INVALID;
+
+ tdm->num_channels = tx_num;
+ } else {
+ /* rx */
+ if (!rx_slot) {
+ dev_err(dai->dev, "rx slot not found\n");
+ return -EINVAL;
+ }
+ if (rx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) {
+ dev_err(dai->dev, "invalid rx num %d\n",
+ rx_num);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < rx_num; i++)
+ tdm->ch_mapping[i] = rx_slot[i];
+
+ for (i = rx_num; i < AFE_PORT_MAX_AUDIO_CHAN_CNT; i++)
+ tdm->ch_mapping[i] = Q6AFE_CMAP_INVALID;
+
+ tdm->num_channels = rx_num;
+ }
+
+ break;
+ default:
+ dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
+ __func__, dai->id);
+ return -EINVAL;
+ }
+
+ return rc;
+}
+
+static int q6tdm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
+ struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm;
+
+ tdm->bit_width = params_width(params);
+ tdm->sample_rate = params_rate(params);
+ tdm->num_channels = params_channels(params);
+ tdm->data_align_type = dai_data->priv[dai->id].data_align;
+ tdm->sync_src = dai_data->priv[dai->id].sync_src;
+ tdm->sync_mode = dai_data->priv[dai->id].sync_mode;
+
+ return 0;
+}
static void q6afe_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
@@ -144,38 +323,6 @@
}
-static int q6afe_mi2s_prepare(struct snd_pcm_substream *substream,
- struct snd_soc_dai *dai)
-{
- struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
- int rc;
-
- if (dai_data->is_port_started[dai->id]) {
- /* stop the port and restart with new port config */
- rc = q6afe_port_stop(dai_data->port[dai->id]);
- if (rc < 0) {
- dev_err(dai->dev, "fail to close AFE port (%d)\n", rc);
- return rc;
- }
- }
-
- rc = q6afe_i2s_port_prepare(dai_data->port[dai->id],
- &dai_data->port_config[dai->id].i2s_cfg);
- if (rc < 0) {
- dev_err(dai->dev, "fail to prepare AFE port %x\n", dai->id);
- return rc;
- }
-
- rc = q6afe_port_start(dai_data->port[dai->id]);
- if (rc < 0) {
- dev_err(dai->dev, "fail to start AFE port %x\n", dai->id);
- return rc;
- }
- dai_data->is_port_started[dai->id] = true;
-
- return 0;
-}
-
static int q6afe_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
@@ -191,12 +338,31 @@
}
}
- if (dai->id == HDMI_RX)
+ switch (dai->id) {
+ case HDMI_RX:
q6afe_hdmi_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].hdmi);
- else if (dai->id >= SLIMBUS_0_RX && dai->id <= SLIMBUS_6_TX)
+ break;
+ case SLIMBUS_0_RX ... SLIMBUS_6_TX:
q6afe_slim_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].slim);
+ break;
+ case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
+ rc = q6afe_i2s_port_prepare(dai_data->port[dai->id],
+ &dai_data->port_config[dai->id].i2s_cfg);
+ if (rc < 0) {
+ dev_err(dai->dev, "fail to prepare AFE port %x\n",
+ dai->id);
+ return rc;
+ }
+ break;
+ case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
+ q6afe_tdm_port_prepare(dai_data->port[dai->id],
+ &dai_data->port_config[dai->id].tdm);
+ break;
+ default:
+ return -EINVAL;
+ }
rc = q6afe_port_start(dai_data->port[dai->id]);
if (rc < 0) {
@@ -252,11 +418,17 @@
Q6AFE_LPASS_CLK_SRC_INTERNAL,
Q6AFE_LPASS_CLK_ROOT_DEFAULT,
freq, dir);
- case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
+ case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
+ case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
return q6afe_port_set_sysclk(port, clk_id,
Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
Q6AFE_LPASS_CLK_ROOT_DEFAULT,
freq, dir);
+ case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
+ return q6afe_port_set_sysclk(port, clk_id,
+ Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO,
+ Q6AFE_LPASS_CLK_ROOT_DEFAULT,
+ freq, dir);
}
return 0;
@@ -276,6 +448,96 @@
{"Tertiary MI2S Playback", NULL, "TERT_MI2S_RX"},
{"Quaternary MI2S Playback", NULL, "QUAT_MI2S_RX"},
+ {"Primary TDM0 Playback", NULL, "PRIMARY_TDM_RX_0"},
+ {"Primary TDM1 Playback", NULL, "PRIMARY_TDM_RX_1"},
+ {"Primary TDM2 Playback", NULL, "PRIMARY_TDM_RX_2"},
+ {"Primary TDM3 Playback", NULL, "PRIMARY_TDM_RX_3"},
+ {"Primary TDM4 Playback", NULL, "PRIMARY_TDM_RX_4"},
+ {"Primary TDM5 Playback", NULL, "PRIMARY_TDM_RX_5"},
+ {"Primary TDM6 Playback", NULL, "PRIMARY_TDM_RX_6"},
+ {"Primary TDM7 Playback", NULL, "PRIMARY_TDM_RX_7"},
+
+ {"Secondary TDM0 Playback", NULL, "SEC_TDM_RX_0"},
+ {"Secondary TDM1 Playback", NULL, "SEC_TDM_RX_1"},
+ {"Secondary TDM2 Playback", NULL, "SEC_TDM_RX_2"},
+ {"Secondary TDM3 Playback", NULL, "SEC_TDM_RX_3"},
+ {"Secondary TDM4 Playback", NULL, "SEC_TDM_RX_4"},
+ {"Secondary TDM5 Playback", NULL, "SEC_TDM_RX_5"},
+ {"Secondary TDM6 Playback", NULL, "SEC_TDM_RX_6"},
+ {"Secondary TDM7 Playback", NULL, "SEC_TDM_RX_7"},
+
+ {"Tertiary TDM0 Playback", NULL, "TERT_TDM_RX_0"},
+ {"Tertiary TDM1 Playback", NULL, "TERT_TDM_RX_1"},
+ {"Tertiary TDM2 Playback", NULL, "TERT_TDM_RX_2"},
+ {"Tertiary TDM3 Playback", NULL, "TERT_TDM_RX_3"},
+ {"Tertiary TDM4 Playback", NULL, "TERT_TDM_RX_4"},
+ {"Tertiary TDM5 Playback", NULL, "TERT_TDM_RX_5"},
+ {"Tertiary TDM6 Playback", NULL, "TERT_TDM_RX_6"},
+ {"Tertiary TDM7 Playback", NULL, "TERT_TDM_RX_7"},
+
+ {"Quaternary TDM0 Playback", NULL, "QUAT_TDM_RX_0"},
+ {"Quaternary TDM1 Playback", NULL, "QUAT_TDM_RX_1"},
+ {"Quaternary TDM2 Playback", NULL, "QUAT_TDM_RX_2"},
+ {"Quaternary TDM3 Playback", NULL, "QUAT_TDM_RX_3"},
+ {"Quaternary TDM4 Playback", NULL, "QUAT_TDM_RX_4"},
+ {"Quaternary TDM5 Playback", NULL, "QUAT_TDM_RX_5"},
+ {"Quaternary TDM6 Playback", NULL, "QUAT_TDM_RX_6"},
+ {"Quaternary TDM7 Playback", NULL, "QUAT_TDM_RX_7"},
+
+ {"Quinary TDM0 Playback", NULL, "QUIN_TDM_RX_0"},
+ {"Quinary TDM1 Playback", NULL, "QUIN_TDM_RX_1"},
+ {"Quinary TDM2 Playback", NULL, "QUIN_TDM_RX_2"},
+ {"Quinary TDM3 Playback", NULL, "QUIN_TDM_RX_3"},
+ {"Quinary TDM4 Playback", NULL, "QUIN_TDM_RX_4"},
+ {"Quinary TDM5 Playback", NULL, "QUIN_TDM_RX_5"},
+ {"Quinary TDM6 Playback", NULL, "QUIN_TDM_RX_6"},
+ {"Quinary TDM7 Playback", NULL, "QUIN_TDM_RX_7"},
+
+ {"PRIMARY_TDM_TX_0", NULL, "Primary TDM0 Capture"},
+ {"PRIMARY_TDM_TX_1", NULL, "Primary TDM1 Capture"},
+ {"PRIMARY_TDM_TX_2", NULL, "Primary TDM2 Capture"},
+ {"PRIMARY_TDM_TX_3", NULL, "Primary TDM3 Capture"},
+ {"PRIMARY_TDM_TX_4", NULL, "Primary TDM4 Capture"},
+ {"PRIMARY_TDM_TX_5", NULL, "Primary TDM5 Capture"},
+ {"PRIMARY_TDM_TX_6", NULL, "Primary TDM6 Capture"},
+ {"PRIMARY_TDM_TX_7", NULL, "Primary TDM7 Capture"},
+
+ {"SEC_TDM_TX_0", NULL, "Secondary TDM0 Capture"},
+ {"SEC_TDM_TX_1", NULL, "Secondary TDM1 Capture"},
+ {"SEC_TDM_TX_2", NULL, "Secondary TDM2 Capture"},
+ {"SEC_TDM_TX_3", NULL, "Secondary TDM3 Capture"},
+ {"SEC_TDM_TX_4", NULL, "Secondary TDM4 Capture"},
+ {"SEC_TDM_TX_5", NULL, "Secondary TDM5 Capture"},
+ {"SEC_TDM_TX_6", NULL, "Secondary TDM6 Capture"},
+ {"SEC_TDM_TX_7", NULL, "Secondary TDM7 Capture"},
+
+ {"TERT_TDM_TX_0", NULL, "Tertiary TDM0 Capture"},
+ {"TERT_TDM_TX_1", NULL, "Tertiary TDM1 Capture"},
+ {"TERT_TDM_TX_2", NULL, "Tertiary TDM2 Capture"},
+ {"TERT_TDM_TX_3", NULL, "Tertiary TDM3 Capture"},
+ {"TERT_TDM_TX_4", NULL, "Tertiary TDM4 Capture"},
+ {"TERT_TDM_TX_5", NULL, "Tertiary TDM5 Capture"},
+ {"TERT_TDM_TX_6", NULL, "Tertiary TDM6 Capture"},
+ {"TERT_TDM_TX_7", NULL, "Tertiary TDM7 Capture"},
+
+ {"QUAT_TDM_TX_0", NULL, "Quaternary TDM0 Capture"},
+ {"QUAT_TDM_TX_1", NULL, "Quaternary TDM1 Capture"},
+ {"QUAT_TDM_TX_2", NULL, "Quaternary TDM2 Capture"},
+ {"QUAT_TDM_TX_3", NULL, "Quaternary TDM3 Capture"},
+ {"QUAT_TDM_TX_4", NULL, "Quaternary TDM4 Capture"},
+ {"QUAT_TDM_TX_5", NULL, "Quaternary TDM5 Capture"},
+ {"QUAT_TDM_TX_6", NULL, "Quaternary TDM6 Capture"},
+ {"QUAT_TDM_TX_7", NULL, "Quaternary TDM7 Capture"},
+
+ {"QUIN_TDM_TX_0", NULL, "Quinary TDM0 Capture"},
+ {"QUIN_TDM_TX_1", NULL, "Quinary TDM1 Capture"},
+ {"QUIN_TDM_TX_2", NULL, "Quinary TDM2 Capture"},
+ {"QUIN_TDM_TX_3", NULL, "Quinary TDM3 Capture"},
+ {"QUIN_TDM_TX_4", NULL, "Quinary TDM4 Capture"},
+ {"QUIN_TDM_TX_5", NULL, "Quinary TDM5 Capture"},
+ {"QUIN_TDM_TX_6", NULL, "Quinary TDM6 Capture"},
+ {"QUIN_TDM_TX_7", NULL, "Quinary TDM7 Capture"},
+
{"TERT_MI2S_TX", NULL, "Tertiary MI2S Capture"},
{"PRI_MI2S_TX", NULL, "Primary MI2S Capture"},
{"SEC_MI2S_TX", NULL, "Secondary MI2S Capture"},
@@ -289,7 +551,7 @@
};
static struct snd_soc_dai_ops q6i2s_ops = {
- .prepare = q6afe_mi2s_prepare,
+ .prepare = q6afe_dai_prepare,
.hw_params = q6i2s_hw_params,
.set_fmt = q6i2s_set_fmt,
.shutdown = q6afe_dai_shutdown,
@@ -303,6 +565,15 @@
.set_channel_map = q6slim_set_channel_map,
};
+static struct snd_soc_dai_ops q6tdm_ops = {
+ .prepare = q6afe_dai_prepare,
+ .shutdown = q6afe_dai_shutdown,
+ .set_sysclk = q6afe_mi2s_set_sysclk,
+ .set_tdm_slot = q6tdm_set_tdm_slot,
+ .set_channel_map = q6tdm_set_channel_map,
+ .hw_params = q6tdm_hw_params,
+};
+
static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
@@ -591,6 +862,86 @@
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
},
+ Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0),
+ Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1),
+ Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2),
+ Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3),
+ Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4),
+ Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5),
+ Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6),
+ Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7),
+ Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0),
+ Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1),
+ Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2),
+ Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3),
+ Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4),
+ Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5),
+ Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6),
+ Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7),
+ Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
+ Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
+ Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
+ Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
+ Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
+ Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
+ Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
+ Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
+ Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0),
+ Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1),
+ Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2),
+ Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3),
+ Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4),
+ Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5),
+ Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6),
+ Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7),
+ Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0),
+ Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1),
+ Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2),
+ Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3),
+ Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4),
+ Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5),
+ Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6),
+ Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6),
+ Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7),
+ Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0),
+ Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1),
+ Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2),
+ Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3),
+ Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4),
+ Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5),
+ Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6),
+ Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6),
+ Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7),
+ Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0),
+ Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1),
+ Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2),
+ Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3),
+ Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4),
+ Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5),
+ Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6),
+ Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7),
+ Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0),
+ Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1),
+ Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2),
+ Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3),
+ Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4),
+ Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5),
+ Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6),
+ Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7),
};
static int q6afe_of_xlate_dai_name(struct snd_soc_component *component,
@@ -640,6 +991,171 @@
0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("PRI_MI2S_TX", "Primary MI2S Capture",
0, 0, 0, 0),
+
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_0", "Primary TDM0 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_1", "Primary TDM1 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_2", "Primary TDM2 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_3", "Primary TDM3 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_4", "Primary TDM4 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_5", "Primary TDM5 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_6", "Primary TDM6 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_RX_7", "Primary TDM7 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_0", "Primary TDM0 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_1", "Primary TDM1 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_2", "Primary TDM2 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_3", "Primary TDM3 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_4", "Primary TDM4 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_5", "Primary TDM5 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_6", "Primary TDM6 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_TX_7", "Primary TDM7 Capture",
+ 0, 0, 0, 0),
+
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_0", "Secondary TDM0 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_1", "Secondary TDM1 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_2", "Secondary TDM2 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_3", "Secondary TDM3 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_4", "Secondary TDM4 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_5", "Secondary TDM5 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_6", "Secondary TDM6 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_7", "Secondary TDM7 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_0", "Secondary TDM0 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_1", "Secondary TDM1 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_2", "Secondary TDM2 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_3", "Secondary TDM3 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_4", "Secondary TDM4 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_5", "Secondary TDM5 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_6", "Secondary TDM6 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_7", "Secondary TDM7 Capture",
+ 0, 0, 0, 0),
+
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_0", "Tertiary TDM0 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_1", "Tertiary TDM1 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_2", "Tertiary TDM2 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_3", "Tertiary TDM3 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_4", "Tertiary TDM4 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_5", "Tertiary TDM5 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_6", "Tertiary TDM6 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_7", "Tertiary TDM7 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_0", "Tertiary TDM0 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_1", "Tertiary TDM1 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_2", "Tertiary TDM2 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_3", "Tertiary TDM3 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_4", "Tertiary TDM4 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_5", "Tertiary TDM5 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_6", "Tertiary TDM6 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_7", "Tertiary TDM7 Capture",
+ 0, 0, 0, 0),
+
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_0", "Quaternary TDM0 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_1", "Quaternary TDM1 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_2", "Quaternary TDM2 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_3", "Quaternary TDM3 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_4", "Quaternary TDM4 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_5", "Quaternary TDM5 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_6", "Quaternary TDM6 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_7", "Quaternary TDM7 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_0", "Quaternary TDM0 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_1", "Quaternary TDM1 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_2", "Quaternary TDM2 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_3", "Quaternary TDM3 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_4", "Quaternary TDM4 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_5", "Quaternary TDM5 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_6", "Quaternary TDM6 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_7", "Quaternary TDM7 Capture",
+ 0, 0, 0, 0),
+
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_0", "Quinary TDM0 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_1", "Quinary TDM1 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_2", "Quinary TDM2 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_3", "Quinary TDM3 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_4", "Quinary TDM4 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_5", "Quinary TDM5 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_6", "Quinary TDM6 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_7", "Quinary TDM7 Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_0", "Quinary TDM0 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_1", "Quinary TDM1 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_2", "Quinary TDM2 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_3", "Quinary TDM3 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_4", "Quinary TDM4 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_5", "Quinary TDM5 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_6", "Quinary TDM6 Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_7", "Quinary TDM7 Capture",
+ 0, 0, 0, 0),
};
static const struct snd_soc_component_driver q6afe_dai_component = {
@@ -688,6 +1204,45 @@
priv->sd_line_mask |= BIT(lines[i]);
break;
+ case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
+ priv = &data->priv[id];
+ ret = of_property_read_u32(node, "qcom,tdm-sync-mode",
+ &priv->sync_mode);
+ if (ret) {
+ dev_err(dev, "No Sync mode from DT\n");
+ break;
+ }
+ ret = of_property_read_u32(node, "qcom,tdm-sync-src",
+ &priv->sync_src);
+ if (ret) {
+ dev_err(dev, "No Sync Src from DT\n");
+ break;
+ }
+ ret = of_property_read_u32(node, "qcom,tdm-data-out",
+ &priv->data_out_enable);
+ if (ret) {
+ dev_err(dev, "No Data out enable from DT\n");
+ break;
+ }
+ ret = of_property_read_u32(node, "qcom,tdm-invert-sync",
+ &priv->invert_sync);
+ if (ret) {
+ dev_err(dev, "No Invert sync from DT\n");
+ break;
+ }
+ ret = of_property_read_u32(node, "qcom,tdm-data-delay",
+ &priv->data_delay);
+ if (ret) {
+ dev_err(dev, "No Data Delay from DT\n");
+ break;
+ }
+ ret = of_property_read_u32(node, "qcom,tdm-data-align",
+ &priv->data_align);
+ if (ret) {
+ dev_err(dev, "No Data align from DT\n");
+ break;
+ }
+ break;
default:
break;
}
diff --git a/sound/soc/qcom/qdsp6/q6afe.c b/sound/soc/qcom/qdsp6/q6afe.c
index de00300..01f4321 100644
--- a/sound/soc/qcom/qdsp6/q6afe.c
+++ b/sound/soc/qcom/qdsp6/q6afe.c
@@ -31,6 +31,7 @@
#define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106
#define AFE_PARAM_ID_HDMI_CONFIG 0x00010210
#define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C
+#define AFE_MODULE_TDM 0x0001028A
#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235
@@ -39,6 +40,8 @@
#define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212
#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D
+#define AFE_PARAM_ID_TDM_CONFIG 0x0001029D
+#define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297
/* I2S config specific */
#define AFE_API_VERSION_I2S_CONFIG 0x1
@@ -113,10 +116,194 @@
#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006
#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007
+/* Start of the range of port IDs for TDM devices. */
+#define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000
+
+/* End of the range of port IDs for TDM devices. */
+#define AFE_PORT_ID_TDM_PORT_RANGE_END \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1)
+
+/* Size of the range of port IDs for TDM ports. */
+#define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \
+ (AFE_PORT_ID_TDM_PORT_RANGE_END - \
+ AFE_PORT_ID_TDM_PORT_RANGE_START+1)
+
+#define AFE_PORT_ID_PRIMARY_TDM_RX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_1 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_2 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_3 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_4 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_5 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_6 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C)
+#define AFE_PORT_ID_PRIMARY_TDM_RX_7 \
+ (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E)
+
+#define AFE_PORT_ID_PRIMARY_TDM_TX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_1 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_2 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_3 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_4 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_5 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_6 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C)
+#define AFE_PORT_ID_PRIMARY_TDM_TX_7 \
+ (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E)
+
+#define AFE_PORT_ID_SECONDARY_TDM_RX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_1 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_2 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_3 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_4 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_5 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_6 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C)
+#define AFE_PORT_ID_SECONDARY_TDM_RX_7 \
+ (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E)
+
+#define AFE_PORT_ID_SECONDARY_TDM_TX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_1 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_2 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_3 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_4 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_5 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_6 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C)
+#define AFE_PORT_ID_SECONDARY_TDM_TX_7 \
+ (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E)
+
+#define AFE_PORT_ID_TERTIARY_TDM_RX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_1 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_2 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_3 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_4 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_5 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_6 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C)
+#define AFE_PORT_ID_TERTIARY_TDM_RX_7 \
+ (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E)
+
+#define AFE_PORT_ID_TERTIARY_TDM_TX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_1 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_2 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_3 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_4 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_5 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_6 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C)
+#define AFE_PORT_ID_TERTIARY_TDM_TX_7 \
+ (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E)
+
+#define AFE_PORT_ID_QUATERNARY_TDM_RX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C)
+#define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \
+ (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E)
+
+#define AFE_PORT_ID_QUATERNARY_TDM_TX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C)
+#define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \
+ (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E)
+
+#define AFE_PORT_ID_QUINARY_TDM_RX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40)
+#define AFE_PORT_ID_QUINARY_TDM_RX_1 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x02)
+#define AFE_PORT_ID_QUINARY_TDM_RX_2 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x04)
+#define AFE_PORT_ID_QUINARY_TDM_RX_3 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x06)
+#define AFE_PORT_ID_QUINARY_TDM_RX_4 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x08)
+#define AFE_PORT_ID_QUINARY_TDM_RX_5 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A)
+#define AFE_PORT_ID_QUINARY_TDM_RX_6 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C)
+#define AFE_PORT_ID_QUINARY_TDM_RX_7 \
+ (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E)
+
+#define AFE_PORT_ID_QUINARY_TDM_TX \
+ (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41)
+#define AFE_PORT_ID_QUINARY_TDM_TX_1 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x02)
+#define AFE_PORT_ID_QUINARY_TDM_TX_2 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x04)
+#define AFE_PORT_ID_QUINARY_TDM_TX_3 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x06)
+#define AFE_PORT_ID_QUINARY_TDM_TX_4 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x08)
+#define AFE_PORT_ID_QUINARY_TDM_TX_5 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A)
+#define AFE_PORT_ID_QUINARY_TDM_TX_6 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C)
+#define AFE_PORT_ID_QUINARY_TDM_TX_7 \
+ (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E)
+
#define Q6AFE_LPASS_MODE_CLK1_VALID 1
#define Q6AFE_LPASS_MODE_CLK2_VALID 2
#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
+#define AFE_API_VERSION_TDM_CONFIG 1
+#define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1
#define TIMEOUT_MS 1000
#define AFE_CMD_RESP_AVAIL 0
@@ -245,10 +432,27 @@
u16 reserved;
} __packed;
+struct afe_param_id_tdm_cfg {
+ u32 tdm_cfg_minor_version;
+ u32 num_channels;
+ u32 sample_rate;
+ u32 bit_width;
+ u16 data_format;
+ u16 sync_mode;
+ u16 sync_src;
+ u16 nslots_per_frame;
+ u16 ctrl_data_out_enable;
+ u16 ctrl_invert_sync_pulse;
+ u16 ctrl_sync_data_delay;
+ u16 slot_width;
+ u32 slot_mask;
+} __packed;
+
union afe_port_config {
struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
struct afe_param_id_slimbus_cfg slim_cfg;
struct afe_param_id_i2s_cfg i2s_cfg;
+ struct afe_param_id_tdm_cfg tdm_cfg;
} __packed;
@@ -261,9 +465,18 @@
uint32_t enable;
};
+struct afe_param_id_slot_mapping_cfg {
+ u32 minor_version;
+ u16 num_channels;
+ u16 bitwidth;
+ u32 data_align_type;
+ u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
+} __packed;
+
struct q6afe_port {
wait_queue_head_t wait;
union afe_port_config port_cfg;
+ struct afe_param_id_slot_mapping_cfg *scfg;
struct aprv2_ibasic_rsp_result_t result;
int token;
int id;
@@ -318,6 +531,166 @@
QUATERNARY_MI2S_RX, 1, 1},
[QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX,
QUATERNARY_MI2S_TX, 0, 1},
+ [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX,
+ PRIMARY_TDM_RX_0, 1, 1},
+ [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX,
+ PRIMARY_TDM_TX_0, 0, 1},
+ [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1,
+ PRIMARY_TDM_RX_1, 1, 1},
+ [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1,
+ PRIMARY_TDM_TX_1, 0, 1},
+ [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2,
+ PRIMARY_TDM_RX_2, 1, 1},
+ [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2,
+ PRIMARY_TDM_TX_2, 0, 1},
+ [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3,
+ PRIMARY_TDM_RX_3, 1, 1},
+ [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3,
+ PRIMARY_TDM_TX_3, 0, 1},
+ [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4,
+ PRIMARY_TDM_RX_4, 1, 1},
+ [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4,
+ PRIMARY_TDM_TX_4, 0, 1},
+ [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5,
+ PRIMARY_TDM_RX_5, 1, 1},
+ [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5,
+ PRIMARY_TDM_TX_5, 0, 1},
+ [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6,
+ PRIMARY_TDM_RX_6, 1, 1},
+ [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6,
+ PRIMARY_TDM_TX_6, 0, 1},
+ [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7,
+ PRIMARY_TDM_RX_7, 1, 1},
+ [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7,
+ PRIMARY_TDM_TX_7, 0, 1},
+ [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX,
+ SECONDARY_TDM_RX_0, 1, 1},
+ [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX,
+ SECONDARY_TDM_TX_0, 0, 1},
+ [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1,
+ SECONDARY_TDM_RX_1, 1, 1},
+ [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1,
+ SECONDARY_TDM_TX_1, 0, 1},
+ [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2,
+ SECONDARY_TDM_RX_2, 1, 1},
+ [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2,
+ SECONDARY_TDM_TX_2, 0, 1},
+ [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3,
+ SECONDARY_TDM_RX_3, 1, 1},
+ [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3,
+ SECONDARY_TDM_TX_3, 0, 1},
+ [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4,
+ SECONDARY_TDM_RX_4, 1, 1},
+ [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4,
+ SECONDARY_TDM_TX_4, 0, 1},
+ [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5,
+ SECONDARY_TDM_RX_5, 1, 1},
+ [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5,
+ SECONDARY_TDM_TX_5, 0, 1},
+ [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6,
+ SECONDARY_TDM_RX_6, 1, 1},
+ [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6,
+ SECONDARY_TDM_TX_6, 0, 1},
+ [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7,
+ SECONDARY_TDM_RX_7, 1, 1},
+ [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7,
+ SECONDARY_TDM_TX_7, 0, 1},
+ [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX,
+ TERTIARY_TDM_RX_0, 1, 1},
+ [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX,
+ TERTIARY_TDM_TX_0, 0, 1},
+ [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1,
+ TERTIARY_TDM_RX_1, 1, 1},
+ [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1,
+ TERTIARY_TDM_TX_1, 0, 1},
+ [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2,
+ TERTIARY_TDM_RX_2, 1, 1},
+ [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2,
+ TERTIARY_TDM_TX_2, 0, 1},
+ [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3,
+ TERTIARY_TDM_RX_3, 1, 1},
+ [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3,
+ TERTIARY_TDM_TX_3, 0, 1},
+ [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4,
+ TERTIARY_TDM_RX_4, 1, 1},
+ [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4,
+ TERTIARY_TDM_TX_4, 0, 1},
+ [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5,
+ TERTIARY_TDM_RX_5, 1, 1},
+ [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5,
+ TERTIARY_TDM_TX_5, 0, 1},
+ [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6,
+ TERTIARY_TDM_RX_6, 1, 1},
+ [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6,
+ TERTIARY_TDM_TX_6, 0, 1},
+ [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7,
+ TERTIARY_TDM_RX_7, 1, 1},
+ [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7,
+ TERTIARY_TDM_TX_7, 0, 1},
+ [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX,
+ QUATERNARY_TDM_RX_0, 1, 1},
+ [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX,
+ QUATERNARY_TDM_TX_0, 0, 1},
+ [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1,
+ QUATERNARY_TDM_RX_1, 1, 1},
+ [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1,
+ QUATERNARY_TDM_TX_1, 0, 1},
+ [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2,
+ QUATERNARY_TDM_RX_2, 1, 1},
+ [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2,
+ QUATERNARY_TDM_TX_2, 0, 1},
+ [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3,
+ QUATERNARY_TDM_RX_3, 1, 1},
+ [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3,
+ QUATERNARY_TDM_TX_3, 0, 1},
+ [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4,
+ QUATERNARY_TDM_RX_4, 1, 1},
+ [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4,
+ QUATERNARY_TDM_TX_4, 0, 1},
+ [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5,
+ QUATERNARY_TDM_RX_5, 1, 1},
+ [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5,
+ QUATERNARY_TDM_TX_5, 0, 1},
+ [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6,
+ QUATERNARY_TDM_RX_6, 1, 1},
+ [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6,
+ QUATERNARY_TDM_TX_6, 0, 1},
+ [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7,
+ QUATERNARY_TDM_RX_7, 1, 1},
+ [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7,
+ QUATERNARY_TDM_TX_7, 0, 1},
+ [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX,
+ QUINARY_TDM_RX_0, 1, 1},
+ [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX,
+ QUINARY_TDM_TX_0, 0, 1},
+ [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1,
+ QUINARY_TDM_RX_1, 1, 1},
+ [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1,
+ QUINARY_TDM_TX_1, 0, 1},
+ [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2,
+ QUINARY_TDM_RX_2, 1, 1},
+ [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2,
+ QUINARY_TDM_TX_2, 0, 1},
+ [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3,
+ QUINARY_TDM_RX_3, 1, 1},
+ [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3,
+ QUINARY_TDM_TX_3, 0, 1},
+ [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4,
+ QUINARY_TDM_RX_4, 1, 1},
+ [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4,
+ QUINARY_TDM_TX_4, 0, 1},
+ [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5,
+ QUINARY_TDM_RX_5, 1, 1},
+ [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5,
+ QUINARY_TDM_TX_5, 0, 1},
+ [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6,
+ QUINARY_TDM_RX_6, 1, 1},
+ [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6,
+ QUINARY_TDM_TX_6, 0, 1},
+ [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7,
+ QUINARY_TDM_RX_7, 1, 1},
+ [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7,
+ QUINARY_TDM_TX_7, 0, 1},
};
static void q6afe_port_free(struct kref *ref)
@@ -331,6 +704,7 @@
spin_lock_irqsave(&afe->port_list_lock, flags);
list_del(&port->node);
spin_unlock_irqrestore(&afe->port_list_lock, flags);
+ kfree(port->scfg);
kfree(port);
}
@@ -601,7 +975,9 @@
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID;
ret = q6afe_set_lpass_clock(port, &ccfg);
break;
- case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
+ case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
+ case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
+ case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
cset.clk_id = clk_id;
cset.clk_freq_in_hz = freq;
@@ -697,6 +1073,42 @@
EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare);
/**
+ * q6afe_tdm_port_prepare() - Prepare tdm afe port.
+ *
+ * @port: Instance of afe port
+ * @cfg: TDM configuration for the afe port
+ *
+ */
+void q6afe_tdm_port_prepare(struct q6afe_port *port,
+ struct q6afe_tdm_cfg *cfg)
+{
+ union afe_port_config *pcfg = &port->port_cfg;
+
+ pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG;
+ pcfg->tdm_cfg.num_channels = cfg->num_channels;
+ pcfg->tdm_cfg.sample_rate = cfg->sample_rate;
+ pcfg->tdm_cfg.bit_width = cfg->bit_width;
+ pcfg->tdm_cfg.data_format = cfg->data_format;
+ pcfg->tdm_cfg.sync_mode = cfg->sync_mode;
+ pcfg->tdm_cfg.sync_src = cfg->sync_src;
+ pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame;
+
+ pcfg->tdm_cfg.slot_width = cfg->slot_width;
+ pcfg->tdm_cfg.slot_mask = cfg->slot_mask;
+ port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL);
+ if (!port->scfg)
+ return;
+
+ port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG;
+ port->scfg->num_channels = cfg->num_channels;
+ port->scfg->bitwidth = cfg->bit_width;
+ port->scfg->data_align_type = cfg->data_align_type;
+ memcpy(port->scfg->ch_mapping, cfg->ch_mapping,
+ sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT);
+}
+EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare);
+
+/**
* q6afe_hdmi_port_prepare() - Prepare hdmi afe port.
*
* @port: Instance of afe port
@@ -886,6 +1298,17 @@
return ret;
}
+ if (port->scfg) {
+ ret = q6afe_port_set_param_v2(port, port->scfg,
+ AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG,
+ AFE_MODULE_TDM, sizeof(*port->scfg));
+ if (ret) {
+ dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
+ port_id, ret);
+ return ret;
+ }
+ }
+
pkt_size = APR_HDR_SIZE + sizeof(*start);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
@@ -970,6 +1393,10 @@
case AFE_PORT_ID_QUATERNARY_MI2S_TX:
cfg_type = AFE_PARAM_ID_I2S_CONFIG;
break;
+ case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7:
+ cfg_type = AFE_PARAM_ID_TDM_CONFIG;
+ break;
+
default:
dev_err(dev, "Invalid port id 0x%x\n", port_id);
return ERR_PTR(-EINVAL);
diff --git a/sound/soc/qcom/qdsp6/q6afe.h b/sound/soc/qcom/qdsp6/q6afe.h
index 5ca54a9..c7ed542 100644
--- a/sound/soc/qcom/qdsp6/q6afe.h
+++ b/sound/soc/qcom/qdsp6/q6afe.h
@@ -5,7 +5,7 @@
#include <dt-bindings/sound/qcom,q6afe.h>
-#define AFE_PORT_MAX 48
+#define AFE_PORT_MAX 105
#define MSM_AFE_PORT_TYPE_RX 0
#define MSM_AFE_PORT_TYPE_TX 1
@@ -144,6 +144,8 @@
/* Clock attribute for invert and no couple case */
#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
+#define Q6AFE_CMAP_INVALID 0xFFFF
+
struct q6afe_hdmi_cfg {
u16 datatype;
u16 channel_allocation;
@@ -168,10 +170,25 @@
int fmt;
};
+struct q6afe_tdm_cfg {
+ u16 num_channels;
+ u32 sample_rate;
+ u16 bit_width;
+ u16 data_format;
+ u16 sync_mode;
+ u16 sync_src;
+ u16 nslots_per_frame;
+ u16 slot_width;
+ u16 slot_mask;
+ u32 data_align_type;
+ u16 ch_mapping[AFE_MAX_CHAN_COUNT];
+};
+
struct q6afe_port_config {
struct q6afe_hdmi_cfg hdmi;
struct q6afe_slim_cfg slim;
struct q6afe_i2s_cfg i2s_cfg;
+ struct q6afe_tdm_cfg tdm;
};
struct q6afe_port;
@@ -186,6 +203,7 @@
void q6afe_slim_port_prepare(struct q6afe_port *port,
struct q6afe_slim_cfg *cfg);
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
+void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
int clk_src, int clk_root,
diff --git a/sound/soc/qcom/qdsp6/q6routing.c b/sound/soc/qcom/qdsp6/q6routing.c
index 08c25c2..593f66b 100644
--- a/sound/soc/qcom/qdsp6/q6routing.c
+++ b/sound/soc/qcom/qdsp6/q6routing.c
@@ -26,6 +26,223 @@
#define DRV_NAME "q6routing-component"
+#define Q6ROUTING_RX_MIXERS(id) \
+ SOC_SINGLE_EXT("MultiMedia1", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia2", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia3", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia4", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia5", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia6", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia7", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("MultiMedia8", id, \
+ MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,\
+ msm_routing_put_audio_mixer),
+
+#define Q6ROUTING_RX_DAPM_ROUTE(mix_name, s) \
+ { mix_name, "MultiMedia1", "MM_DL1" }, \
+ { mix_name, "MultiMedia2", "MM_DL2" }, \
+ { mix_name, "MultiMedia3", "MM_DL3" }, \
+ { mix_name, "MultiMedia4", "MM_DL4" }, \
+ { mix_name, "MultiMedia5", "MM_DL5" }, \
+ { mix_name, "MultiMedia6", "MM_DL6" }, \
+ { mix_name, "MultiMedia7", "MM_DL7" }, \
+ { mix_name, "MultiMedia8", "MM_DL8" }, \
+ { s, NULL, mix_name }
+
+#define Q6ROUTING_TX_DAPM_ROUTE(mix_name) \
+ { mix_name, "PRI_MI2S_TX", "PRI_MI2S_TX" }, \
+ { mix_name, "SEC_MI2S_TX", "SEC_MI2S_TX" }, \
+ { mix_name, "QUAT_MI2S_TX", "QUAT_MI2S_TX" }, \
+ { mix_name, "TERT_MI2S_TX", "TERT_MI2S_TX" }, \
+ { mix_name, "PRIMARY_TDM_TX_0", "PRIMARY_TDM_TX_0"}, \
+ { mix_name, "PRIMARY_TDM_TX_1", "PRIMARY_TDM_TX_1"}, \
+ { mix_name, "PRIMARY_TDM_TX_2", "PRIMARY_TDM_TX_2"}, \
+ { mix_name, "PRIMARY_TDM_TX_3", "PRIMARY_TDM_TX_3"}, \
+ { mix_name, "PRIMARY_TDM_TX_4", "PRIMARY_TDM_TX_4"}, \
+ { mix_name, "PRIMARY_TDM_TX_5", "PRIMARY_TDM_TX_5"}, \
+ { mix_name, "PRIMARY_TDM_TX_6", "PRIMARY_TDM_TX_6"}, \
+ { mix_name, "PRIMARY_TDM_TX_7", "PRIMARY_TDM_TX_7"}, \
+ { mix_name, "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, \
+ { mix_name, "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, \
+ { mix_name, "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, \
+ { mix_name, "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, \
+ { mix_name, "SEC_TDM_TX_4", "SEC_TDM_TX_4"}, \
+ { mix_name, "SEC_TDM_TX_5", "SEC_TDM_TX_5"}, \
+ { mix_name, "SEC_TDM_TX_6", "SEC_TDM_TX_6"}, \
+ { mix_name, "SEC_TDM_TX_7", "SEC_TDM_TX_7"}, \
+ { mix_name, "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, \
+ { mix_name, "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, \
+ { mix_name, "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, \
+ { mix_name, "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, \
+ { mix_name, "TERT_TDM_TX_4", "TERT_TDM_TX_4"}, \
+ { mix_name, "TERT_TDM_TX_5", "TERT_TDM_TX_5"}, \
+ { mix_name, "TERT_TDM_TX_6", "TERT_TDM_TX_6"}, \
+ { mix_name, "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, \
+ { mix_name, "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, \
+ { mix_name, "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, \
+ { mix_name, "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, \
+ { mix_name, "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, \
+ { mix_name, "QUAT_TDM_TX_4", "QUAT_TDM_TX_4"}, \
+ { mix_name, "QUAT_TDM_TX_5", "QUAT_TDM_TX_5"}, \
+ { mix_name, "QUAT_TDM_TX_6", "QUAT_TDM_TX_6"}, \
+ { mix_name, "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, \
+ { mix_name, "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, \
+ { mix_name, "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, \
+ { mix_name, "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, \
+ { mix_name, "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, \
+ { mix_name, "QUIN_TDM_TX_4", "QUIN_TDM_TX_4"}, \
+ { mix_name, "QUIN_TDM_TX_5", "QUIN_TDM_TX_5"}, \
+ { mix_name, "QUIN_TDM_TX_6", "QUIN_TDM_TX_6"}, \
+ { mix_name, "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}
+
+#define Q6ROUTING_TX_MIXERS(id) \
+ SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_0", PRIMARY_TDM_TX_0, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_1", PRIMARY_TDM_TX_1, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_2", PRIMARY_TDM_TX_2, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_3", PRIMARY_TDM_TX_3, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_4", PRIMARY_TDM_TX_4, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_5", PRIMARY_TDM_TX_5, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_6", PRIMARY_TDM_TX_6, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("PRIMARY_TDM_TX_7", PRIMARY_TDM_TX_7, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_0", SECONDARY_TDM_TX_0, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_1", SECONDARY_TDM_TX_1, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_2", SECONDARY_TDM_TX_2, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_3", SECONDARY_TDM_TX_3, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_4", SECONDARY_TDM_TX_4, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_5", SECONDARY_TDM_TX_5, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_6", SECONDARY_TDM_TX_6, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("SEC_TDM_TX_7", SECONDARY_TDM_TX_7, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_0", TERTIARY_TDM_TX_0, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_1", TERTIARY_TDM_TX_1, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_2", TERTIARY_TDM_TX_2, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_3", TERTIARY_TDM_TX_3, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_4", TERTIARY_TDM_TX_4, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_5", TERTIARY_TDM_TX_5, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_6", TERTIARY_TDM_TX_6, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("TERT_TDM_TX_7", TERTIARY_TDM_TX_7, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_0", QUATERNARY_TDM_TX_0, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_1", QUATERNARY_TDM_TX_1, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_2", QUATERNARY_TDM_TX_2, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_3", QUATERNARY_TDM_TX_3, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_4", QUATERNARY_TDM_TX_4, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_5", QUATERNARY_TDM_TX_5, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_6", QUATERNARY_TDM_TX_6, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUAT_TDM_TX_7", QUATERNARY_TDM_TX_7, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_0", QUINARY_TDM_TX_0, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_1", QUINARY_TDM_TX_1, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_2", QUINARY_TDM_TX_2, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_3", QUINARY_TDM_TX_3, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_4", QUINARY_TDM_TX_4, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_5", QUINARY_TDM_TX_5, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_6", QUINARY_TDM_TX_6, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer), \
+ SOC_SINGLE_EXT("QUIN_TDM_TX_7", QUINARY_TDM_TX_7, \
+ id, 1, 0, msm_routing_get_audio_mixer, \
+ msm_routing_put_audio_mixer),
+
struct session_data {
int state;
int port_id;
@@ -207,430 +424,185 @@
}
static const struct snd_kcontrol_new hdmi_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", HDMI_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0,
- msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(HDMI_RX) };
static const struct snd_kcontrol_new primary_mi2s_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", PRIMARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(PRIMARY_MI2S_RX) };
static const struct snd_kcontrol_new secondary_mi2s_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SECONDARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SECONDARY_MI2S_RX) };
static const struct snd_kcontrol_new quaternary_mi2s_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", QUATERNARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(QUATERNARY_MI2S_RX) };
static const struct snd_kcontrol_new tertiary_mi2s_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", TERTIARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", TERTIARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", TERTIARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", TERTIARY_MI2S_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
-
+ Q6ROUTING_RX_MIXERS(TERTIARY_MI2S_RX) };
static const struct snd_kcontrol_new slimbus_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SLIMBUS_0_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_0_RX) };
static const struct snd_kcontrol_new slimbus_1_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SLIMBUS_1_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_1_RX) };
static const struct snd_kcontrol_new slimbus_2_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SLIMBUS_2_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_2_RX) };
static const struct snd_kcontrol_new slimbus_3_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SLIMBUS_3_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_3_RX) };
static const struct snd_kcontrol_new slimbus_4_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_4_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_4_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_4_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_4_RX) };
static const struct snd_kcontrol_new slimbus_5_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SLIMBUS_5_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_5_RX) };
static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = {
- SOC_SINGLE_EXT("MultiMedia1", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia2", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia3", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia4", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia5", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia6", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia7", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("MultiMedia8", SLIMBUS_6_RX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_RX_MIXERS(SLIMBUS_6_RX) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_0_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_0) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_1_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_1) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_2_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_2) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_3_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_3) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_4_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_4) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_5_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_5) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_6_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_6) };
+
+static const struct snd_kcontrol_new pri_tdm_rx_7_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_7) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_0_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_0) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_1_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_1) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_2_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_2) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_3_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_3) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_4_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_4) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_5_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_5) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_6_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_6) };
+
+static const struct snd_kcontrol_new sec_tdm_rx_7_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_7) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_0_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_0) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_1_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_1) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_2_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_2) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_3_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_3) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_4_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_4) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_5_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_5) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_6_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_6) };
+
+static const struct snd_kcontrol_new tert_tdm_rx_7_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_7) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_0_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_0) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_1) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_2) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_3) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_4_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_4) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_5_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_5) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_6_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_6) };
+
+static const struct snd_kcontrol_new quat_tdm_rx_7_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_7) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_0) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_1_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_1) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_2_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_2) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_3_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_3) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_4_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_4) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_5_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_5) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_6_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_6) };
+
+static const struct snd_kcontrol_new quin_tdm_rx_7_mixer_controls[] = {
+ Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_7) };
+
static const struct snd_kcontrol_new mmul1_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA1) };
static const struct snd_kcontrol_new mmul2_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA2) };
static const struct snd_kcontrol_new mmul3_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA3) };
static const struct snd_kcontrol_new mmul4_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA4) };
static const struct snd_kcontrol_new mmul5_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA5) };
static const struct snd_kcontrol_new mmul6_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA6) };
static const struct snd_kcontrol_new mmul7_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA7) };
static const struct snd_kcontrol_new mmul8_mixer_controls[] = {
- SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
- SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX,
- MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
- msm_routing_put_audio_mixer),
-};
+ Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA8) };
static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = {
/* Frontend AIF */
@@ -689,6 +661,130 @@
SND_SOC_DAPM_MIXER("TERT_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
tertiary_mi2s_rx_mixer_controls,
ARRAY_SIZE(tertiary_mi2s_rx_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_0_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_0_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_1_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_1_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_2_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_2_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_3_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_3_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_4_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_4_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_5_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_5_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_6_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_6_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ pri_tdm_rx_7_mixer_controls,
+ ARRAY_SIZE(pri_tdm_rx_7_mixer_controls)),
+
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_0_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_0_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_1_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_1_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_2_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_2_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_3_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_3_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_4_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_4_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_5_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_5_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_6_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_6_mixer_controls)),
+ SND_SOC_DAPM_MIXER("SEC_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ sec_tdm_rx_7_mixer_controls,
+ ARRAY_SIZE(sec_tdm_rx_7_mixer_controls)),
+
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_0_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_0_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_1_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_1_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_2_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_2_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_3_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_3_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_4_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_4_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_5_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_5_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_6_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_6_mixer_controls)),
+ SND_SOC_DAPM_MIXER("TERT_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ tert_tdm_rx_7_mixer_controls,
+ ARRAY_SIZE(tert_tdm_rx_7_mixer_controls)),
+
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_0_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_0_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_1_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_1_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_2_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_2_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_3_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_3_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_4_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_4_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_5_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_5_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_6_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_6_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUAT_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quat_tdm_rx_7_mixer_controls,
+ ARRAY_SIZE(quat_tdm_rx_7_mixer_controls)),
+
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_0_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_0_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_1_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_1_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_2_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_2_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_3_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_3_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_4_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_4_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_5_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_5_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_6_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_6_mixer_controls)),
+ SND_SOC_DAPM_MIXER("QUIN_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
+ quin_tdm_rx_7_mixer_controls,
+ ARRAY_SIZE(quin_tdm_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0,
mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0,
@@ -709,154 +805,74 @@
};
static const struct snd_soc_dapm_route intercon[] = {
- {"HDMI Mixer", "MultiMedia1", "MM_DL1"},
- {"HDMI Mixer", "MultiMedia2", "MM_DL2"},
- {"HDMI Mixer", "MultiMedia3", "MM_DL3"},
- {"HDMI Mixer", "MultiMedia4", "MM_DL4"},
- {"HDMI Mixer", "MultiMedia5", "MM_DL5"},
- {"HDMI Mixer", "MultiMedia6", "MM_DL6"},
- {"HDMI Mixer", "MultiMedia7", "MM_DL7"},
- {"HDMI Mixer", "MultiMedia8", "MM_DL8"},
- {"HDMI_RX", NULL, "HDMI Mixer"},
-
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SLIMBUS_0_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Audio Mixer"},
-
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SLIMBUS_1_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"SLIMBUS_1_RX", NULL, "SLIMBUS_1_RX Audio Mixer"},
-
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SLIMBUS_2_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"SLIMBUS_2_RX", NULL, "SLIMBUS_2_RX Audio Mixer"},
-
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SLIMBUS_3_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"SLIMBUS_3_RX", NULL, "SLIMBUS_3_RX Audio Mixer"},
-
- {"SLIMBUS_4_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_4_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_4_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_4_RX", NULL, "SLIMBUS_4_RX Audio Mixer"},
-
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SLIMBUS_5_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"SLIMBUS_5_RX", NULL, "SLIMBUS_5_RX Audio Mixer"},
-
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SLIMBUS_6_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"SLIMBUS_6_RX", NULL, "SLIMBUS_6_RX Audio Mixer"},
-
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"QUAT_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
- {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX Audio Mixer"},
-
- {"TERT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"TERT_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"TERT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"TERT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX Audio Mixer"},
-
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL5"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"SEC_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL7"},
- {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX Audio Mixer"},
-
- {"PRI_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
- {"PRI_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
- {"PRI_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
- {"PRI_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
- {"PRI_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
- {"PRI_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
- {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX Audio Mixer"},
-
- {"MultiMedia1 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia1 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia1 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia1 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia2 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia2 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia2 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia2 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia3 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia3 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia3 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia3 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia4 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia4 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia4 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia4 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia5 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia5 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia5 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia5 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia6 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia6 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia6 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia6 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia7 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia7 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia7 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia7 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
-
- {"MultiMedia8 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
- {"MultiMedia8 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
- {"MultiMedia8 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"},
- {"MultiMedia8 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"},
+ Q6ROUTING_RX_DAPM_ROUTE("HDMI Mixer", "HDMI_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_0_RX Audio Mixer", "SLIMBUS_0_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_1_RX Audio Mixer", "SLIMBUS_1_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_2_RX Audio Mixer", "SLIMBUS_2_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_3_RX Audio Mixer", "SLIMBUS_3_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_4_RX Audio Mixer", "SLIMBUS_4_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_5_RX Audio Mixer", "SLIMBUS_5_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_6_RX Audio Mixer", "SLIMBUS_6_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_MI2S_RX Audio Mixer", "QUAT_MI2S_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_MI2S_RX Audio Mixer", "TERT_MI2S_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_MI2S_RX Audio Mixer", "SEC_MI2S_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRI_MI2S_RX Audio Mixer", "PRI_MI2S_RX"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_0 Audio Mixer",
+ "PRIMARY_TDM_RX_0"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_1 Audio Mixer",
+ "PRIMARY_TDM_RX_1"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_2 Audio Mixer",
+ "PRIMARY_TDM_RX_2"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_3 Audio Mixer",
+ "PRIMARY_TDM_RX_3"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_4 Audio Mixer",
+ "PRIMARY_TDM_RX_4"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_5 Audio Mixer",
+ "PRIMARY_TDM_RX_5"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_6 Audio Mixer",
+ "PRIMARY_TDM_RX_6"),
+ Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_7 Audio Mixer",
+ "PRIMARY_TDM_RX_7"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_0 Audio Mixer", "SEC_TDM_RX_0"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_1 Audio Mixer", "SEC_TDM_RX_1"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_2 Audio Mixer", "SEC_TDM_RX_2"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_3 Audio Mixer", "SEC_TDM_RX_3"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_4 Audio Mixer", "SEC_TDM_RX_4"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_5 Audio Mixer", "SEC_TDM_RX_5"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_6 Audio Mixer", "SEC_TDM_RX_6"),
+ Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_7 Audio Mixer", "SEC_TDM_RX_7"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_0 Audio Mixer", "TERT_TDM_RX_0"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_1 Audio Mixer", "TERT_TDM_RX_1"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_2 Audio Mixer", "TERT_TDM_RX_2"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_3 Audio Mixer", "TERT_TDM_RX_3"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_4 Audio Mixer", "TERT_TDM_RX_4"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_5 Audio Mixer", "TERT_TDM_RX_5"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_6 Audio Mixer", "TERT_TDM_RX_6"),
+ Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_7 Audio Mixer", "TERT_TDM_RX_7"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_0 Audio Mixer", "QUAT_TDM_RX_0"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_1 Audio Mixer", "QUAT_TDM_RX_1"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_2 Audio Mixer", "QUAT_TDM_RX_2"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_3 Audio Mixer", "QUAT_TDM_RX_3"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_4 Audio Mixer", "QUAT_TDM_RX_4"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_5 Audio Mixer", "QUAT_TDM_RX_5"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_6 Audio Mixer", "QUAT_TDM_RX_6"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_7 Audio Mixer", "QUAT_TDM_RX_7"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_0 Audio Mixer", "QUIN_TDM_RX_0"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_1 Audio Mixer", "QUIN_TDM_RX_1"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_2 Audio Mixer", "QUIN_TDM_RX_2"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_3 Audio Mixer", "QUIN_TDM_RX_3"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_4 Audio Mixer", "QUIN_TDM_RX_4"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_5 Audio Mixer", "QUIN_TDM_RX_5"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_6 Audio Mixer", "QUIN_TDM_RX_6"),
+ Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_7 Audio Mixer", "QUIN_TDM_RX_7"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia1 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia2 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia3 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia4 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia5 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia6 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia7 Mixer"),
+ Q6ROUTING_TX_DAPM_ROUTE("MultiMedia8 Mixer"),
{"MM_UL1", NULL, "MultiMedia1 Mixer"},
{"MM_UL2", NULL, "MultiMedia2 Mixer"},
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index b516f92..cc63b90 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -590,14 +590,23 @@
{
struct snd_soc_rtdcom_list *rtdcom;
+ if (!driver_name)
+ return NULL;
+
for_each_rtdcom(rtd, rtdcom) {
- if ((rtdcom->component->driver->name == driver_name) ||
- strcmp(rtdcom->component->driver->name, driver_name) == 0)
+ const char *component_name = rtdcom->component->driver->name;
+
+ if (!component_name)
+ continue;
+
+ if ((component_name == driver_name) ||
+ strcmp(component_name, driver_name) == 0)
return rtdcom->component;
}
return NULL;
}
+EXPORT_SYMBOL_GPL(snd_soc_rtdcom_lookup);
struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card,
const char *dai_link, int stream)
@@ -1191,11 +1200,6 @@
rtd->platform = platform;
}
- if (!rtd->platform) {
- dev_err(card->dev, "ASoC: platform %s not registered\n",
- dai_link->platform_name);
- goto _err_defer;
- }
soc_add_pcm_runtime(card, rtd);
return 0;
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 9d4748e..405408a 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -430,6 +430,8 @@
static void dapm_kcontrol_free(struct snd_kcontrol *kctl)
{
struct dapm_kcontrol_data *data = snd_kcontrol_chip(kctl);
+
+ list_del(&data->paths);
kfree(data->wlist);
kfree(data);
}
diff --git a/tools/build/Build.include b/tools/build/Build.include
index 418871d..d9048f1 100644
--- a/tools/build/Build.include
+++ b/tools/build/Build.include
@@ -12,6 +12,7 @@
# Convenient variables
comma := ,
squote := '
+pound := \#
###
# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
@@ -43,11 +44,11 @@
###
# Replace >$< with >$$< to preserve $ when reloading the .cmd file
# (needed for make)
-# Replace >#< with >\#< to avoid starting a comment in the .cmd file
+# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
# (needed for make)
# Replace >'< with >'\''< to be able to enclose the whole string in '...'
# (needed for the shell)
-make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1)))))
+make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
###
# Find any prerequisites that is newer than target or that does not exist.
@@ -62,8 +63,8 @@
$(fixdep) $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp; \
rm -f $(depfile); \
mv -f $(dot-target).tmp $(dot-target).cmd, \
- printf '\# cannot find fixdep (%s)\n' $(fixdep) > $(dot-target).cmd; \
- printf '\# using basic dep data\n\n' >> $(dot-target).cmd; \
+ printf '$(pound) cannot find fixdep (%s)\n' $(fixdep) > $(dot-target).cmd; \
+ printf '$(pound) using basic dep data\n\n' >> $(dot-target).cmd; \
cat $(depfile) >> $(dot-target).cmd; \
printf '\n%s\n' 'cmd_$@ := $(make-cmd)' >> $(dot-target).cmd)
diff --git a/tools/objtool/Makefile b/tools/objtool/Makefile
index e6acc28..8ae824d 100644
--- a/tools/objtool/Makefile
+++ b/tools/objtool/Makefile
@@ -35,7 +35,7 @@
LDFLAGS += -lelf $(LIBSUBCMD)
# Allow old libelf to be used:
-elfshdr := $(shell echo '\#include <libelf.h>' | $(CC) $(CFLAGS) -x c -E - | grep elf_getshdr)
+elfshdr := $(shell echo '$(pound)include <libelf.h>' | $(CC) $(CFLAGS) -x c -E - | grep elf_getshdr)
CFLAGS += $(if $(elfshdr),,-DLIBELF_USE_DEPRECATED)
AWK = awk
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
new file mode 100644
index 0000000..b4791b4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
@@ -0,0 +1,1453 @@
+[
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
+ "EventCode": "0x2E",
+ "Counter": "0,1,2,3",
+ "UMask": "0x41",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LONGEST_LAT_CACHE.MISS",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "L2 cache request misses"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
+ "EventCode": "0x2E",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4f",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "L2 cache requests"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
+ "EventCode": "0x30",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "L2_REJECT_XQ.ALL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Requests rejected by the XQ"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
+ "EventCode": "0x31",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "CORE_REJECT_L2Q.ALL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Requests rejected by the L2Q"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.",
+ "EventCode": "0x51",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DL1.REPLACEMENT",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "L1 Cache evictions for dirty data"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
+ "EventCode": "0x86",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "EventCode": "0xB7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x21",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Locked load uops retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x41",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x42",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x43",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.SPLIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts the number of load uops retired.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x81",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts the number of store uops retired.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x82",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Store uops retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x83",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.ALL",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Memory uops retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired that hit the L1 data cache.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired that hit L2 (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired that missed L2 (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads retired that hit WCB (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.",
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads retired that came from DRAM (Precise event capable)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010008",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040008",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000008",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000008",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000008",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010020",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040020",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000020",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000020",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000020",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010400",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040400",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000400",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000400",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000400",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000011000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000041000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200001000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000001000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000001000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000012000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000042000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200002000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000002000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000002000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000014800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000044800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200004800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000004800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000004800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000018000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000048000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200008000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000008000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000008000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000013010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000043010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200003010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000003010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000003010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000013091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000043091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200003091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000003091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000003091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000010022",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0000040022",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x0200000022",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x1000000022",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x4000000022",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x00000132b7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x00000432b7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x02000032b7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. ",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x10000032b7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6, 0x1a7",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
+ "Offcore": "1"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
+ "EventCode": "0xB7",
+ "MSRValue": "0x40000032b7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
+ "PDIR_COUNTER": "na",
+ "MSRIndex": "0x1a6",
+ "SampleAfterValue": "100007",
+ "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "Offcore": "1"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
new file mode 100644
index 0000000..a787896
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
@@ -0,0 +1,62 @@
+[
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ICACHE.HIT",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ICACHE.MISSES",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ICACHE.ACCESSES",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
+ "EventCode": "0xE7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MS_DECODED.MS_ENTRY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "MS decode starts"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
+ "EventCode": "0xE9",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Decode restrictions due to predicting wrong instruction length"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
new file mode 100644
index 0000000..91e0815
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
@@ -0,0 +1,38 @@
+[
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",
+ "EventCode": "0x13",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops that split a page (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",
+ "EventCode": "0x13",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Store uops that split a page (Precise event capable)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.",
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "Machine clears due to memory ordering issue"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
new file mode 100644
index 0000000..b860374
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
@@ -0,0 +1,98 @@
+[
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
+ "EventCode": "0x86",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "FETCH_STALL.ALL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles code-fetch stalled due to any reason."
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
+ "EventCode": "0x86",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding."
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
+ "EventCode": "0xCA",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Unfilled issue slots per cycle"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
+ "EventCode": "0xCA",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
+ "EventCode": "0xCA",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Unfilled issue slots per cycle to recover"
+ },
+ {
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts hardware interrupts received by the processor.",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "HW_INTERRUPTS.RECEIVED",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "203",
+ "BriefDescription": "Hardware interrupts received"
+ },
+ {
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "HW_INTERRUPTS.MASKED",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles hardware interrupts are masked"
+ },
+ {
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles pending interrupts are masked"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
new file mode 100644
index 0000000..ccf1aed
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
@@ -0,0 +1,544 @@
+[
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
+ "EventCode": "0x00",
+ "Counter": "Fixed counter 0",
+ "UMask": "0x1",
+ "PEBScounters": "32",
+ "EventName": "INST_RETIRED.ANY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Instructions retired (Fixed event)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
+ "EventCode": "0x00",
+ "Counter": "Fixed counter 1",
+ "UMask": "0x2",
+ "PEBScounters": "33",
+ "EventName": "CPU_CLK_UNHALTED.CORE",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Core cycles when core is not halted (Fixed event)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
+ "EventCode": "0x00",
+ "Counter": "Fixed counter 2",
+ "UMask": "0x3",
+ "PEBScounters": "34",
+ "EventName": "CPU_CLK_UNHALTED.REF_TSC",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Reference cycles when core is not halted (Fixed event)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.",
+ "EventCode": "0x03",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LD_BLOCKS.DATA_UNKNOWN",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
+ "EventCode": "0x03",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LD_BLOCKS.STORE_FORWARD",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
+ "EventCode": "0x03",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LD_BLOCKS.4K_ALIAS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
+ "EventCode": "0x03",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LD_BLOCKS.UTLB_MISS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
+ "EventCode": "0x03",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "LD_BLOCKS.ALL_BLOCK",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Loads blocked (Precise event capable)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
+ "EventCode": "0x0E",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "UOPS_ISSUED.ANY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Uops issued to the back end per cycle"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
+ "EventCode": "0x3C",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "CPU_CLK_UNHALTED.CORE_P",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Core cycles when core is not halted"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
+ "EventCode": "0x3C",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "CPU_CLK_UNHALTED.REF",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Reference cycles when core is not halted"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
+ "EventCode": "0x9C",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "UOPS_NOT_DELIVERED.ANY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
+ "EventCode": "0xC0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "INST_RETIRED.ANY_P",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Instructions retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired.",
+ "EventCode": "0xC0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "EventName": "INST_RETIRED.PREC_DIST",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts uops which retired.",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "UOPS_RETIRED.ANY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Uops retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "UOPS_RETIRED.MS",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "MS uops retired (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of floating point divide uops retired.",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "UOPS_RETIRED.FPDIV",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Floating point divide uops retired (Precise Event Capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of integer divide uops retired.",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "UOPS_RETIRED.IDIV",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Integer divide uops retired (Precise Event Capable)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts machine clears for any reason.",
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MACHINE_CLEARS.ALL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "All machine clears"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.",
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MACHINE_CLEARS.SMC",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "Self-Modifying Code detected"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MACHINE_CLEARS.FP_ASSIST",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "Machine clears due to FP assists"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "Machine clears due to memory disambiguation"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation",
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MACHINE_CLEARS.PAGE_FAULT",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "Machines clear due to a page fault"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired branch instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7e",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.JCC",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired conditional branch instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts the number of taken branch instructions retired.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired taken branch instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xbf",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.FAR_BRANCH",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired far branch instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xeb",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts near return branch instructions retired.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf7",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.RETURN",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired near return instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts near CALL branch instructions retired.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf9",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.CALL",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired near call instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts near indirect CALL branch instructions retired.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xfb",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.IND_CALL",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired near indirect call instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts near relative CALL branch instructions retired.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xfd",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.REL_CALL",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired near relative call instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0xfe",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_INST_RETIRED.TAKEN_JCC",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7e",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_MISP_RETIRED.JCC",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0xeb",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf7",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_MISP_RETIRED.RETURN",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0xfb",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_MISP_RETIRED.IND_CALL",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0xfe",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts core cycles if either divide unit is busy.",
+ "EventCode": "0xCD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "CYCLES_DIV_BUSY.ALL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Cycles a divider is busy"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts core cycles the integer divide unit is busy.",
+ "EventCode": "0xCD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "CYCLES_DIV_BUSY.IDIV",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles the integer divide unit is busy"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts core cycles the floating point divide unit is busy.",
+ "EventCode": "0xCD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "CYCLES_DIV_BUSY.FPDIV",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Cycles the FP divide unit is busy"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
+ "EventCode": "0xE6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BACLEARS.ALL",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "BACLEARs asserted for any branch type"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts BACLEARS on return instructions.",
+ "EventCode": "0xE6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BACLEARS.RETURN",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "BACLEARs asserted for return branch"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
+ "EventCode": "0xE6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "BACLEARS.COND",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "BACLEARs asserted for conditional branch"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
new file mode 100644
index 0000000..0b53a3b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
@@ -0,0 +1,218 @@
+[
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x08",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walk completed due to a demand load to a 4K page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x08",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x08",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walk completed due to a demand load to a 1GB page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
+ "EventCode": "0x08",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walks outstanding due to a demand load every cycle."
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Page walk completed due to a demand data store to a 4K page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Page walk completed due to a demand data store to a 1GB page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walks outstanding due to a demand data store every cycle."
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks.",
+ "EventCode": "0x4F",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "EPT.WALK_PENDING",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walks outstanding due to walking the EPT every cycle"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
+ "EventCode": "0x81",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ITLB.MISS",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "ITLB misses"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x85",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x85",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.",
+ "EventCode": "0x85",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "2000003",
+ "BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page"
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
+ "EventCode": "0x85",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "ITLB_MISSES.WALK_PENDING",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Page walks outstanding due to an instruction fetch every cycle."
+ },
+ {
+ "CollectPEBSRecord": "1",
+ "PublicDescription": "Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3.",
+ "EventCode": "0xBD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "TLB_FLUSHES.STLB_ANY",
+ "PDIR_COUNTER": "na",
+ "SampleAfterValue": "20003",
+ "BriefDescription": "STLB flushes"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts load uops retired that caused a DTLB miss.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x11",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts store uops retired that caused a DTLB miss.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x12",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)"
+ },
+ {
+ "PEBS": "2",
+ "CollectPEBSRecord": "2",
+ "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.",
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x13",
+ "PEBScounters": "0,1,2,3",
+ "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
+ "SampleAfterValue": "200003",
+ "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 4ea0683..fe1a2c4 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -9,6 +9,7 @@
GenuineIntel-6-36,v4,bonnell,core
GenuineIntel-6-35,v4,bonnell,core
GenuineIntel-6-5C,v8,goldmont,core
+GenuineIntel-6-7A,v1,goldmontplus,core
GenuineIntel-6-3C,v24,haswell,core
GenuineIntel-6-45,v24,haswell,core
GenuineIntel-6-46,v24,haswell,core
diff --git a/tools/perf/tests/topology.c b/tools/perf/tests/topology.c
index a59db7c..81ede20 100644
--- a/tools/perf/tests/topology.c
+++ b/tools/perf/tests/topology.c
@@ -66,6 +66,27 @@
session = perf_session__new(&file, false, NULL);
TEST_ASSERT_VAL("can't get session", session);
+ /* On platforms with large numbers of CPUs process_cpu_topology()
+ * might issue an error while reading the perf.data file section
+ * HEADER_CPU_TOPOLOGY and the cpu_topology_map pointed to by member
+ * cpu is a NULL pointer.
+ * Example: On s390
+ * CPU 0 is on core_id 0 and physical_package_id 6
+ * CPU 1 is on core_id 1 and physical_package_id 3
+ *
+ * Core_id and physical_package_id are platform and architecture
+ * dependend and might have higher numbers than the CPU id.
+ * This actually depends on the configuration.
+ *
+ * In this case process_cpu_topology() prints error message:
+ * "socket_id number is too big. You may need to upgrade the
+ * perf tool."
+ *
+ * This is the reason why this test might be skipped.
+ */
+ if (!session->header.env.cpu)
+ return TEST_SKIP;
+
for (i = 0; i < session->header.env.nr_cpus_avail; i++) {
if (!cpu_map__has(map, i))
continue;
@@ -91,7 +112,7 @@
{
char path[PATH_MAX];
struct cpu_map *map;
- int ret = -1;
+ int ret = TEST_FAIL;
TEST_ASSERT_VAL("can't get templ file", !get_temp(path));
@@ -106,12 +127,9 @@
goto free_path;
}
- if (check_cpu_topology(path, map))
- goto free_map;
- ret = 0;
-
-free_map:
+ ret = check_cpu_topology(path, map);
cpu_map__put(map);
+
free_path:
unlink(path);
return ret;
diff --git a/tools/perf/util/bpf-loader.c b/tools/perf/util/bpf-loader.c
index 72c107f..c02d2cf 100644
--- a/tools/perf/util/bpf-loader.c
+++ b/tools/perf/util/bpf-loader.c
@@ -66,7 +66,7 @@
}
obj = bpf_object__open_buffer(obj_buf, obj_buf_sz, name);
- if (IS_ERR(obj)) {
+ if (IS_ERR_OR_NULL(obj)) {
pr_debug("bpf: failed to load buffer\n");
return ERR_PTR(-EINVAL);
}
@@ -102,14 +102,14 @@
pr_debug("bpf: successfull builtin compilation\n");
obj = bpf_object__open_buffer(obj_buf, obj_buf_sz, filename);
- if (!IS_ERR(obj) && llvm_param.dump_obj)
+ if (!IS_ERR_OR_NULL(obj) && llvm_param.dump_obj)
llvm__dump_obj(filename, obj_buf, obj_buf_sz);
free(obj_buf);
} else
obj = bpf_object__open(filename);
- if (IS_ERR(obj)) {
+ if (IS_ERR_OR_NULL(obj)) {
pr_debug("bpf: failed to load %s\n", filename);
return obj;
}
diff --git a/tools/perf/util/dso.c b/tools/perf/util/dso.c
index 00c98c9..505c13b 100644
--- a/tools/perf/util/dso.c
+++ b/tools/perf/util/dso.c
@@ -352,6 +352,8 @@
if ((strncmp(name, "[kernel.kallsyms]", 17) == 0) ||
(strncmp(name, "[guest.kernel.kallsyms", 22) == 0) ||
(strncmp(name, "[vdso]", 6) == 0) ||
+ (strncmp(name, "[vdso32]", 8) == 0) ||
+ (strncmp(name, "[vdsox32]", 9) == 0) ||
(strncmp(name, "[vsyscall]", 10) == 0)) {
m->kmod = false;
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
index f9157ae..d404bed 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
@@ -113,6 +113,7 @@
bool have_cyc;
bool fixup_last_mtc;
bool have_last_ip;
+ enum intel_pt_param_flags flags;
uint64_t pos;
uint64_t last_ip;
uint64_t ip;
@@ -226,6 +227,8 @@
decoder->return_compression = params->return_compression;
decoder->branch_enable = params->branch_enable;
+ decoder->flags = params->flags;
+
decoder->period = params->period;
decoder->period_type = params->period_type;
@@ -1097,6 +1100,15 @@
return ret;
}
+static inline bool intel_pt_fup_with_nlip(struct intel_pt_decoder *decoder,
+ struct intel_pt_insn *intel_pt_insn,
+ uint64_t ip, int err)
+{
+ return decoder->flags & INTEL_PT_FUP_WITH_NLIP && !err &&
+ intel_pt_insn->branch == INTEL_PT_BR_INDIRECT &&
+ ip == decoder->ip + intel_pt_insn->length;
+}
+
static int intel_pt_walk_fup(struct intel_pt_decoder *decoder)
{
struct intel_pt_insn intel_pt_insn;
@@ -1109,10 +1121,11 @@
err = intel_pt_walk_insn(decoder, &intel_pt_insn, ip);
if (err == INTEL_PT_RETURN)
return 0;
- if (err == -EAGAIN) {
+ if (err == -EAGAIN ||
+ intel_pt_fup_with_nlip(decoder, &intel_pt_insn, ip, err)) {
if (intel_pt_fup_event(decoder))
return 0;
- return err;
+ return -EAGAIN;
}
decoder->set_fup_tx_flags = false;
if (err)
@@ -1376,7 +1389,6 @@
{
intel_pt_log("ERROR: Buffer overflow\n");
intel_pt_clear_tx_flags(decoder);
- decoder->have_tma = false;
decoder->cbr = 0;
decoder->timestamp_insn_cnt = 0;
decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC;
@@ -1604,7 +1616,6 @@
case INTEL_PT_PSB:
case INTEL_PT_TSC:
case INTEL_PT_TMA:
- case INTEL_PT_CBR:
case INTEL_PT_MODE_TSX:
case INTEL_PT_BAD:
case INTEL_PT_PSBEND:
@@ -1620,6 +1631,10 @@
decoder->pkt_step = 0;
return -ENOENT;
+ case INTEL_PT_CBR:
+ intel_pt_calc_cbr(decoder);
+ break;
+
case INTEL_PT_OVF:
return intel_pt_overflow(decoder);
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h
index fc1752d..51c18d6 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h
@@ -60,6 +60,14 @@
INTEL_PT_ERR_MAX,
};
+enum intel_pt_param_flags {
+ /*
+ * FUP packet can contain next linear instruction pointer instead of
+ * current linear instruction pointer.
+ */
+ INTEL_PT_FUP_WITH_NLIP = 1 << 0,
+};
+
struct intel_pt_state {
enum intel_pt_sample_type type;
int err;
@@ -106,6 +114,7 @@
unsigned int mtc_period;
uint32_t tsc_ctc_ratio_n;
uint32_t tsc_ctc_ratio_d;
+ enum intel_pt_param_flags flags;
};
struct intel_pt_decoder;
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c
index ba4c9dd..d426761 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c
@@ -366,7 +366,7 @@
if (len < offs)
return INTEL_PT_NEED_MORE_BYTES;
byte = buf[offs++];
- payload |= (byte >> 1) << shift;
+ payload |= ((uint64_t)byte >> 1) << shift;
}
packet->type = INTEL_PT_CYC;
diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
index d9573c1..3b118fa 100644
--- a/tools/perf/util/intel-pt.c
+++ b/tools/perf/util/intel-pt.c
@@ -784,6 +784,7 @@
unsigned int queue_nr)
{
struct intel_pt_params params = { .get_trace = 0, };
+ struct perf_env *env = pt->machine->env;
struct intel_pt_queue *ptq;
ptq = zalloc(sizeof(struct intel_pt_queue));
@@ -865,6 +866,9 @@
}
}
+ if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
+ params.flags |= INTEL_PT_FUP_WITH_NLIP;
+
ptq->decoder = intel_pt_decoder_new(¶ms);
if (!ptq->decoder)
goto out_free;
@@ -1560,6 +1564,7 @@
if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
switch (ptq->switch_state) {
+ case INTEL_PT_SS_NOT_TRACING:
case INTEL_PT_SS_UNKNOWN:
case INTEL_PT_SS_EXPECTING_SWITCH_IP:
err = intel_pt_next_tid(pt, ptq);
diff --git a/tools/scripts/Makefile.include b/tools/scripts/Makefile.include
index 654efd9..5f3f1f4 100644
--- a/tools/scripts/Makefile.include
+++ b/tools/scripts/Makefile.include
@@ -101,3 +101,5 @@
QUIET_INSTALL = @printf ' INSTALL %s\n' $1;
endif
endif
+
+pound := \#
diff --git a/tools/testing/selftests/ftrace/test.d/functions b/tools/testing/selftests/ftrace/test.d/functions
index f2019b3..6a4982d 100644
--- a/tools/testing/selftests/ftrace/test.d/functions
+++ b/tools/testing/selftests/ftrace/test.d/functions
@@ -15,12 +15,27 @@
echo nop > current_tracer
}
-reset_trigger() { # reset all current setting triggers
- grep -v ^# events/*/*/trigger |
+reset_trigger_file() {
+ # remove action triggers first
+ grep -H ':on[^:]*(' $@ |
while read line; do
cmd=`echo $line | cut -f2- -d: | cut -f1 -d" "`
- echo "!$cmd" > `echo $line | cut -f1 -d:`
+ file=`echo $line | cut -f1 -d:`
+ echo "!$cmd" >> $file
done
+ grep -Hv ^# $@ |
+ while read line; do
+ cmd=`echo $line | cut -f2- -d: | cut -f1 -d" "`
+ file=`echo $line | cut -f1 -d:`
+ echo "!$cmd" > $file
+ done
+}
+
+reset_trigger() { # reset all current setting triggers
+ if [ -d events/synthetic ]; then
+ reset_trigger_file events/synthetic/*/trigger
+ fi
+ reset_trigger_file events/*/*/trigger
}
reset_events_filter() { # reset all current setting filters
